Power amplifier circuit

Abstract

Maintaining the characteristics of the power amplifier circuit without affecting cost. The power amplifier circuit has multiple amplification stages, including: a first amplification stage that amplifies the input high-frequency signal; a second amplification stage that amplifies the output of the first amplification stage; and a switching stage disposed on the power supply path to the first amplification stage, wherein power is supplied to the first amplification stage via the switching stage, and the switching stage sets the power supply to the first amplification stage to be on or off, and the power is directly supplied to the second amplification stage without passing through the switching stage.

Description

Technical Field

[0001] This invention relates to a power amplifier circuit. Background Technology

[0002] A power amplifier circuit that amplifies high-frequency signals by cascading multiple stages of amplifiers is known in the past (e.g., Patent Document 1). In Patent Document 1, power supply voltages are supplied to the multiple stages of amplifiers via switches.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 9-8675 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] As in Patent Document 1, by turning the switch on or off, the power supply to each stage of the amplifier can be set to be on or off, thereby preventing device breakdown due to excessive power supply voltage. However, in the structure of Patent Document 1, the characteristics of the power amplifier circuit may be degraded due to the on-resistance of the switch. Furthermore, in the structure of Patent Document 1, there is a possibility that the size of the switch will be increased, thus increasing the size of the power amplifier circuit as well.

[0008] This disclosure was made in view of the above-mentioned problems, and its purpose is to maintain the characteristics of the power amplifier circuit without affecting the cost.

[0009] Solution for solving the problem

[0010] To address the aforementioned problems and achieve the objective, a power amplifier circuit according to a certain embodiment of the present disclosure has a multi-stage amplification section, comprising: a first amplification section that amplifies an input high-frequency signal; a second amplification section that amplifies the output of the first amplification section; and a switching section disposed on the power supply path to the first amplification section, wherein power is supplied to the first amplification section via the switching section, the switching section setting the power supply to the first amplification section to be on or off, and the power is directly supplied to the second amplification section without passing through the switching section.

[0011] Another aspect of the power amplifier circuit disclosed herein has only one stage of amplification, the power amplifier circuit comprising: a first amplification stage for amplifying an input high-frequency signal; and a switching stage disposed on a power supply path to the first amplification stage, wherein power is supplied to the first amplification stage via the switching stage, the switching stage setting the power supply to the first amplification stage to be on or off, the first amplification stage having: an input terminal for receiving a signal to be amplified; a first FET having a gate for which a signal input to the input terminal is applied; a second FET connected together with the first FET between a power supply and a reference potential; an output terminal disposed between the second FET and a load for outputting the amplified signal; and a voltage divider resistor circuit for generating a bias applied to the gate of the second FET, the first FET and the second FET being cascaded.

[0012] The effects of the invention

[0013] According to this disclosure, the characteristics of the power amplifier circuit can be maintained without affecting the cost. Attached Figure Description

[0014] Figure 1 This is a diagram showing the structure of the power amplifier circuit of the first comparative example.

[0015] Figure 2 This is a diagram showing the structure of the power amplifier circuit of the second comparative example.

[0016] Figure 3 This is a diagram showing the power amplifier circuit of the first embodiment.

[0017] Figure 4 This is a diagram illustrating a structural example of a communication device that includes a power amplifier circuit.

[0018] Figure 5 This is a diagram showing the structure of the amplification section used in the power amplifier circuit of the third comparative example.

[0019] Figure 6 This is a diagram showing an example of a structure where a switch is connected to the amplifier section.

[0020] Figure 7 This is a diagram showing the amplification section used in the power amplifier circuit of the fourth comparative example.

[0021] Figure 8 This is a diagram showing the amplification section used in the power amplifier circuit of the second embodiment.

[0022] Figure 9 It is a graph illustrating the relationship between the various voltage values.

[0023] Figure 10This is a diagram showing the amplification section used in the power amplifier circuit of the third embodiment.

[0024] Figure 11 It means to make Figure 10 The waveform diagram of the inverted output signal of the comparator in the example.

[0025] Figure 12 This is a diagram showing the input and output voltages of the switch located between the power supply and the amplification section.

[0026] Figure 13 This is a diagram showing the input voltage and gate bias of the switch.

[0027] Figure 14 This is a diagram illustrating an example of the change in on-resistance.

[0028] Figure 15 This is a diagram illustrating an example of a switch based solely on PMOS.

[0029] Figure 16 This is a diagram illustrating an example of a switch based solely on NMOS.

[0030] Figure 17 This is a diagram showing examples of PMOS and NMOS-based switches.

[0031] Figure 18 This is a diagram showing the amplification section used in the power amplifier circuit of the fourth embodiment.

[0032] Figure 19 This is a diagram used to illustrate the hysteresis characteristics of the comparator's output signal.

[0033] Figure 20 It means Figure 18 A diagram illustrating the structure of a variable resistor.

[0034] Figure 21 This is a diagram showing the structure of the power amplifier circuit according to the fifth embodiment.

[0035] Figure 22 This is a diagram illustrating a structural example of a communication device that includes a power amplifier circuit. Detailed Implementation

[0036] Hereinafter, embodiments of the present invention will be described in detail based on the accompanying drawings. In the following descriptions of each embodiment, structural parts that are the same or equivalent to those in other embodiments will be labeled with the same reference numerals, and their descriptions will be simplified or omitted. The present invention is not limited to these embodiments. Furthermore, the constituent elements of each embodiment include constituent elements that can be easily replaced by those skilled in the art, or substantially the same constituent elements. In addition, the structures described below can be appropriately combined. Furthermore, structural omissions, substitutions, or modifications can be made without departing from the spirit of the invention.

[0037] (First Implementation)

[0038] To facilitate understanding of the first embodiment, the first comparative example and the second comparative example will be described first. Figure 1 This is a diagram showing the structure of the power amplifier circuit 100a in the first comparative example. Figure 1 In this circuit, power amplifier circuit 100a is a two-stage amplifier circuit, having amplification sections 101 and 201. The first-stage (pre-amplifier) ​​amplification section 101 is the amplification section of the driver stage. Amplification section 101 amplifies the signal input to input terminal Tin and outputs the amplified signal to amplification section 201. The second-stage (post-amplifier) ​​amplification section 201 is the amplification section of the power stage. Amplification section 201 amplifies the signal output from amplification section 101 and outputs the amplified signal from output terminal Tout.

[0039] Furthermore, the power amplifier circuit 100a includes a switch SWa that is shared by both amplification sections 101 and 201. That is, a switch SWa corresponding to both amplification sections 101 and 201 is provided. A voltage based on the power supply Vcc is supplied to amplification sections 101 and 201 via the switch SWa. In addition, in this example, transistors with emitter ground are provided in the output sections of both amplification sections 101 and 201. Therefore, a voltage based on the power supply Vcc is applied to the output side of amplification sections 101 and 201.

[0040] Figure 1 The operation of the first comparative example shown is as follows. In the power amplifier circuit 100a, when switch SWA is in the ON state, a voltage based on the power supply Vcc is supplied to amplification units 101 and 201. As a result, amplification units 101 and 201 perform amplification operations. When switch SWA is in the OFF state, no voltage based on the power supply Vcc is supplied to amplification units 101 and 201. At this time, amplification units 101 and 201 do not perform amplification operations.

[0041] Figure 2 This is a diagram showing the structure of the power amplifier circuit 100b in the second comparative example. Figure 2Unlike power amplifier circuit 100a, power amplifier circuit 100b has a switch SWb corresponding to amplification unit 101 and a switch SWc corresponding to amplification unit 201. A voltage based on power supply Vcc is supplied to amplification unit 101 via switch SWb. A voltage based on power supply Vcc is supplied to amplification unit 201 via switch SWc.

[0042] Figure 2 The operation of the second comparative example is as follows: In the power amplifier circuit 100b, when switch SWb is in the ON state, a voltage based on the power supply Vcc is supplied to the amplification unit 101. Therefore, the amplification unit 101 performs amplification. When switch SWb is in the OFF state, no voltage based on the power supply Vcc is supplied to the amplification unit 101. At this time, the amplification unit 101 does not perform amplification. When switch SWc is in the ON state, a voltage based on the power supply Vcc is supplied to the amplification unit 201. Therefore, the amplification unit 201 performs amplification. When switch SWc is in the OFF state, no voltage based on the power supply Vcc is supplied to the amplification unit 201. At this time, the amplification unit 201 does not perform amplification.

[0043] Furthermore, the on-resistance of the switches can sometimes affect the characteristics of the power amplifier circuit when the power supply to each stage of the amplifier is turned on or off. In particular, the current flowing through the power stage amplifier, which is the second stage (the next stage), is larger than that of the driver stage (the first stage). Therefore, when a switch is placed in the power stage amplifier, the amplification characteristics of the power stage amplifier may deteriorate significantly. To reduce the on-resistance of the switches, it is necessary to increase the size of the transistors constituting the switches. However, increasing the size of the transistors constituting the switches results in an overall increase in the size of the device, which is undesirable. For example, regarding the switch SWA (refer to...) Figure 1 ), switch SWc (refer to) Figure 2 This leads to the problem that increasing the transistor size is necessary to reduce the on-resistance of the transistors used to implement these switches. Increasing the transistor size results in a larger device size, which significantly impacts cost and is therefore undesirable.

[0044] Figure 3 This is a diagram showing the power amplifier circuit 100 of the first embodiment. (Compared with reference to...) Figure 1 , Figure 2The first and second comparative examples described herein also have multi-stage amplification sections 101 and 201. The power amplifier circuit 100 includes a switch VccSW. The switch VccSW is located on the power supply path from the power supply Vcc to the amplification section 101. Power is supplied to the amplification section 101 from the power supply Vcc via the switch VccSW. The switch VccSW sets the power supply from the power supply Vcc to the amplification section 101 to be either on or off. The switch VccSW corresponds to the switching section of this disclosure. The amplification section 101 corresponds to the first amplification section of this disclosure. Furthermore, a power amplifier circuit with two stages of amplification is described here, but any circuit with two or more stages is acceptable; the number of stages is not limited, and amplification sections with three or more stages may also be used.

[0045] The switch VccSW is controlled to be in the on state when the voltage based on the power supply Vcc is below a predetermined threshold. The switch VccSW is controlled to be in the off state when the voltage based on the power supply Vcc exceeds a predetermined threshold. The predetermined threshold is, for example, the maximum drive voltage of the amplifier 101.

[0046] Power is supplied directly to the amplification section 201 from the power supply Vcc without passing through the switch VccSW. Therefore, a switch corresponding to the amplification section 201 is not required. Compared with the first and second comparative examples, the size of the transistor can be suppressed. The amplification section 201 corresponds to the second amplification section of this disclosure.

[0047] In the power amplifier circuit 100, when the switch VccSW is in the on state, similarly to the first and second comparative examples, the amplification unit 101 amplifies the signal input to the input terminal Tin and outputs the amplified signal to the amplification unit 201. The amplification unit 201 amplifies the output signal of the amplification unit 101 and outputs the amplified output signal from the output terminal Tout.

[0048] A switch VccSW corresponding to amplification section 101 is provided, but a switch corresponding to amplification section 201 is not provided. When the voltage of the power supply Vcc is above a predetermined threshold, switch VccSW is kept in the off state. By controlling switch VccSW in this way, the characteristics of the power amplifier circuit can be maintained without affecting cost.

[0049] In the power amplifier circuit 100, the amplification section 101 can be formed on a silicon die, while the amplification section 201 can be formed on a chip other than the silicon die. The silicon die refers to a chip using Si, such as a chip using an SOI (Silicon-on-Insulator) substrate. The chip other than the silicon die is, for example, a chip made of GaAs. According to this structure, as described later, even when the amplification section 101 is composed of multiple transistors stacked on the silicon die, the maximum voltage applied to the power amplifier circuit can be suppressed, ensuring withstand voltage and preventing degradation of the power amplifier circuit's characteristics.

[0050] (communication device)

[0051] Here, a communication device including a power amplifier circuit will be described. Figure 4 This is a diagram illustrating a structural example of a communication device including a power amplifier circuit. Figure 4 In this communication device 1000, there are a power amplifier circuit M1, frequency band selection switches BS1 and BS2, filters SF1 to SF5, antenna switches AS1 and AS2, antennas ANT1 and ANT2, a power control unit 400, a baseband IC (Integrated Circuit) 500, and a switch VddSW. The switch VddSW is equivalent to the switching unit of this disclosure.

[0052] The power amplifier circuit M1 is a PA (Power Amplifier) ​​module, which functions as a power amplifier circuit. The power amplifier circuit M1 includes an amplification section 101 for the driver stage, amplification sections 201 and 202 for the power stage, switches SW1 and SW2, and a control circuit 301.

[0053] The output of the amplification section 101 in the driver stage is output to the input of the amplification section 201 in the power stage via switch SW1. Additionally, the output of the amplification section 101 in the driver stage is output to the input of the amplification section 202 in the power stage via switch SW2. Amplification section 101 is the amplification section of the pre-amplifier stage, i.e., the driver stage. Amplification sections 201 and 202 are the amplification sections of the post-amplifier stage, i.e., the power stage.

[0054] The power stage amplification sections 201 and 202 are, for example, constructed from bipolar transistors. The control circuit 301 is a circuit that outputs control signals for controlling the amplification sections 101 and 201. For example, the control circuit 301 inputs a gate bias control signal SSW to the amplification section 101. The control circuit 301 inputs bias currents to the amplification sections 201 and 202. The amplification section 101 and the control circuit 301 are, for example, implemented using an SOI (Silicon on Insulator) substrate 801. The amplification sections 201 and 202 are, for example, implemented using GaAs substrates 901 and 902.

[0055] Here, switches SW1 and SW2 are controlled such that when one is in the on state, the other is in the off state. Therefore, in the power stage amplification sections 201 and 202, when one is performing amplification, the other is in a standby state where no amplification is performed. That is, amplification section 201 and amplification section 202 are selectively in an operating state, and in a standby state when not in an operating state. The amplification section 201 and amplification section 202 in the amplification operating state operates, for example, in any of the following modes: High Power Mode (HPM), Middle Power Mode (MPM), or Low Power Mode (LPM).

[0056] Frequency band selection switch BS1 selects the frequency band based on the frequency band selection control signal SS. Frequency band selection switch BS2 selects the frequency band based on the frequency band selection control signal SS.

[0057] Filters SF1 to SF5 are, for example, SAW (Surface Acoustic Wave) filters. Filters SF1 and SF2 extract the desired frequency band signal from the output of frequency band selection switch BS1. Filters SF3 to SF5 extract the desired frequency band signal from the output of frequency band selection switch BS2.

[0058] Antenna switch AS1 selects the output of filter SF1 or SF2 based on the frequency band selection control signal SS. Antenna switch AS2 selects the output of filter SF3, filter SF4, or filter SF5 based on the frequency band selection control signal SS. Antenna ANT1 transmits the signal selected by antenna switch AS1 in the form of electromagnetic waves. Antenna ANT2 transmits the signal selected by antenna switch AS2 in the form of electromagnetic waves.

[0059] The power control unit 400 is a power control module for outputting power supply Vdd. Power supply Vdd is input to the power amplifier circuit M1. The power control unit 400 includes, for example, a DC-DC (Direct Current-Direct Current) converter that converts the DC voltage level. Furthermore, in the first embodiment described above, a bipolar transistor is used as the basis for the power supply designation "Vcc," but in the following description, a FET (Field Effect Transistor, hereinafter referred to as FET) is used as the basis for the power supply designation "Vdd."

[0060] The baseband IC 500 sends an RF signal to the power amplifier circuit M1. Additionally, based on the desired output frequency band, the baseband IC 500 sends control signals CS and SS to various components within the communication device 1000. The baseband IC 500 sends the SS frequency band selection control signal to the frequency band selection switches BS1 and BS2, and the antenna switches AS1 and AS2. The baseband IC 500 outputs a signal to control the power supply Vdd output from the power control unit 400.

[0061] A switch VddSW is installed on the power supply path from the power supply Vdd to the amplifier 101. Power is supplied from the power supply Vdd to the amplifier 101 via the switch VddSW. The switch VddSW sets the power supply to the amplifier 101 to be on or off. The switch VddSW corresponds to the switching unit of this disclosure.

[0062] (action)

[0063] The baseband IC 500 controls various parts of the communication device 1000 to transmit RF signals by ensuring that signals travel along a desired path. The RF signal is input to the power amplifier circuit M1 and amplified by the amplification section 101 of the driver stage. The amplified RF signal from the amplification section 101 is then input to the power stage amplification section 201 or 202, depending on the states of switches SW1 and SW2. The signal amplified by the amplification section 201 is output from antenna ANT1 via frequency band selection switch BS1, filter SF1 or SF2, and antenna switch AS1. Conversely, the signal amplified by the amplification section 202 is output from antenna ANT2 via frequency band selection switch BS2, filters SF3-SF5, and antenna switch AS2.

[0064] The power control unit 400 is controlled by the baseband IC 500. The voltage value of the power supply Vdd output by the power control unit 400 is controlled according to the output power of the amplifier unit 201 or 202 in the operating state. Therefore, the voltage value of the power supply Vdd changes. For example, the voltage value of the power supply Vdd changes when performing average power tracking (APT) or envelope tracking (ET).

[0065] (Second Implementation)

[0066] To facilitate understanding of the second embodiment, the third and fourth comparative examples will be described first. Figure 5 This is a diagram showing the structure of the amplification section used in the power amplifier circuit of the third comparative example. Figure 5 This indicates the structure excluding the amplification section of the switch VddSW, which will be described later. Figure 5In the amplification section, there are multiple field-effect transistors, namely FETs 11, 12, 13, 14, 15, 16, resistors 21, 22, 23, 24, 25, 26, resistors 31, 32, 33, 34, 35, 36, capacitors 41, 42, 43, 44, 45, 46, FET 17, choke coil L11, bypass capacitor C11, and bias circuit B1.

[0067] FETs 11, 12, 13, 14, 15, and 16 are positioned between a reference potential and the power supply Vdd. FETs 11, 12, 13, 14, 15, and 16 are cascaded through adjacent drain-source connections. That is, the source of FET 11 is connected to the reference potential, and the drain of FET 11 is connected to the source of FET 12. The drain of FET 12 is connected to the source of FET 13. The drain of FET 13 is connected to the source of FET 14. The drain of FET 14 is connected to the source of FET 15. The drain of FET 15 is connected to the source of FET 16. The drain of FET 16 is connected to the power supply Vdd via a choke coil L11. In this specification, FET 11 is sometimes referred to as the first FET, and FET 12 is sometimes referred to as the second FET. The reference potential is, for example, ground. The same applies in the following description.

[0068] Although the voltage value of the power supply Vdd is a fixed value, it can be varied as described later. An output terminal RFout is connected between the choke coil L11 and FET 16. The output terminal RFout is connected to the amplification section of the subsequent stage. The output terminal RFout is connected to the power supply Vdd via the choke coil L11.

[0069] Resistor 31 and capacitor 41 are configured correspondingly to FET 11. One end of resistor 31 and one end of capacitor 41 are connected to the gate of FET 11, respectively. The other end of capacitor 41 is connected to the input terminal RFin. The signal to be amplified is input to the input terminal RFin.

[0070] Resistor 32 and capacitor 42 are disposed correspondingly to FET 12. One end of resistor 32 and one end of capacitor 42 are respectively connected to the gate of FET 12. The other end of capacitor 42 is connected to a reference potential.

[0071] Resistor 33 and capacitor 43 are disposed correspondingly to FET 13. One end of resistor 33 and one end of capacitor 43 are respectively connected to the gate of FET 13. The other end of capacitor 43 is connected to a reference potential.

[0072] Resistor 34 and capacitor 44 are disposed correspondingly to FET 14. One end of resistor 34 and one end of capacitor 44 are respectively connected to the gate of FET 14. The other end of capacitor 44 is connected to a reference potential.

[0073] Resistor 35 and capacitor 45 are disposed correspondingly to FET 15. One end of resistor 35 and one end of capacitor 45 are respectively connected to the gate of FET 15. The other end of capacitor 45 is connected to a reference potential.

[0074] Resistor 36 and capacitor 46 are disposed correspondingly to FET 16. One end of resistor 36 and one end of capacitor 46 are respectively connected to the gate of FET 16. The other end of capacitor 46 is connected to a reference potential.

[0075] The drain and gate of FET 17 are connected, forming a so-called diode connection. FET 17 is positioned between resistor 21 and the reference potential.

[0076] Resistors 21, 22, 23, 24, 25, and 26 are trapezoidal resistors connected in series between the power supply Vdd and the reference potential. Resistors 21, 22, 23, 24, 25, and 26 form a voltage divider resistor circuit 20. The voltage divider resistor circuit 20 divides the potential difference between the power supply Vdd and the reference potential, generating a bias voltage applied to the gates of FETs 12 to FET 16. By using identical trapezoidal resistors for each of resistors 21, 22, 23, 24, 25, and 26, it is possible to prevent reversal of the gate bias voltage at each stage due to mismatches in the resistor pairing. Here, "identical trapezoidal resistors" refers to trapezoidal resistors manufactured using the same process and materials.

[0077] One end of resistor 21 is connected to the drain and gate of FET 17. The other end of resistor 21 is connected to a reference potential via the diode of FET 17. FET 17 is connected to the reference potential side of the voltage divider circuit 20. Therefore, FET 17 is positioned between the voltage divider circuit 20 and the reference potential.

[0078] In the voltage divider resistor circuit 20, resistors 21 and 22 are connected in series. The junction of resistors 21 and 22 is connected to the other end of resistor 32. The voltage at the junction of resistors 21 and 22 is applied as bias voltage vg2 to the gate of FET 12. Resistor 22 and 23 are connected in series. The junction of resistors 22 and 23 is connected to the other end of resistor 33. The voltage at the junction of resistors 22 and 23 is applied as bias voltage vg3 to the gate of FET 13. Resistor 23 and 24 are connected in series. The junction of resistors 23 and 24 is connected to the other end of resistor 34. The voltage at the junction of resistors 23 and 24 is applied as bias voltage vg4 to the gate of FET 14. Resistor 24 and 25 are connected in series. The junction of resistors 24 and 25 is connected to the other end of resistor 35. The voltage at the junction of resistors 24 and 25 is applied as bias voltage vg5 to the gate of FET 15. Resistor 25 and 26 are connected in series. The junction of resistors 25 and 26 is connected to the other end of resistor 36. The voltage at the junction of resistors 25 and 26 is applied as bias voltage vg6 to the gate of FET 16. The other end of resistor 31 is connected to bias circuit B1. The bias voltage vg1 output by bias circuit B1 is applied to the gate of FET 11 via resistor 31.

[0079] The choke coil L11 is connected in series between the power supply voltage Vdd and the amplifier section 101. One end of the bypass capacitor C11 is connected to the junction of one end of the choke coil L11 and the power supply voltage Vdd. The other end of the bypass capacitor C11 is connected to the reference potential.

[0080] Figure 5 The amplification unit 101 shown operates as follows: A bias voltage (i.e., gate bias voltage) generated by the resistor division in the voltage divider circuit 20 is applied to the gates of FETs 12 to FET 16. The amplification unit 101 amplifies the high-frequency signal input to the input terminal RFin. The amplified signal is output from the output terminal RFout.

[0081] In this example, FETs 11 through FET 16 are included, and the six FETs are cascaded together. The number of cascaded FETs (hereinafter referred to as the stacking number) is determined in such a way that the withstand voltage can be ensured under the maximum voltage applied by the power supply Vdd. That is, the stacking number is determined in such a way that breakdown will not occur even when the maximum voltage is applied. Hereinafter, the aforementioned maximum voltage is sometimes referred to as the AMR voltage (Absolute Maximum Ratings).

[0082] However, when the operating range of the power supply Vdd, which is required to ensure the characteristics of the power amplifier circuit, deviates from the AMR voltage, a greater number of stacks is needed to ensure the withstand voltage for the AMR voltage than is required for the operating range of the power supply Vdd. As the number of stacks increases, the on-resistance of the FETs closest to the power supply Vdd increases, leading to a degradation in the characteristics of the power amplifier circuit. For example, if a stack of "4" is sufficient to ensure the withstand voltage for the operating range of the power supply Vdd, then a stack of "6" is needed to ensure the withstand voltage for the AMR voltage. In this case, within the operating range, the two FETs 15 and 16 closest to the power supply Vdd act as on-resistance, contributing to the degradation of the power amplifier circuit's characteristics.

[0083] Figure 6 This diagram illustrates a structural example of connecting the switch VddSW to the amplification section. Figure 6 In this configuration, a switch VddSW is inserted between the power supply Vdd wiring and the choke coil L11. Additionally, the number of stacked amplifier sections 101 is "4".

[0084] When the voltage value of the power supply Vdd exceeds the operating range, the switch VddSW is turned off. This suppresses the maximum voltage of the power supply Vdd applied to the power amplifier circuit to a value within or slightly exceeding the operating range. With this structure, the maximum voltage applied to the power amplifier circuit can be suppressed, ensuring withstand voltage while reducing the number of stacked power amplifier circuits. Since the number of stacked circuits can be reduced, the characteristics of the power amplifier circuit can be prevented from deteriorating. Furthermore, the operating range is the voltage range used to drive the amplification section 101, referring to the voltage range below the maximum drive voltage of the amplification section 101. That is, the meaning of "exceeding the operating range" is the same as the meaning of "exceeding the maximum drive voltage of the amplification section 101".

[0085] Here, the switch VddSW is inserted between the power supply Vdd and the choke coil L11, so the on-resistance of the switch VddSW can be seen on DC. However, at high frequencies, it is grounded through the bypass capacitor C11, thus eliminating the on-resistance of the switch VddSW.

[0086] Furthermore, if the voltage of the power supply Vdd exceeds its operating range, and the switch VddSW is in a fully off state, then only the voltage of the power supply Vdd is applied to the switch VddSW. If the semiconductor process used to form the power amplifier circuit does not have a FET capable of supporting the AMR voltage of the power supply Vdd, it is necessary to increase the number of FETs cascaded in the switch VddSW to meet the voltage requirements.

[0087] Figure 7This is a diagram showing the amplification section used in the power amplifier circuit of the fourth comparative example. Figure 7 This indicates a structure in which the voltage-resistance switch VddSWa is connected to the amplifier section 101. Figure 7 In this circuit, switch VddSWa includes switches SSW1 and SSW2, and resistors Rsw1 and Rsw2.

[0088] Switches SSW1 and SSW2 are both implemented using FETs, for example. One end of switch SSW1 is connected to the wiring of the power supply Vdd. The other end of switch SSW1 is connected to one end of switch SSW2. The other end of switch SSW2 is connected to the drain of FET 14 via choke coil L11. Choke coil L11 is connected in series between switch VddSWa and amplification section 101.

[0089] One end of resistor Rsw1 is connected to the wiring of power supply Vdd. The other end of resistor Rsw1 is connected to one end of resistor Rsw2. The other end of resistor Rsw2 is connected to a reference potential. The voltage divided by resistors Rsw1 and Rsw2 is applied to the connection point of switch SSW1 and switch SSW2.

[0090] like Figure 7 As shown, when FET-based switches SSW1 and SSW2 are cascaded, the applied voltage can be distributed to each FET, but the on-resistance of the FET becomes a multiple of the number of stacked FETs. Furthermore, the area of ​​the FET also becomes a multiple of the number of stacked FETs. When the on-resistance is the same as that of a single FET, the area of ​​the FET becomes the square of the number of stacked FETs. Regarding the on-resistance of switch VddSWa, its influence can be reduced at high frequencies, but due to the voltage drop caused by the DC current in amplification section 101, there is a drawback: when the on-resistance of switch VddSWa is large, the voltage applied to amplification section 101 during operation decreases.

[0091] Furthermore, if the voltage of the power supply Vdd exceeds its operating range, and switch VddSWa is completely turned off, then only the voltage of the power supply Vdd is applied to switch VddSWa. Therefore, the FET-based switches SSW1 and SSW2 used in switch VddSWa need to have a withstand voltage higher than the AMR voltage.

[0092] Figure 8This diagram illustrates the amplification section used in the power amplifier circuit of the second embodiment. To eliminate the problems arising in the fourth comparative example described above, in the second embodiment, a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) based switch (hereinafter referred to as a PMOS switch) TrP is combined with an N-type MOSFET based switch (hereinafter referred to as an NMOS switch) TrN, and used as a transmission gate. The source of the PMOS switch TrP is connected to the power supply Vdd. The drain of the NMOS switch TrN is connected to the power supply Vdd. The drain of the PMOS switch TrP is connected to the source of the NMOS switch TrN, and power is supplied to the amplification section 101 from this connection point. The PMOS switch TrP corresponds to the PMOS transistor of this disclosure. The NMOS switch TrN corresponds to the NMOS transistor of this disclosure.

[0093] The switch VddSW has a PMOS gate bias circuit PB. The PMOS gate bias circuit PB applies a bias voltage to the gate of the PMOS switch TrP. The PMOS gate bias circuit PB applies a bias voltage to the gate of the PMOS switch TrP such that the PMOS switch TrP is in the off state when the voltage of the power supply Vdd is above a specified threshold, and in the on state when the voltage of the power supply Vdd is below the specified threshold.

[0094] The PMOS switch TrP is in the off state when the voltage of the power supply Vdd is above a specified threshold, and in the on state when the voltage of the power supply Vdd is below the specified threshold. Here, assuming that the switch VddSW is completely off, it is necessary to ensure the withstand voltage against the AMR voltage solely through the switch VddSW. Therefore, when the voltage of the power supply Vdd is high and the switch VddSW is off, a voltage below the voltage value of the power supply Vdd within the operating range is also applied to the amplification unit 101. Thus, the voltage of the power supply Vdd is divided between the switch VddSW and the amplification unit 101, ensuring their respective withstand voltages.

[0095] Specifically, when the PMOS switch TrP is in the off state, a voltage approximately half the AMR voltage (hereinafter referred to as voltage VREG) is continuously applied to the gate of the NMOS switch TrN, thereby causing the NMOS switch TrN to perform source follower operation. Therefore, a voltage equal to the difference between voltage VREG and the threshold voltage of the NMOS switch TrN is applied to the amplification section 101 to divide the voltage of the power supply Vdd. Furthermore, voltage VREG can be generated in the power amplifier circuit.

[0096] In addition, a voltage is continuously applied to the upper end of the amplifying unit 101, that is, the drain of the FET 14. However, when the switch VddSW is in the cut-off state, the amplifying unit 101 is also made in the cut-off state. Specifically, the bias voltage vg1 from the bias circuit B1 is set to 0 [V], and the FET 11 is cut off. As a result, the amplifying unit 101 does not amplify the RF signal, and the RF signal is no longer output from the output terminal RFout. Thus, it is possible to implement a breakdown countermeasure for the amplifying unit 201 or 202 (refer to Figure 4 ) at the subsequent stage of the amplifying unit 101.

[0097] (Relationship of each voltage value)

[0098] Figure 9 is a diagram illustrating the relationship of each voltage value. Figure 9 It shows the voltage VPA at the upper end of the amplifying unit 101 (the output voltage of the switch VddSW) after the switch VddSW is made in the cut-off state, the voltage Voff for making the switch VddSW in the cut-off state, and the AMR voltage Vamr.

[0099] In Figure 9 , the arrow Y1 indicates the withstand voltage required for the switch VddSW. The arrow Y2 indicates the withstand voltage required for the amplifying unit 101. The double-headed arrow Y3 indicates the voltage in the operating range.

[0100] As Figure 9 shown, the voltage Voff for making the switch VddSW in the cut-off state is set between the AMR voltage Vamr and the maximum voltage in the operating range. The withstand voltage of the amplifying unit 101 needs to be designed to be larger than the voltage Voff for making the switch VddSW in the cut-off state. That is, the maximum voltage value in the operating range < the voltage Voff for making the switch VddSW in the cut-off state < the withstand voltage of the amplifying unit 101 < the AMR voltage.

[0101] In addition, the voltage VPA at the upper end of the amplifying unit 101 after the switch VddSW is made in the cut-off state needs to be set to be less than or equal to the voltage Voff for making the switch VddSW in the cut-off state. That is, the voltage value at the upper end of the amplifying unit 101 in the cut-off state of the switch VddSW ≤ the voltage Voff for making the switch VddSW in the cut-off state.

[0102] Moreover, the withstand voltage of the switch VddSW needs to be larger than the voltage difference between the AMR voltage Vamr and the voltage VPA at the upper end of the amplifying unit 101 after the switch VddSW is made in the cut-off state. That is, (AMR voltage Vamr - the voltage VPA at the upper end of the amplifying unit 101 in the cut-off state of the switch VddSW) < the withstand voltage of the amplifying unit 101.

[0103] (Third Embodiment)

[0104] Figure 10This diagram illustrates the amplification section used in the power amplifier circuit of the third embodiment. The third embodiment is a structure that adds a comparator CMP, resistors R0 and R1, an inverter INV, and a reference voltage source Vref to the structure of the second embodiment.

[0105] Resistors R0 and R1 divide the voltage between the power supply Vdd and the reference potential, and input this voltage to the non-inverting input terminal (+ side) of comparator CMP. The reference voltage of the reference voltage source Vref is input to the inverting input terminal (- side) of comparator CMP. Comparator CMP compares the voltage of the power supply Vdd with the reference voltage of the reference voltage source Vref. The reference voltage of the reference voltage source Vref can be generated in the power amplifier circuit.

[0106] When the voltage divided by resistors R0 and R1 across the power supply Vdd exceeds the reference voltage of the reference voltage source Vref, the output signal of comparator CMP switches from a low level to a high level. By switching the output signal of comparator CMP from low to high, the PMOS switch TrP is controlled to be turned off. The threshold voltage of the comparator CMP based on the reference voltage source Vref needs to be larger than the operating range of the power supply Vdd and is set to be below the withstand voltage of the amplification section 101.

[0107] Furthermore, the output signal of comparator CMP is inverted by inverter INV and then input to bias circuit B1. This switches the bias voltage vg1 from bias circuit B1 to amplifier 101 from high to low. In this way, amplifier 101 no longer outputs an RF signal, preventing subsequent amplifiers 201 or 202 from being damaged.

[0108] Figure 11 It means to make Figure 10 The waveform of an example of the inverted output signal of the comparator CMP in the diagram is shown. That is, Figure 11 It means Figure 10 The waveform diagram of the output signal of the inverter INV in the example is shown. Figure 11 As shown, the output voltage Vinv of the inverter INV changes from a high level to a low level at a voltage Voff that is slightly beyond the operating voltage range of the power supply Vdd used during normal operation and lower than the AMR voltage. When the output voltage Vinv of the inverter INV changes in this way, the bias voltage vg1 from the bias circuit B1 to the amplifier 101 switches from a high level to a low level. As a result, the amplifier 101 no longer outputs an RF signal, which prevents the subsequent amplifiers 201 or 202 from being damaged.

[0109] Figure 12 This is a diagram showing the input and output voltages of the switch VddSW, which is located between the power supply Vdd and the amplifier section 101. Figure 12 The solid line in the figure represents the input voltage VddSWin to the switch VddSW. Figure 12 The dashed line in the figure represents the output voltage VddSWout from the switch VddSW.

[0110] like Figure 12 As shown, the input voltage VddSWin to switch VddSW rises within the range of the AMR voltage. In response, the output voltage VddSWout from switch VddSW rises along with the input voltage VddSWin, but drops at a voltage Voff that is somewhat beyond the operating voltage range of amplifier 101 and less than the withstand voltage of amplifier 101. This is because the gate bias voltage from the PMOS gate bias circuit PB decreases, and switch TrP becomes off. Even when switch TrP is off, switch TrN is on. At this time, the output voltage VddSWout becomes the voltage level near the gate bias voltage VREG of switch TrN.

[0111] If the switch VddSW were not used, the withstand voltage (stack count) of the amplifier section 101 would have to be designed to match the AMR voltage. However, by using the switch VddSW, a voltage higher than the power supply voltage Vdd required to turn off the switch VddSW is not applied to the amplifier section 101. Therefore, the stack count of the amplifier section 101 can be designed with a voltage lower than the AMR voltage, reducing the stack count. Because the stack count can be reduced, the characteristics of the amplifier section 101 within the operating voltage range can be improved.

[0112] Figure 13 This is a graph showing the input voltage and gate bias of switch VddSW. Figure 13 This represents the input voltage VddSWin of switch VddSW, the gate bias voltage Vgp of switch TrP, and the gate bias voltage Vgn of switch TrN. While switch VddSW is in the ON state, the gate bias voltage Vgp of switch TrP is controlled to prevent it from exceeding the source-gate voltage withstand voltage of switch TrP due to the rise in the power supply voltage Vdd. After switch VddSW is turned off, it reaches the same potential as the power supply Vdd, putting switch TrP in the OFF state.

[0113] Regarding switch TrN, a voltage VREG is continuously applied as the gate bias Vgn, regardless of the on / off state of switch VddSW. This ensures that the output voltage of switch VddSW remains constant even after switch TrP becomes off. For example, control can be applied to make the output voltage of switch VddSW approximately 3V, while still ensuring the withstand voltage of switch VddSW. That is, regardless of the voltage value of the power supply Vdd, a voltage is applied to switch TrN such that the source potential of switch TrN is less than a specified threshold (e.g., less than...). Figure 12 A gate bias voltage Vgn (half the AMR voltage shown) is applied. This causes switch TrN to perform source follower operation, maintaining the source potential of switch TrN below the breakdown voltage of the power amplifier circuit. In other words, even when the PMOS switch TrP is in the off state, a voltage VREG is continuously applied to the gate of the NMOS switch TrN, thereby causing the NMOS switch TrN to perform source follower operation.

[0114] Additionally, sometimes the voltage value of the power supply Vdd is controlled. For example, in APT control, the voltage value of the power supply Vdd is controlled to match the output power. In this case, the voltage value of the power supply Vdd varies within a wide range of high and low values.

[0115] Figure 14 This is a diagram illustrating an example of the change in on-resistance. Figure 14 Curve S1 represents the change in on-resistance of the PMOS-based switch TrP. Figure 14 (The dashed line in the image) and the curve S2 showing the change in on-resistance of the NMOS-based switch TrN. Figure 14 The solid line in the figure) and the curve S3 showing the change in on-resistance of switches based on PMOS and NMOS. Figure 14 (A dashed line in the middle). Furthermore... Figure 14 This represents the on-resistance calculated without the switch VddSW being in the off state.

[0116] Figure 15 This is a diagram illustrating an example of a PMOS-based switch VddSWP. Figure 15 The switch VddSWP only has a PMOS-based switch TrP. Figure 16 This is a diagram illustrating an example of a switch VddSWN based solely on NMOS. Figure 16 The switch VddSWN only has an NMOS-based switch TrN. Figure 17 This is a diagram illustrating examples of PMOS and NMOS-based switches VddSW.

[0117] return Figure 14 In the case of only the PMOS switch TrP and the switch VddSWP (refer to...) Figure 15When the voltage of the power supply Vdd decreases, the gate-source voltage Vgs of the switch VddSWP decreases, and the on-resistance increases. Additionally, in the case of the switch VddSWN with only NMOS switch TrN (refer to...), Figure 16 The gate bias is the voltage VREG. Therefore, when the power supply voltage Vdd increases, the gate-source voltage Vgs of the switch VddSWN cannot be guaranteed, leading to an increase in on-resistance. When the power supply voltage Vdd decreases, unlike the PMOS switch TrP, the gate-source voltage Vgs increases, thus reducing the on-resistance.

[0118] In the second and third embodiments described above, a structure combining switch TrP and switch TrN is adopted (see...). Figure 17 Therefore, it is possible to suppress the increase in the on-resistance of switch VddSW throughout the entire operating range of power supply Vdd.

[0119] (Fourth Implementation)

[0120] Figure 18 This diagram illustrates the amplification section used in the power amplifier circuit of the fourth embodiment. In the fourth embodiment, a variable resistor VR is used instead of resistor R1 in the structure of the third embodiment. The output signal of comparator CMP sometimes repeatedly exhibits high-level and low-level voltages near the threshold. Thus, when high-level or low-level voltages repeatedly appear, the on and off states of switch VddSW sometimes repeatedly occur.

[0121] Therefore, in this embodiment, the output signal of the comparator CMP is made to have a hysteresis characteristic, thereby preventing the aforementioned repetition. Specifically, the output of the inverter INV is used to control the resistance value of the variable resistor VR, thus making the output signal of the comparator CMP have a hysteresis characteristic.

[0122] Figure 19 This diagram illustrates the hysteresis characteristics of the output signal of comparator CMP. When the power supply Vdd is equal to the voltage Voff, the output signal of comparator CMP transitions from a high level to a low level. Figure 19 (See arrow YD in the diagram). On the other hand, when the power supply Vdd is equal to the voltage Von, the output signal of the comparator CMP changes from low to high (…). Figure 19 (See arrow YU in the diagram). That is, the output signal of the comparator CMP is either a high-level voltage or a low-level voltage, and it causes a transition from a high level to a low level (…). Figure 19 The arrow YD in the diagram represents the transition from low to high level. Figure 19 The arrow YU in the image has hysteresis characteristics.

[0123] return Figure 18In this embodiment, a switch SWin and a matching circuit MN1 are provided between the input terminal RFin and the amplification unit 101. Additionally, a matching circuit MN2 and a switch SWout are provided between the amplification unit 101 and the output terminal RFout. Furthermore, a level conversion circuit LVS is provided to convert the level of the output signal of the inverter INV.

[0124] The level of the output signal of the inverter INV can also be converted using a level conversion circuit LVS, and the switches SWin and SWout can be controlled based on the output signal of the level conversion circuit LVS. Alternatively, the output signal of the comparator CMP can be used to turn off switches SWin and SWout when the switch TrP of switch VddSW is turned off, thereby turning off the amplifier section 101.

[0125] Figure 20 It means Figure 18 A diagram illustrating an example structure of the variable resistor VR. Figure 20 In this configuration, the variable resistor VR includes resistors R11 and R12, and FET 19. One end of resistor R11 is connected to resistor R0. The other end of resistor R11 is connected to one end of resistor R12. The other end of resistor R12 is connected to a reference potential. The drain of FET 19 is connected to one end of resistor R12. The source of FET 19 is connected to the other end of resistor R12. An inverter INV (refer to...) is applied to the gate of FET 19. Figure 18 The output signal of ).

[0126] When the output signal of inverter INV is high, FET 19 is in the ON state. Conversely, when the output signal of inverter INV is low, FET 19 is in the OFF state. Therefore, the voltage input to comparator CMP differs depending on whether the output signal of inverter INV is high or low. Therefore, as shown in the reference... Figure 19 As explained, this allows the output signal of the comparator CMP to transition from a high level to a low level. Figure 19 The arrow YD in the diagram represents the transition from low to high level. Figure 19 The arrow YU in the diagram has hysteresis characteristics. By making it hysteretic, it is possible to prevent repeated high-level voltage and low-level voltage from occurring near the threshold.

[0127] (Fifth Implementation)

[0128] Figure 21 This is a diagram showing the structure of the power amplifier circuit 100c according to the fifth embodiment. Figure 21 In the middle, the power amplifier circuit 100c and the reference Figure 3The power amplifier circuit 100c described is different from the one described above, having only one stage of amplification 101. That is, the power amplifier circuit 100c has an amplification 101 as a first-stage amplifier and a switch VccSW corresponding to the amplification 101. A voltage based on the power supply Vcc is supplied to the amplification 101 via the switch VccSW. The switch VccSW is equivalent to the switching section of this disclosure. The amplification 101 is equivalent to the first amplification section of this disclosure. It is assumed that a transistor with its emitter grounded is provided in the output section of the amplification 101 in this example. Therefore, a voltage based on the power supply Vcc is applied to the output side of the amplification 101.

[0129] The switch VccSW is controlled to be in the on state when the voltage based on the power supply Vcc is below a predetermined threshold. The switch VccSW is controlled to be in the off state when the voltage based on the power supply Vcc exceeds a predetermined threshold. The predetermined threshold is, for example, the maximum drive voltage of the amplifier 101.

[0130] With reference Figure 8 Similar to the second embodiment described, the amplification section 101 includes cascaded FETs (not shown). The number of FETs stacked is determined such that withstand voltage can be ensured under the maximum voltage applied by the power supply Vcc. That is, the number of stacks is determined such that breakdown will not occur even when the maximum voltage is applied. Moreover, as in the reference... Figure 8 The second embodiment described is similar, with the amplification unit 101 having a voltage divider resistor circuit (not shown) for generating a bias voltage applied to the gates of each FET.

[0131] Therefore, the power amplifier circuit 100c includes an amplification section 101 that amplifies the input high-frequency signal, and a switch VccSW disposed on the power supply path to the amplification section 101. Power is then supplied to the amplification section 101 via the switch VccSW, which sets the power supply to the amplification section 101 to either on or off. (Refer to reference...) Figure 8 The second embodiment described herein is similar, with the amplification unit 101 comprising: an input terminal for receiving a signal to be amplified; a first FET having a gate for receiving the signal applied to the input terminal; a second FET connected together with the first FET between a power supply and a reference potential; and an output terminal disposed between the second FET and a load for outputting the amplified signal, wherein the first FET and the second FET are cascaded. Furthermore, the relationship between the voltage values ​​and the reference... Figure 9 The relationships described are the same.

[0132] Figure 21The power amplifier circuit 100c shown operates as follows: When the switch VccSW is in the ON state, a voltage based on the power supply Vcc is supplied to the amplification unit 101. As a result, the amplification unit 101 performs amplification. The amplification unit 101 amplifies the signal input to the input terminal Tin and outputs the amplified signal from the output terminal Tout. When the switch VccSW is in the OFF state, no voltage based on the power supply Vcc is supplied to the amplification unit 101. At this time, the amplification unit 101 does not perform amplification.

[0133] In the power amplifier circuit 100c, the amplification section 101 may also be formed on a silicon chip. A silicon chip refers to a chip that uses Si, such as a chip using an SOI (Silicon-on-Insulator) substrate. When the amplification section 101 is composed of multiple transistors stacked on the silicon chip, it is possible to suppress the maximum voltage applied to the power amplifier circuit, ensuring voltage withstand capability and preventing degradation of the power amplifier circuit's characteristics.

[0134] (communication device)

[0135] Here, a communication device including a power amplifier circuit 100c will be described. Figure 22 This is a diagram illustrating a structural example of a communication device 1000a including a power amplifier circuit 100c. (Refer to reference...) Figure 4 Unlike the described communication device 1000, communication device 1000a only has one output system to the antenna. That is, communication device 1000a includes a power amplifier circuit M1a, a frequency band selection switch BS1, filters SF1 and SF2, an antenna switch AS1, an antenna ANT1, a power control unit 400, a baseband IC 500, and a switch VddSW. Switch VddSW corresponds to the switching unit of this disclosure.

[0136] The power amplifier circuit M1a is a PA (Power Amplifier) ​​module, which functions as a power amplifier circuit. The power amplifier circuit M1a includes an amplification section 101 and a control circuit 301.

[0137] The output of the amplifier section 101 is input to the frequency band selection switch BS1 as the output of the power amplifier circuit M1a. The control circuit 301 is a circuit that outputs control signals for controlling the amplifier section 101. For example, the control circuit 301 inputs a gate bias control signal SSW to the amplifier section 101. The amplifier section 101 and the control circuit 301 are implemented, for example, on an SOI substrate 801a. Regarding... Figure 22 Other structures and actions within, and references Figure 4 The communication device described is the same as 1000.

[0138] The present disclosure may take the following forms regarding the description of the claims.

[0139] <1>

[0140] A power amplifier circuit having multiple amplification stages, the power amplifier circuit comprising:

[0141] The first amplification section amplifies the input high-frequency signal;

[0142] The second amplification section amplifies the output of the first amplification section; and

[0143] A switching section is disposed on the power supply path to the first amplification section.

[0144] Power is supplied to the first amplification unit via the switching unit.

[0145] The switching unit sets the power supply to the first amplification unit to be on or off.

[0146] The power is supplied directly to the second amplification unit without passing through the switching unit.

[0147] <2>

[0148] according to <1> The power amplifier circuit, wherein,

[0149] The first amplified portion is formed on a silicon chip.

[0150] The second enlarged portion is formed on a chip other than the silicon chip.

[0151] <3>

[0152] according to <1> or <2> The power amplifier circuit, wherein,

[0153] It also includes a power supply that supplies power to the first amplification section and the second amplification section.

[0154] The switching unit includes:

[0155] A PMOS transistor, the source of which is connected to the power supply; and

[0156] An NMOS transistor, the drain of which is connected to the power supply.

[0157] The drain of the PMOS transistor is connected to the source of the NMOS transistor, and power is supplied to the first amplification section from the connection point between the drain of the PMOS transistor and the source of the NMOS transistor.

[0158] The PMOS transistor is in a cutoff state when the voltage of the power supply exceeds a predetermined threshold, and in a conduction state when the voltage of the power supply is below the predetermined threshold.

[0159] Regardless of the voltage value of the power supply, a gate bias voltage is applied to the NMOS transistor such that the source potential of the NMOS transistor is lower than a predetermined threshold when the PMOS transistor is in the off state.

[0160] <4>

[0161] according to <3> The power amplifier circuit, wherein,

[0162] It also includes a bias circuit that applies a bias voltage to the PMOS transistor.

[0163] The bias circuit applies a bias voltage to the gate of the PMOS transistor such that the PMOS transistor is in a cutoff state when the voltage of the power supply exceeds a predetermined threshold, and in a conduction state when the voltage of the power supply is below the predetermined threshold.

[0164] <5>

[0165] according to <4> The power amplifier circuit, wherein,

[0166] It also includes a comparator that compares the voltage of the power supply with a specified reference voltage.

[0167] The bias circuit applies a bias voltage to the PMOS transistor based on the comparison result of the comparator.

[0168] <6>

[0169] according to <5> The power amplifier circuit, wherein,

[0170] The comparator outputs a high-level or low-level voltage signal.

[0171] The transition from the high level to the low level and the transition from the low level to the high level are made to have hysteresis characteristics.

[0172] <7>

[0173] according to <1> to <6> The power amplifier circuit described in any one of the above, wherein,

[0174] It also includes: a choke coil connected in series between the switching section and the first amplification section; and a bypass capacitor disposed between the choke coil and the reference potential.

[0175] <8>

[0176] according to <1> to <7> The power amplifier circuit described in any one of the above, wherein,

[0177] The first enlarged part has:

[0178] The input terminal receives the signal that should be amplified.

[0179] A first FET having a gate to which a signal is applied to the input terminal;

[0180] The second FET, together with the first FET, is connected between the power supply and the reference potential;

[0181] An output terminal, located between the second FET and the load, outputs the amplified signal; and

[0182] The voltage divider resistor circuit is used to generate the bias voltage applied to the gate of the second FET.

[0183] The first FET and the second FET are cascaded together by connecting adjacent drain and source terminals.

[0184] <9>

[0185] according to <1> to <8> The power amplifier circuit described in any one of the above, wherein,

[0186] The power supply voltage varies depending on the output power of the power amplifier circuit.

[0187] <10>

[0188] A power amplifier circuit having only one amplification stage, the power amplifier circuit comprising:

[0189] The first amplification section amplifies the input high-frequency signal; and

[0190] A switching section is disposed on the power supply path to the first amplification section.

[0191] Power is supplied to the first amplification unit via the switching unit.

[0192] The switching unit sets the power supply to the first amplification unit to be on or off.

[0193] The first enlarged part has:

[0194] The input terminal receives the signal that should be amplified.

[0195] A first FET having a gate to which a signal is applied to the input terminal;

[0196] The second FET, together with the first FET, is connected between the power supply and the reference potential;

[0197] An output terminal, located between the second FET and the load, outputs the amplified signal; and

[0198] The voltage divider resistor circuit is used to generate the bias voltage applied to the gate of the second FET.

[0199] The first FET and the second FET are cascaded together by connecting adjacent drain and source terminals.

[0200] Explanation of reference numerals in the attached figures

[0201] 11~17 FET

[0202] 20V voltage divider resistor circuit

[0203] Resistors 21~26, 31~36, R0, R1, R11, R12, Rsw1, Rsw2

[0204] 41~46 Capacitors

[0205] Power amplifier circuits 100, 100a, 100b, and 100c

[0206] Enlarged sections 101, 201, and 202

[0207] 1000, 1000a communication device

[0208] ANT1 and ANT2 antennas

[0209] AS1, AS2 antenna switches

[0210] B1 Bias Circuit

[0211] BS1 and BS2 frequency band selection switches

[0212] C11 Bypass Capacitor

[0213] CMP comparator

[0214] 500 baseband IC

[0215] INV inverter

[0216] L11 Choke Coil

[0217] LVS level conversion circuit

[0218] M1, M1a power amplifier circuit

[0219] MN1 and MN2 matching circuits

[0220] PB gate bias circuit

[0221] RFin input terminal

[0222] RFout output terminal

[0223] SF1~SF5 filters

[0224] SSW1, SSW2, SW1, SW2 switches

[0225] SWA, SWb, SWc switches

[0226] VR variable resistor

Claims

1. A power amplifier circuit having a multi-stage amplification section, the power amplifier circuit comprising: The first amplification section amplifies the input high-frequency signal; The second amplification section amplifies the output of the first amplification section; as well as A switching section is disposed on the power supply path to the first amplification section. Power is supplied to the first amplification unit via the switching unit. The switching unit sets the power supply to the first amplification unit to be on or off. The power is supplied directly to the second amplification unit without passing through the switching unit.

2. The power amplifier circuit according to claim 1, wherein, The first amplified portion is formed on a silicon chip. The second enlarged portion is formed on a chip other than the silicon chip.

3. The power amplifier circuit according to claim 1 or 2, wherein, It also includes a power supply that supplies power to the first amplification section and the second amplification section. The switching unit includes: A P-type metal-oxide-semiconductor transistor, i.e., a PMOS transistor, has its source connected to the power supply; and An N-type metal-oxide-semiconductor transistor, also known as an NMOS transistor, has its drain connected to the power supply. The drain of the PMOS transistor is connected to the source of the NMOS transistor, and power is supplied to the first amplification section from the connection point between the drain of the PMOS transistor and the source of the NMOS transistor. The PMOS transistor is in a cutoff state when the voltage of the power supply exceeds a predetermined threshold, and in a conduction state when the voltage of the power supply is below the predetermined threshold. Regardless of the voltage value of the power supply, a gate bias voltage is applied to the NMOS transistor such that the source potential of the NMOS transistor is lower than a predetermined threshold when the PMOS transistor is in the off state.

4. The power amplifier circuit according to claim 3, wherein, It also includes a bias circuit that applies a bias voltage to the PMOS transistor. The bias circuit applies a bias voltage to the gate of the PMOS transistor such that the PMOS transistor is in a cutoff state when the voltage of the power supply exceeds a predetermined threshold, and in a conduction state when the voltage of the power supply is below the predetermined threshold.

5. The power amplifier circuit according to claim 4, wherein, It also includes a comparator that compares the voltage of the power supply with a specified reference voltage. The bias circuit applies a bias voltage to the PMOS transistor based on the comparison result of the comparator.

6. The power amplifier circuit according to claim 5, wherein, The comparator outputs a high-level or low-level voltage signal. The transition from the high level to the low level and the transition from the low level to the high level are made to have hysteresis characteristics.

7. The power amplifier circuit according to claim 1 or 2, wherein, It also includes: a choke coil connected in series between the switching section and the first amplification section; and a bypass capacitor disposed between the choke coil and the reference potential.

8. The power amplifier circuit according to claim 1 or 2, wherein, The first enlarged part has: The input terminal receives the signal that should be amplified. The first field-effect transistor, i.e. the first FET, has a gate to which a signal is applied to the input terminal; The second field-effect transistor, also known as the second FET, is connected together with the first FET between the power supply and the reference potential. The output terminal is located between the second FET and the load, and outputs the amplified signal. as well as The voltage divider resistor circuit is used to generate the bias voltage applied to the gate of the second FET. The first FET and the second FET are cascaded together by connecting adjacent drain and source terminals.

9. The power amplifier circuit according to claim 1 or 2, wherein, The power supply voltage varies depending on the output power of the power amplifier circuit.

10. A power amplifier circuit having only one stage of amplification, the power amplifier circuit comprising: The first amplification section amplifies the input high-frequency signal; as well as A switching section is disposed on the power supply path to the first amplification section. Power is supplied to the first amplification unit via the switching unit. The switching unit sets the power supply to the first amplification unit to be on or off. The first enlarged part has: The input terminal receives the signal that should be amplified. The first field-effect transistor, i.e. the first FET, has a gate to which a signal is applied to the input terminal; The second field-effect transistor, also known as the second FET, is connected together with the first FET between the power supply and the reference potential. An output terminal, located between the second FET and the load, outputs the amplified signal; and The voltage divider resistor circuit is used to generate the bias voltage applied to the gate of the second FET. The first FET and the second FET are cascaded together by connecting adjacent drain and source terminals.

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