Encoding method, decoding method and related apparatus

Abstract

The application provides an encoding method, a decoding method and related devices. A first construction is performed on a part of N bit positions. The first construction selects bit positions for carrying information bits twice by setting two different pre-frozen sets. On the one hand, the first construction is beneficial to balancing the reliability of bit positions and the degree of influence of rate matching, thereby improving the encoding performance and the decoding performance and improving the communication quality. On the other hand, the first construction performed on a part of N bit positions is beneficial to reducing the construction complexity.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and in particular to an encoding method, a decoding method, and related apparatus. Background Technology

[0002] Polar codes are the first coding scheme that can be rigorously proven to "achieve" Shannon channel capacity. They have the advantages of good decoding performance and low complexity. They have been selected by the 3rd Generation Partnership Project (3GPP) as the control channel coding scheme for enhanced mobile broadband (eMBB) scenarios.

[0003] In the polar code encoding process, the transmitting device selects K bit positions from N bit positions to carry an information bit sequence of length K. Based on the information bit sequence and the K bit positions, it constructs a bit sequence of length N to be encoded. Then, it encodes the bit sequence to be encoded to obtain an encoded bit sequence of length N. When the length N of the encoded bit sequence is greater than the length E of the transmitted bit sequence (called the output bit sequence), the transmitting device performs rate matching on the encoded bit sequence, that is, it punches or shortens NE bit positions (called rate-matching bit positions) to obtain an output bit sequence of length E, and then sends the output bit sequence of length E to the receiving device.

[0004] The transmitting device can determine the reliability of each of the N bit positions. For Polar codes that support rate matching, when the rate matching method is shortening or puncturing, the transmitting device pre-freezes the N and N rate-matching bit positions and selects the K bit positions with the highest reliability from the remaining E bit positions (called non-rate-matching bit positions) to carry the information bit sequence.

[0005] However, rate matching reduces the reliability of non-rate-matched bit positions. This means that the K bit positions selected based on reliability are not actually the K bit positions with high reliability after rate matching, which degrades the coding performance of Polar codes and thus reduces communication quality. Summary of the Invention

[0006] Because rate matching alters the reliability of bit positions, for clarity, the reliability without considering rate matching will be referred to as the first reliability, and the reliability with rate matching will be referred to as the second reliability. When the transmitting device pre-freezes a small number of bit positions, bit positions more affected by rate matching are more likely to be used to carry information bits, thus degrading coding performance. Conversely, when the transmitting device pre-freezes a large number of bit positions, bit positions with higher first reliability may be unusable to carry information bits, similarly degrading coding performance.

[0007] Therefore, this application provides an encoding method, a decoding method, and related apparatus. The method and related apparatus provided in this application are described below.

[0008] Firstly, this application provides an encoding method. This method can be executed by a first device. In this application, the first device can refer to a first equipment or a component within the first equipment. The first equipment can be a terminal device or a network device. The components within the first equipment can be hardware modules such as communication modules, processors, circuits, chips, or chip systems, or they can be logic modules or software capable of implementing all or part of the functions of the first equipment.

[0009] In the method provided in the first aspect, a first device acquires an information bit sequence, the information bit sequence comprising K information bits, where K is an integer greater than 1. After acquiring the information bit sequence, the first device performs polar code encoding on the information bit sequence to obtain an encoded bit sequence. The information bit sequence carries K1 bit positions out of N1 bit positions and K-K1 bit positions out of N2 bit positions, where N1 and N2 are different bit positions within the N bit positions, N1, N2, and N are positive integers, N1 and N2 are respectively less than N, and K1 is a positive integer less than K. Furthermore, K2 bit positions out of the K-K1 bit positions are determined based on reliability and a first set, and K3 bit positions out of the K-K1 bit positions (excluding K2 bit positions) are determined based on the reliability and a second set, where K2 and K3 are positive integers less than K-K1. The first set and the second set each include one or more pre-frozen bit positions from the N2 bit positions. After obtaining the encoded bit sequence, the first device outputs the output bit sequence, which is obtained based on the encoded bit sequence.

[0010] The reliability here refers to the reliability without considering rate matching or the reliability before rate matching. Therefore, this reliability can be understood as the first reliability introduced above.

[0011] By including different numbers of pre-frozen bit positions in the first and second sets—for example, the first set containing fewer pre-frozen bit positions than the second set—it is advantageous to select K2 bit positions with higher first reliability from N2 bit positions. Furthermore, from the bit positions other than K2 bit positions in the N2 bit positions, it avoids selecting bit positions that are more affected by rate matching, and instead selects K3 bit positions that are less affected by rate matching. This improves the second reliability of the K-K1 bit positions selected from the N2 bit positions, enhances coding performance, and improves communication quality.

[0012] The process of selecting K-K1 bit positions from N2 bit positions involves multiple parameters, including the number of pre-frozen bit positions in the first set, the number of pre-frozen bit positions in the second set, the values ​​of K2, and K3. Making N2 less than N reduces the complexity of optimizing these parameters, thus facilitating their configuration and further improving the second reliability of the K-K1 bit positions selected from N2 bit positions, thereby enhancing coding performance and communication quality.

[0013] Optionally, the output bit sequence is obtained by rate matching the encoded bit sequence.

[0014] Secondly, this application provides an encoding method. This method can be executed by a second device. In this application, the second device can refer to a second equipment or a component within the second equipment. The second equipment can be a terminal device or a network device. The components within the second equipment can be hardware modules such as communication modules, processors, circuits, chips, or chip systems within the second equipment, or they can be logic modules or software capable of implementing all or part of the functions of the second equipment.

[0015] In the method provided in the second aspect, a second device receives an input bit sequence and performs polar code decoding on the bit sequence to be decoded to obtain an information bit sequence. The bit sequence to be decoded is obtained based on the input bit sequence. The information bit sequence includes K information bits, where K is an integer greater than 1. The information bit sequence is carried in K1 bit positions out of N1 bit positions and K-K1 bit positions out of N2 bit positions. The N1 bit positions and the N2 bit positions are different bit positions among the N bit positions. N1, N2, and N are positive integers, and K1 is a positive integer less than K. Furthermore, the K2 bit positions out of the K-K1 bit positions are determined based on reliability and a first set. The K3 bit positions out of the K-K1 bit positions, excluding the K2 bit positions, are determined based on the reliability and a second set. K2 and K3 are positive integers less than K-K1. The first set and the second set each include one or more pre-frozen bit positions among the N2 bit positions.

[0016] The reliability here refers to the reliability without considering rate matching or the reliability before rate matching. Therefore, this reliability can be understood as the first reliability introduced above.

[0017] By including different numbers of pre-frozen bit positions in the first and second sets—for example, the first set containing fewer pre-frozen bit positions than the second set—it is advantageous to select K2 bit positions with higher first reliability from N2 bit positions. Furthermore, from the bit positions other than K2 bit positions in the N2 bit positions, it avoids selecting bit positions that are more affected by rate matching, and instead selects K3 bit positions that are less affected by rate matching. This improves the second reliability of the K-K1 bit positions selected from the N2 bit positions, enhances decoding performance, and improves communication quality.

[0018] The process of selecting K-K1 bit positions from N2 bit positions involves multiple parameters, including, for example, the number of pre-frozen bits in the first set, the number of pre-frozen bits in the second set, the values ​​of K2, and K3. Making N2 less than N reduces the complexity of optimizing these parameters, thus facilitating their configuration and further improving the second reliability of the K-K1 bit positions selected from N2 bit positions, thereby enhancing decoding performance and communication quality.

[0019] Optionally, the bit sequence to be decoded is obtained by rate matching the input bit sequence.

[0020] Based on the first or second aspect, one or more of the following implementation methods can be provided.

[0021] In a possible implementation method, the first reliability of K2 bit positions is determined based on the sorting of the K2 bit positions in the reliability sequence, and the first reliability of K3 bit positions is determined based on the sorting of the K3 bit positions in the reliability sequence. Wherein, the reliability sequence is a sequence of N bit positions arranged in a first order, and the first order is the order of the first reliability from small to large or from large to small.

[0022] In a possible implementation method, N1 and N2 are determined based on E and N, where E represents the length of the output bit sequence, N represents the length of the coded bit sequence, N is greater than E, and the output bit sequence is obtained by rate matching the coded bit sequence. Determining N1 and N2 based on E and N helps to flexibly determine the values of N1 and N2, which is beneficial to reducing N2 and lowering the construction complexity.

[0023] In a possible implementation method, when E / N is greater than a threshold, N1 + N2 = N. Based on E / N being greater than the threshold, the N bit positions have a smaller number of rate-matching bit positions. Splitting the N bit positions into two parts (i.e., N1 bit positions and N2 bit positions) is beneficial to reducing the complexity of splitting the N bit positions.

[0024] In a possible implementation method, when E / N is less than a threshold, N1 + N2 < N. Based on E / N being less than the threshold, the N bit positions have a larger number of rate-matching bit positions. Splitting the N bit positions into more than two parts (i.e., N1 bit positions, N2 bit positions, and other bit positions) is beneficial to reducing the number of rate-matching bit positions in the N2 bit positions, reducing the complexity of optimizing these multiple parameters, and thus is beneficial to optimizing the configuration of these multiple parameters, further improving the second reliability of the K - K1 bit positions selected from the N2 bit positions, improving the decoding performance, and enhancing the communication quality.

[0025] In this application, the rate-matching bit positions are the bit positions for puncturing or shortening. In the formulas of this application, " / " represents division.

[0026] In a possible implementation method, the threshold is 3 / 4, or the threshold is 7 / 8. Based on the threshold being 3 / 4, E > 3N / 4, N1 + N2 = N; or E < 3N / 4, N1 + N2 < N

[0027] In a possible implementation method, when E / N is equal to the threshold, N1 + N2 = N, or N1 + N2 < N.

[0028] In one possible implementation, the bit positions other than the N1 and N2 bit positions out of the N bit positions are rate-matching bit positions. Assuming the number of bit positions other than the N1 and N2 bit positions out of the N bit positions is N3, then N1 + N2 + N3 = N. By making all N3 bit positions rate-matching bit positions, the complexity of selecting bit positions to carry information bits from these N3 bit positions is avoided, reducing the complexity of selecting K bit positions.

[0029] In one possible implementation, N1 = N / 2, N2 = N / 2 n Where n is a positive integer, and 1 / 2 n ≥E / N-1 / 2>1 / 2 n+1 Making N1 and N2 integer powers of 2 helps reduce the complexity of selecting bit positions from N1 and N2 bit positions respectively to carry information bits.

[0030] In one possible implementation, the N1 bit positions are N1 consecutive bit positions out of the N bit positions, the N2 bit positions are N2 consecutive bit positions out of the N bit positions, and the N3 bit positions are N3 consecutive bit positions out of the N bit positions. Segmenting the consecutive bit positions is beneficial for hardware implementation and reduces construction complexity.

[0031] In one possible implementation, the N1 bit positions do not include rate-matching bit positions, and the N1 bit positions are the N1 bit positions that are farthest from the rate-matching bit positions among the N bit positions. Since bit positions farthest from the rate-matching position are less affected by rate matching, based on the first reliability, it is advantageous to select K1 bits with high actual reliability from the N1 bit positions, thereby reducing the complexity of the scheme while ensuring encoding or decoding performance.

[0032] The N1 bit positions that are farthest from the rate matching bit position among the N bit positions can be understood as the bit position farthest from the rate matching bit position (called the farthest bit position) and the N1-1 bit positions adjacent to the farthest bit position.

[0033] The rate matching method is puncturing. The punctured bit positions are the NE bit positions with smaller indices out of N bit positions, and the N1 bit positions are the N1 bit positions with larger indices out of the N bit positions. The NE bit positions with smaller indices can be understood as the bit position with the smallest index and the NE-1 bit positions adjacent to the bit position with the smallest index. The N1 bit positions with larger indices out of the N bit positions can be understood as the bit position with the largest index and the N1-1 bit positions adjacent to the bit position with the largest index.

[0034] Based on the rate matching method of shortening, the shortened bit positions are the NE bit positions with larger indices among the N bit positions, and the N1 bit positions are the N1 bit positions with smaller indices among the N bit positions. The NE bit positions with larger indices among the N bit positions can be understood as the bit position with the largest index and the NE-1 bit positions adjacent to the bit position with the largest index. The N1 bit positions with smaller indices among the N bit positions can be understood as the bit position with the smallest index and the N1-1 bit positions adjacent to the bit position with the smallest index.

[0035] In one possible implementation, the N2 bit positions are the N2 bit positions that are adjacent to the N1 bit positions among the N bit positions.

[0036] In one possible implementation, the N2 bit positions include rate-matching bit positions. Accordingly, the first set and the second set may each include rate-matching bit positions, and the first set and / or the second set may further include one or more non-rate-matching bit positions (referred to as neighboring bit positions) adjacent to the rate-matching bit positions. Alternatively, the N2 bit positions may not include rate-matching bit positions, and the N2 bit positions may be located between the rate-matching bit positions and the N1 bit positions. Accordingly, the first set and the second set may each include the neighboring bit positions adjacent to the rate-matching bit positions.

[0037] Although the N2 bit positions include rate-matching bit positions or neighboring bit positions adjacent to rate-matching bit positions, by making the first set and the second set contain different numbers of pre-frozen bit positions, for example, the first set contains fewer pre-frozen bit positions than the second set, it is advantageous to select K2 bit positions with higher first reliability and K3 bit positions less affected by rate matching. This is advantageous to select K-K1 bit positions with high actual reliability from the N2 bit positions to carry information bits, thereby improving coding performance and decoding performance, and enhancing communication quality.

[0038] In this application, N1 bit positions can be understood as the first set of bit positions, N2 bit positions as the second set of bit positions, and N3 bit positions as the third set of bit positions. The first, second, and third set of bit positions each include a subset of the N bit positions. For any two sets of the first, second, or third set of bit positions, these two sets are disjoint, or in other words, they do not contain the same bit positions.

[0039] In this application, K1 bit positions can be understood as a first set of information bit positions, K2 bit positions as a second set of information bit positions, and K3 bit positions as a third set of information bit positions. The first set of information bit positions includes the K1 bit positions used to carry K1 information bits, the second set of information bit positions includes the K2 bit positions used to carry K2 information bits, and the third set of information bit positions includes the K3 bit positions used to carry K3 information bits. Furthermore, the second and third sets of information bit positions are disjoint, or in other words, they do not contain the same bit positions. For any two different sets of the first, second, or third set of information bit positions, these two sets are used to carry different information bits.

[0040] Each of the N bit positions can have its own index (called a bit position index), and different bit positions generally have different bit position indices. Therefore, the process of determining the N1, N2, and N3 bit positions from the N bit positions can be understood as the process of determining the N1, N2, and N3 bit position indices from the N bit position indices. Correspondingly, the first set of bit positions, the second set of bit positions, and the third set of bit positions can be understood as the N1, N2, and N3 bit position indices, respectively.

[0041] This application does not limit the specific method by which the first device or the second device determines the K-K1 bit positions from the second set of bit positions (i.e., the N2 bit positions). The following example illustrates how the first device determines the K-K1 bit positions from the N2 bit positions. The method by which the second device determines the K-K1 bit positions from the N2 bit positions can be understood by referring to the method performed by the first device.

[0042] In one possible implementation, a first device determines a second set of information bit positions based on a first set and a first reliability sequence of the polar code. The first set indicates the frozen (or pre-frozen) bit positions in the first reliability sequence when determining the second set of information bit positions. The first reliability sequence indicates the order of reliability (or reliability degree) of the second set of bit positions (i.e., N2 bit positions) in the polar code. The second set of information bit positions indicates K2 bit positions, where K2 carries K2 information bits out of the K-K1 information bits, and K2 is a positive integer. The first device then determines a third set of information bit positions based on a second set and the first reliability sequence. The second set indicates the frozen (or pre-frozen) bit positions in the first reliability sequence when determining the third set of information bit positions. The third set of information bit positions indicates K3 bit positions, where K3 carry K3 information bits out of the K-K1 information bits, excluding the K2 information bits, where K2 + K3 = K - K1.

[0043] The first set is also called the first frozen bit position set or the first pre-frozen bit position set. The second set is also called the second frozen bit position set or the second pre-frozen bit position set.

[0044] The K-K1 bits in the information bit sequence can be all payload bits, or they can contain both payload bits and check bits.

[0045] The above scheme selects information bits in two stages: K2 information bits are selected in the first stage and K3 information bits are selected in the second stage. This method helps to accurately select the bits with the highest reliability as information bits, which can improve encoding and decoding performance (such as error correction performance) and thus help improve communication performance.

[0046] In one possible implementation, the first set is used to indicate punched or shortened bits.

[0047] In one possible implementation, the first set is the same as the rate-matching position set, which is used to indicate punctured or shortened bits.

[0048] In one possible implementation, K2 is related to K, for example, in, This indicates rounding up, where F is a positive number less than 1. Optionally, F can be a predefined or pre-configured value. Optionally, F is greater than 1 / 2 and less than 1. Or, optionally, F is greater than 3 / 4 and less than 1. Optionally, F = 15 / 16.

[0049] In one possible implementation, K2 is associated with one or more of K-K1, E-N1, R, or N2; where R represents the bit rate and R = K / E.

[0050] The above scheme allows for flexible configuration of the size of K2, which helps to select reliable bits as information bits, thereby improving encoding and decoding performance, and ultimately enhancing communication performance.

[0051] In one possible implementation, K2 increases as K-K1 increases. The larger the total number of information bits to be selected, K-K1, the larger the size of the second information bit position set, K2, which helps in selecting reliable bits as the second information bit position set.

[0052] The above scheme allows for flexible configuration of the size of K2, which helps to select reliable bits as information bits, thereby improving encoding and decoding performance, and ultimately enhancing communication performance.

[0053] In one possible implementation, K2 increases as R increases. The larger R is, the larger the total number of information bits to be selected, K-K1. The larger the total number of information bits to be selected, K-K1, the larger the size of the second information bit position set, K2, which helps to select reliable bits as the second information bit position set.

[0054] The above scheme allows for flexible configuration of the size of K2, which helps to select reliable bits as information bits, thereby improving encoding and decoding performance, and ultimately enhancing communication performance.

[0055] In one possible implementation, when (E-N1) / N2 is greater than or equal to Z0, K2 increases as (E-N1) / N2 increases; when (E-N1) / N2 is less than Z0 but greater than or equal to Z1, K2 does not change with the change of (E-N1) / N2; when (E-N1) / N2 is less than Z1, K2 decreases as (E-N1) / N2 increases; wherein Z0 and Z1 are both greater than 0 and less than 1, and Z0 is greater than Z1.

[0056] The above scheme allows for flexible configuration of the size of K2, which helps to select reliable bits as information bits, thereby improving encoding and decoding performance, and ultimately enhancing communication performance.

[0057] In one possible implementation, when 9 / 16 <= (E-N1) / N2, When 17 / 32<=(E-N1) / N2<9 / 16, When (E-N1) / N2<17 / 32, in, This indicates rounding up to the nearest integer.

[0058] In one possible implementation, the bit rate R is less than or equal to 7 / 8.

[0059] In one possible implementation, the first set includes a rate-matching position set, and the number of bits in the first set is greater than the number of bits in the rate-matching position set, which is used to indicate punched or shortened bits.

[0060] In one possible implementation, the first set is a proper subset of the second set.

[0061] In one possible implementation, K2 is associated with one or more of K-K1, E-N1, or N2.

[0062] The above scheme allows for flexible configuration of the size of K2, which helps to select reliable bits as information bits, thereby improving encoding and decoding performance, and ultimately enhancing communication performance.

[0063] In one possible implementation, K2 increases as (E-N1) / N2 increases.

[0064] The above scheme allows for flexible configuration of the size of K2, which helps to select reliable bits as information bits, thereby improving encoding and decoding performance, and ultimately enhancing communication performance.

[0065] In one possible implementation, when 3 / 4 <= (E-N1) / N2, When 5 / 8<=(E-N1) / N2<3 / 4, When (E-N1) / N2<5 / 8, in, This indicates rounding up to the nearest integer.

[0066] In one possible implementation, the bits in the first set are a series of consecutive bits in a natural order bit sequence, which consists of N2 consecutive bits sorted from smallest to largest.

[0067] In one possible implementation, the second set of information bit positions has no intersection with the third set of information bit positions, and the reliability of the bits in the third set of information bit positions is lower than the reliability of the bits in the second set of information bit positions.

[0068] In one possible implementation, the index of each bit in the third information bit position set is greater than or equal to N² / 2.

[0069] In one possible implementation, the bits in the second set are a series of consecutive bits in a natural order bit sequence, which consists of N2 consecutive bits sorted from smallest to largest.

[0070] In one possible implementation, the second set consists of the first N² / 2 bits of the natural order bit sequence.

[0071] In one possible implementation, the number of bits in the first set increases as N2 increases and decreases as E-N1 increases.

[0072] In one possible implementation, the K2 bits are the K2 bits with the highest reliability in the second reliability sequence, and the second reliability sequence is composed of bits from the first reliability sequence excluding the first set.

[0073] In one possible implementation, the K3 bits are the K3 bits with the highest reliability in the third reliability sequence, excluding the second information bit position set, and the third reliability sequence is composed of the bits in the first reliability sequence excluding the second set.

[0074] The first set and the second set are consecutive bits in a natural order bit sequence, which facilitates hardware implementation and reduces construction complexity.

[0075] Thirdly, this application provides a communication device comprising a plurality of functional modules. The plurality of functional modules interact to implement the method described in the first aspect or any possible implementation thereof. Accordingly, the communication device may be the first device mentioned in the first aspect.

[0076] In one possible implementation, multiple functional modules include a processing unit and a transceiver unit. The transceiver unit performs sending and / or receiving operations, while the processing unit performs internal processing operations, which can be operations other than sending and receiving. For example, the processing unit acquires the information bit sequence, performs polar code encoding on the information bit sequence to obtain an encoded bit sequence, and the transceiver unit outputs an output bit sequence derived from the encoded bit sequence.

[0077] Fourthly, this application provides a communication device comprising a plurality of functional modules. The plurality of functional modules interact to implement the method described in the second aspect or any possible implementation thereof. Accordingly, the communication device may be the second device mentioned in the second aspect.

[0078] In one possible implementation, multiple functional modules include a processing unit and a transceiver unit. The transceiver unit performs transmitting and / or receiving operations, while the processing unit performs internal processing operations, which can be operations other than transmitting and receiving. For example, the transceiver unit receives an input bit sequence, and the processing unit performs polar code decoding on the bit sequence to be decoded to obtain an information bit sequence, wherein the bit sequence to be decoded is obtained based on the input bit sequence.

[0079] Fifthly, this application provides a communication device comprising at least one processor, the at least one processor being configured to execute a computer program stored in a memory to implement the method as described in the first aspect and any implementation thereof, or the processor being configured to execute the computer program stored in the memory to implement the method as described in the second aspect and any implementation thereof.

[0080] Optionally, the communication device further includes the memory. The at least one processor is coupled to the memory.

[0081] Sixthly, this application provides a chip or chip system including at least one processor for supporting a communication device in implementing the method described in the first aspect or any implementation thereof, or in implementing the method described in the second aspect or any implementation thereof. For example, the chip may be a baseband chip, a modem chip, a SoC chip (such as an SoC chip containing a modem core), a SIP chip, or a communication module, etc.

[0082] In one possible design, the chip or chip system may further include a memory for storing program instructions and data necessary for the communication device. The chip system may be composed of chips or may include chips and other discrete devices. Optionally, the chip system may also include interface circuitry that provides program instructions and / or data to the at least one processor.

[0083] In a seventh aspect, this application provides a communication device including at least one logic circuit and an input / output interface, wherein the logic circuit is used to implement the method described in the first aspect or any implementation thereof, or to implement the method described in the second aspect or any implementation thereof.

[0084] Eighthly, this application provides a computer-readable storage medium having a computer program or instructions stored thereon, which, when executed by a processor, cause the method described in the first aspect or any implementation thereof to be performed, or the method described in the second aspect or any implementation thereof to be performed.

[0085] Ninthly, this application provides a computer program product containing instructions that, when run on a computer, cause the method described in the first aspect or any implementation thereof to be executed, or the method described in the second aspect or any implementation thereof to be executed.

[0086] In a tenth aspect, this application provides a communication system comprising a first device and a second device. The first device is used to perform the method of the first aspect or any possible implementation thereof, and the second device is used to perform the method of the second aspect or any possible implementation thereof. Alternatively, the first device may be a communication device provided in the third aspect, and the second device may be a communication device provided in the fourth aspect.

[0087] The technical effects of any of the design methods in aspects three through ten can be found in the technical effects of the corresponding design methods in aspects one through two above, and will not be repeated here. Attached Figure Description

[0088] Figure 1a An 8×8 polarization transformation matrix is ​​shown;

[0089] Figure 1b This schematically illustrates the process of constructing polar codes in NR;

[0090] Figure 1c A schematic diagram of SC decoding;

[0091] Figure 2 The architecture of the communication system used in this application is illustrated schematically;

[0092] Figure 3 This schematically illustrates the communication process between the first device and the second device;

[0093] Figure 4 A flowchart illustrating the method provided in this application;

[0094] Figure 5 An example is shown to illustrate one implementation of S402;

[0095] Figure 6 An example is shown of one implementation of S406;

[0096] Figure 7 This schematically illustrates one specific implementation of the first device executing S501;

[0097] Figure 8a This illustration schematically shows the structure of a communication device provided in this application;

[0098] Figure 8b This illustration schematically shows the structure of another communication device provided in this application;

[0099] Figure 9 A simplified structural diagram of a terminal device is shown;

[0100] Figure 10 A simplified schematic diagram of a network device is shown. Detailed Implementation

[0101] To facilitate understanding by those skilled in the art, some terms used in the embodiments of this application are explained below.

[0102] 1) Polar codes

[0103] Polar codes are the first coding scheme that can be rigorously proven to "achieve" Shannon channel capacity. They have the advantages of good decoding performance and low complexity, and have been selected by 3GPP as the control channel coding scheme for the eMBB scenario.

[0104] 2) Polar code encoding

[0105] Polar codes are a type of linear block code, where the polarization transformation matrix is ​​G. N The polarization transformation matrix can also be denoted as G, and it can also be called the encoding matrix or the generator matrix. The encoding process is as follows: in It is a binary row vector, that is, a binary sequence of length N, where N is the code length of the polar code; G N It is an N×N matrix, and It can be defined as the Kronecker product of log2(N) matrices F2.

[0106]

[0107] During the encoding process of polar codes, A portion of the bits are used to carry information; these information-carrying bits are called information bits, and the set of information bit indices is denoted as A. The remaining bits are set to fixed values ​​agreed upon beforehand by the receiver and transmitter; this set is called the fixed bit set or frozen bit set, and its bit position index is represented by the complement of A, A' ... C This indicates that the encoding process of polar codes is equivalent to: Here, G N (A) is G N G is a submatrix obtained by considering the rows corresponding to the bit position indices in set A. N (A C ) is G N In the set A C The submatrix obtained by the rows corresponding to the bit position indices in μ. A for The set of information bits in the data is K in number; for The set of frozen bits in the code, numbered (NK), is a known set of bits. These frozen bits are usually set to 0, but can be arbitrarily set as long as the receiver and transmitter agree beforehand. The encoded output of the polar code can be simplified to: Here μ A for The set of information bits in μ A Let G be a row vector of length K, i.e., |A| = K, where |A| represents the number of elements in set A, K is the block size, or K is the number of information bits, or K is the size of the set of information bits. N (A) is matrix G N G is a submatrix obtained by considering the rows corresponding to the bit position indices in set A. N (A) is a K×N matrix.

[0108] Figure 1a An 8×8 polarization transformation matrix is ​​shown. Figure 1aThis example illustrates a specific encoding process, where the left side can be understood as the side to be encoded, with bit positions denoted by u, and the right side can be understood as the encoding side (or codeword side), with bit positions denoted by x. The process from left to right represents the encoding of the bit sequence by the transmitting end. The information bits to be encoded are represented by the sequence u (0, 0, 0, 0, 0, 0, 1, 1). After polarization transformation, the encoded bits are represented by the sequence x (0, 1, 0, 1, 0, 1, 0, 1). Mapping x to modulation symbols allows transmission through channel W. Bit positions corresponding to high channel reliability are used to map information bits, while bit positions corresponding to low channel reliability are used to map frozen bits. For example... Figure 1a As shown, {u0, u1, u2, u4} are the positions of the frozen bits, and {u3, u5, u6, u7} are the positions of the information bits.

[0109] See Figure 1a In the encoding process, two adjacent columns constitute a coding layer. The left column of bits represents the input bits of the coding layer, and the right column represents the output bits. For example, in the leftmost coding layer, the input bit sequence is (0, 0, 0, 0, 0, 0, 1, 1), and the output bit sequence is (0, 0, 0, 0, 0, 0, 0, 1). The operation symbols in the middle of the coding layer... This represents the XOR operation, specifically... express The bits in the current row and A single XOR operation between the bits in the row. The bits on the right represent the result of the operation. For example, in the leftmost coding layer, the first input bit (value 0) and the second input bit (value 0) are processed... The operation yields the first output bit (with a value of 0).

[0110] 3) Polar code construction

[0111] The process of constructing polar codes is the process of selecting set A, and it determines the performance of polar codes.

[0112] The construction process of polar codes typically involves determining N polarization channels based on the code length N, each corresponding to one of the N rows of the polarization transformation matrix. The channel reliability of each polarization channel is then determined. The bit position indices of the top K polarization channels with the highest reliability are used as elements of set A. The bit position indices of the remaining (NK) polarization channels are used as the bit position index set A for the frozen bits. C The elements. Set A determines the position of the information bits, set A. C This determines the position of the frozen bits.

[0113] Bit positions with higher reliability are designated as information bit positions (data), while bit positions with lower reliability are designated as frozen bit positions. In 5G NR, the frozen and information bit positions of the polar code are determined based on the reliability sequence. Taking an 8-bit polar code as an example, assuming the reliability sequence is [0 1 2 4 3 5 6 7], the reliability of the bit positions from highest to lowest is: bit position 7, bit position 6, bit position 5, bit position 3, bit position 4, bit position 2, bit position 1, and bit position 0. When constructing a polar code with an 8-bit code length and an information length of 4 bits, bit positions 7, 6, 5, and 3 are selected from the end to the beginning as information bit positions; that is, {u7, u6, u5, u3} are set as information bit positions, and {u4, u2, u1, u0} are set as frozen bit positions.

[0114] As can be seen from the encoding process of polar codes, the code length of a polar code is an integer power of 2. However, in actual communication, the code length needs to be flexibly configured according to the available resources. When the length (N) of the encoded bit sequence differs from the length (E) of the transmitted bit sequence, a rate matching method is needed to achieve flexible and variable code length.

[0115] For polar codes that support rate matching, when the rate matching method is shortening or puncturing, NE rate matching bit positions are pre-frozen, and the information bit positions are determined from the other bit positions before encoding and transmission. This application refers to the pre-frozen bit positions as pre-frozen bit positions. Figure 1b The diagram illustrates the process of constructing polar codes in NR. Figure 1b In this context, the additional pre-frozen set includes other pre-frozen bit positions besides the punched bit positions.

[0116] 4) Polar code decoding

[0117] In one possible implementation, Polar codes are decoded using a successive cancellation decoding (SC) algorithm. In SC, the log likelihood ratio (LLR) sequence of the information bits is calculated sequentially. For an information bit, if LLR > 0, the bit is set to 0; if LLR < 0, the bit is set to 1. For frozen bits, the bit is set to 0 regardless of the LLR value. A simple illustration of SC decoding is shown below. Figure 1c As shown. Figure 1cThere are a total of 8 computation nodes, including 4 f nodes and 4 g nodes. The computation of an f node requires two LLR inputs to its right, and the computation of a g node requires two LLR inputs to its right and one "partial sum" input above it. Note that the output can only be calculated after the inputs have been calculated. Based on the above rules, starting from the received signal on the right, the 8 nodes are calculated sequentially, resulting in the decoding sequence ①→②→③→④, which is the SC decoding process.

[0118] The technical solution provided in this application can be applied to any of a variety of communication systems. For example, these various communication systems may include: Long Term Evolution (LTE) systems, satellite communications, 5th Generation (5G) mobile communication systems (such as New Radio (NR) systems), and the three major application scenarios of 5G mobile communication systems. These three application scenarios include enhanced mobile broadband (eMBB), ultra-reliable and low-latency communication (URLLC), and eMTC. The technical solution provided in this application can also be applied to future communication systems. Specifically, it can be applied to Bluetooth communication systems, wireless local area network (WLAN) communication systems, wireless fidelity (WiFi) communication systems, or narrowband internet of things (NB-IoT) communication systems.

[0119] Figure 2 The architecture of the communication system used in this application is illustrated schematically. Figure 2 As shown, the communication system includes network equipment, terminal equipment A, and terminal equipment B. Figure 2 Taking a communication system that includes three devices as an example, the communication system may optionally include more or fewer devices. Figure 2 Taking the example that any two devices in a communication system can communicate with each other, optionally, some devices in the communication system cannot communicate directly with each other.

[0120] In this application, the terminal equipment may be user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device.

[0121] Terminal devices can be devices that provide voice / data connectivity to users, such as handheld devices with wireless connectivity, in-vehicle devices, and mobile devices mounted on vehicles. Examples of terminal devices currently include: smartphones, mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability UE (REDCAP UE), Internet of Things (IoT) devices, wireless terminals in industrial control, wireless terminals in autonomous driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, and wireless local loops. The embodiments of this application do not limit the scope to terminal devices such as loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, wearable devices, terminal devices in 5G networks, or terminal devices in future evolved public land mobile networks (PLMNs). In vehicle-to-everything (V2X) communication, a communication terminal mounted on a vehicle is a type of terminal device, and a roadside unit (RSU) can also be considered a terminal device. Terminal devices can also be vehicle-mounted devices, such as vehicle-mounted devices, vehicle-mounted modules, vehicle-mounted chips, on-board units (OBUs), or telematics boxes (T-BOXs). Drones carrying communication terminals can also be considered a type of terminal device.A terminal can also be other devices with terminal functions. For example, a terminal can also be a device that plays a terminal function in device-to-device (D2D) communication.

[0122] The wearable devices mentioned earlier, also known as wearable smart devices or smart wearable devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not just hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific application function and require the use of other devices such as smartphones, such as various smart bracelets, smart helmets, and smart jewelry for vital sign monitoring.

[0123] In this application, a network device is a device deployed in a wireless access network to provide wireless communication functions for terminal devices. A network device may also be referred to as an access network (AN) device, a radio access network (RAN) device, an access node, a network node, or a communication device, etc.

[0124] Specifically, the network equipment can be access network equipment for cellular systems related to the 3rd Generation Partnership Project (3GPP). For example, 3GPP-related cellular systems include fourth-generation (4G) mobile communication systems, 5G mobile communication systems, or future mobile communication systems. The network equipment can also be access network equipment in open RAN (O-RAN or ORAN) or cloud radio access network (CRAN). Alternatively, the network equipment can also be access network equipment in a communication system resulting from the integration of two or more of the above communication systems.

[0125] For example, network devices can be evolved Node B (eNB), radio network controller (RNC), Node B (NB), base station controller (BSC), base transceiver station (BTS), home base station (e.g., home-evolved Node B, or home Node B, HNB), baseband unit (BBU), access point (AP) in a wireless fidelity (WIFI) system, macro base station, micro base station, wireless relay node, donor node, wireless controller in a CRAN scenario, wireless backhaul node, transmission point (TP), or transmission reception point (TRP).

[0126] For example, network equipment can also be access network equipment in a 5G mobile communication system, such as a next-generation NodeB (gNB) in a new radio (NR) system, a transmit receiver point (TRP), a TP, or one or a group of antenna panels (including multiple antenna panels) of a base station in a 5G mobile communication system.

[0127] A base station includes a baseband unit (BBU) and a remote radio unit (RRU). The BBU and RRU can be located in different places; for example, the RRU can be deployed remotely to a high-traffic area, while the BBU is located in the central equipment room. Alternatively, the BBU and RRU can be located in the same equipment room. They can also be different components within the same rack. Network equipment can also be either a BBU or an RRU.

[0128] For example, network devices can also be network nodes that constitute a gNB or transmission point, such as a centralized unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU).

[0129] CU and DU can be separate entities or included in the same network element, such as BBU. RU can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs). Alternatively, network equipment can also be servers, wearable devices, vehicles, or in-vehicle equipment. For example, in V2X technology, network equipment can be roadside units (RSUs).

[0130] It should be noted that CU (or CU-CP and CU-UP), DU, or RU may have different names in different systems, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called an open centralized unit (O-CU) or an open CU, DU can also be called an open distributed unit (O-DU), centralized unit control plane (CU-CP) can also be called an open centralized unit control plane (O-CU-CP) or an open CU-CP, centralized unit user plane (CU-UP) can also be called an open centralized unit user plane (O-CU-UP) or an open CU-UP, and RU can also be called an open radio unit (O-RU). This application does not impose any specific limitations. Any of the units CU, CU-CP, CU-UP, DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0131] More specifically, the technical solution provided in this application can be applied to the communication process between a first device and a second device in a communication system. This application does not limit the types of the first and second devices. For example, the first device and the second device may be a network device and a terminal device, respectively; or, respectively, a terminal device and a network device; or, both may be network devices; or, both may be terminal devices. The first device may have the function of sending information; therefore, the first device can also be called a transmitting device. The second device may have the function of receiving information; therefore, the second device can also be called a receiving device. Optionally, the first device may also have the function of receiving information, and the second device may also have the function of sending information.

[0132] To ensure the quality of communication between the first device and the second device, the first device and the second device can perform encoding and decoding processing on the information. Figure 3 This schematically illustrates the communication process between the first and second devices. For example... Figure 3 As shown, the first device can obtain the information generated by the source, and after performing source coding, channel coding and modulation on the information in sequence, output the modulation symbol. After receiving the modulation symbol, the second device performs demodulation, channel decoding and source recovery on the modulation symbol in sequence, and sends the recovered information to the sink, where the sink processes the information.

[0133] Channel coding and channel decoding play a crucial role in the reliability of information transmission. For polar codes that support rate matching, when the rate matching method is shortening or puncturing, the first device pre-freezes the NE rate-matched bit positions and determines the K most reliable bit positions from the remaining E bit positions (called non-rate-matched bit positions) as the information bit positions.

[0134] However, when the first device pre-freezes a small number of bit positions, it is easy for bit positions that are more affected by rate matching to be used to carry information bits, thereby degrading the coding performance; when the first device pre-freezes a large number of bit positions, it is easy for bit positions with higher first reliability to be unable to be used to carry information bits, thereby degrading the coding performance.

[0135] To address this, this application provides an encoding method that, for a polar code supporting rate matching, performs block construction on the polar code and performs a first construction on a subset of N bit positions. Specifically, it selects bit positions from this subset of bit positions using two different pre-frozen sets to carry information bits. On one hand, the first construction facilitates the selection of bit positions with higher first reliability and bit positions less affected by rate matching, thereby using bit positions with higher second reliability to carry information bits, improving encoding and decoding performance, and enhancing communication quality. On the other hand, performing the first construction on a subset of N bit positions helps reduce the complexity of the first construction.

[0136] In the methods described below, the first device can be a first device or a component of the first device, and the second device can be a second device or a component of the second device. In this application, the components in the device are hardware modules such as communication modules, processors, circuits, chips, or chip systems in the device, or they can be logic modules or software that can realize all or part of the functions of the first device.

[0137] Figure 4 A flowchart illustrating the method provided in this application. Figure 4 The communication methods shown include S401 to S406.

[0138] S401, The first device acquires the information bit sequence;

[0139] Information bit sequences are information in binary form. This information can be information generated by a source (called source information). Or, as... Figure 3 As shown, this information can be the information obtained by source encoding of source information (referred to as source encoded information). Optionally, the information bit sequence can be the payload information bit sequence, or the information bit sequence can be a bit sequence containing payload information bits and cyclic redundancy check (CRC) bits.

[0140] Optionally, S401 can be understood as the first device generating source information. Alternatively, S401 can be understood as the first device generating source information, performing source encoding on the source information to obtain an information bit sequence. Alternatively, S401 can be understood as the first device receiving source information, performing source encoding on the source information to obtain an information bit sequence.

[0141] S402. The first device performs polar code encoding on the information bit sequence to obtain the encoded bit sequence;

[0142] After obtaining the encoded bit sequence, the first device can obtain the output bit sequence based on the encoded bit sequence. For example, the first device can perform rate matching on the encoded bit sequence to obtain the output bit sequence. Here, the encoded bit sequence can be understood as the encoded bit sequence described above, and the output bit sequence can be understood as the transmitted bit sequence described above.

[0143] The information bit sequence is carried in K1 bit positions out of N1 bit positions and K-K1 bit positions out of N2 bit positions. N1 bit positions and N2 bit positions are different bit positions among N bit positions. N1, N2 and N are positive integers, and K1 is a positive integer less than K. Furthermore, K2 bit positions out of K-K1 bit positions are determined based on reliability and a first set. K3 bit positions out of K-K1 bit positions other than K2 bit positions are determined based on reliability and a second set. K2 and K3 are positive integers less than K-K1. The first set and the second set each include one or more pre-frozen bit positions among the N2 bit positions.

[0144] In one possible implementation, the first device can encode the information bit sequence using polar codes based on the information bit position set A. Assuming the polar code encoding length is N (where N is an integer power of 2), the length of the output bit sequence is E (where E is a positive integer less than N), and the length of the information bit sequence to be encoded is K, meaning the information bit sequence includes K bits, where K is an integer greater than 1 and K is less than E, then the information bit position set A includes K bit positions out of N bit positions. For ease of description, this application refers to the bit positions in the information bit position set A as information bit positions.

[0145] The set of information bit positions A includes a first set of information bit positions A1, a second set of information bit positions A2, and a third set of information bit positions A3. Any two sets in A1, A2, and A3 are disjoint. Assume that A1, A2, and A3 each contain K1, K2, and K3 information bit positions, respectively, where K1, K2, and K3 are positive integers less than K, and K1 + K2 + K3 = K. The first set of information bit positions A1 can also be referred to as containing K1 bit positions. Since K2 + K3 = K - K1, the second information bit position set A2 and the third information bit position set A3 include K - K1 bit positions. The second information bit position set A2 and the third information bit position set A3 can also be called K - K1 bit positions. The second information bit position set A2 can also be called K2 bit positions out of the K - K1 bit positions. The third information bit position set A3 can also be called K3 bit positions out of the K - K1 bit positions excluding these K2 bit positions.

[0146] N bit positions can be divided into M sets of bit positions, where M is a positive integer greater than or equal to 2. The M sets of bit positions include a first set of bit positions and a second set of bit positions. Assume the first set of bit positions contains N1 bit positions, and the second set contains N2 bit positions, where N1 and N2 are positive integers less than N, and N1 + N2 is less than or equal to N. The first set of bit positions can also be called the N1 bit positions, and the second set of bit positions can also be called the N2 bit positions. Any two sets of bit positions in the M sets of bit positions are disjoint. Therefore, the N1 bit positions and the N2 bit positions are distinct bit positions within the N bit positions.

[0147] The first set of information bit positions A1 belongs to the first set of bit positions, which can be understood as the above K1 bit positions being the bit positions among the above N1 bit positions. The second set of information bit positions A2 and the third set of information bit positions A3 each belong to the second set of bit positions, which can be understood as the above K-K1 bit positions being the bit positions among the above N2 bit positions.

[0148] For example, the second set of information bit positions A2 is determined based on reliability and the first set, and the third set of information bit positions A3 is determined based on reliability and the second set. The first set and the second set each include one or more pre-frozen bit positions from the second set of bit positions (i.e., the aforementioned N2 bit positions). Hereinafter, the first set will be referred to as the first pre-frozen set B1, and the second set will be referred to as the second pre-frozen set B2.

[0149] S403. The first device modulates the output bit sequence to obtain a modulation symbol;

[0150] After obtaining the output bit sequence, the first device can modulate the output bit sequence to obtain the modulation symbol.

[0151] The modulation symbols are in a form suitable for wireless transmission; for example, the modulation symbols are analog signals. This application does not limit the modulation technique used by the modulation module. For example, the modulation technique used by the modulation module can be quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), or 64QAM, etc.

[0152] S404. The first device transmits modulation symbols, and correspondingly, the second device receives modulation symbols.

[0153] After the first device receives the modulation symbol, it can transmit the modulation symbol. Correspondingly, the second device can receive the modulation symbol.

[0154] For example, the first device can transmit the modulation symbol via an antenna, the modulation symbol is transmitted through a wireless channel, and the second device can receive the modulation symbol via an antenna.

[0155] S405, The second device demodulates the modulation symbols to obtain the input bit sequence;

[0156] After receiving the modulation symbol, the second device can demodulate the modulation symbol to obtain the input bit sequence. This input bit sequence can be an LLR sequence.

[0157] Since the modulation symbols may change in the channel (e.g., noise or fading), the input bit sequence obtained by the second device demodulation may differ from the output bit sequence before modulation by the first device. The input bit sequence can be understood as the output bit sequence containing noise.

[0158] S406. The second device performs polar code decoding on the bit sequence to be decoded to obtain the information bit sequence.

[0159] After obtaining the input bit sequence, the second device can obtain the bit sequence to be decoded based on the input bit sequence, and perform polar code decoding on the bit sequence to be decoded based on the information bit position set A to obtain the information bit sequence. Optionally, the second device can send the obtained information bit sequence to the destination.

[0160] For successful decoding, the polar code decoding method used by the second device for the bit sequence to be decoded must correspond to the polar code encoding method used by the first device for the information bit sequence, that is, S402 and S405 correspond to each other.

[0161] The polar code decoding method used by the second device for the input bit sequence must correspond to the polar code encoding method used by the first device for the information bit sequence. This includes the following: the set A of information bit positions selected by the second device during polar code decoding is the same as the set A of information bit positions selected by the first device during polar code encoding. The conditions satisfied by the set A of information bit positions can be found in the relevant content in S402, and will not be repeated here.

[0162] By including different numbers of pre-frozen bit positions in the first pre-frozen set B1 and the second pre-frozen set B2—for example, the first pre-frozen set B1 containing fewer pre-frozen bit positions than the second pre-frozen set B2—it is advantageous to select K2 bit positions with higher first reliability from the second bit position set as the second information bit position set. Furthermore, during the selection of the third information bit position set from bit positions other than those in the second bit position set, bit positions highly affected by rate matching are avoided; instead, K3 bit positions less affected by rate matching are selected. This improves the second reliability of the information bit positions selected from the second bit position set, enhances coding and decoding performance, and improves communication quality.

[0163] For ease of description, the method of selecting the second and third information bit position sets from the second bit position set is called the first construction method. The first construction method involves multiple parameters, such as the number of pre-frozen bit positions in the first pre-frozen set B1, the number of pre-frozen bit positions in the second pre-frozen set B2, the values ​​of K2 and K3, etc. Using the first construction method on a subset of the N bit positions helps reduce the complexity of optimizing these multiple parameters, thereby facilitating the optimization of their configuration, further improving the second reliability of the information bit positions selected from the second bit position set, improving coding and decoding performance, and enhancing communication quality.

[0164] This application does not limit the specific implementation of S402. Figure 5 An example is shown of one implementation of S402. For example... Figure 5 S402 may include S501 to S504.

[0165] S501, The first device determines the information bit location set A;

[0166] As described above, the information bit position set A indicates the K information bit positions out of N bit positions used to carry an information bit sequence of length K. Optionally, the information bit position set A includes indices of the K information bit positions. In this application, the index can also be called a sequence number. Hereinafter, we will take the indices of the 1st bit position, the 2nd bit position, ..., the Nth bit position as examples, where the indices are 0, 1, ..., N-1 respectively.

[0167] S502, The first device obtains the bit sequence to be encoded based on the information bit position set A and the information bit sequence;

[0168] After determining the information bit position set A, the first device can obtain a bit sequence of length N to be encoded based on the information bit position set A and the information bit sequence. The bit sequence to be encoded can be understood as described above. The set of K information bit positions A in the bit sequence to be encoded indicates K information bits in the bit sequence. The other bit positions in the bit sequence to be encoded, excluding the K information bit positions, carry a first fixed value. This first fixed value can be a value predefined or pre-configured between the first and second devices. Generally, the first fixed value can be 0. During decoding, the second device decodes the other bit positions (excluding the K information bit positions) to the pre-configured first fixed value, such as 0.

[0169] S503. The first device encodes the bit sequence to be encoded to obtain the encoded bit sequence;

[0170] The first device can encode the bit sequence to be encoded based on the polar code's encoding matrix, obtaining an encoded bit sequence of length N. The encoding matrix can be understood as G, as described earlier. N The encoded bit sequence can be understood as described above.

[0171] S504. The first device performs rate matching on the encoded bit sequence to obtain the output bit sequence.

[0172] Based on the fact that the length N of the encoded bit sequence is greater than the length E of the output bit sequence, the first device performs rate matching on the encoded bit sequence. This application does not limit the rate matching method used by the first device.

[0173] In one possible implementation, the rate matching method used by the first device is puncturing. Accordingly, the first device can puncture (or punch) NE bit positions in the encoded bit sequence instead of transmitting them. The bit positions used for puncturing can be called punctured bit positions. The NE punctured bit positions are generally the NE bit positions with smaller indices among the N bit positions; for example, the indices of the NE punctured bit positions include 0, 1, ..., NE-1.

[0174] In one possible implementation, the first device employs a shortening rate matching method. Accordingly, the first device can carry a second fixed value at NE bit positions in the coded bit sequence, and does not transmit these NE bit positions. The bit positions used to carry the second fixed value can be called shortened bit positions. The NE shortened bit positions are generally the NE bit positions with the largest indices among the N bit positions; for example, the indices of the NE shortened bit positions include E+1, E+2, ..., N-1.

[0175] In this application, the second fixed value can be a predefined or preconfigured value; optionally, the second fixed value is 0. In this application, the punctured bit position and the shortened bit position can be collectively referred to as the rate-matching bit position.

[0176] In one possible implementation, rate matching is achieved using a circular buffer.

[0177] This application does not limit the specific implementation of S406. Figure 6 An example is shown of one implementation of S406. For example... Figure 6 S406 may include S601 to S604.

[0178] S601, The second device performs rate matching on the input bit sequence to obtain the bit sequence to be decoded;

[0179] The second device performs rate matching on the input bit sequence of length E to obtain the bit sequence to be decoded of length N.

[0180] The polar code decoding method used by the second device for the input bit sequence and the polar code encoding method used by the first device for the information bit sequence need to correspond to each other. This may include the de-rate matching method used by the second device for the input bit sequence and the rate matching method used by the first device for the encoded bit sequence corresponding to each other.

[0181] Assuming the first device uses puncturing as the rate matching method for the encoded bit sequence, the second device can set the LLR of the NE punctured bit positions in the bit sequence to be decoded to 0. For example, the LLR of the NE bit positions with indices 0, 1, ..., and NE-1 in the bit sequence to be decoded is set to 0, and the other E bit positions in the bit sequence to be decoded carry an input bit sequence of length E.

[0182] Assuming the first device uses a shortening rate matching method for the encoded bit sequence, the second device can set the LLR of the NE shortened bit positions in the bit sequence to be decoded to infinity. For example, the LLR of the NE bit positions with indices E+1, E+2, ..., N-1 in the bit sequence to be decoded is set to infinity, and the other E bit positions in the bit sequence to be decoded carry an input bit sequence of length E.

[0183] S602, The second device decodes the bit sequence to be decoded to obtain the decoded bit sequence;

[0184] The second device can decode a bit sequence of length N to be decoded, and obtain a decoded bit sequence of length N.

[0185] S603, The second device determines the information bit location set A;

[0186] The information bit position set A indicates the K information bit positions out of N bit positions used to carry an information bit sequence of length K.

[0187] S604. The second device obtains the information bit sequence based on the information bit position set A and the decoded bit sequence.

[0188] The second device can obtain an information bit sequence of length K based on the information bit position set A and the decoding bit sequence of length N.

[0189] Figure 6 Taking the execution of S603 after S602 as an example, optionally, S603 can be executed before S602 or S601, as long as S603 is executed before S604.

[0190] To ensure that the set of information bit positions A selected by the second device during polar code decoding is the same as the set of information bit positions A selected by the first device during polar code encoding, the specific implementation of S501 by the first device and the specific implementation of S603 by the second device can be the same. Figure 7 This schematically illustrates one specific implementation of the first device performing S501. Optionally, Figure 7 The process shown is a specific implementation of the second device executing S603.

[0191] like Figure 7 As shown, S501 may include S701 to S705.

[0192] S701, The first device determines N;

[0193] The first device can determine N, where N is an integer power of 2 greater than or equal to E. Assume E = 252 and N = 256.

[0194] S702. The first device determines the rate matching method and the positions of NE rate matching bits based on K and E.

[0195] This application does not limit the method by which the first device determines the rate matching mode. In one possible implementation, the rate matching mode is determined based on the bit rate. For example, when K / E <= 7 / 16, the punched bit rate matching mode is selected; conversely, when K / E > 7 / 16, the shortened bit rate matching mode is selected.

[0196] The NE rate-matching bit positions can be referred to as the rate-matching bit position set Q. This application does not limit the method by which the first device determines the rate-matching bit position set Q. In one implementation, when puncturing is selected, the first device uses the first NE bit positions (i.e., the NE bit positions with smaller indices) as the rate-matching bit position set Q. When shortening is selected, the first device uses the last NE positions (i.e., the NE bit positions with larger indices) as the rate-matching bit position set Q.

[0197] S703. The first device divides the N bit positions into M bit position sets according to the N, E and NE rate matching bit positions, wherein the M bit position sets include the first bit position set and the second bit position set.

[0198] The set of M bit positions can be understood by referring to the relevant content above. For example, any two sets of M bit positions are disjoint. For instance, the set of M bit positions includes a first set of bit positions and a second set of bit positions. The first set of bit positions contains N1 bit positions, and the second set of bit positions contains N2 bit positions.

[0199] Optionally, based on the premise that N1+N2 is less than N, the set of M bit positions can also include a third set of bit positions, which includes N3 bit positions. All bit positions in the third set are rate-matching bit positions, where N1+N2+N3=N.

[0200] The N1 bit positions in the first bit position set and the N2 bit positions in the second bit position set can be understood by referring to the previously introduced N1 bit positions and N2 bit positions, respectively. For example, the first bit position set and the second bit position set satisfy one or more of the first or second conditions. The first condition includes: N1 = N / 2, N2 = N / 2 n Where n is a positive integer, and 1 / 2 n ≥E / N-1 / 2>1 / 2 n+1 The second condition includes: the N1 bit positions do not include the rate matching bit positions, and the N1 bit positions are the N1 bit positions that are farthest from the rate matching bit positions among the N bit positions; the N2 bit positions are the N2 bit positions that are adjacent to the N1 bit positions among the N bit positions.

[0201] Based on the fact that the first and second bit position sets satisfy the second condition, the N1 bit positions in the output bit sequence (referred to as the first sub-output bit sequence) correspond to the N1 bit positions in the first bit position set, and the other E-N1 bit positions in the output bit sequence (referred to as the second sub-output bit sequence) correspond to the E-N1 bit positions in the second bit position set. In this application, the length of the first sub-output bit sequence is denoted as E1, and the length of the second sub-output bit sequence is denoted as E2. Therefore, E1 = N1, and E2 = E-N1. Assuming the length of the third sub-output bit sequence corresponding to the third bit position set in the output bit sequence is denoted as E3, since all bit positions in the third bit position set are rate-matching bit positions, E3 = 0. The length of the third sub-output bit sequence is 0, therefore, there is no need to select information bits in the third bit position set, reducing construction complexity.

[0202] The following example illustrates a specific instance of S703, using the first bit position set and the second bit position set satisfying the first and second conditions.

[0203] In the first example of S703, assuming N = 64, E = 60, the rate matching method is puncturing, and the indices of the NE rate matching bit positions include 0, 1, 2, and 3, then n = 1, N1 = N / 2 = 32, N2 = N / 2 = 32, the indices of the N1 bit positions in the first bit position set include 32, 33, ..., and 63, and the indices of the N2 bit positions in the second bit position set include 0, 1, ..., and 31. E1 = 32, E2 = E - N1 = 28.

[0204] In the second example of S703, assuming N = 64, E = 44, the rate matching method is puncturing, and the indices of the NE rate matching bit positions include 0, 1, ..., and 19, then n = 2, N1 = N / 2 = 32, N2 = N / 2 = 16, N3 = 64 - 32 - 16 = 16. The indices of the N1 bit positions in the first bit position set include 32, 33, ..., and 63; the indices of the N2 bit positions in the second bit position set include 16, 17, ..., and 31; and the indices of the N3 bit positions in the third bit position set include 0, 1, ..., 15. E1 = 32, E2 = E - N1 = 12, E3 = 0.

[0205] In the third example of S703, assuming N = 64, E = 60, the rate matching method is shortened, and the indices of the NE rate-matched bit positions include 60, 61, 62, and 63, then n = 1, N1 = N / 2 = 32, N2 = N / 2 = 32, the indices of the N1 bit positions in the first bit position set include 0, 1, ..., and 31, and the indices of the N2 bit positions in the second bit position set include 32, 33, ..., and 63. E1 = 32, E2 = E - N1 = 28.

[0206] In the fourth example of S703, assuming N = 64, E = 44, the rate matching method is shortened, and the indices of the NE rate-matched bit positions include 44, 45, ..., and 63, then n = 2, N1 = N / 2 = 32, N2 = N / 2 = 16, N3 = 64 - 32 - 16 = 16. The indices of the N1 bit positions in the first bit position set include 0, 1, ..., and 31; the indices of the N2 bit positions in the second bit position set include 32, 33, ..., and 47; and the indices of the N3 bit positions in the third bit position set include 48, 49, ..., and 63. E1 = 32, E2 = E - N1 = 12, E3 = 0.

[0207] S704. The first device determines the first information bit position set A1 from the first bit position set;

[0208] S705, the first device determines a second information bit position set A2 from the second bit position set based on the first pre-frozen set B1 and the reliability, and determines a third information bit position set A3 from the second bit position set based on the second pre-frozen set B2 and the reliability.

[0209] After the first device divides N bit positions into M bit position sets, it determines the first information bit position set A1 from the first bit position set of the M bit position sets, and determines the second information bit position set A2 and the third information bit position set A3 from the second bit position set of the M bit position sets, thereby determining the information bit position set A, which is the union of the first information bit position set A1, the second information bit position set A2, and the third information bit position set A3.

[0210] The number of information bit positions selected by the first device from each of the M bit position sets can be predefined or preconfigured. For example, the first device selects J1 information bit positions from the first bit position set (i.e., the first information bit position set A1) and J2 bit positions from the second bit position set (i.e., the second information bit position set A2 and the third information bit position set A3), where J1 can be understood as K1 as described above, and J2 can be understood as K2+K3. Optionally, if the M bit position sets also include a third bit position set, the first device selects J3 bit positions from the third bit position set. Since all bit positions in the third bit position set are rate-matching bit positions, J3 = 0, and J1+J2 = K.

[0211] The allocation of J1 and J2 is related to the number of rate-matched bit positions (i.e., NE), used to make the selected set of information bit positions A more reliable. Generally, as the number of punched bit positions or shortened bit positions increases, J2 / J1 decreases.

[0212] Continuing with the first example in S703, N=64, E=60, assume K=26, and optionally, J1=21, J2=5.

[0213] Continuing with the second example in S703, N=64, E=44, assume K=18, and optionally, J1=17, J2=1, J3=0.

[0214] Continuing with the third example in S703, N=64, E=60, assume K=30, and optionally, J1=9, J2=21.

[0215] Continuing with the fourth example in S703, N=64, E=44, assume K=22, and optionally, J1=14, J2=8, J3=0.

[0216] pass Figure 7The polar code construction method shown in this application breaks down the problem of constructing polar codes for N bit positions into the problem of constructing polar codes for M bit position sets respectively. This is beneficial for the first device to select information bit positions in different bit position sets using different construction methods.

[0217] For example, S705 can be understood as the first device selecting an information bit position from the second bit position set using a first construction method. In S704, the first device can select an information bit position from the first bit position set using methods other than the first construction method.

[0218] This application does not limit the method used by the first device to construct the bit position set. For any bit position set (denoted as bit position set i) among M bit position sets, it is assumed that bit position set i includes Ni bit positions, and the length of the sub-output bit sequence corresponding to bit position set i is Ei, and the number of information bit positions corresponding to bit position set i is ki. In one possible implementation, based on Ei equal to 0 or Ei equal to Ni, the first device selects information bit positions from bit position set i using a method other than the first construction method. Conversely, based on Ei not equal to 0 and Ei not equal to Ni, the first device selects information bit positions from bit position set i using the first construction method. Wherein, based on Ei equal to 0, bit position set i can be understood as corresponding to the third bit position set. Based on Ei equal to Ni, bit position set i can be understood as corresponding to the first bit position set.

[0219] Below, an example is given illustrating how the first device determines the positions of ki information bits in the bit position set i using methods other than the first construction method. Here, the bit position set i can be understood as the first bit position set introduced earlier, and correspondingly, i can be understood as 1.

[0220] The first device can determine J1 bit positions with high reliability from the bit position set 1 as J1 information bit positions, where J1 can be understood as K1 as described above. This reliability can be understood as the first reliability described above. The first device can determine the reliability of each bit position in the bit position set 1 based on the reliability sequence. The set of indices of these J1 information bit positions can be denoted as...

[0221] The following example illustrates the method flow for the first device to determine the positions of ki information bits in the bit position set i using the first construction method. Here, the bit position set i can be understood as the second bit position set introduced earlier, and correspondingly, i can be understood as 2. The method flow can be divided into steps 1 to 4.

[0222] Step 1: The first device determines the first pre-frozen set B1;

[0223] In one possible implementation, based on the rate matching method of puncturing, the first pre-frozen set B1 includes the X bit positions with smaller indices from the bit position set 2. Optionally, X = 3N. i / 4-E i / 2.

[0224] In one possible implementation, based on the rate matching method being shortened, the first pre-frozen set B1 includes the X bit positions with larger indices from the bit position set 2. Optionally, X = N. i -E i .

[0225] Step 2: The first device determines T information bit positions in the bit position set 2 based on the first pre-frozen set B1 and the reliability.

[0226] The first device determines the remaining bit positions in the bit position set 2, excluding the first pre-frozen set B1 (denoted as bit position set C1), and selects T bit positions (i.e., T information bit positions) with higher reliability from bit position set C1. For example, the first device can determine a sequence of position indices in bit position set C1 arranged in ascending order of reliability (called reliability sequence S1), and select T bit positions (i.e., T information bit positions) with higher reliability from bit position set C1 based on reliability sequence S1. For instance, the first device extracts T indices from the reliability sequence S1 from back to front; the T bit positions corresponding to these T indices are the T information bit positions. The indices of the T information bit positions can be denoted as...

[0227] This application does not limit the method of determining T. Optionally, the first device determines T based on E2 and N2. For example, in, This represents rounding down. This simplifies the calculation formula for T and is beneficial for hardware implementation.

[0228] Step 3: The first device determines the second pre-frozen set B2;

[0229] Based on the rate matching method of puncturing or shortening, the second pre-frozen set B2 includes the Y bit positions with smaller indices from the bit position set 2. Optionally, Y = N² / 2.

[0230] Step 4: The first device determines J2-T information bit positions in the bit position set 2 based on the second pre-frozen set B2 and the reliability.

[0231] The first device determines the remaining bit positions in the bit position set 2, excluding the second pre-frozen set B2 (denoted as bit position set C2), and selects J2-T bit positions (i.e., J2-T information bit positions) with higher reliability from the bit position set C2. For example, the first device can determine a sequence of position indices in the bit position set C2 arranged in ascending order of reliability (called a reliability sequence S2), and select J2-T bit positions with higher reliability from the bit position set C2 based on the reliability sequence S2. For instance, the first device extracts J2-T indices from the reliability sequence S2 from back to front; the J2-T bit positions corresponding to these J2-T indices are the J2-T information bit positions. The indices of the J2-T information bit positions can be denoted as...

[0232] The first device determines the set of indices of the information bit positions from the bit position set 2. for and The union of the indices of the information bit positions determined by the first device from bit position set 1 and bit position set 2. for and The union of .

[0233] The following example illustrates the process by which the first device determines J1 information bit positions and J2 information bit positions from bit position set 1 and bit position set 2, respectively.

[0234] Continuing with the first example of S703, where N=64, E=60, the rate matching method is puncturing, N1=N2=32, J1=21, J2=5, E1=32, E2=28. The first device can determine that the indices of the bit positions in bit position set 1 include 32, 33, ..., and 63, and further determine that the sequence of the 32 bit position indices corresponding to bit position set 1 arranged in ascending order of reliability (called reliability sequence 1) is [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63]. The first device can select 21 information bit positions from bit position set 1, and the set of indices of these 21 information bit positions... Among them, reliability sequence 1 can be obtained based on the Q sequence in the NR standard.

[0235] The first device can also determine that the indices of the bit positions in the bit position set 2 include 0, 1, ..., and 31, X = 10, and further determine that the indices of the bit positions in the first pre-frozen set B1 include 0, 1, ..., 9, and the reliability sequence S1 is [16 17 10 18 12 20 24 11 19 13 14 21 26 25 22 28 15 23 27 29 30 31]. The first device can also determine T = 4, and further determine...

[0236] The first device can also determine that Y = 16, the bit positions in the first pre-frozen set B1 include 0, 1, ..., 15, and the reliability sequence S2 is [16 17 18 20 24 19 21 26 25 22 28 23 27 29 30 31]. The first device can also determine that J2-T = 5-4 = 1, and thus determine...

[0237]

[0238] Accordingly, the first device determines the set of indices of the K information bit positions from bit position set 1 and bit position set 2. for and The union of, i.e.:

[0239]

[0240] Continuing with the second example of S703, where N=64, E=44, the rate matching method is puncturing, N1=32, N2=16, N3=16, J1=17, J2=1, J3=0, E1=32, E2=12, E3=0. The first device can determine that the indices of the bit positions in bit position set 1 include 32, 33, ..., and 63, and thus determine that the reliability sequence 1 corresponding to bit position set 1 is [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63]. Assuming J1=17, the first device selects the set of indices of 17 information bit positions from bit position set 1.

[0241] The first device can also determine that the indices of the bit positions in the bit position set 2 include 16, 17, ..., and 31, X = 6, and further determine that the indices of the bit positions in the first pre-frozen set B1 include 16, 17, ..., 21, and the reliability sequence S1 is [24 26 25 22 28 23 27 29 30 31]. The first device can also determine T = 1, and further determine...

[0242] The first device can also determine Y = 8, and the indices of the bit positions in the first pre-frozen set B1 include 16, 17, ..., 23. The first device can also determine J2-T = 1-1 = 0, and thus determine... It is an empty set.

[0243] Therefore, the first device determines the set of indices of the K information bit positions from bit position set 1 and bit position set 2. for and The union of, i.e.

[0244] Continuing with the third example of S703, where N=64, E=60, the rate matching method is shortened, N1=N2=32, E1=32, E2=28, J1=9, J2=21. The first device can determine that the indices of the bit positions in the bit position set 1 include 0, 1, ..., and 31, and thus determine that the reliability sequence 1 corresponding to the bit position set 1 is [0 1 2 4 8 16 3 5 9 6 17 10 18 12 20 24 7 11 19 13 14 21 26 25 22 28 15 23 27 29 30 31]. The first device selects the set of indices of the 9 information bit positions from the bit position set 1.

[0245] The first device can also determine that the indices of the bit positions in the bit position set 2 include 32, 33, ..., and 63, X = 4, and further determine that the indices of the bit positions in the first pre-frozen set B1 include 60, 61, 62, 63, and the reliability sequence S1 is [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 47 55 59]. The first device can also determine T = 21, and further determine...

[0246]

[0247] The first device can determine that Y = 16, and the indices of the bit positions in the first pre-frozen set B1 include 48, 49, ..., 63. The first device can also determine that J2-T = 21-21 = 0, and thus determine... It is an empty set.

[0248] Therefore, the first device determines the set of indices of the K information bit positions from bit position set 1 and bit position set 2. for and The union of, i.e.:

[0249]

[0250] Continuing with the fourth example of S703, where N=64, E=44, the rate matching method is shortened, N1=32, N2=16, N3=16, E1=32, E2=12, E3=0, J1=14, J2=8, J3=0. The first device can determine that the indices of the bit positions in the bit position set 1 include 0, 1, ..., and 31, and thus determine that the reliability sequence 1 corresponding to the bit position set 1 is [0 1 2 4 8 16 3 5 9 6 17 10 18 12 20 24 711 19 13 14 21 26 25 22 28 15 23 27 29 30 31]. Assuming J1=14, the first device selects the set of indices of 14 information bit positions from the bit position set 1.

[0251] The first device can also determine that the indices of the bit positions in the bit position set 2 include 32, 33, ..., and 47, X = 4, and further determine that the indices of the bit positions in the first pre-frozen set B1 include 44, 45, 46, and 47, and the reliability sequence S1 is [32 33 34 36 40 35 37 38 41 42 39 43]. The first device can also determine T = 8, and further determine...

[0252] The first device can determine that Y = 8, and the indices of the bit positions in the first pre-frozen set B1 include 40, 41, ..., 47. The first device can determine that J2 - T = 8 - 8 = 0, and thus determine... It is an empty set.

[0253] Accordingly, the first device determines the set of indices of the K information bit positions from bit position set 1 and bit position set 2. for and The union of, i.e.:

[0254]

[0255] Optionally, the first device can perform Figure 4 The method comprises all or part of the method steps performed by the first device.

[0256] In one possible implementation, the first device executes S401 and S402, but does not execute S403 or the steps executed by the first device in S404. Assuming the first device is a component of a first device, which also includes a transmitting device other than the first device, the transmitting device executes S403 and the steps executed by the first device in S404. Accordingly, the first device outputting the bit sequence can be understood as the first device outputting the bit sequence to the transmitting device.

[0257] In one possible implementation, the first device executes steps S401, S402, and S403, but does not execute the steps in S404 performed by the first device. Assuming that the transmitting device in the first device is used to execute the steps in S404 performed by the first device, the output bit sequence of the first device can be understood as the first device modulating the output bit sequence and then outputting the modulated symbols to the transmitting device.

[0258] In one possible implementation, the first device executes steps S401 to S403, and also executes the steps performed by the first device in S404. Accordingly, the output bit sequence of the first device can be understood as the first device modulating the output bit sequence and then sending the modulation symbols to the second device, for example, by sending the modulation symbols to the second device through an antenna.

[0259] Optionally, the second device can perform Figure 4 The second device performs all or part of the method steps in the method.

[0260] In one possible implementation, the second device executes the steps in S404, and then executes S405 to S406. Accordingly, the second device receiving the input bit sequence can be understood as the second device receiving modulation symbols from the first device, for example, receiving modulation symbols transmitted by the first device via an antenna, demodulating the modulation symbols, and obtaining the input bit sequence.

[0261] In one possible implementation, the second device executes S406, but does not execute the method steps performed by the second device in S404, and does not execute S405. Assuming the second device is a component of a second device, and the second device also includes a receiving device other than the second device, the receiving device is used to execute the steps performed by the second device in S404 and S404 itself. Accordingly, the second device receiving the input bit sequence can be understood as the second device receiving the input bit sequence from the receiving device of the second device.

[0262] In one possible implementation, the second device executes S406 and S405, but does not execute the method steps performed by the second device in S404. Assuming that the receiving device of the second device is used to execute the method steps performed by the second device in S404, the receiving of the input bit sequence by the second device can be understood as the second device receiving modulation symbols from the receiving device of the second device, demodulating the modulation symbols, and obtaining the input bit sequence.

[0263] During the execution of S402 by the first device, specific actions can be performed. Figure 5 The method flow is shown. During the execution of S406 by the second device, the specific execution can be as follows: Figure 6 The method flow is described.

[0264] The first device executes Figure 5 The process shown in S501 can be specifically executed. Figure 7 The method flow is shown. The second device executes... Figure 6 The process shown in S603 can be specifically executed. Figure 7 The method flow is described.

[0265] This application also provides a communication device. Figure 8a The structure of the communication device is illustrated schematically. For example... Figure 8a As shown, the communication device 8a includes a processing unit 81a and a transceiver unit 82a. The transceiver unit 82a performs transmission and / or reception operations, while the processing unit 81a performs other internal operations besides transmission and reception operations.

[0266] Optional, Figure 8a The communication device 8a shown can be the communication device provided in the third aspect above or the first device described above. Optionally, Figure 8a The communication device 8a shown is used to perform Figure 4 The method shown involves the first device performing all or part of the method steps, or performing... Figure 5 The methods and steps shown, or the execution Figure 7 The steps are shown.

[0267] Optional, Figure 8a The communication device 8a shown can be the communication device provided in the fourth aspect above or the second device described above. Optionally, Figure 8a The communication device 8a shown is used to perform Figure 4 The second device in the method shown performs all or part of the method steps, or performs... Figure 6 The methods and steps shown, or the execution Figure 7 The steps are shown.

[0268] Optional, Figure 8aThe communication device 8a shown also includes a storage unit 83a, which is used to store the program code and data of the communication device.

[0269] In this application, the processing unit can be a processor. The processor can execute computer execution instructions stored in the storage unit, causing the chip to perform... Figure 4 The method shown involves the first device performing all or part of the method steps, or performing... Figure 4 The second device in the method shown performs all or part of the method steps, or performs... Figure 5 The methods and steps shown, or the execution Figure 7 The steps are shown.

[0270] This storage unit can be a memory, and the transceiver unit can be implemented by a transceiver or transceiver-related circuitry. The transceiver unit can also be called a communication module or communication interface. For example, the function of the transceiver unit can be implemented by interface circuitry or data transceiver circuitry on a processor.

[0271] The preceding text also describes a communication apparatus provided in the fifth aspect of this application. This communication apparatus includes at least one processor, which executes a computer program stored in a memory, causing the processor to perform... Figure 4 The method shown involves the first device performing all or part of the method steps, or performing... Figure 4 The second device in the method shown performs all or part of the method steps, or performs... Figure 5 The methods and steps shown, or the execution Figure 7 The steps are shown.

[0272] The preceding text also describes the chip (or chip device or chip system) provided in the sixth aspect of this application, which includes a processor for calling a computer program or computer instructions stored in memory to cause the processor to execute... Figure 4 The method shown involves the first device performing all or part of the method steps, or performing... Figure 4 The second device in the method shown performs all or part of the method steps, or performs... Figure 5 The methods and steps shown, or the execution Figure 7 The method steps are shown. Optionally, the processor is coupled to the memory via an interface.

[0273] In this application, any processor or chip mentioned herein may be a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or one or more integrated circuits for controlling the execution of a program that controls the methods provided in any of the foregoing embodiments. The processor may be single-core or multi-core. For example, the processor may include a modem chip, or a SoC chip or SIP chip containing modem cores.

[0274] The memory mentioned above can be memory within the processor, such as registers or cache. Memory can also be memory located outside the main memory, such as read-only memory (ROM) or other types of static storage devices that can store static information and instructions, such as random access memory (RAM).

[0275] The preceding text also describes a communication device provided in the seventh aspect of this application, which includes at least one logic circuit and an input / output interface, wherein the input / output interface can be an interface circuit. Figure 8b The structure of the communication device is illustrated schematically. For example... Figure 8b As shown, the communication device 8b includes a logic circuit 81b and an interface circuit 82b. The logic circuit 81b is used to implement... Figure 4 The method shown involves the first device performing all or part of the method steps, or performing... Figure 4 The second device in the method shown performs all or part of the method steps, or performs... Figure 5 The methods and steps shown, or the execution Figure 7 The method steps are shown. The interface circuit 82b is used to output the information processed by the logic circuit 81b, or to input the information to be processed into the logic circuit 81b for processing. For example, the interface circuit 82b is used to output a bit sequence or to receive an input bit sequence, as detailed in the previous description.

[0276] like Figure 8b As shown, in one possible design, the communication device 8b may further include a memory 83b for storing necessary computer programs. Optionally, the logic circuit 81b implements the above functions by executing the computer program in the memory 83b. Optionally, the interface circuit 82 implements the above functions by executing the computer program in the memory 83b.

[0277] In one possible implementation, the communication device 8b is a chip or chip system.

[0278] The preceding text also describes a computer-readable storage medium provided in the eighth aspect of this application, the storage medium including computer instructions that, when executed on a computer, cause the computer to perform... Figure 4 The method shown involves the first device performing all or part of the method steps, or performing... Figure 4 The second device in the method shown performs all or part of the method steps, or performs... Figure 5 The methods and steps shown, or the execution Figure 7 The steps are shown.

[0279] The preceding text also described the computer program product including computer instructions provided in the ninth aspect of this application, which, when run on a computer, causes the computer to perform actions such as... Figure 4 The method shown involves the first device performing all or part of the method steps, or performing... Figure 4 The second device in the method shown performs all or part of the method steps, or performs... Figure 5 The methods and steps shown, or the execution Figure 7 The steps are shown.

[0280] The preceding text also describes a communication system provided in aspect ten of this application, which includes the first and second devices described above, or includes the first and second equipment described above. For example, the communication system is as follows: Figure 2 As shown.

[0281] In this application, when the communication device is a terminal device, Figure 9 A simplified structural diagram of a terminal device is shown. (For example...) Figure 9 As shown, the terminal device includes a processor, a memory, and a transceiver. The memory can store computer program code, and the transceiver includes a transmitter 931, a receiver 932, radio frequency circuitry (not shown in the figure), an antenna 933, and input / output devices (not shown in the figure).

[0282] The processor is primarily used for processing communication protocols and data; controlling terminal devices; executing software programs; and processing data from those programs. The memory is primarily used for storing software programs and data. The radio frequency (RF) circuitry is primarily used for converting baseband signals to RF signals and processing RF signals. The antenna is primarily used for transmitting and receiving RF signals in the form of electromagnetic waves. Input / output devices may include touchscreens, displays, or keyboards. These devices are primarily used for receiving user input and outputting data to the user. It should be noted that some types of terminal devices may not have input / output devices.

[0283] When data needs to be transmitted, the processor performs baseband processing on the data to be transmitted and outputs a baseband signal to the radio frequency (RF) circuit. The RF circuit then processes the baseband signal and transmits it outwards as electromagnetic waves via an antenna. When data is sent to the terminal device, the RF circuit receives the RF signal through the antenna. The RF circuit converts the RF signal back into a baseband signal and outputs it to the processor. The processor converts the baseband signal back into data and processes that data. For ease of explanation, Figure 9 Only one memory, processor, and transceiver are shown in the illustration. In actual terminal devices, there may be one or more processors and one or more memories. Memory may also be referred to as storage medium or storage device, etc. Memory may be set up independently of the processor or integrated with the processor; this application does not limit this.

[0284] In the embodiments of this application, the antenna and radio frequency circuit with transceiver function can be regarded as the transceiver unit of the terminal device, and the processor with processing function can be regarded as the processing unit of the terminal device.

[0285] like Figure 9 As shown, the terminal device includes a processor 910, a memory 920, and a transceiver 930. The processor 910 can also be referred to as a processing unit, processing board, processing unit, or processing device, etc. The transceiver 930 can also be referred to as a transceiver unit, transceiver, or transceiver device, etc.

[0286] Optionally, the devices in transceiver 930 used to implement the receiving and / or transmitting functions can be considered as transceiver units. A transceiver may also be referred to as a transceiver module, transceiver circuit, etc.

[0287] Processor 910 is used to execute the processing operations performed by the first or second device in the above examples. Transceiver 930 is used to execute the transmit and receive operations performed by the first or second device in the above method examples. It should be understood that... Figure 9 This is merely an example and not a limitation; the terminal device described above, which includes a transceiver unit and a processing unit, may not rely on... Figure 9 The structure shown.

[0288] When the communication device 900 is a chip, the chip includes a processor, a memory, and a transceiver. The transceiver can be an input / output circuit or a communication interface. The processor can be a processing unit integrated on the chip, a microprocessor, or an integrated circuit. In the above method embodiments, the transmitting operation of the first or second device can be understood as the chip's output, and the receiving operation of the first or second device in the above method embodiments can be understood as the chip's input.

[0289] In this application, when the communication device is a network device, for example, a base station, Figure 10A simplified schematic diagram of a base station structure is shown. The base station includes sections 1010, 1020, and 1030.

[0290] The 1010 section is mainly used for baseband processing and controlling the base station; the 1010 section is usually the control center of the base station, which can be called the processor, and is used to control the base station to perform the processing operations of the communication device in the above method embodiment.

[0291] Section 1020 is primarily used to store computer program code and data.

[0292] Section 1030 is primarily used for transmitting and receiving radio frequency (RF) signals, as well as converting RF signals to baseband signals. Section 1030 is commonly referred to as a transceiver unit, transceiver module, transceiver, transceiver circuit, or transceiver. The transceiver module of section 1030, also known as a transceiver, includes antenna 1033 and RF circuitry (not shown in the figure), where the RF circuitry is mainly used for RF processing. Optionally, the device in section 1030 that performs the receiving function can be considered a receiver, and the device that performs the transmitting function can be considered a transmitter; that is, section 1030 includes receiver 1032 and transmitter 1031. The receiver can also be called a receiving unit, receiver circuit, or receiving unit, and the transmitter can be called a transmitting module, transmitter, or transmitting circuit.

[0293] Sections 1010 and 1020 may include one or more single boards, each of which may include one or more processors and one or more memories. The processors are used to read and execute programs in the memories to implement baseband processing functions and control the base station. If multiple single boards exist, they can be interconnected to enhance processing capabilities. As an optional implementation, multiple single boards may share one or more processors, or multiple single boards may share one or more memories, or multiple single boards may simultaneously share one or more processors.

[0294] For example, in one implementation, the transceiver module in section 1030 is used for the transceiver actions performed by the first or second device in the above method example. The processor in section 1010 is used to perform actions other than the transceiver actions performed by the first or second device in the above method example (i.e., to process related actions).

[0295] It should be understood that Figure 10 This is for illustrative purposes only and not as a limitation. The network devices mentioned above, including processors, memory, and transceivers, may be independent of... Figure 10 The structure shown.

[0296] When the communication device 1000 is a chip, the chip includes a transceiver, a memory, and a processor. The transceiver can be an input / output circuit or a communication interface; the processor can be a processor integrated on the chip, a microprocessor, or an integrated circuit. In the above method embodiments, the transmitting operation of the first or second device can be understood as the chip's output, and the receiving operation of the first or second device in the above method embodiments can be understood as the chip's input.

[0297] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the explanations and beneficial effects of the relevant contents in any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, and will not be repeated here.

[0298] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0299] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0300] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0301] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the essential contribution of the technical solution of this application, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0302] In this application, unless otherwise specified, the same or similar parts between the various embodiments can be referred to each other. In the various embodiments of this application, and the various methods / designs / implementations within each embodiment, unless otherwise specified or logically conflicting, the terminology and / or descriptions between different embodiments and between the various methods / designs / implementations within each embodiment are consistent and can be mutually referenced. The technical features in different embodiments and the various methods / designs / implementations within each embodiment can be combined to form new embodiments, methods, or implementations based on their inherent logical relationships. The following descriptions of the embodiments of this application do not constitute a limitation on the scope of protection of this application.

[0303] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An encoding method, characterized in that, include: Obtain an information bit sequence, wherein the information bit sequence comprises K information bits, where K is an integer greater than 1; The information bit sequence is polar-coded to obtain an encoded bit sequence, wherein the information bit sequence carries K1 bit positions out of N1 bit positions and K-K1 bit positions out of N2 bit positions. The N1 bit positions and the N2 bit positions are different bit positions among the N bit positions, N1, N2 and N are positive integers, K1 is a positive integer less than K, and the K2 bit positions out of the K-K1 bit positions are determined based on reliability and a first set. The K3 bit positions out of the K-K1 bit positions other than the K2 bit positions are determined based on the reliability and a second set, where K2 and K3 are positive integers less than K-K1. The first set and the second set each include one or more pre-frozen bit positions among the N2 bit positions. Output a bit sequence, which is obtained based on the encoded bit sequence.

2. A decoding method, characterized in that, include: Receive the input bit sequence; Polar code decoding is performed on the bit sequence to be decoded to obtain an information bit sequence. The bit sequence to be decoded is obtained based on the input bit sequence. The information bit sequence includes K information bits, where K is an integer greater than 1. The information bit sequence is carried in K1 bit positions out of N1 bit positions and K-K1 bit positions out of N2 bit positions. The N1 bit positions and the N2 bit positions are different bit positions out of N bit positions. N1, N2, and N are positive integers, and K1 is a positive integer less than K. Furthermore, the K2 bit positions out of the K-K1 bit positions are determined based on reliability and a first set. The K3 bit positions out of the K-K1 bit positions, excluding the K2 bit positions, are determined based on the reliability and a second set. K2 and K3 are positive integers less than K-K1. The first set and the second set each include one or more pre-frozen bit positions out of the N2 bit positions.

3. The method according to claim 1 or 2, characterized in that, N1 and N2 are determined based on E and N, where E represents the length of the output bit sequence, N represents the length of the encoded bit sequence, and N is greater than E. The output bit sequence is obtained by rate matching the encoded bit sequence.

4. The method according to claim 3, characterized in that, When E / N is greater than the threshold, N1 + N2 = N; or, when E / N is less than the threshold, N1 + N2 = N. <N。 5. The method according to claim 4, characterized in that, If E > 3N / 4, then N1 + N2 = N; or, if E < 3N / 4, then N1 + N2 = N. <N。 6. The method according to claim 4 or 5, characterized in that, Of the N bit positions, the bit positions other than the N1 bit positions and the N2 bit positions are rate-matching bit positions, which are bit positions used for punching or shortening.

7. The method according to any one of claims 4-6, characterized in that, N1 = N / 2, N2 = N / 2 n Where n is a positive integer, and 1 / 2 n ≥(E / N-1 / 2)>1 / 2 n+1 .

8. The method according to any one of claims 1-7, characterized in that, The N1 bit positions do not include the rate matching bit positions, and the N1 bit positions are the N1 bit positions that are farthest from the rate matching bit positions among the N bit positions, wherein the rate matching bit positions are bit positions used for punching or shortening.

9. The method according to any one of claims 1-8, characterized in that, The N2 bit positions include rate matching bit positions; or, the N2 bit positions do not include rate matching bit positions, and the N2 bit positions are located between the rate matching bit positions and the N1 bit positions, wherein the rate matching bit positions are bit positions used for punching or shortening.

10. A communication device, characterized in that, It includes one or more functional modules that interact with each other to implement the method of any one of claims 1-9.

11. A communication device, characterized in that, It includes a processor and an interface circuit, the processor being configured to communicate with other devices via the interface circuit and to perform the method according to any one of claims 1-9.

12. A computer program product, characterized in that, The computer program product includes instructions that, when executed on a processor, cause the processor to perform the method of any one of claims 1-9.

13. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed by a communication device, implement the method described in any one of claims 1-9.

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