Wireless clock synchronization control method for wireless sensor network

Abstract

The application relates to a wireless clock synchronization control method for a wireless sensor network, which solves the technical problems of low synchronization precision, huge communication cost and slow synchronization speed of the existing clock synchronization method of the wireless sensor network without satellite signal dependence, wherein the clock phase information of a master node is first sent to a slave node, then the FPGA of the slave node calculates the phase difference of the clock phase of the master and slave nodes, then a frequency control word is calculated by using a fuzzy PI algorithm, and finally the DCO in the FPGA of the slave node is controlled through the frequency control word, so that the phase of the local clock of the slave node is adjusted. The application is suitable for large-scale wireless sensor arrays, unmanned aerial vehicle clusters and the like.

Description

Technical Field

[0001] This invention relates to the field of wireless sensor network technology, and more specifically, to a wireless clock synchronization control method for wireless sensor networks. Background Technology

[0002] Wireless Sensor Networks (WSNs) are distributed sensor networks that use tens of thousands of sensors to sense and inspect the external world, monitoring and collecting information on various objects within the network's distributed area in real time. This information is then transmitted wirelessly to gateway nodes, enabling the detection and tracking of targets within a specified range. WSNs can also connect to the internet via wired or wireless means. WSNs have been widely applied in military reconnaissance, smart homes, environmental monitoring, industrial control, agriculture, livestock management, traffic management, and medical monitoring, demonstrating broad application scenarios and enormous market potential.

[0003] Clock synchronization is a key mechanism for wireless sensor network systems that need to work together, and it is also a key means to improve accuracy. At present, the main ways to achieve high-precision clock synchronization are: (1) Relying on satellite signals. Although the timing technology based on GNSS or GPS is mature, it is easy to lose signals in environments such as indoors, underground mines or in bad weather, and has poor robustness. (2) Schemes based on PTP or SyncE have strict requirements on network topology and are complex to implement. Wireless clock synchronization schemes based on Wi-Fi or Zigbee usually only achieve synchronization accuracy at the microsecond level, which cannot meet the high precision requirements at the nanosecond level. (3) When using UWB (ultra-wideband) signals as information transmission medium for wireless synchronization, although the conventional message-passing-based PI / PID control algorithm reduces the requirements for channel impulse response, the convergence speed is slow and the communication overhead is large. The slow convergence speed leads to a slow synchronization speed. The PI controller with fixed parameters has poor adaptability to different initial phase errors and requires a large number of iterations to converge, resulting in huge network communication overhead. Summary of the Invention

[0004] This application aims to address the technical problems of low synchronization accuracy, huge communication overhead, and slow synchronization speed in existing clock synchronization methods for wireless sensor networks when they do not rely on satellite signals. It provides a high-precision, low-cost, and fast wireless clock synchronization control method for wireless sensor networks.

[0005] This application provides a wireless clock synchronization control method for wireless sensor networks, comprising the following steps: Step S1: The first FPGA measures the local clock phase information of the master node, while the second FPGA measures the local clock phase information of the slave node. Step S2, Phase Information Transmission: Under the control of the first MCU, the first RF module sends the master node local clock phase information to the second RF module; The second radio frequency module receives the local clock phase information of the master node. Under the control of the second MCU, the local clock phase information of the master node is sent to the second FPGA. The second FPGA is equipped with a fuzzy PI controller, a second DCO, and a second TDC module. Step S3, calculate the phase difference: The second TDC module processes the local clock phase information of the master node and the local clock phase information of the slave node, and outputs the phase difference between the local clock phase information of the master node and the local clock phase information of the slave node. and its change ; Step S4: The second FPGA uses a fuzzy PI algorithm to calculate the frequency control word; Step S5: Control the second DCO through the frequency control word, thereby adjusting the phase of the slave node's local clock.

[0006] Preferably, step S4 is performed through the following steps: Step S401, phase difference and its change As the input to the fuzzy PI controller, the frequency control word is the control quantity, and the setpoint is the target phase difference; Step S402, phase difference The fuzzy phase difference is obtained after fuzzification. Change The change in fuzzy phase difference is obtained after fuzzification. ; Step S403, blurring phase difference and the change in fuzzy phase difference As input for fuzzy inference, seven fuzzy subsets, NB, NM, NS, ZE, PS, PM, and PB, are taken within the fuzzy universe of discourse, and a triangular membership function is used. Step S404: Calculate the bandwidth ratio λ; Step S405: Calculate the proportional parameter using the following formula. and integral parameters : ; In the above formula, for: ; In the calculation formula, It is the frequency of the node's local clock. This refers to the traction range of the second DCO. The frequency of the master node's local clock. This refers to the bit width of the accumulator in the second DCO. Step S406, obtain the proportional parameters. and integral parameters Then, the fuzzy PI controller outputs a frequency control word to the second DCO.

[0007] Preferably, in step S403, the fuzzy inference uses the Mamdani algorithm.

[0008] Preferably, step S1 is performed through the following process: The master node's first FPGA generates a start measurement enable signal, which is sent out by the first RF module under the control of the first MCU. The first FPGA generates start flag information and begins measuring clock phase information. After a period of time, the first FPGA generates a stop measurement enable signal, which is sent out by the first RF module under the control of the first MCU. The first FPGA generates stop flag information and stops measuring clock phase information, thus obtaining the master node's local clock phase information. From the node, when the second RF module receives the start measurement enable signal sent by the first RF module, the second FPGA generates start flag information and starts measuring clock phase information; after a period of time, when the second RF module receives the stop measurement enable signal sent by the first RF module, the second FPGA generates stop flag information and stops measuring clock phase information, thus obtaining the local clock phase information of the slave node.

[0009] Preferably, in step S4, the obtained , The data is stored as two COE type files. During FPGA programming, the COE files are initialized into the two ROM IP cores.

[0010] The beneficial effects of this application are that it achieves phase approximation of the clocks between master and slave nodes through adaptive adjustment, resulting in extremely high synchronization accuracy, reaching nanosecond-level (<10ns). Furthermore, the synchronization speed is fast. The fuzzy PI algorithm ensures rapid convergence, reducing wireless communication overhead. The system also exhibits strong robustness.

[0011] Further features and aspects of this application will be clearly described in the following detailed description with reference to the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the wireless communication principle between the master node and the slave node, showing the clock phase information. Figure 2 This is an overall flowchart of a wireless clock synchronization control method for wireless sensor networks; Figure 3 This is a flowchart illustrating how a handshake is achieved through symmetrical bidirectional information transmission to simultaneously measure the clock phase information of both the master node and the slave node. Figure 4 This is a block diagram illustrating the communication principle between the second MCU and the second TDC module in the second FPGA from the node. Figure 5 This is a schematic diagram of the fuzzy PI algorithm control process; Figure 6 It is the fuzzy input membership curve in the fuzzy PI algorithm; Figure 7 It is the fuzzy logic control rule table in the fuzzy PI algorithm; Figure 8 This is the fuzzy logic control rule table in the fuzzy PI algorithm. (Continued from the previous section) Figure 7 The table shown; Figure 9 It is the curve of the proportional-integral parameter as a function of the bandwidth ratio; Figure 10 This is a schematic diagram of fuzzification processing in the fuzzy PI algorithm; Figure 11 These are the results of comparative experiments on the convergence of the fuzzy PI controller of this invention and the ordinary PI controller; Figure 12 This is the experimental result of the synchronization between the master node clock and the slave node clock; Figure 13 It is the fuzzy output membership curve in the fuzzy PI algorithm.

[0013] Explanation of symbols in the diagram: 1. Master node, 1-1. First RF module, 1-2. First MCU, 1-3. First FPGA; 2. Slave node, 2-1. Second RF module, 2-2. Second MCU, 2-3. Second FPGA. Detailed Implementation

[0014] The application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] The specific embodiments described below are merely preferred embodiments of this application, and the scope of protection of this application is not limited thereto. Those skilled in the art can make modifications or variations based on the principles, concepts, and spirit of this application, and the resulting technical solutions should all be covered within the scope of protection of this application.

[0016] like Figure 1 As shown, the first FPGA1-3 in master node 1 is used to generate a local clock. The digitally controlled oscillator (DCO) in the first FPGA1-3 is also used to measure the phase information of the master node's local clock. The first radio frequency module 1-1 is used to transmit the master node's local clock phase information to slave node 2 wirelessly. The master node's local clock phase information calculated and processed by the first FPGA1-3 is sent to the first MCU1-2, and the first MCU1-2 controls the first radio frequency module 1-1 to send the master node's local clock phase information to slave node 2.

[0017] The second RF module 2-1 in node 2 receives the master node local clock phase information sent by the first RF module 1-1. Under the control of the second MCU 2-2, the received master node local clock phase information is sent to the second FPGA 2-3. The second FPGA 2-3 in node 2 generates a local clock (the digitally controlled oscillator in the second FPGA 2-3 is a DCO), measures the phase information of the clock, calculates the phase difference between the clock phase information and the master node local clock phase information, and generates a frequency control word based on the phase difference using a fuzzy PI algorithm to adjust the local clock output, i.e., adjust the slave node local clock output.

[0018] like Figure 2 As shown, the wireless clock synchronization control method for wireless sensor networks mainly includes the following steps: The first step is to measure the clock phase information of master node 1 and the clock phase information of slave node 2.

[0019] Measure the clock phase information of master node 1, and simultaneously measure the clock phase information of slave node 2.

[0020] To ensure the validity of clock phase information measurements, refer to Figure 3 A handshake is performed through symmetrical bidirectional information transmission to achieve synchronization of the measurement enable signal.

[0021] Master Node 1: The first FPGA1-3 generates a start measurement enable signal, which is sent out by the first RF module 1-1 under the control of the first MCU1-2. The first FPGA1-3 generates a start flag and begins measuring clock phase information. After a period of time, the first FPGA1-3 generates a stop measurement enable signal, which is sent out by the first RF module 1-1 under the control of the first MCU1-2. The first FPGA1-3 then generates a stop flag and stops measuring clock phase information, thus obtaining the master node's local clock phase information.

[0022] From node 2, when the second RF module 2-1 receives the start measurement enable signal sent by the first RF module 1-1, the second FPGA 2-3 generates start flag information and begins measuring clock phase information. After a period of time, when the second RF module 2-1 receives the stop measurement enable signal sent by the first RF module 1-1, the second FPGA 2-3 generates stop flag information and stops measuring clock phase information, thus obtaining the local clock phase information of the slave node.

[0023] In this process, the wireless transmission delay of the signal can be canceled using the PTP method described in the IEEE 1588 protocol.

[0024] It should be noted that the specific method for measuring the clock phase of the FPGA chip can be as follows: using a time-to-digital converter (TDC), forming a coarse and fine two-level counter in the form of a 64-bit counter + a cascaded 50-level carry4 chain, and calibrating the delay chain by using code density testing. 1,000,000 random numbers are generated using the LFSR polynomial in Verilog language, and weighted calibration is performed according to the bin width. After calibration, the output is performed by looking up a table according to the internal LUT, which reduces the integral nonlinearity and differential nonlinearity error of the TDC.

[0025] The second step is the transmission of phase information.

[0026] Under the control of the first MCU1-2, the first RF module 1-1 sends out the local clock phase information of the master node.

[0027] The second radio frequency module 2-1 receives the master node local clock phase information sent by the first radio frequency module 1-1.

[0028] Under the control of the second MCU2-2, the master node's local clock phase information is sent to the second FPGA2-3. (Reference) Figure 4 The second FPGA2-3 includes a fuzzy PI controller, a second DCO, and a second TDC module. The second MCU2-2 sends the master node local clock phase information to the second TDC module, and the second DCO outputs the slave node local clock phase information.

[0029] The third step involves the second FPGA (2-3) performing computational processing, as referenced. Figure 5 The second TDC module compares the local clock phase information of the master node with that of the slave node, and outputs the phase difference between the local clock phase information of the master node and the slave node. and its change .

[0030] Phase difference It is expressed as a time difference, and the unit is ns.

[0031] The fourth step is to use the fuzzy PI algorithm to calculate the frequency control word.

[0032] refer to Figure 5 Phase difference and its change The frequency control word (FCW) serves as the input to the fuzzy PI controller. The setpoint is the target phase difference, with a value of 1 ns.

[0033] Phase difference The fuzzy phase difference is obtained after fuzzification. Change The change in fuzzy phase difference is obtained after fuzzification. The phase comparison range is [-2π, 2π], so the phase difference is... The maximum value M_TDC is 2π. The fuzziness factor is... The scaling factor is set to 6. For ease of FPGA implementation, a discrete fuzzy universe of discourse {-6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6} is used. Phase difference... Greater than The phase difference is considered too large at times, and only considered small when the phase difference is close to locking. Therefore, a nonlinear fuzzy method is used in the process of fuzzifying physical quantities into fuzzy quantities. The fuzzy partitions are shown in Table 1: Table 1, fuzzy partitioning.

[0034]

[0035] Choosing an appropriate membership function is crucial for fuzzy control. The membership function must conform to the actual situation and reflect the real characteristics of the objective fuzzy phenomenon. Common membership functions include trapezoidal functions, triangular functions, double sigmoid functions, Gaussian functions, and generalized bell functions. For more sensitive control, the membership function can be set to be narrower. For smoother and more sluggish control, the membership function can be set to be wider and flatter. Here, in the context of fuzzy phase difference... and the change in fuzzy phase difference As input for fuzzy inference, seven fuzzy subsets (NB, NM, NS, ZE, PS, PM, and PB) are selected within the fuzzy universe of discourse, and a highly sensitive triangular membership function is used. The membership curves of the seven fuzzy subsets are shown below. Figure 6 As shown in the diagram. A schematic diagram of the blurring process is shown below. Figure 10 As shown.

[0036] The reliability of fuzzy control hinges on the fuzzy control rules. These rules should be complete, providing a corresponding output for any fuzzy input. Therefore, the following can be obtained: Figure 7 and Figure 8 The fuzzy logic control rules are shown.

[0037] The fuzzy inference method uses the Mamdani algorithm, and the control rule is: if the input Belongs to fuzzy subset A, input If the input λ belongs to fuzzy subset B, then the output λ belongs to fuzzy subset C. A and B are the seven fuzzy subsets of the input, and C is the five fuzzy subsets of the output.

[0038] Fuzzy membership function with bandwidth ratio λ can be obtained through fuzzy control inference. However, the PI adaptive controller needs to output a precise value of bandwidth ratio λ in order to adjust the proportional-integral parameters. Therefore, it is necessary to transform the fuzzy set of output values ​​into a definite value, that is, to perform defuzzification. Defuzzification adopts the area centroid method, which is a very accurate defuzzification method. The centroid of the area enclosed by the membership function curve and the horizontal axis is taken as the final output value of the fuzzy inference system. The mathematical expectation of the fuzzy values ​​with respect to membership degree in the fuzzy domain is calculated and then divided by the sum of the membership degrees of the fuzzy values, as shown in Equation (1).

[0039]

[0040] In formula (1), It is a fuzzy output universe of discourse with a minimum value of 0.02 and a maximum value of 0.1; The fuzzy output membership degree, after defuzzification, can output the precise bandwidth ratio λ, which is the optimal bandwidth ratio required by the system. Thus, the relationship between the bandwidth ratio and the fuzzy inference input signal is obtained.

[0041] Based on the precise value of the bandwidth ratio λ, the proportional parameter is calculated using the following formulas (2) and (3). and integral parameters .

[0042]

[0043] In formulas (2) and (3), for:

[0044] In formula (4), It is the frequency of the node's local clock. This refers to the traction range of the second DCO. The frequency of the master node's local clock. This represents the bit width of the accumulator in the second DCO.

[0045] Obtain the proportional parameters and integral parameters After calculation and processing, the fuzzy PI controller outputs a frequency control word (FCW) to the second DCO.

[0046] As can be seen, this invention derives the optimal bandwidth ratio λ of the system based on the system state, and then calculates the corresponding proportional and integral parameters. The adaptive proportional and integral parameters are achieved by continuously adjusting the bandwidth ratio λ. and Regarding the curve of bandwidth ratio λ change, as shown below Figure 9 As shown, a larger bandwidth ratio results in a larger proportional-integral parameter and a larger response rate of the corresponding control curve, but also a larger system overshoot. Conversely, a smaller bandwidth ratio results in a smaller overshoot and a more stable system. When the phase difference is large, a larger bandwidth is needed to accelerate the response speed; when the phase difference is small, a smaller bandwidth is needed to improve stability. Therefore, based on the magnitude of the phase difference, an appropriate bandwidth, i.e., a different bandwidth ratio λ, is selected to optimize both response speed and stability. When the phase difference is large, a larger bandwidth ratio λ is chosen to increase the system bandwidth and accelerate the system response speed. When the phase difference is small or loop lock-in occurs, a smaller bandwidth ratio λ is chosen to reduce the system loop bandwidth and enhance system stability.

[0047] The fifth step is to adjust the phase of the local clock of the slave node using the frequency control word.

[0048] The second DCO is controlled by the frequency control word (FCW), thereby precisely adjusting the phase of the slave node's local clock. This achieves adaptive adjustment and ultimately enables phase approximation of the clocks between the master and slave nodes.

[0049] The fuzzy PI algorithm used in this invention is designed for scenarios where master-slave node clock synchronization is achieved through wireless message passing. It boasts a fast convergence speed, improving convergence speed by 40%–60% compared to using a conventional fixed-parameter PI controller. (Reference) Figure 11 Experiments verified that the step response under initial errors of -8ns, 4ns, and -1ns was compared within a 20ms simulation time, confirming fast convergence. Furthermore, even with extreme errors (e.g., 8ns), the convergence step count remained stable between 60-80 steps, significantly reducing wireless communication overhead. Extremely high synchronization accuracy: through high-frequency processing using FPGA and TDC, in hardware measurements (comparison of 1PPS pulses per second between master and slave nodes), such as... Figure 12 As shown, CH1 is the master node clock signal, and CH2 is the slave node clock signal, achieving high-precision wireless clock synchronization at the nanosecond level (<10ns), with fast synchronization speed. The system is highly robust: the fuzzy control mechanism enables the control process to have a strong adaptive capability to different initial states.

[0050] The local clock phase is measured using a TDC with built-in calibration function on the FPGA. The system bandwidth ratio is dynamically calculated using fuzzy rules based on the FPGA, and then the scaling parameter is adaptively adjusted. and integral parameters .

[0051] A filtering algorithm is introduced between the frequency control word and the DCO to smooth the step response of the frequency control word caused by the low sampling rate of wireless communication, thereby improving the accuracy of phase adjustment.

[0052] To quickly implement the adjustment of scaling parameters in FPGA and integral parameters It can perform fast multiplication operations, respectively... , The calculation results are stored as two COE type files. When programming the FPGA, the COE file containing the proportional-integral parameters is initialized into two ROM IP cores. In this way, when the algorithm is running, the corresponding parameters can be directly obtained by looking up the table based on the phase difference between the master and slave nodes and the change in phase difference.

Claims

1. A wireless clock synchronization control method for wireless sensor networks, characterized in that, Includes the following steps: Step S1: The first FPGA measures the local clock phase information of the master node, while the second FPGA measures the local clock phase information of the slave node. Step S2, Phase Information Transmission: Under the control of the first MCU, the first radio frequency module sends the local clock phase information of the master node to the second radio frequency module; The second radio frequency module receives the local clock phase information of the master node, and under the control of the second MCU, the local clock phase information of the master node is sent to the second FPGA; the second FPGA is equipped with a fuzzy PI controller, a second DCO and a second TDC module; Step S3, calculate the phase difference: The second TDC module processes the local clock phase information of the master node and the local clock phase information of the slave node, and outputs the phase difference between the local clock phase information of the master node and the local clock phase information of the slave node. and its change ; Step S4: The second FPGA calculates the frequency control word using a fuzzy PI algorithm; Step S5: Control the second DCO through the frequency control word, thereby adjusting the phase of the slave node's local clock.

2. The wireless clock synchronization control method for wireless sensor networks according to claim 1, characterized in that, Step S4 is performed through the following steps: Step S401, the phase difference and its change As the input to the fuzzy PI controller, the frequency control word is the control quantity, and the setpoint is the target phase difference; Step S402, the phase difference The fuzzy phase difference is obtained after fuzzification. Change The change in fuzzy phase difference is obtained after fuzzification. ; Step S403, the fuzzy phase difference and the change in fuzzy phase difference As input for fuzzy inference, seven fuzzy subsets, NB, NM, NS, ZE, PS, PM, and PB, are taken within the fuzzy universe of discourse, and a triangular membership function is used. Step S404: Calculate the bandwidth ratio λ; Step S405: Calculate the proportional parameter using the following formula. and integral parameters : ； In the above formula, for: ； In the calculation formula, It is the frequency of the node's local clock. This refers to the traction range of the second DCO. The frequency of the master node's local clock. This refers to the bit width of the accumulator in the second DCO; Step S406, obtain the proportional parameters. and integral parameters Then, the fuzzy PI controller outputs a frequency control word to the second DCO.

3. The wireless clock synchronization control method for wireless sensor networks according to claim 2, characterized in that, In step S403, the fuzzy inference uses the Mamdani algorithm.

4. The wireless clock synchronization control method for wireless sensor networks according to claim 1, characterized in that, Step S1 is performed through the following process: The master node, the first FPGA generates a start measurement enable signal, which is then sent out by the first radio frequency module under the control of the first MCU; The first FPGA generates a start flag and begins measuring clock phase information. After a period of time, the first FPGA generates a stop measurement enable signal, which is then sent out by the first radio frequency module under the control of the first MCU. The first FPGA generates termination flag information, stops measuring clock phase information, and obtains the master node's local clock phase information. In the slave node, when the second RF module receives the start measurement enable signal sent by the first RF module, the second FPGA generates start flag information and starts measuring clock phase information; after a period of time, when the second RF module receives the stop measurement enable signal sent by the first RF module, the second FPGA generates stop flag information and stops measuring clock phase information, thus obtaining the slave node's local clock phase information.

5. The wireless clock synchronization control method for wireless sensor networks according to claim 2, characterized in that, In step S4, the obtained , The data is stored as two COE type files. During FPGA programming, the COE files are initialized into the two ROM IP cores.

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