Memory devices and methods of forming the same, memory systems

Abstract

The present disclosure provides a memory device and a method of forming the same, a memory system, the memory device comprising a first semiconductor structure and a second semiconductor structure stacked along a first direction; the first semiconductor structure comprising a memory array, a plurality of bit lines, a first conductive connection layer, and a second conductive connection layer; the second conductive connection layer being located between the first conductive connection layer and the second semiconductor structure in the first direction; the second semiconductor structure comprising a plurality of sense amplifiers; one sense amplifier being coupled with two bit lines, and a dominant conductive line in a coupling path between one of the two bit lines coupled with the sense amplifier and the sense amplifier being located in the first conductive connection layer, and a dominant conductive line in a coupling path between the other of the two bit lines coupled with the sense amplifier and the sense amplifier being located in the second conductive connection layer; an extension size of the dominant conductive line in a direction perpendicular to the first direction in the coupling path being greater than an extension size of other conductive lines in the coupling path in the direction perpendicular to the first direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and a method for forming the same, and a memory system. Background Technology

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and products. For example, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor memory device in computers. Summary of the Invention

[0003] This disclosure provides a memory device, a method for forming the same, and a memory system.

[0004] In a first aspect, embodiments of this disclosure provide a memory device, including a first semiconductor structure and a second semiconductor structure stacked along a first direction; wherein...

[0005] The first semiconductor structure includes a memory array, a plurality of bit lines coupled to the memory array, a first conductive connection layer and a second conductive connection layer; the second conductive connection layer is located between the first conductive connection layer and the second semiconductor structure in the first direction;

[0006] The second semiconductor structure includes a plurality of sense amplifiers; one of the sense amplifiers is coupled to two bit lines, and the dominant wire in the coupling path between one of the two bit lines coupled to the sense amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two bit lines coupled to the sense amplifier is located in the second conductive connection layer; the extension dimension of the dominant wire in the coupling path in the direction perpendicular to the first direction is greater than the extension dimension of the other conductive lines in the coupling path in the direction perpendicular to the first direction.

[0007] In one optional implementation, the plurality of bit lines are located between the memory array and the first conductive interconnect layer in the first direction; the plurality of bit lines extend along a second direction and are arranged along the second direction and a third direction; the second direction is perpendicular to the third direction and is also perpendicular to the first direction.

[0008] The storage array includes a first storage block; the plurality of bit lines include a plurality of first bit lines coupled to the first storage block; the dominant wire in the coupling path between one of the two first bit lines adjacent to the third-order upward and the sense amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two first bit lines adjacent to the third-order upward and the sense amplifier is located in the second conductive connection layer.

[0009] In one alternative implementation, the dominant wires in the first conductive connection layer and the dominant wires in the second conductive connection layer, which are coupled to one of the sensing amplifiers, are arranged along the first direction.

[0010] In one optional implementation, the plurality of bit lines further includes a plurality of second bit lines coupled to the first memory block; the second bit lines are arranged alternately with the first bit lines in the third direction.

[0011] The dominant wire in the coupling path between one of the two adjacent second bit lines in the third direction and the sense amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two adjacent second bit lines in the third direction and the sense amplifier is located in the second conductive connection layer.

[0012] In one alternative implementation, the storage array further includes:

[0013] A second memory block and a third memory block; the first memory block is located between the second memory block and the third memory block in the second direction; the plurality of bit lines further include a plurality of third bit lines coupled to the second memory block and a plurality of fourth bit lines coupled to the third memory block; one first bit line and one third bit line are coupled to the same sense amplifier; one second bit line and one fourth bit line are coupled to the same sense amplifier.

[0014] In one alternative implementation, the sensing amplifier coupled to the first bit line is stacked with the first memory block in the first direction; the sensing amplifier coupled to the second bit line is stacked with the third memory block in the first direction.

[0015] In one optional implementation, the first semiconductor structure further includes:

[0016] A first conductive structure extending along the first direction, one end of the first conductive structure at opposite ends along the first direction being connected to the bit line, and the other end of the first conductive structure at opposite ends along the first direction being coupled to the main wire in the first conductive connection layer.

[0017] A second conductive structure extending along the first direction, one end of which is opposite to the bit line along the first direction is connected to the bit line, and the other end of which is opposite to the bit line along the first direction is coupled to the main wire in the second conductive connection layer.

[0018] In one optional implementation, the first semiconductor structure further includes:

[0019] A third conductive connection layer is located between the first conductive connection layer and the second conductive connection layer; the coupling path between one of the two bit lines coupled to one of the sensing amplifiers and the sensing amplifier also includes a conductive line in the third conductive connection layer, and the coupling path between the other of the two bit lines coupled to one of the sensing amplifiers and the sensing amplifier also includes a conductive line in the third conductive connection layer.

[0020] In one alternative embodiment, the memory device further includes:

[0021] A bonding layer is located between the first semiconductor structure and the second semiconductor structure; the bonding layer includes a bonding structure; the bonding structure is coupled to a dominant wire in the first conductive connection layer, or the bonding structure is coupled to a dominant wire in the second conductive connection layer; the coupling path between the bit line and the sensing amplifier includes the bonding structure.

[0022] In one optional embodiment, the second semiconductor structure further includes:

[0023] A fourth conductive connection layer is located between the plurality of sense amplifiers and the bonding layer; the bonding structure is coupled to the conductive lines in the fourth conductive connection layer, and the conductive lines in the fourth conductive connection layer are coupled to the sense amplifiers; the coupling path between the bit line and the sense amplifier includes the conductive lines in the fourth conductive connection layer.

[0024] In one alternative implementation, the storage array includes:

[0025] Storage cells arranged in an array along the second direction and the third direction; the storage cells include a transistor structure and a capacitor structure coupled to the transistor structure.

[0026] In a second aspect, embodiments of this disclosure provide a memory system, including:

[0027] At least one memory as described in any of the above embodiments;

[0028] A controller is coupled to at least one of the memories and configured to control the memory device.

[0029] Thirdly, embodiments of this disclosure provide a method for forming a memory device, including:

[0030] Forming a first semiconductor structure includes: forming a memory array, a plurality of bit lines coupled to the memory array, a first conductive interconnect layer, and a second conductive interconnect layer;

[0031] Forming a second semiconductor structure includes: forming a plurality of sense amplifiers;

[0032] The first semiconductor structure and the second semiconductor structure are stacked along a first direction; the second conductive connection layer is located between the first conductive connection layer and the second semiconductor structure in the first direction; one of the sensing amplifiers is coupled to two bit lines, and the dominant wire in the coupling path between one of the two bit lines coupled to the sensing amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two bit lines coupled to the sensing amplifier is located in the second conductive connection layer; the extension dimension of the dominant wire in the coupling path in the direction perpendicular to the first direction is greater than the extension dimension of the other conductive lines in the coupling path in the direction perpendicular to the first direction.

[0033] In one optional embodiment, the plurality of bit lines are located between the memory array and the first conductive interconnect layer in the first direction; the plurality of bit lines extend along a second direction and are arranged along the second direction and a third direction; the second direction is perpendicular to the third direction and is also perpendicular to the first direction; forming the memory array includes: forming a first memory block;

[0034] The formation of the plurality of bit lines includes: forming a plurality of first bit lines coupled to the first memory block; the dominant wire in the coupling path between one of the two first bit lines adjacent to the third upward is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two first bit lines adjacent to the third upward is located in the second conductive connection layer.

[0035] In one alternative implementation, forming a plurality of bit lines further includes:

[0036] A plurality of second bit lines are formed that are coupled to the first memory block; the second bit lines are arranged alternately with the first bit lines in the third direction; the dominant wire in the coupling path between one of the two adjacent second bit lines in the third direction and the sense amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two adjacent second bit lines in the third direction and the sense amplifier is located in the second conductive connection layer.

[0037] In one alternative implementation, forming the storage array further includes:

[0038] A second memory block and a third memory block are formed; the first memory block is located between the second memory block and the third memory block in the second direction; the plurality of bit lines further include a plurality of third bit lines coupled to the second memory block and a plurality of fourth bit lines coupled to the third memory block; one first bit line and one third bit line are coupled to the same sense amplifier; one second bit line and one fourth bit line are coupled to the same sense amplifier.

[0039] In one alternative implementation, forming the first semiconductor structure further includes:

[0040] Before forming the first conductive connection layer and the second conductive connection layer, a first conductive structure extending along the first direction and a second conductive structure extending along the first direction are formed; one end of the first conductive structure at opposite ends along the first direction is connected to a bit line, and one end of the second conductive structure at opposite ends along the first direction is connected to a bit line.

[0041] After the first conductive connection layer and the second conductive connection layer are formed, one end of the opposite ends of the first conductive structure along the first direction is coupled to the dominant wire in the first conductive connection layer, and the other end of the opposite ends of the second conductive structure along the first direction is coupled to the dominant wire in the second conductive connection layer.

[0042] In one alternative implementation, forming the first semiconductor structure further includes:

[0043] A third conductive connection layer is formed; the third conductive connection layer is located between the first conductive connection layer and the second conductive connection layer; the coupling path between one of the two bit lines coupled to one of the sensing amplifiers and the sensing amplifier also includes a conductive line in the third conductive connection layer, and the coupling path between the other of the two bit lines coupled to one of the sensing amplifiers and the sensing amplifier also includes a conductive line in the third conductive connection layer.

[0044] In an optional embodiment, the method of forming the memory device further includes:

[0045] A bonding layer is formed between the first semiconductor structure and the second semiconductor structure; the bonding layer includes a bonding structure; the bonding structure is coupled to a dominant wire in the first conductive connection layer, or the bonding structure is coupled to a dominant wire in the second conductive connection layer; the coupling path between the bit line and the sense amplifier includes the bonding structure.

[0046] In one optional implementation, forming the second semiconductor structure further includes:

[0047] A fourth conductive connection layer is formed; the fourth conductive layer is located on one side of the plurality of sense amplifiers in the first direction; the conductive lines in the fourth conductive layer are coupled to the sense amplifiers, and the bonding structure is coupled to the conductive lines in the fourth conductive connection layer; the coupling path between the bit line and the sense amplifier includes the conductive lines in the fourth conductive connection layer.

[0048] In one alternative implementation, forming the storage array includes:

[0049] A memory cell array is formed along the second direction and the third direction; the memory cell includes a transistor structure and a capacitor structure coupled to the transistor structure.

[0050] In the technical solution provided in this disclosure, the dominant wire in the coupling path between one of the two bit lines coupled to a sense amplifier in the memory device and the sense amplifier is located in a first conductive connection layer, and the dominant wire in the coupling path between the other of the two bit lines coupled to the sense amplifier is located in a second conductive connection layer. The parasitic capacitance between the dominant wires in the first conductive connection layer or the parasitic capacitance between the dominant wires in the second conductive connection layer can be used to compensate for the parasitic capacitance between adjacent bit lines, thereby reducing the degree of decrease in sensing margin caused by the parasitic capacitance between adjacent bit lines and improving the reliability of the memory device. Attached Figure Description

[0051] Figure 1 A schematic diagram of an electronic device provided in an embodiment of this disclosure;

[0052] Figure 2 A schematic diagram of DRAM provided for an embodiment of this disclosure;

[0053] Figure 3a A circuit diagram of a sensing amplifier provided in an embodiment of this disclosure;

[0054] Figure 3bA schematic diagram of the voltage on the bit line during the read operation provided in the embodiments of this disclosure. Figure 1 ;

[0055] Figure 4 A schematic diagram of a memory device provided in an embodiment of this disclosure;

[0056] Figure 5 This is a schematic diagram of a storage cell in a storage array provided in an embodiment of the present disclosure;

[0057] Figure 6 A schematic diagram of the peripheral circuitry stacked with a memory block, provided for an embodiment of this disclosure;

[0058] Figure 7 A cross-sectional schematic diagram of a memory device provided in an embodiment of this disclosure;

[0059] Figure 8 This is a schematic diagram showing the arrangement of multiple bit lines coupled to a memory array, provided in an embodiment of this disclosure.

[0060] Figure 9 A schematic diagram of the voltage on the bit line during the read operation provided in the embodiments of this disclosure. Figure 2 ;

[0061] Figure 10 A schematic diagram of the arrangement of various structures in a memory device in a first direction, provided for an embodiment of the present disclosure;

[0062] Figure 11 A schematic diagram showing the connection of bit lines, main power lines, and a sense amplifier in a memory device provided in an embodiment of this disclosure;

[0063] Figure 12 A schematic diagram of the arrangement of the dominant wires coupled to the first and third position lines, provided as a specific example of this disclosure. Figure 1 ;

[0064] Figure 13 for Figure 12 A schematic diagram of the cross section along line AA';

[0065] Figure 14 A schematic diagram of the arrangement of the main conductors coupled to the second and fourth bit lines, provided as a specific example of this disclosure;

[0066] Figure 15 for Figure 14 A schematic diagram of the cross section along line BB';

[0067] Figure 16 Schematic diagram three of the voltage on the bit line during the read operation provided in the embodiments of this disclosure;

[0068] Figure 17A schematic diagram of the arrangement of the dominant wires coupled to the first and third position lines, provided as a specific example of this disclosure. Figure 2 ;

[0069] Figure 18 This is a schematic flowchart illustrating a method for forming a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0070] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0071] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0072] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0073] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0074] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0075] Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this disclosure. The electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0076] like Figure 1 As shown, electronic device 1 may include a memory system 10 and a host 20. The memory system 10 may include a controller 110 and a memory 120. The host 20 may include a processor of electronic device 1, such as a central processing unit (CPU) or a system-on-chip (SoC) (e.g., an application processor (AP)). The controller 110 is coupled to both the host 20 and the memory 120, and the controller 110 may be configured to communicate with the host 20 and control the memory 120.

[0077] In some embodiments, controller 110 may be configured to control operations of memory 120, such as read operations, erase operations, write operations, refresh operations, etc. In some embodiments, controller 110 is also configured to process error correction codes (ECCs) regarding data read from or written to memory 120. In other embodiments, controller 110 may also be configured to perform any other suitable operation, such as formatting memory 120.

[0078] In some embodiments, controller 110 can receive data, commands, and addresses from host 20, and can send data, commands, and addresses to memory 120. Specifically, controller 110 may include command generator 111, address generator 112, device interface 113, and host interface 114. Controller 110 can receive data, commands, and addresses from host 20 through host interface 114, decode commands received from host 20 through command generator 111 to generate an access command CMD, and provide the access command CMD to memory 120 through device interface 113. Controller 110 can decode addresses received from host interface 114 through address generator 112 to generate an address ADDR to be accessed in memory array 121, and provide the address ADDR to be accessed to memory 120 through device interface 113. The access command may be a signal instructing memory 120 to write or read data by accessing one or more memory cells in memory array 121 corresponding to address ADDR. In addition, the controller 110 can also send a refresh command to the memory 120. The refresh command can be a signal instructing the memory 120 to read and rewrite data by accessing one or more memory cells of the memory array 121 corresponding to the address ADDR.

[0079] In some specific examples, memory 120 can be random access memory (RAM), such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), double-data-rate SDRAM (DDR SDRAM), phase-change random access memory (PRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), etc. The following explanation will use DRAM as an example.

[0080] In some embodiments, Figure 2 This is a schematic diagram of a DRAM according to an embodiment of the present disclosure. (Referring to...) Figure 1 and Figure 2The DRAM includes a memory array 121 and peripheral circuitry 122 coupled to the memory array 121. The peripheral circuitry 122 may include a sense amplifier circuit 1221, a row decoder 1222, a column decoder 1223, a data input / output buffer 1224, etc. The memory array 121 includes multiple memory cells arranged in an array. Multiple memory cells in the same row are coupled to word lines WL, and multiple memory cells in the same column are coupled to bit lines BL. Each memory cell includes a transistor T and a capacitor C. The word line WL is connected to the gate of transistor T, the bit line BL is connected to one of the source and drain of transistor T, and the other of the source and drain of transistor T is connected to one electrode of capacitor C. The other electrode of capacitor C is connected to a fixed voltage. The memory cell is configured to store "1" or "0" by utilizing the amount of charge stored in capacitor C. By specifying row and column addresses, individual memory cells in a DRAM chip can be accessed independently, and data stored in them can be read, written, or refreshed.

[0081] In some embodiments, the sensing amplifier circuit 1221 may include a plurality of sensing amplifiers, each sensing amplifier being coupled to two bit lines. Figure 3a This is a circuit diagram of the sensing amplifier provided in an embodiment of the present disclosure, such as... Figure 3a As shown, bit line BL and its complementary bit line BLN are coupled to a sense amplifier SA. The sense amplifier SA may include four transistors, where transistors P1 and P2 are PMOS transistors, and transistors N1 and N2 are NMOS transistors. The gate of transistor P1 is coupled to the complementary bit line BLN, the drain is coupled to the bit line BL, and the source is coupled to the P-type sense amplifier control signal (Sense-Amplifier P-Fet Control, SAP). The gate of transistor P2 is coupled to the bit line BL, the drain is coupled to the complementary bit line BLN, and the source is coupled to SAP. The gate of transistor N1 is coupled to the complementary bit line BLN, the drain is coupled to the bit line BL, and the source is coupled to the N-type sense amplifier control signal (Sense-Amplifier N-Fet Control, SAN). The gate of transistor N2 is coupled to the bit line BL, the drain is coupled to the complementary bit line BLN, and the source is coupled to SAN.

[0082] It should be noted that, Figure 3a The circuit structure of the sensing amplifier SA shown is merely an example and is not intended as a specific limitation on the sensing amplifier in the memory device provided in this disclosure.

[0083] Figure 3b A schematic diagram of the voltage on the bit line during the read operation provided in the embodiments of this disclosure. Figure 1 Here, we take the example where the bit line BL is coupled to the selected memory cell in the read operation, and the selected memory cell stores "0" as the data. Refer to the reference... Figure 3a and Figure 3b Before the charge sharing phase S1, the transistor T of the memory cell is in the off state, and the bit line BL and its complementary bit line BLN can be pre-charged to the same voltage. Then, in the charge sharing phase S1, the transistor T of the memory cell is turned on, and the charge stored in the capacitor C of the memory cell can be transferred to the bit line BL, causing the voltage on the bit line BL to drop. Thus, after the voltage on the bit line BL stabilizes, a voltage difference will be generated between the bit line BL and the complementary bit line BLN. This voltage difference is the sensing margin. In the sensing phase S2 after the charge sharing phase S1, the sensing amplifier SA receives a low-level signal SAN and a high-level signal SAP. Transistors P2 and N1 are turned on, causing the voltage on the bit line BL to drop further and the voltage on the complementary bit line BLN to rise. Thus, the sensing amplifier SA can further amplify the voltage difference between the bit line BL and the complementary bit line BLN, so that the data "0" stored in the memory cell can be read.

[0084] Figure 4 A schematic diagram of a memory device provided in an embodiment of this disclosure, such as... Figure 4 As shown, the memory device includes a first semiconductor structure 200, a second semiconductor structure 300, and a bonding layer 400 located between the first semiconductor structure 200 and the second semiconductor structure 300, all stacked along the Z-direction. In the above embodiment, the memory array 121 can be located in the first semiconductor structure 200, and the peripheral circuitry 122 can be located in the second semiconductor structure 300. The memory array 121 and the peripheral circuitry 122 can be coupled through a bonding structure 401 in the bonding layer 400, thereby forming a three-dimensional memory device, which is beneficial for achieving high-density integration of DRAM. Here, the bonding layer 400 can be a hybrid bonding layer formed by a hybrid bonding process, including a dielectric layer and a bonding structure 401 penetrating the dielectric layer along the Z-direction.

[0085] Figure 5 This is a schematic diagram of a storage bank in a storage array provided in an embodiment of the present disclosure. The storage array 121 includes at least one storage bank, and the storage bank includes a plurality of storage blocks arranged in an array. Figure 6The schematic diagram provided as a specific example shows the peripheral circuitry stacked with a memory block. The peripheral circuitry stacked with a memory block in the Z direction may include a sense amplifier (SA), a word line driver (WLD), and a control logic circuit coupled to the memory block.

[0086] In this embodiment of the disclosure, the peripheral circuitry coupled to the memory block can be stacked with the memory block in the Z direction, thereby further reducing the area of ​​the memory device. In addition, the length of the conductive connection path between the memory array and the peripheral circuitry can be shortened.

[0087] In some specific examples, Figure 7 This is a cross-sectional schematic diagram of a memory device provided in an embodiment of the present disclosure. The memory device includes a first semiconductor structure 200 and a second semiconductor structure 300 stacked along a first direction. Specifically, the first semiconductor structure 200 includes a memory array 201, and the second semiconductor structure 300 includes peripheral circuitry 301. The memory array 201 includes a plurality of memory cells 202 arranged in a second and third direction. Each memory cell 202 includes a transistor structure 203 and a capacitor structure 204 coupled to the transistor structure 203. The plurality of memory cells 202 arranged along the second direction are coupled to bit lines 205 extending along the second direction. The bit lines 205 can be coupled to a bonding structure 401 in a bonding layer 400 through an interconnect structure in a first interconnect layer 210. The bonding structure 401 can be coupled to a sense amplifier 302 in the peripheral circuitry 301 through an interconnect structure in a second interconnect layer 310.

[0088] In this embodiment, the interconnect structures in the first interconnect layer 210, the bonding structure 401 in the bonding layer 400, and the interconnect structures in the second interconnect layer 310 can constitute a coupling path between the bit line 205 in the first semiconductor structure 200 and the sense amplifier 302 in the second semiconductor structure 300. Here, the interconnect structure may include multiple conductive lines extending in a direction perpendicular to the first direction and multiple conductive structures connecting two adjacent conductive lines in the first direction. Figure 7 The number of conductive lines and conductive structures shown is for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0089] In this embodiment of the disclosure, the second direction is perpendicular to the third direction and is also perpendicular to the first direction. Here, the first direction is the Z direction, the second direction is the X direction, and the third direction is the Y direction, for example.

[0090] In some embodiments, Figure 8 This is a schematic diagram of the arrangement of multiple bit lines coupled to a memory array provided in an embodiment of this disclosure, in conjunction with reference to... Figure 7 and Figure 8 Multiple bit lines 205 are located between the memory array 201 and the second semiconductor structure 300, and are at substantially the same height in a first direction. The multiple bit lines 205 extend along a second direction and are arranged along both the second and third directions. The bit lines 205 coupled to a memory block are arranged along the third direction. The bit lines 205 comprise a conductive material, and a dielectric material is filled between them. Parasitic capacitance is generated between adjacent bit lines 205, and as the integration density of the memory device increases, the spacing between adjacent bit lines 205 shortens, making the coupling effect between adjacent bit lines 205 increasingly severe.

[0091] Figure 9 A schematic diagram of the voltage on the bit line during the read operation provided in the embodiments of this disclosure. Figure 2 Combined with reference Figure 8 and Figure 9 Two adjacent bit lines BL coupled to a memory block and BL For example, when the voltage applied to the selected word line causes the transistors in multiple selected memory cells arranged along a third direction to conduct, if it is related to BL... The selected coupled memory cell stores "0" as its data, and is associated with BL. The selected coupled memory cell stores "1" as the data during the charge sharing phase S1, BL The voltage on BL drops. The voltage rises due to BL BL The coupling effect caused by the parasitic capacitance between them may lead to BL The rate of voltage drop on the plate decreases, which in turn leads to BL Its complementary bit line BLN The sensing margin between them decreases, for example, in the case of BL. Coupled selected memory cell and BL When all selected coupled memory cells store "0", BL Its complementary bit line BLN The sensing margin between them is M1, while with BL The selected coupled memory cell stores "0" as its data, and is associated with BL. When the selected coupled memory cell stores "1" as the data, BL Its complementary bit line BLN The sensing margin between them decreases to M2, and this decrease in sensing margin may lead to a decrease in the sensing margin with BL. and BLN The coupled sense amplifier cannot properly amplify BL. With BLN The voltage difference between them can ultimately lead to read errors and reduce the reliability of the memory device.

[0092] In some specific examples, to improve the efficiency of read operations, read operations can be performed simultaneously on multiple memory cells coupled to a word line. In this case, when only one memory cell stores data different from the data stored in the other memory cells, the problem of reduced sensing margin caused by parasitic capacitance between bit lines becomes more severe. For example, when the data to be read is "...1110111...", during the charge sharing phase, the voltage on the bit line coupled to the memory cell storing "0" needs to decrease, but the voltages on multiple adjacent bit lines will increase. The coupling effect between bit lines will significantly suppress the decreasing trend of the voltage on that bit line, resulting in a severe compression of the sensing margin, which may ultimately prevent the "0" from being read. Similarly, when the data to be read is "...0001000...", during the charge sharing phase, the voltage on the bit line coupled to the memory cell storing "1" needs to rise, but the voltage on multiple bit lines adjacent to this bit line will drop. The coupling effect between bit lines will greatly suppress the rising trend of the voltage on this bit line, which will severely compress the sensing margin and may ultimately make it impossible to read "1".

[0093] Therefore, in order to improve the reliability of memory device read operations, it is necessary to minimize the negative impact of parasitic capacitance between bit lines on sensing margin. To this end, the present disclosure proposes the following implementation methods.

[0094] This disclosure provides a memory device, Figure 10 This is a schematic diagram showing the arrangement of various structures in a memory device according to an embodiment of the present disclosure in a first direction. (Referring to...) Figure 7 and Figure 10 The memory device includes a first semiconductor structure 200 and a second semiconductor structure 300 stacked along a first direction. The first semiconductor structure 200 includes a memory array 201, a plurality of bit lines 205 coupled to the memory array 201, a first conductive interconnect layer 500, and a second conductive interconnect layer 600. The second conductive interconnect layer 600 is located between the first conductive interconnect layer 500 and the second semiconductor structure 300 in the first direction. The second semiconductor structure 300 includes a plurality of sense amplifiers 302. Here, both the first conductive interconnect layer 500 and the second conductive interconnect layer 600 are located in the first interconnect layer 210 of the first semiconductor structure 200. In addition, the first interconnect layer 210 may also include other conductive interconnect layers.

[0095] It should be noted that, Figure 10 The diagram only shows the relative positional relationship of the various structures in the memory device in a first direction, and is not intended as a limitation on the shape or size of the various structures in the memory device.

[0096] In some embodiments, in conjunction with reference Figure 7 and Figure 10 The memory device further includes: a bonding layer 400 located between the first semiconductor structure 200 and the second semiconductor structure 300; the bonding layer 400 includes a bonding structure 401; the bonding structure 401 is coupled to a dominant wire in the first conductive connection layer 500, or the bonding structure 401 is coupled to a dominant wire in the second conductive connection layer 600; the coupling path between the bit line 205 and the sense amplifier 302 includes the bonding structure 401.

[0097] In some embodiments, the second semiconductor structure 300 further includes: a fourth conductive connection layer 700 located between the plurality of sense amplifiers 302 and the bonding layer 400; the bonding structure 401 is coupled to conductive lines in the fourth conductive connection layer 700, and the conductive lines in the fourth conductive connection layer 700 are coupled to the sense amplifiers 302; the coupling path between the bit line 205 and the sense amplifiers 302 includes the conductive lines in the fourth conductive connection layer 700. Here, the fourth conductive connection layer 700 may be at least one conductive connection layer in the second interconnect layer 310.

[0098] In some embodiments, the dominant wire in the coupling path between one of the two bit lines 205 coupled to a sensing amplifier 302 and the sensing amplifier 302 is located in a first conductive connection layer 500, while the dominant wire in the coupling path between the other of the two bit lines 205 coupled to the sensing amplifier 302 and the sensing amplifier 302 is located in a second conductive connection layer 600. Here, the extension dimension of the dominant wire in the coupling path between the bit line 205 and the sensing amplifier 302 in the direction perpendicular to the first direction is greater than the extension dimension of the other conductive lines in the coupling path in the direction perpendicular to the first direction.

[0099] It should be noted that, in this embodiment, the conductive lines located in the same conductive connection layer are at substantially the same height in the first direction, and the coupling path between the bit line 205 and the sensing amplifier 302 may include multiple conductive lines located in different conductive connection layers. The dimensions of the conductive lines include their length, width, and thickness. The thickness direction of the conductive line is the first direction. The length direction of the conductive line, i.e., the extension direction of the conductive line, can be any direction perpendicular to the first direction, and the extension directions of different conductive lines can be different, but all are perpendicular to the first direction. The width direction of the conductive line is perpendicular to its length direction, and the width of the conductive line is less than its length. The dimension of the conductive line in its extension direction is the extension dimension of the conductive line in the direction perpendicular to the first direction, which is also the length of the conductive line. The dominant line in the coupling path is the conductive line with the largest extension dimension in the direction perpendicular to the first direction among the multiple conductive lines in the coupling path, i.e., the longest conductive line.

[0100] The connection relationships between bit lines, main power lines, and sense amplifiers in the memory device provided in this disclosure will now be described with reference to specific examples.

[0101] Figure 11 This is a schematic diagram illustrating the connection of bit lines, dominant wires, and a sensing amplifier in a memory device according to an embodiment of this disclosure. The memory array includes a first memory block Block 1, a second memory block Block 0, and a third memory block Block 2. The first memory block Block 1 is located between the second memory block Block 0 and the third memory block Block 2 in a second direction. The coupling path between the bit line 205 and the sensing amplifier 302 includes a dominant wire 501 located in a first conductive connection layer or a dominant wire 601 located in a second conductive connection layer. Here, for ease of observation, the dominant wire 501 in the first conductive connection layer is shown as a perspective view.

[0102] In some embodiments, the first semiconductor structure 200 further includes: a first conductive structure 211 extending along a first direction, one end of which is connected to a bit line 205 at opposite ends along the first direction, and the other end of which is coupled to a dominant wire 501 in a first conductive connection layer; and a second conductive structure 212 extending along the first direction, one end of which is connected to the bit line 205 at opposite ends along the first direction, and the other end of which is coupled to a dominant wire 601 in a second conductive connection layer. Here, either the first conductive structure 211 or the second conductive structure 212 can be connected to one end of the bit line 205 at opposite ends in a second direction, and the bit line 205 can be coupled to the dominant wire 501 in the first conductive connection layer via the first conductive structure 211 or to the dominant wire 601 in the second conductive connection layer via the second conductive structure 212.

[0103] In some embodiments, the dominant wire 501 in the first conductive interconnect layer extends along the second direction and is arranged along the third direction, and the dominant wire 601 in the second conductive interconnect layer extends along the second direction and is arranged along the third direction. Furthermore, the opposite ends of the dominant wire in the second direction can be connected to two conductive structures extending along the first direction, respectively. One conductive structure can couple the dominant wire to the bit line 205, and the other conductive structure can couple the dominant wire to the sensing amplifier 302. That is, the electrical signal transmitted to the sensing amplifier 302 via the bit line 205 will be transmitted from one end of the dominant wire to the other end in the second direction.

[0104] In some embodiments, the dominant wire 501 in the first conductive interconnect layer coupled to a sensing amplifier 302 and the dominant wire 601 in the second conductive interconnect layer are arranged along a first direction.

[0105] In this embodiment, the extension and arrangement of the dominant wire 501 in the first conductive connection layer and the extension and arrangement of the dominant wire 601 in the second conductive connection layer are similar to the extension and arrangement of the plurality of bit lines 205. The dominant wire 501 in the first conductive connection layer and the dominant wire 601 in the second conductive connection layer, which are coupled to a sensing amplifier 302, are arranged along a first direction, which is beneficial to setting the dominant wires without increasing the area of ​​the memory device.

[0106] In some embodiments, the plurality of bit lines 205 include a first bit line 2051 coupled to the first memory block Block 1. Here, two first bit lines 2051 coupled to the first memory block Block 1 that are adjacent in the third direction are taken as an example. The dominant wire in the coupling path between one of the two adjacent first bit lines 2051 in the third direction and the sense amplifier 302 is located in the first conductive connection layer 500, that is, it can be the dominant wire 501 in the first conductive connection layer. The dominant wire in the coupling path between the other of the two adjacent first bit lines 2051 in the third direction and the sense amplifier 302 is located in the second conductive connection layer 600, that is, it can be the dominant wire 601 in the second conductive connection layer.

[0107] In some embodiments, the plurality of bit lines 205 further include a plurality of third bit lines 2053 coupled to the second memory block Block 0. A first bit line 2051 and a third bit line 2053 are coupled to the same sense amplifier 302. For the first bit line 2051 and the third bit line 2053 coupled to the same sense amplifier 302, the dominant wire in the coupling path between the first bit line 2051 and the sense amplifier 302 and the dominant wire in the coupling path between the third bit line 2053 and the sense amplifier 302 are located in different conductive interconnect layers. For example, when the first bit line 2051 is coupled to the third bit line 2053, the dominant wire in the coupling path between the first bit line 2051 and the sense amplifier 302 is coupled to the third bit line 2053. When the dominant wire in the coupling path between bit line 2051 and sensing amplifier 302 is the dominant wire 501 in the first conductive connection layer, the dominant wire in the coupling path between the third bit line 2053 and sensing amplifier 302 is the dominant wire 601 in the second conductive connection layer; when the dominant wire in the coupling path between the first bit line 2051 and sensing amplifier 302 is the dominant wire 601 in the second conductive connection layer, the dominant wire in the coupling path between the third bit line 2053 and sensing amplifier 302 is the dominant wire 501 in the first conductive connection layer.

[0108] In some embodiments, the plurality of bit lines 205 further include a plurality of second bit lines 2052 coupled to the first bit line 2051 in the third direction. The dominant wire in the coupling path between one of the two adjacent second bit lines 2052 in the third direction and the sense amplifier 302 is located in the first conductive connection layer 500, and the dominant wire in the coupling path between the other of the two adjacent second bit lines 2052 in the third direction and the sense amplifier 302 is located in the second conductive connection layer 600.

[0109] In some embodiments, the plurality of bit lines also include a plurality of fourth bit lines 2054 coupled to the third memory block Block2, and a second bit line 2052 and a fourth bit line 2054 are coupled to the same sense amplifier 302.

[0110] In this embodiment of the present disclosure, the first bit line 2051 and the second bit line 2052 coupled to the first memory block Block 1 are arranged alternately in the third direction, and the conductive structure connected to the first bit line 2051 is close to the second memory block Block 0, and the conductive structure connected to the second bit line 2052 is close to the third memory block Block 2. One first bit line 2051 and one third bit line 2053 coupled to the second memory block Block 0 are coupled to the same sense amplifier 302, and one second bit line 2052 and one fourth bit line 2054 coupled to the third memory block Block 2 are coupled to the same sense amplifier 302.

[0111] In some specific examples, the sensing amplifier 302 coupled to the first bit line 2051 is stacked with the first memory block Block 1 in the first direction, and the sensing amplifier 302 coupled to the second bit line 2052 is stacked with the third memory block Block 2 in the first direction. As a result, the extension dimensions of other conductive lines in the coupling path between the bit line 205 and the sensing amplifier 302 can be minimized.

[0112] In some specific examples, taking the first storage block Block1 as the selected storage block in the read operation as an example, the third bit line 2053 coupled to the second storage block Block0 can be the complementary bit line of the first bit line 2051, and the fourth bit line 2054 coupled to the third storage block Block2 can be the complementary bit line of the second bit line 2052.

[0113] Figure 12 and Figure 13 A schematic diagram of the arrangement of the main conductors coupled to the first and third conductors is provided as a specific example, wherein, Figure 13 for Figure 12 Schematic diagram of the cross section along line AA', BL <1> BL <3> BL <5> and BL <7> Both are first-line 2051, BLN <1> BLN <3> BLN <5> and BLN <7> Both are third bit lines 2053. For the first bit line 2051 and third bit line 2053 coupled to the same sense amplifier 302, for example BL... <1> and BLN <1> The dominant wire coupled to the first line 2051 and the dominant wire coupled to the third line 2053 are located in different conductive connection layers; for two first lines 2051 adjacent in the third direction, the dominant wire coupled to one first line 2051 and the dominant wire coupled to the other first line 2051 are located in different conductive connection layers, for example, with BL <1> Coupled main wire and with BL <3> The coupled main conductors are located in the first conductive connection layer 500 and the second conductive connection layer 600, respectively; a main conductor coupled to the first main conductor 2051 and a main conductor coupled to the third main conductor 2053 are located in the same conductive connection layer and are adjacent to each other in the third direction, for example, with BL. <3> Coupled main wire and with BLN <1> The main conductive wires of the coupling are all located in the second conductive connection layer 600, and are connected to the BLN. <1> BL coupled to the same sense amplifier <1> BL <3> If it is adjacent to the third party upwards, then it is in relation to BL. <3> Coupled main wire and with BLN <1> Parasitic capacitance can be generated between the coupled main wires.

[0114] Figure 14 and Figure 15 A schematic diagram of the arrangement of the main conductors coupled to the first and third conductors is provided as a specific example, wherein, Figure 15 for Figure 14 Schematic diagram of the cross section along line BB', BL <0> BL <2> BL <4> and BL <6> Both are second-line 2052, BLN <0> BLN <2> BLN <4> and BLN <6> Both are the fourth bit line 2054. For the second bit line 2052 and the fourth bit line 2054 coupled to the same sense amplifier 302, for example BL... <0> and BLN <0> The dominant wire coupled to the second bit line 2052 and the dominant wire coupled to the fourth bit line 2054 are located in different conductive connection layers; for two second bit lines 2052 adjacent in the third direction, the dominant wire coupled to one second bit line 2052 and the dominant wire coupled to the other second bit line 2052 are located in different conductive connection layers, for example, with BL <0> Coupled main wire and with BL <2> The coupled main conductors are located in the first conductive connection layer 500 and the second conductive connection layer 600, respectively; a main conductor coupled to the second bit line 2052 and a main conductor coupled to the fourth bit line 2054 are located in the same conductive connection layer and are adjacent to each other in the third direction, for example, with BL. <2> Coupled main wire and with BLN <0> The main conductors of the coupling are all located in the second conductive connection layer 600 and are adjacent to each other on the third upward side. Therefore, in relation to BL... <2> Coupled main wire and with BLN <0> Parasitic capacitance can be generated between the coupled main wires.

[0115] Based on the specific examples above, in this embodiment of the disclosure, with a first line (e.g., BL) <x>) Coupled to the third bit line of the same sense amplifier (e.g., BLN) <x>The dominant wire in the coupling path between the sensor amplifier and the sensing amplifier can be connected to another first wire (e.g., BL).<x+2> The dominant wires in the coupling path between the sensor amplifier and the first conductor are located in the same conductive interconnect layer and are adjacent to each other on the third side upwards. Therefore, it is possible to utilize the first conductor (BL) with another first conductor.<x+2> The main conductor coupled with the third conductor (BLN) <x>Parasitic capacitance between coupled main conductors compensates for adjacent first conductors (BL). <x>) and the second bit line (e.g., BL)<x+1> Parasitic capacitance between ) . Similarly, with a second bit line (e.g., BL<x+1> ) Coupled to the fourth bit line of the same sense amplifier (e.g., BLN)<x+1> The dominant wire in the coupling path between the sensor amplifier and the sensing amplifier can be connected to another second bit line (e.g., BL).<x+3> The dominant wires in the coupling path between the sensor amplifier and the second bit line are located in the same conductive interconnect layer and are adjacent to each other on the third side upwards. Therefore, it is possible to utilize the second bit line (BL) with the second bit line.<x+3> The main conductor coupled to the fourth bit (BLN)<x+1> Parasitic capacitance between coupled main conductors compensates for adjacent first conductors (BL). <x>) and the second line (BL)<x+1> The parasitic capacitance between adjacent bit lines is reduced. Therefore, the memory device provided in this disclosure can reduce the degree of decrease in sensing margin caused by parasitic capacitance between adjacent bit lines, resulting in higher reliability.

[0116] Figure 16 This is a schematic diagram of the voltage on the bit line during the read operation provided in this embodiment of the disclosure, in conjunction with BL. <x>The selected coupled memory cell stores "0" as its data, and is associated with BL.<x+1> Coupled selected memory cell and BL<x+2> Taking the selected coupled memory cell as an example where all the data stored is "1", during the charge sharing phase S1, BL <x>The voltage on BL drops.<x+1> The voltage and BL<x+2> The voltages on all rise due to the adjacent BL on the third side upwards. <x>BL<x+1> The coupling effect caused by the parasitic capacitance between them may suppress BL <x>The drop in voltage on BL caused <x>The rate of voltage drop on BL decreases. <x>With BLN <x>The sensing margin between them may be compressed to M3. However, in the memory device provided in this disclosure, due to BLN... <x>The dominant wire and BL in the coupling path between the sensor amplifier and the sensor amplifier<x+2> The dominant wires in the coupling path between the sensor amplifier and the BLN are located in the same conductive interconnect layer and are adjacent in a third direction. The coupling effect caused by the parasitic capacitance between them can make the BLN... <x>The voltage on it rises, thus allowing BL to <x>With BLN <x>The sensing margin between them is compensated to M4, so that BL <x>With BLN <x>There is still a large sensing margin between them. During the sensing phase S2, the sensing amplifier can still output BL. <x>With BLN <x>The voltage difference between them can be amplified to the point that it can be compared with BL. <x>The degree to which data stored in coupled memory cells can be correctly read can improve the reliability of memory devices.

[0117] In some embodiments, Figure 17 This is a schematic diagram of the arrangement of the main conductors coupled to the first and third position lines according to an embodiment of the present disclosure. Figure 2 The first semiconductor structure 200 further includes a third conductive connection layer 800 located between the first conductive connection layer 500 and the second conductive connection layer 600; the coupling path between one of the two bit lines coupled to a sensing amplifier and the sensing amplifier also includes a conductive line 801 in the third conductive connection layer, and the coupling path between the other of the two bit lines coupled to the sensing amplifier also includes a conductive line 801 in the third conductive connection layer. Here, the conductive line 801 in the third conductive connection layer can act as a jumper. Specifically, when using the parasitic capacitance between adjacent dominant wires 501 in the first conductive connection layer or between adjacent dominant wires 601 in the second conductive connection layer to compensate for the parasitic capacitance between adjacent bit lines, the limited length of the dominant wires may result in insufficient parasitic capacitance between the dominant wires to compensate for the parasitic capacitance between adjacent bit lines. In this case, the parasitic capacitance between the conductive lines 801 in the third conductive connection layer can also be used to compensate for the parasitic capacitance between adjacent bit lines. In addition, some of the conductive lines in the third conductive connection layer 800 can also serve as signal shielding, preventing large parasitic capacitances from being generated between the main conductor 501 in the first conductive connection layer and the conductive line 601 in the second conductive connection layer.

[0118] Based on a concept similar to the memory devices described above, this disclosure also provides a memory system including at least one memory device from any of the above embodiments and a controller, wherein the controller is coupled to the memory device and configured to control the memory device. The composition and function of the memory system can be referred to the foregoing embodiments. Figure 1 The description will not be repeated here.

[0119] Based on a concept similar to the memory device described above, this disclosure also provides a method for forming a memory device. Figure 18 This is a schematic flowchart of a method for forming a memory device according to an embodiment of the present disclosure. The method for forming a memory device includes the following steps:

[0120] S10: Forming a first semiconductor structure, including: forming a memory array, a plurality of bit lines coupled to the memory array, a first conductive connection layer and a second conductive connection layer;

[0121] S20: Forming a second semiconductor structure, including: forming a plurality of sense amplifiers;

[0122] S30: The first semiconductor structure and the second semiconductor structure are stacked and arranged along a first direction; the second conductive connection layer is located between the first conductive connection layer and the second semiconductor structure in the first direction; one of the sensing amplifiers is coupled to two bit lines, and the dominant wire in the coupling path between one of the two bit lines coupled to the sensing amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two bit lines coupled to the sensing amplifier is located in the second conductive connection layer.

[0123] In this embodiment of the disclosure, the extension dimension of the dominant wire in the coupling path in the direction perpendicular to the first direction is greater than the extension dimension of the other conductive wires in the coupling path in the direction perpendicular to the first direction.

[0124] In some embodiments, a plurality of bit lines are located between the memory array and the first conductive interconnect layer in a first direction; the plurality of bit lines extend along a second direction and are arranged along the second direction and a third direction; the second direction is perpendicular to the third direction and is also perpendicular to the first direction.

[0125] In some embodiments, forming a memory array includes: forming a first memory block; forming a plurality of bit lines includes: forming a plurality of first bit lines coupled to the first memory block; the dominant wire in the coupling path between one of two third-adjacent first bit lines and a sense amplifier is located in a first conductive interconnect layer, and the dominant wire in the coupling path between the other of two third-adjacent first bit lines and the sense amplifier is located in a second conductive interconnect layer.

[0126] In some embodiments, forming a plurality of bit lines further includes: forming a plurality of second bit lines coupled to a first memory block; the second bit lines are arranged alternately with the first bit lines in a third-order direction; the dominant wire in the coupling path between one of the two adjacent second bit lines in the third-order direction and the sense amplifier is located in a first conductive connection layer, and the dominant wire in the coupling path between the other of the two adjacent second bit lines in the third-order direction and the sense amplifier is located in a second conductive connection layer.

[0127] In some embodiments, forming the memory array further includes: forming a second memory block and a third memory block; a first memory block being located between the second memory block and the third memory block in a second direction; the plurality of bit lines further includes a plurality of third bit lines coupled to the second memory block and a plurality of fourth bit lines coupled to the third memory block; a first bit line and a third bit line being coupled to the same sense amplifier; a second bit line and a fourth bit line being coupled to the same sense amplifier.

[0128] In some embodiments, forming the first semiconductor structure further includes: before forming the first conductive connection layer and the second conductive connection layer, forming a first conductive structure extending along a first direction and a second conductive structure extending along a first direction; one end of the first conductive structure at opposite ends along the first direction is connected to a bit line, and one end of the second conductive structure at opposite ends along the first direction is connected to a bit line; after forming the first conductive connection layer and the second conductive connection layer, the other end of the first conductive structure at opposite ends along the first direction is coupled to a dominant wire in the first conductive connection layer, and the other end of the second conductive structure at opposite ends along the first direction is coupled to a dominant wire in the second conductive connection layer.

[0129] In some embodiments, forming the first semiconductor structure further includes: forming a third conductive connection layer; the third conductive connection layer is located between the first conductive connection layer and the second conductive connection layer; the coupling path between one of the two bit lines coupled to a sense amplifier and the sense amplifier further includes a conductive line in the third conductive connection layer, and the coupling path between the other of the two bit lines coupled to a sense amplifier and the sense amplifier further includes a conductive line in the third conductive connection layer.

[0130] In some embodiments, the method of forming a memory device further includes: forming a bonding layer between a first semiconductor structure and a second semiconductor structure; the bonding layer includes a bonding structure; the bonding structure is coupled to a dominant wire in a first conductive interconnect layer, or the bonding structure is coupled to a dominant wire in a second conductive interconnect layer; the coupling path between a bit line and a sense amplifier includes a bonding structure.

[0131] In some embodiments, forming the second semiconductor structure further includes: forming a fourth conductive connection layer; the fourth conductive layer is located on one side of a plurality of sense amplifiers in a first direction; conductive lines in the fourth conductive layer are coupled to the sense amplifiers, and bonding structures are coupled to the conductive lines in the fourth conductive connection layer; the coupling path between the bit lines and the sense amplifiers includes the conductive lines in the fourth conductive connection layer.

[0132] In some embodiments, forming a memory array includes: forming memory cells arranged in an array along a second direction and a third direction; the memory cells include a transistor structure and a capacitor structure coupled to the transistor structure.

[0133] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0134] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0135] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.< / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. A memory device, characterized in that, It includes a first semiconductor structure and a second semiconductor structure stacked along a first direction; wherein, The first semiconductor structure includes a memory array, a plurality of bit lines coupled to the memory array, a first conductive connection layer and a second conductive connection layer; the second conductive connection layer is located between the first conductive connection layer and the second semiconductor structure in the first direction; The second semiconductor structure includes a plurality of sense amplifiers; one of the sense amplifiers is coupled to two bit lines, and the dominant wire in the coupling path between one of the two bit lines coupled to the sense amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two bit lines coupled to the sense amplifier is located in the second conductive connection layer; the extension dimension of the dominant wire in the coupling path in the direction perpendicular to the first direction is greater than the extension dimension of the other conductive lines in the coupling path in the direction perpendicular to the first direction.

2. The memory device according to claim 1, characterized in that, The plurality of bit lines are located between the memory array and the first conductive interconnect layer in the first direction; the plurality of bit lines extend along the second direction and are arranged along the second direction and the third direction; the second direction is perpendicular to the third direction and is also perpendicular to the first direction; The storage array includes a first storage block; the plurality of bit lines include a plurality of first bit lines coupled to the first storage block; the dominant wire in the coupling path between one of the two first bit lines adjacent to the third-order upward and the sense amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two first bit lines adjacent to the third-order upward and the sense amplifier is located in the second conductive connection layer.

3. The memory device according to claim 1, characterized in that, The dominant wires in the first conductive connection layer and the dominant wires in the second conductive connection layer, which are coupled to one of the sensing amplifiers, are arranged along the first direction.

4. The memory device according to claim 2, characterized in that, The plurality of bit lines also include a plurality of second bit lines coupled to the first memory block; the second bit lines are arranged alternately with the first bit lines in the third direction; The dominant wire in the coupling path between one of the two adjacent second bit lines in the third direction and the sense amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two adjacent second bit lines in the third direction and the sense amplifier is located in the second conductive connection layer.

5. The memory device according to claim 4, characterized in that, The storage array also includes: A second memory block and a third memory block; the first memory block is located between the second memory block and the third memory block in the second direction; the plurality of bit lines further include a plurality of third bit lines coupled to the second memory block and a plurality of fourth bit lines coupled to the third memory block; one first bit line and one third bit line are coupled to the same sense amplifier; one second bit line and one fourth bit line are coupled to the same sense amplifier.

6. The memory device according to claim 5, characterized in that, The sensing amplifier coupled to the first bit line is stacked with the first memory block in the first direction; the sensing amplifier coupled to the second bit line is stacked with the third memory block in the first direction.

7. The memory device according to claim 1, characterized in that, The first semiconductor structure further includes: A first conductive structure extending along the first direction, one end of the first conductive structure at opposite ends along the first direction being connected to the bit line, and the other end of the first conductive structure at opposite ends along the first direction being coupled to the main wire in the first conductive connection layer. A second conductive structure extending along the first direction, one end of which is opposite to the bit line along the first direction is connected to the bit line, and the other end of which is opposite to the bit line along the first direction is coupled to the main wire in the second conductive connection layer.

8. The memory device according to claim 1, characterized in that, The first semiconductor structure further includes: A third conductive connection layer is located between the first conductive connection layer and the second conductive connection layer; the coupling path between one of the two bit lines coupled to one of the sensing amplifiers and the sensing amplifier also includes a conductive line in the third conductive connection layer, and the coupling path between the other of the two bit lines coupled to one of the sensing amplifiers and the sensing amplifier also includes a conductive line in the third conductive connection layer.

9. The memory device according to claim 2, characterized in that, The memory device further includes: A bonding layer is located between the first semiconductor structure and the second semiconductor structure; the bonding layer includes a bonding structure; the bonding structure is coupled to a dominant wire in the first conductive connection layer, or the bonding structure is coupled to a dominant wire in the second conductive connection layer; the coupling path between the bit line and the sensing amplifier includes the bonding structure.

10. The memory device according to claim 9, characterized in that, The second semiconductor structure also includes: A fourth conductive connection layer is located between the plurality of sense amplifiers and the bonding layer; the bonding structure is coupled to the conductive lines in the fourth conductive connection layer, and the conductive lines in the fourth conductive connection layer are coupled to the sense amplifiers; the coupling path between the bit line and the sense amplifier includes the conductive lines in the fourth conductive connection layer.

11. The memory device according to claim 2, characterized in that, The storage array includes: Storage cells arranged in an array along the second direction and the third direction; the storage cells include a transistor structure and a capacitor structure coupled to the transistor structure.

12. A memory system, characterized in that, include: At least one memory as described in any one of claims 1 to 11; A controller is coupled to at least one of the memories and configured to control the memory device.

13. A method for forming a memory device, characterized in that, include: Forming a first semiconductor structure includes: forming a memory array, a plurality of bit lines coupled to the memory array, a first conductive interconnect layer, and a second conductive interconnect layer; Forming a second semiconductor structure includes: forming a plurality of sense amplifiers; The first semiconductor structure and the second semiconductor structure are stacked along a first direction; the second conductive connection layer is located between the first conductive connection layer and the second semiconductor structure in the first direction; one of the sensing amplifiers is coupled to two bit lines, and the dominant wire in the coupling path between one of the two bit lines coupled to the sensing amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two bit lines coupled to the sensing amplifier is located in the second conductive connection layer; the extension dimension of the dominant wire in the coupling path in the direction perpendicular to the first direction is greater than the extension dimension of the other conductive lines in the coupling path in the direction perpendicular to the first direction.

14. The method for forming a memory device according to claim 13, characterized in that, The plurality of bit lines are located between the memory array and the first conductive interconnect layer in the first direction; the plurality of bit lines extend along the second direction and are arranged along the second direction and the third direction. The second direction is perpendicular to the third direction, and both are perpendicular to the first direction; The formation of the storage array includes: forming a first storage block; The formation of the plurality of bit lines includes: forming a plurality of first bit lines coupled to the first memory block; the dominant wire in the coupling path between one of the two first bit lines adjacent to the third upward is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two first bit lines adjacent to the third upward is located in the second conductive connection layer.

15. The method for forming a memory device according to claim 14, characterized in that, The formation of multiple bit lines also includes: A plurality of second bit lines are formed that are coupled to the first memory block; the second bit lines are arranged alternately with the first bit lines in the third direction; the dominant wire in the coupling path between one of the two adjacent second bit lines in the third direction and the sense amplifier is located in the first conductive connection layer, and the dominant wire in the coupling path between the other of the two adjacent second bit lines in the third direction and the sense amplifier is located in the second conductive connection layer.

16. The method of forming a memory device according to claim 15, characterized in that, The formation of the storage array also includes: A second memory block and a third memory block are formed; the first memory block is located between the second memory block and the third memory block in the second direction; the plurality of bit lines further include a plurality of third bit lines coupled to the second memory block and a plurality of fourth bit lines coupled to the third memory block; one first bit line and one third bit line are coupled to the same sense amplifier; one second bit line and one fourth bit line are coupled to the same sense amplifier.

17. The method of forming a memory device according to claim 13, characterized in that, The formation of the first semiconductor structure also includes: Before forming the first conductive connection layer and the second conductive connection layer, a first conductive structure extending along the first direction and a second conductive structure extending along the first direction are formed; one end of the first conductive structure at opposite ends along the first direction is connected to a bit line, and one end of the second conductive structure at opposite ends along the first direction is connected to a bit line. After the first conductive connection layer and the second conductive connection layer are formed, one end of the opposite ends of the first conductive structure along the first direction is coupled to the dominant wire in the first conductive connection layer, and the other end of the opposite ends of the second conductive structure along the first direction is coupled to the dominant wire in the second conductive connection layer.

18. The method of forming a memory device according to claim 13, characterized in that, The formation of the first semiconductor structure also includes: A third conductive connection layer is formed; the third conductive connection layer is located between the first conductive connection layer and the second conductive connection layer; the coupling path between one of the two bit lines coupled to one of the sensing amplifiers and the sensing amplifier also includes a conductive line in the third conductive connection layer, and the coupling path between the other of the two bit lines coupled to one of the sensing amplifiers and the sensing amplifier also includes a conductive line in the third conductive connection layer.

19. The method of forming a memory device according to claim 13, characterized in that, The method for forming the memory device further includes: A bonding layer is formed between the first semiconductor structure and the second semiconductor structure; the bonding layer includes a bonding structure; the bonding structure is coupled to a dominant wire in the first conductive connection layer, or the bonding structure is coupled to a dominant wire in the second conductive connection layer; the coupling path between the bit line and the sense amplifier includes the bonding structure.

20. The method for forming a memory device according to claim 19, characterized in that, The formation of the second semiconductor structure also includes: A fourth conductive connection layer is formed; the fourth conductive layer is located on one side of the plurality of sense amplifiers in the first direction; the conductive lines in the fourth conductive layer are coupled to the sense amplifiers, and the bonding structure is coupled to the conductive lines in the fourth conductive connection layer; the coupling path between the bit line and the sense amplifier includes the conductive lines in the fourth conductive connection layer.

21. The method of forming a memory device according to claim 14, characterized in that, The formation of the storage array includes: A memory cell array is formed along the second direction and the third direction; the memory cell includes a transistor structure and a capacitor structure coupled to the transistor structure.

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