Flip chip silver mirror light emitting diode chip and method of manufacturing the same

Abstract

The application discloses a flip silver mirror light emitting diode chip and a preparation method thereof, and relates to the technical field of semiconductors. According to the application, a first annular groove is formed on a Bragg reflection layer, and a region surrounded by the first annular groove forms a first protruding part. When a P-type first insulating layer via hole is prepared subsequently, the thickness of photoresist of an edge region of the P-type first insulating layer via hole can be improved in a targeted manner, so that the etching resistance of the photoresist of the edge of the P-type first insulating layer via hole is improved. In the process of ICP etching for preparing the P-type first insulating layer via hole, the defects of sawtooth deformation and optical heterochromia of the edge region of the P-type first insulating layer via hole can be effectively improved, so that the AOI detection yield of the flip silver mirror light emitting diode chip is significantly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a flip-chip silver mirror light-emitting diode chip and its fabrication method. Background Technology

[0002] In the field of semiconductor lighting technology, flip-chip light-emitting diodes (LEDs) have attracted much attention due to their unique structural design and performance advantages. Their back-emitting light characteristic optimizes the light output path and improves light extraction efficiency; excellent heat dissipation effectively reduces the chip's operating temperature, ensuring stable device operation; good solderability, high thrust, and high reliability enable them to exhibit outstanding adaptability and stability in the assembly and long-term use of various electronic devices, thus leading to their widespread application in numerous fields.

[0003] A flip-chip LED typically includes a substrate, an epitaxial wafer, a P-electrode, and an N-electrode. The epitaxial wafer comprises an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a Bragg mirror, a metal reflective layer, a first insulating layer, an N-type connection metal layer, a P-type connection metal layer, and a second insulating layer, all stacked on the substrate. During the fabrication of the flip-chip LED, after the first insulating layer is prepared, N-type and P-type vias are etched into it. This allows the P-type connection metal layer to be electrically connected to the metal reflective layer through the vias, and the N-type connection metal layer to be electrically connected to the N-type semiconductor layer through the vias.

[0004] Currently, the industry commonly uses inductively coupled plasma (ICP) etching to fabricate N-type and P-type first insulating layer vias. The process includes the following steps: coating a photoresist layer on the surface of the first insulating layer; then removing a portion of the photoresist to form P-type and N-type photoresist layer openings, exposing the insulating layer at the locations corresponding to the pre-set N-type and P-type first insulating layer vias; then using ICP etching to remove the insulating layer at the exposed locations, followed by photoresist removal, thus forming the N-type and P-type first insulating layer vias. However, since the first insulating layer is generally made of Al2O3, the etching rate of the photoresist is greater than that of the first insulating layer during the etching process. Furthermore, due to the large height difference between the positions of the preset N-type and P-type first insulating layer vias, the photoresist thickness around the openings in the traditional P-type photoresist layer is relatively thin. This causes the edges of the traditional P-type photoresist layer openings to thin rapidly during the etching process, resulting in a decrease in the blocking ability of the edges of the P-type photoresist layer openings. Consequently, after the etching is completed, the hole walls of the P-type first insulating layer vias will exhibit over-etching, making it easy for the hole walls of the P-type first insulating layer vias to form serrations or optical discoloration. This leads to a low AOI (automatic optical inspection) yield of the resulting flip-chip LED chips. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a flip-chip silver mirror light-emitting diode chip and its preparation method, which can improve the defects of sawtooth deformation and optical discoloration in the edge region of the P-type first insulating layer via, thereby improving the AOI inspection yield of the flip-chip silver mirror light-emitting diode chip.

[0006] To address the aforementioned technical problems, this invention provides a method for fabricating a flip-chip silver mirror light-emitting diode, comprising the following steps: (1) Provide a substrate having an epitaxial layer; (2) A Bragg reflector layer is formed on the epitaxial layer; (3) A first annular groove is formed at a predetermined position on the Bragg reflector layer; wherein, the area of ​​the Bragg reflector layer surrounded by the first annular groove forms a first protrusion; (4) A metal reflective layer is deposited on the surface of the Bragg reflective layer, wherein a second annular groove is formed at the position corresponding to the first annular groove and a second protrusion is formed at the position corresponding to the first protrusion. (5) A first insulating layer is deposited on the surface of the metal reflective layer and the Bragg reflective layer not covered by the metal reflective layer; the first insulating layer forms a third annular groove at the position corresponding to the second annular groove and a third protrusion at the position corresponding to the second protrusion, so that there is a height difference between the bottom end of the third annular groove and the top end of the third protrusion. (6) Photoresist is applied to the surface of the first insulating layer and the third annular groove to form a photoresist layer. The upper surface of the photoresist layer is a flat surface so that the thickness of the photoresist on the third annular groove is greater than the thickness of the photoresist on the surface of the third protrusion. (7) A P-type photoresist layer opening is formed in the photoresist layer to expose the top surface of the third protrusion, and the third annular groove surrounds the outer periphery of the P-type photoresist layer opening; (8) Etch away the third protrusion exposed in the opening of the P-type photoresist layer, remove the photoresist, and form a P-type first insulating layer through hole.

[0007] As an improvement to the above technical solution, in step (7), the shape of the bottom opening of the P-type photoresist layer aperture corresponds to the shape of the top surface of the third protrusion; The distance between the edge of the bottom opening of the P-type photoresist layer aperture and the edge of the top surface of the third protrusion is ≤50nm; The depth of the first annular groove is ≥ 80% of the thickness of the Bragg reflective layer.

[0008] As an improvement to the above technical solution, the top width of the first annular groove is 3μm~5μm, and the bottom width of the first annular groove is 2μm~4μm.

[0009] As an improvement to the above technical solution, the included angle between the sidewall of the first annular groove and the horizontal plane is 30°~60°.

[0010] As an improvement to the above technical solution, in step (8), an inductively coupled plasma etching process is used to etch away the third protrusion exposed in the opening of the P-type photoresist layer to form a P-type first insulating layer via; wherein, the etching gas is CF4, the flow rate of CF4 is 10sccm~30sccm; the upper etching power is 400W~500W, and the lower etching power is 150W~280W.

[0011] As an improvement to the above technical solution, in step (5), the material of the first insulating layer is Al2O3, and the thickness is 600Å~1500Å.

[0012] As an improvement to the above technical solution, the thickness of the Bragg reflector layer is 5000Å~10000Å.

[0013] As an improvement to the above technical solution, the Bragg reflector layer is further provided with P-type Bragg reflector conductive vias and N-type Bragg reflector conductive vias; in step (3), while forming P-type Bragg reflector conductive vias and N-type Bragg reflector conductive vias on the Bragg reflector layer, the first annular groove is formed at a preset position on the Bragg reflector layer.

[0014] Accordingly, the present invention also provides a flip-chip silver mirror light-emitting diode chip, which is prepared by the above-described method for preparing a flip-chip silver mirror light-emitting diode chip, comprising a substrate, an epitaxial layer, a Bragg reflective layer, a metal reflective layer and a first insulating layer; The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer. The active light-emitting layer is stacked on the surface of a predetermined region of the N-type semiconductor layer. An N-type conductive step is formed in the region of the N-type semiconductor layer not covered by the active light-emitting layer. The P-type semiconductor layer covers the surface of the active light-emitting layer. The Bragg reflector layer is stacked on the surface of the P-type semiconductor layer and the N-type conductive step. The Bragg reflector layer is provided with a first annular groove, and the area of ​​the Bragg reflector layer surrounded by the first annular groove forms a first protrusion. The metal reflective layer covers the surface of a predetermined area of ​​the Bragg reflective layer, and the metal reflective layer forms a second annular groove at the position corresponding to the first annular groove and a second protrusion at the position corresponding to the first protrusion. The metal reflective layer is partially electrically connected to the P-type semiconductor layer through the Bragg reflective layer. The first insulating layer covers the surface of the metal reflective layer and the Bragg reflective layer not covered by the metal reflective layer. The first insulating layer has a P-type first insulating layer through hole and an N-type first insulating layer through hole. The position of the P-type first insulating layer through hole corresponds to the position of the second protrusion, and the edge of the P-type first insulating layer through hole is located in the second annular groove. The N-type first insulating layer through hole extends to an N-type conductive step.

[0015] As an improvement to the above technical solution, the flip-chip silver mirror light-emitting diode chip further includes a current spreading layer, a current blocking layer, a P-type connection metal layer, an N-type connection metal layer, a second insulating layer, a P-type pad layer, and an N-type pad layer. The current spreading layer covers the surface of the P-type semiconductor layer; The current blocking layer covers the surface of the current spreading layer and the P-type semiconductor layer and N-type conductive step that are not covered by the current spreading layer. A portion of the metal reflective layer passes sequentially through the Bragg reflective layer and the current blocking layer, and is electrically connected to the current spreading layer. The P-type connecting metal layer and the N-type connecting metal layer respectively cover the surface of the first insulating layer; the P-type connecting metal layer contacts the metal reflective layer through the P-type first insulating layer through-hole; the N-type connecting metal layer contacts the N-type conductive step through the N-type first insulating layer through-hole. The second insulating layer covers the surface of the P-type connecting metal layer, the N-type connecting metal layer, and the surface of the first insulating layer not covered by the P-type connecting metal layer and the N-type connecting metal layer, and the second insulating layer provides insulation between the P-type connecting metal layer and the N-type connecting metal layer; The P-type pad layer and the N-type pad layer respectively cover the surface of the second insulating layer. The P-type pad layer is partially in contact with the P-type connection metal layer through the second insulating layer. The N-type pad layer is partially in contact with the N-type connection metal layer through the second insulating layer.

[0016] As an improvement to the above technical solution, the P-type connecting metal layer and the N-type connecting metal layer are obtained by sequentially evaporating Cr metal, Al metal, Ti metal, Pt metal, Ti metal, Pt metal, Ti metal, Au metal, Pt metal and Ti metal; The material of the second insulating layer is a SiO2 thin film; Both the P-type pad layer and the N-type pad layer include a first Ti metal layer, an Al metal layer, a second Ti metal layer, a Pt metal layer, a Ni metal layer, and an Au metal layer stacked sequentially. The thickness of the first Ti metal layer is 1000 Å to 2000 Å, the thickness of the Al metal layer is 10000 Å to 150000 Å, the thickness of the second Ti metal layer is 1000 Å to 2000 Å, the thickness of the Pt metal layer is 1000 Å to 2000 Å, the thickness of the Ni metal layer is 8000 Å to 12000 Å, and the thickness of the Au metal layer is 300 Å to 600 Å.

[0017] Implementing this invention has the following beneficial effects: This invention utilizes the height difference between the bottom of the third annular groove and the top of the third protrusion. When applying photoresist, the third annular groove can be fully filled with photoresist, making the thickness of the photoresist in this area significantly greater than the thickness of the photoresist on the surface of the third protrusion. This ensures that when a P-type photoresist layer opening is subsequently created above the third protrusion, the outer periphery of the P-type photoresist layer opening precisely corresponds to the thick photoresist area on the surface of the third annular groove, thereby specifically improving the etching resistance of the photoresist in the edge area of ​​the P-type photoresist layer opening. During the ICP etching process for fabricating P-type first insulating layer vias, even with the effects of photoresist sidewall etching thinning and etching process fluctuations, the sufficient photoresist thickness at the edge of the P-type first insulating layer via can still maintain a good etching barrier effect. Furthermore, through the structural design of the first annular groove, the edge of the formed P-type first insulating layer via wall falls within the range of the first annular groove, avoiding the problem of over-etching at the edge of the P-type first insulating layer via. This effectively improves defects such as sawtooth deformation and optical discoloration at the edge of the P-type first insulating layer via, thereby effectively improving the AOI inspection yield of flip-chip silver mirror light-emitting diode chips. Attached Figure Description

[0018] Figure 1 A schematic diagram of the structure after forming an opening in the P-type photoresist layer during the fabrication of a flip-chip silver mirror light-emitting diode using traditional methods; Figure 2 This is a schematic diagram of the structure of forming a current spreading layer on the epitaxial layer in the fabrication method of a flip-chip silver mirror light-emitting diode chip according to an embodiment of the present invention; Figure 3 Is Figure 2 A schematic diagram of a structure in which a current blocking layer and a Bragg reflector are formed; Figure 4 Is Figure 3 A schematic diagram of the structure with the first annular groove shown; Figure 5 Is Figure 4 The diagram shows a structure with P-type current blocking layer conductive vias and N-type current blocking layer conductive vias. Figure 6 Is Figure 5 A schematic diagram of a structure in which a metallic reflective layer is formed on the structure shown; Figure 7 Is Figure 6 A schematic diagram of the structure on which the first insulating layer is formed; Figure 8 Is Figure 7 The diagram shows a structure in which a photoresist layer is formed and P-type and N-type photoresist layer openings are made on the photoresist layer. Figure 9 Is Figure 8The diagram shows a structure with P-type and N-type first insulating layer vias and a photoresist layer removed. Figure 10 Is Figure 9 The diagram shows a structure in which a P-type connecting metal layer and an N-type connecting metal layer are formed. Figure 11 Is Figure 10 The diagram shows a structure in which a second insulating layer is formed and P-type and N-type openings are made in the second insulating layer. Figure 12 This is a schematic diagram of the structure of a flip-chip silver mirror light-emitting diode chip according to an embodiment of the present invention; Figure 13 yes Figure 12 A magnified view of part S of the flip-chip silver mirror light-emitting diode shown; The structure includes: substrate 10, epitaxial layer 11, current spreading layer 12, current blocking layer 13, Bragg reflector layer 14, metal reflector layer 15, first insulating layer 16, photoresist layer 17, P-type interconnect metal layer 181, N-type interconnect metal layer 182, second insulating layer 19, P-type pad layer 201, N-type pad layer 202, N-type semiconductor layer 111, active light emitting layer 112, P-type semiconductor layer 113, N-type conductive step 1111, P-type current blocking layer conductive via 131, and N-type current blocking layer. Conductive via 132, P-type Bragg reflector conductive via 141, N-type Bragg reflector conductive via 142, first annular groove 143, first protrusion 144, second annular groove 151, second protrusion 152, P-type first insulating layer via 161, N-type first insulating layer via 162, third annular groove 163, third protrusion 164, P-type photoresist layer opening 171, N-type photoresist layer opening 172, P-type second insulating layer opening 191, N-type second insulating layer opening 192. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0020] Where specific techniques or conditions are not specified in the embodiments, they shall be performed in accordance with the techniques or conditions described in the literature in this field or in accordance with the product instructions. Raw materials whose manufacturers are not specified are all conventional products that can be obtained commercially.

[0021] In the description of this application, it should be understood that the terms "thickness", "width", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features.

[0023] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on the surface" of the second feature include the first feature being directly above or diagonally above the second feature, or simply indicating that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature include the first feature being directly below or diagonally below the second feature, or simply indicating that the first feature is at a lower horizontal level than the second feature.

[0024] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0025] See Figure 1This diagram illustrates the creation of P-type and N-type photoresist layer openings 171 and 172 in a photoresist layer using conventional methods. Compared to the N-type photoresist layer opening 172, the photoresist thickness around the P-type photoresist layer opening 171 is thinner, and the etching rate of the photoresist during etching is greater than that of the first insulating layer. Although existing methods can prevent etching of areas other than the P-type and N-type photoresist layer openings 171 and 172 by setting the thickness of the photoresist layer to be greater than that of the first insulating layer, the photoresist layer openings formed after exposure and development are typically inverted trapezoidal in shape, with a thickness gradient at their edges. This is not an ideally vertical and steep structure, resulting in a thinner photoresist layer at the edges of the openings, especially at the edges of the P-type photoresist layer openings. During the etching process, the plasma's ion bombardment and / or free radical chemical etching, which have both isotropic etching components, act simultaneously on the top of the photoresist and the sidewalls of the aperture. When the etching rate of the photoresist is greater than that of the first insulating layer, the edge region of the P-type photoresist layer aperture is rapidly etched and thinned. After the photoresist thickness at the aperture edge decreases sharply, its physical and chemical barrier capabilities against plasma etching decrease significantly, making it difficult to stably constrain the lateral and longitudinal etching processes. The edge of the P-type photoresist layer aperture 171, which has lost effective barrier, is prone to lateral drilling, making the contour of the P-type first insulating layer via prone to irregular sawtooth deformation. The slight fluctuations in parameters such as plasma power and chamber pressure during the superimposed etching process will further aggravate the etching uniformity deviation, causing severe irregular serrations at the edges of the P-type first insulating layer vias. Furthermore, the morphological undulations and etching depth differences in the edge region of the P-type first insulating layer vias will cause light scattering and thin film interference effects, ultimately resulting in obvious color variations under optical observation, leading to a low AOI yield of the fabricated flip-chip LED.

[0026] To address the above problems, this invention provides a method for fabricating a flip-chip silver mirror light-emitting diode chip, comprising the following steps: (1) A substrate 10 having an epitaxial layer 11 is provided; (2) A Bragg reflector layer 14 is formed on the epitaxial layer 11; (3) A first annular groove 143 is formed at a predetermined position on the Bragg reflector layer 14; wherein, the area surrounded by the first annular groove 143 in the Bragg reflector layer 14 forms a first protrusion 144; specifically, the predetermined position on the Bragg reflector layer 14 refers to the outer periphery of the area corresponding to the predetermined P-type first insulating layer through hole 161. (4) A metal reflective layer 15 is deposited on the surface of the Bragg reflective layer 14. The metal reflective layer 15 has a second annular groove 151 at the position corresponding to the first annular groove 143 and a second protrusion 152 at the position corresponding to the first protrusion 144. (5) A first insulating layer 16 is deposited on the surface of the metal reflective layer 15 and the Bragg reflective layer 14 not covered by the metal reflective layer 15; and the metal reflective layer 15 and the first insulating layer 16 are sequentially covered on the surface of the Bragg reflective layer 14 along the surface morphology of the Bragg reflective layer 14, so that the first insulating layer 16 forms a third annular groove 163 at the position corresponding to the second annular groove 151, and forms a third protrusion 164 at the position corresponding to the second protrusion 152, so that there is a height difference between the bottom end of the third annular groove 163 and the top end of the third protrusion 164 (see Figure 7 ); (6) Photoresist is applied to the surface of the first insulating layer 16 and the third annular groove 163 to form a photoresist layer 17. The upper surface of the photoresist layer is a flat surface so that the thickness of the photoresist on the third annular groove 163 is greater than the thickness of the photoresist on the surface of the third protrusion 164. (7) A P-type photoresist layer opening 171 is formed in the photoresist layer 17 to expose the top surface of the third protrusion 164, and the third annular groove 163 surrounds the outer periphery of the P-type photoresist layer opening. (8) The third protrusion 164 exposed in the P-type photoresist layer opening 171 is removed by inductively coupled plasma etching process, and then the photoresist is removed to form a P-type first insulating layer through hole 161, and the edge of the P-type first insulating layer through hole 161 is located in the second annular groove 151.

[0027] To address the problem in existing ICP etching processes where the etching rate of the photoresist is much higher than that of the first insulating layer 16, leading to rapid thinning of the photoresist at the edge of the P-type first insulating layer via 161 and a decrease in its blocking ability, resulting in over-etching of the edge of the P-type first insulating layer via 161 and ultimately causing jagged edges and optical discoloration, this invention creates a first annular groove 143 on the Bragg reflector layer 14. The first annular groove 143 is annular, and the area enclosed by the first annular groove 143 forms a first protrusion 144. Since the subsequently fabricated first insulating layer 16 conforms to the surface morphology of the Bragg reflector layer, a third annular groove 163 and a third protrusion 164 are correspondingly formed in the first insulating layer 16. By utilizing the height difference between the bottom of the third annular groove 163 and the top of the third protrusion 164, after the photoresist is coated, the third annular groove 163 can be fully filled with photoresist, making the thickness of the photoresist in this area significantly greater than the thickness of the photoresist on the surface of the third protrusion 164. Simultaneously, after creating the P-type photoresist layer opening 171 in the photoresist layer 17, the position of the P-type photoresist layer opening 171 corresponds to the position of the third protrusion 164. The third annular groove 163 surrounds the outer periphery of the P-type photoresist layer opening 171, ensuring that the outer periphery of the P-type photoresist layer opening 171 precisely corresponds to the thick photoresist area on the surface of the third annular groove 163, thus specifically improving the etching resistance of the photoresist in the edge area of ​​the P-type photoresist layer opening 171. During the ICP etching process for fabricating the P-type first insulating layer via 161, even under the influence of photoresist sidewall etching thinning and etching process fluctuations, the sufficient photoresist thickness at the edge of the P-type first insulating layer via 161 can still maintain a good etching barrier effect. Furthermore, through the structural design of the first annular groove 143, the edge of the formed P-type first insulating layer via 161 can significantly improve the problem of over-etching at the edge of the P-type first insulating layer via 161 within the first annular groove 143, effectively improving defects such as sawtooth deformation and optical discoloration at the edge of the P-type first insulating layer via 161, thereby significantly improving the AOI inspection yield of the flip-chip silver mirror light-emitting diode chip.

[0028] It should be noted that in the flip-chip silver mirror light-emitting diode chip, due to the height difference between the N-type semiconductor layer 111 and the P-type semiconductor layer 113, the opening positions of the P-type first insulating layer via 161 and the N-type first insulating layer via 162 also have a height difference. The horizontal height of the opening position of the P-type first insulating layer via 161 is much higher than the horizontal height of the opening position of the N-type first insulating layer via 162. This results in a very thick photoresist layer at the edge of the N-type photoresist layer opening 172 after photoresist coating, providing excellent blocking ability. Therefore, the edge of the N-type first insulating layer via 162 is less prone to optical discoloration and jaggedness. Thus, this invention only requires forming a first annular groove 143 outside the preset projection position of the P-type first insulating layer via 161. Furthermore, since the first annular groove 143 only needs to be formed outside the projection position of the preset P-type first insulating layer through hole 161, the present invention only increases the photoresist thickness around the P-type first insulating layer through hole 161, without increasing the overall photoresist thickness, which can effectively reduce the photoresist cost.

[0029] In one embodiment, in step (7), the shape of the bottom opening of the P-type photoresist layer aperture 171 corresponds to the shape of the top surface of the third protrusion 164; The distance between the edge of the bottom opening of the P-type photoresist layer aperture 171 and the edge of the top surface of the third protrusion 164 is ≤50nm; The depth of the first annular groove 143 is ≥ 80% of the thickness of the Bragg reflective layer 14.

[0030] Through the above improvements, the photoresist thickness around the P-type photoresist layer opening 171 can be specifically increased, and the photoresist thickness around the P-type photoresist layer opening 171 can be ensured to be within an optimal range. This further enhances the etching resistance of the photoresist around the P-type photoresist layer opening 171, further improves the defects such as sawtooth deformation and optical discoloration that appear at the edge of the P-type first insulating layer via 161, and further improves the AOI inspection yield of the flip-chip silver mirror light-emitting diode chip.

[0031] To further explain, the shape of the bottom opening of the P-type photoresist layer aperture 171 and the shape of the top surface of the third protrusion 164 correspond to each other, meaning that their shapes are the same or almost identical. Preferably, the shape of the bottom opening of the P-type photoresist layer aperture 171 and the shape of the top surface of the third protrusion 164 are both circular, elliptical, semi-circular, square, or polygonal, etc.

[0032] It should be noted that the bottom opening edge of the P-type photoresist layer aperture 171 can be located inside or outside the top surface edge of the third protrusion 164, or it can coincide with the top surface edge of the third protrusion 164. It is only necessary to control the distance between the bottom opening edge of the P-type photoresist layer aperture 171 and the top surface edge of the third protrusion 164 to be ≤50nm.

[0033] Specifically, the distance between the edge of the bottom opening of the P-type photoresist layer aperture 171 and the edge of the top surface of the third protrusion 164 is exemplarily 0nm, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, or 50nm. Preferably, the distance between the edge of the bottom opening of the P-type photoresist layer aperture 171 and the edge of the top surface of the third protrusion 164 is ≤10nm. More preferably, the distance between the edge of the bottom opening of the P-type photoresist layer aperture 171 and the edge of the top surface of the third protrusion 164 is 0nm, that is, the edge of the bottom opening of the P-type photoresist layer aperture 171 and the edge of the top surface of the third protrusion 164 coincide, which can further improve the AOI inspection yield of the flip-chip silver mirror light-emitting diode chip.

[0034] Furthermore, the depth of the first annular groove 143 is, for example, 80%, 85%, 90%, 95%, or 100% of the thickness of the Bragg reflector layer 14. Preferably, the depth of the first annular groove 143 is 100% of the thickness of the Bragg reflector layer 14, that is, the depth of the first annular groove 143 is equal to the thickness of the Bragg reflector layer 14. In this case, the first annular groove 143 penetrates the Bragg reflector layer 14, which can further improve the AOI inspection yield of the flip-chip silver mirror light-emitting diode chip.

[0035] In one embodiment, the top width of the first annular groove 143 is 3μm to 5μm, and the bottom width is 2μm to 4μm. On the one hand, the aforementioned width limitation makes the volume of the first annular groove 143 smaller, which can reduce the amount of photoresist used while ensuring the thickness of the photoresist around the opening 171 of the P-type photoresist layer, thus further reducing costs. On the other hand, the trapezoidal structure of the first annular groove 143, which is wider at the top and narrower at the bottom, gives the sidewalls of the first annular groove 143 a certain inclination, preventing the sidewalls of the first annular groove 143 from being too steep. This allows the first insulating layer 16 to be deposited uniformly and continuously in accordance with the morphology of the first annular groove 143, reducing the problem of film thinning or breakage at the corners and bottom of the groove, and ensuring the insulation performance and structural integrity of the first insulating layer 16. Moreover, the difference between the top width and bottom width of the first annular groove 143 is small, and the inclination of its sidewall (i.e. the angle between the sidewall and the horizontal plane) is moderate, which can further improve the morphological defects such as sawtooth deformation and optical discoloration that appear in the edge area of ​​the P-type first insulating layer through hole 161, thereby further improving the AOI inspection yield of the flip-chip silver mirror light-emitting diode chip.

[0036] In one embodiment, the angle between the sidewall of the first annular groove 143 and the horizontal plane is 30°~60°. This is beneficial for further improving defects such as sawtooth deformation and optical discoloration at the edge of the P-type first insulating layer via 161, thereby further improving the AOI inspection yield of the flip-chip silver mirror light-emitting diode chip. If the angle between the sidewall of the first annular groove 143 and the horizontal plane is too small, the photoresist thickness around the opening 171 of the P-type photoresist layer will be less improved during the etching of the P-type first insulating layer via 161, resulting in poor improvement of defects such as sawtooth deformation and optical discoloration, and thus the improvement of the AOI inspection yield of the chip will not be significant. If the angle between the sidewall of the first annular groove 143 and the horizontal plane is too large, the sidewall of the first annular groove 143 will be too steep, which will cause the film layer at the corners and bottom of the first annular groove 143 to easily become thinner or break, which will also lead to a decrease in the AOI inspection yield.

[0037] In one embodiment, in step (8), an inductively coupled plasma etching process is used to etch away the third protrusion 164 exposed in the P-type photoresist layer opening 171 to form a P-type first insulating layer via 161; wherein the etching gas is CF4, the flow rate of CF4 is 10 sccm to 30 sccm; the upper etching power is 400W to 500W, and the lower etching power is 150W to 280W.

[0038] It is worth noting that in the inductively coupled plasma (ICP) etching process, the upper power and lower power are two independently controlled radio frequency (RF) power parameters, corresponding to the ICP source power and bias power respectively, used to synergistically regulate plasma characteristics and etching effect. This embodiment, by etching to form the P-type first insulating layer via 161 under the above process parameter conditions, is beneficial for further improving AOI inspection yield.

[0039] Specifically, the flow rate of CF4 is exemplary to be 10 sccm, 12 sccm, 15 sccm, 18 sccm, 20 sccm, 22 sccm, 25 sccm, 28 sccm or 30 sccm, but is not limited thereto; the upper etching power is exemplary to be 400W, 410W, 420W, 430W, 440W, 450W, 460W, 470W, 480W, 490W or 500W, and the lower etching power is exemplary to be 150W, 160W, 170W, 180W, 190W, 200W, 210W, 220W, 230W, 240W, 250W, 260W, 270W or 280W, but is not limited thereto.

[0040] In one embodiment, in step (5), the material of the first insulating layer 16 is Al2O3, and the thickness is 600Å~1500Å.

[0041] It is worth noting that the material of the first insulating layer 16 in this embodiment is Al2O3. Al2O3 has excellent insulation properties and is dense, which can effectively block leakage between the metal reflective layer 15 and the subsequent electrodes and epitaxial layer 11, improve the device's withstand voltage and reliability, and Al2O3 has better adhesion to the Bragg reflective layer 14 and the metal reflective layer 15.

[0042] In this embodiment, using CF4 as the etching gas, the etching rate of the photoresist is several times that of the Al2O3 etching rate. In one embodiment, the etching rate of Al2O3 is 2 Å / s to 5 Å / s, and the etching rate of the photoresist is 15 Å / s to 25 Å / s. In another embodiment, the etching rate of Al2O3 is 3.2 Å / s, and the etching rate of the photoresist is 19.5 Å / s. In one embodiment, the photoresist used is KMP EP 3200A series photoresist from Kehua, with a viscosity of 5 cP to 60 cP.

[0043] Specifically, the thickness of the first insulating layer 16 is exemplary to be 600 Å, 650 Å, 700 Å, 750 Å, 800 Å, 850 Å, 900 Å, 950 Å, 1000 Å, 1050 Å, 1100 Å, 1150 Å, 1200 Å, 1250 Å, 1300 Å, 1350 Å, 1400 Å, 1450 Å, or 1500 Å, but is not limited to these. It should be noted that Å (Angle) is a unit used to represent extremely small lengths, commonly used to describe the thickness of atomic, molecular, or ultrathin films. Where 1 Å = 10⁻⁶ Å. -10 A meter equals 0.1 nanometers.

[0044] In one embodiment, the thickness of the Bragg reflector layer 14 is 5000 Å to 10000 Å; the first annular groove 143 penetrates the Bragg reflector layer 14.

[0045] Since the first annular groove 143 penetrates the Bragg reflective layer 14, and the thickness of the Bragg reflective layer 14 is relatively thick, several times or even more than 10 times the thickness of the first insulating layer 16, after depositing the metal reflective layer 15 and the first insulating layer 16 on the surface of the Bragg reflective layer 14, there is a large thickness difference between the bottom end of the third annular groove 163 and the top end of the third protrusion 164. After applying photoresist, the thickness of the photoresist around the P-type photoresist layer opening 171 can be significantly increased, which is beneficial to further reduce the sawtooth deformation and optical discoloration defects that appear in the edge area of ​​the P-type first insulating layer through hole 161, thereby further improving the AOI inspection yield of the flip-chip silver mirror light-emitting diode chip.

[0046] Specifically, the thickness of the Bragg reflector 14 is exemplary, but not limited to, 5000 Å, 6000 Å, 7000 Å, 8000 Å, 9000 Å or 10000 Å.

[0047] In one embodiment, the Bragg reflector layer is further provided with P-type Bragg reflector conductive vias and N-type Bragg reflector conductive vias; in step (3), while forming P-type Bragg reflector conductive vias 141 and N-type Bragg reflector conductive vias 142 on the Bragg reflector layer 14, a first annular groove 143 is formed at a preset position on the Bragg reflector layer 14.

[0048] This embodiment prepares a first annular groove 143 at the position corresponding to the projection position of the preset P-type first insulating layer through hole 161 while preparing a P-type Bragg reflective layer conductive through hole 141 and an N-type Bragg reflective layer conductive through hole 142 on the Bragg reflective layer 14. This eliminates the need for a separate process to prepare the first annular groove 143, thus simplifying the preparation process and saving preparation time.

[0049] Specifically, each step in the fabrication method of the flip-chip silver mirror light-emitting diode chip will be described in detail below.

[0050] Regarding step (1), a substrate 10 having an epitaxial layer 11 is provided; Preferably, see Figure 2 The method for preparing a substrate 10 with an epitaxial layer 11 includes the following steps: depositing an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 sequentially on the substrate 10 using an MOCVD process, thereby obtaining a substrate 10 with an epitaxial layer 11.

[0051] Preferably, the N-type semiconductor layer 111 is an N-type GaN layer, the active light-emitting layer 112 is a GaN / InGaN active light-emitting layer, and the P-type semiconductor layer 113 is a P-type GaN layer.

[0052] Preferably, the substrate 10 can be a GaN substrate, a sapphire substrate, or a Si substrate.

[0053] In one implementation, the following steps are included after step (1): An ITO thin film is prepared on the surface of the P-type semiconductor layer 113 using a magnetron sputtering process as a current spreading layer 12. Then, photoresist is coated on the surface of the ITO thin film. Part of the photoresist is removed by exposure and development to expose the ITO under the photoresist. Then, the exposed ITO thin film is removed by ITO etching solution until the P-type semiconductor layer 113 is exposed. The exposed P-type semiconductor layer and the active light-emitting layer 112 under this P-type semiconductor are removed by inductively coupled plasma etching process to form an N-type conductive step 1111, and then the photoresist is removed. Next, SiO2 thin films were prepared using PECVD process in the current spreading layer 12 and the areas not covered by the current spreading layer 12 to obtain the current blocking layer 13.

[0054] Regarding step (2), a Bragg reflector layer 14 is formed on the epitaxial layer 11; Preferably, a Bragg reflector layer 14 is formed on the surface of the current blocking layer 13.

[0055] In one implementation, see Figure 3 Using electron beam evaporation, 3 to 10 sets of SiO2 and TiO2 stacks are sequentially deposited on the surface of the current blocking layer 13 to form a Bragg reflector layer 14; that is, the Bragg reflector layer 14 includes alternating SiO2 layers and TiO2 layers, with an alternating stacking period of 3 to 10 sets.

[0056] Regarding step (3), a first annular groove 143 is formed at a preset position in the Bragg reflective layer 14; wherein, the area in the Bragg reflective layer 14 surrounded by the first annular groove 143 forms a first protrusion 144. In one embodiment, the method for forming the first annular groove 143 at a predetermined position of the Bragg reflective layer 14 is as follows: photoresist is coated on the surface of the Bragg reflective layer 14, and part of the photoresist is removed by exposure and development to expose part of the Bragg reflective layer 14. Then, the exposed Bragg reflective layer 14 is removed by inductively coupled plasma etching process, and then the photoresist is removed to form the first annular groove 143 on the Bragg reflective layer 14.

[0057] Preferably, the P-type Bragg reflector conductive via 141 and the N-type Bragg reflector conductive via 142 are prepared using the same method described above. Specifically, the first annular groove 143 can be prepared simultaneously with the preparation of the P-type Bragg reflector conductive via 141 and the N-type Bragg reflector conductive via 142, thus simultaneously forming the P-type Bragg reflector conductive via 141, the N-type Bragg reflector conductive via 142, and the first annular groove 143 on the Bragg reflector 14. Figure 4 As shown.

[0058] In one implementation, after step (3), the following steps are also included: See Figure 5 Photoresist is applied to the surface of the Bragg reflector layer 14 and to the P-type Bragg reflector conductive via 141, the N-type Bragg reflector conductive via 142 and the first annular groove 143. Then, the photoresist inside the P-type Bragg reflector conductive via 141 and the N-type Bragg reflector conductive via 142 is removed by exposure and development, exposing the current blocking layer 13 under this part of the photoresist. Next, the exposed current blocking layer 13 is removed using BOE etching solution. A P-type current blocking layer conductive via 131 is formed below the P-type Bragg reflector conductive via 141, and an N-type current blocking layer conductive via 132 is formed below the N-type Bragg reflector conductive via 142. Then, the photoresist is removed to obtain... Figure 5 The structure shown.

[0059] Regarding step (4), a metal reflective layer 15 is deposited on the surface of the Bragg reflective layer 14. The metal reflective layer 15 forms a second annular groove 151 at the position corresponding to the first annular groove 143 and a second protrusion 152 at the position corresponding to the first protrusion 144. In one implementation, see Figure 6As shown, negative photoresist is coated on the surface of the Bragg reflective layer 14 and inside the first annular groove 143, the P-type Bragg reflective layer conductive via 141, the N-type Bragg reflective layer conductive via 142, the P-type current blocking layer conductive via 131, and the N-type current blocking layer conductive via 132. Then, some of the photoresist is removed by exposure and development. Next, Ag metal and 2 to 3 pairs of alternating Ti metal and Ni metal layers are deposited sequentially by electron beam evaporation. Then, the metal on top of the photoresist is removed by blue film stripping. Finally, the photoresist is removed to form a metal reflective layer 15. That is, the metal reflective layer 15 includes an Ag metal layer and 2 to 3 pairs of alternating Ti metal layers and Ni metal layers.

[0060] Understandably, the metal reflective layer 15 covers the surface of the Bragg reflective layer 14 along the surface morphology of the Bragg reflective layer 14, so that the metal reflective layer 15 forms a second annular groove 151 at the position corresponding to the first annular groove 143, and a second protrusion 152 at the position corresponding to the first protrusion 144.

[0061] Regarding step (5), depositing a first insulating layer 16 on the surfaces of the metal reflective layer 15 and the Bragg reflective layer 14 not covered by the metal reflective layer 15 includes the following steps: A first insulating layer 16 is fabricated on the surfaces of the metal reflective layer 15 and the Bragg reflective layer 14 not covered by the metal reflective layer 15 using an ALD process. Figure 7 The structure shown. The first insulating layer 16 is made of Al2O3 and has a thickness of 600 Å to 1500 Å.

[0062] Since the metal reflective layer 15 and the first insulating layer 16 are both sequentially covered on the surface of the Bragg reflective layer 14 along the surface morphology of the Bragg reflective layer 14, the first insulating layer 16 forms a third annular groove 163 at the position corresponding to the second annular groove 151, and a third protrusion 164 at the position corresponding to the second protrusion 152, and there is a height difference between the bottom end of the third annular groove 163 and the top end of the third protrusion 164.

[0063] Regarding step (6), photoresist is applied to the surface of the first insulating layer 16 and inside the third annular groove 163 to form a photoresist layer 17. The upper surface of the photoresist layer 17 is a flat surface, so that the thickness of the photoresist on the third annular groove 163 is greater than the thickness of the photoresist on the surface of the third protrusion 164. Preferably, the upper surface of the photoresist layer 17 is parallel to the horizontal plane.

[0064] Regarding step (7), a P-type photoresist layer opening 171 is formed in the photoresist layer 17 to expose the top surface of the third protrusion 164, and the third annular groove 163 surrounds the outer periphery of the P-type photoresist layer opening 171, thereby increasing the photoresist thickness around the P-type photoresist layer opening 171.

[0065] Preferably, while forming the P-type photoresist layer opening 171 in the photoresist layer 17, an N-type photoresist layer opening 172 is formed above the N-type conductive step 1111. The specific method is as follows: A portion of the photoresist at a predetermined position is removed using exposure and development to form the P-type photoresist layer opening 171 and the N-type photoresist layer opening 172, resulting in... Figure 8 The structure shown.

[0066] Regarding step (8), the third protrusion 164 exposed in the P-type photoresist layer opening 171 is etched away using an inductively coupled plasma etching process. Then, the photoresist is removed to form a P-type first insulating layer through-hole 161, and the edge of the P-type first insulating layer through-hole 161 is located in the second annular groove 151.

[0067] Preferably, see Figure 9 As shown, while a P-type first insulating layer via 161 is formed on the first insulating layer 16, an N-type first insulating layer via 162 is formed at the position corresponding to the N-type photoresist layer opening 172. Specifically, the first insulating layer exposed by the P-type photoresist layer opening 171 and the N-type photoresist layer opening 172 is removed using an inductively coupled plasma etching process, and then the photoresist is removed to form the P-type first insulating layer via 161 and the N-type first insulating layer via 162.

[0068] In one implementation, after step (8), the following step is further included: (9) A negative photoresist is coated on the surface of the first insulating layer 16, and the P-type first insulating layer via 161 and the N-type first insulating layer via 162. Then, a portion of the photoresist is removed by exposure and development. Next, Cr, Al, Ti, Pt, Ti, Pt, Ti, Au, Pt, and Ti metals are sequentially deposited using an electron beam evaporation process to form a connecting metal layer. Then, the metal above the photoresist is removed using a blue film stripping process, and the photoresist is removed to form a P-type connecting metal layer 181 and an N-type connecting metal layer 182, as shown below. Figure 10 As shown.

[0069] (10) A SiO2 thin film is deposited using PECVD process at the P-type interconnect metal layer 181 and N-type interconnect metal layer 182, and at the locations not covered by the P-type interconnect metal layer 181 and N-type interconnect metal layer 182, as a second insulating layer 19; then, photoresist is coated on the surface of the second insulating layer 19, and part of the photoresist is removed by exposure and development to expose the second insulating layer 19 under this part of the photoresist; then, the exposed second insulating layer 19 is removed using inductively coupled plasma etching process to form P-type second insulating layer openings 191 and N-type second insulating layer openings 192, and then the photoresist is removed to obtain Figure 11 The structure shown.

[0070] (11) Negative photoresist is coated on the surface of the second insulating layer 19 and inside the P-type second insulating layer opening 191 and N-type second insulating layer opening 192. Part of the photoresist is removed by exposure and development. Then, the first Ti metal, Al metal, second Ti metal, Pt metal, Ni metal, and Au metal are sequentially deposited using an electron beam evaporation process. Next, the metal on top of the photoresist is removed using a blue film stripping process. Then, the photoresist is removed to form the P-type pad layer 201 and the N-type pad layer 202, resulting in... Figure 12 The flip-chip silver mirror light-emitting diode chip shown.

[0071] In the P-type pad layer 201 and N-type pad layer 202, the thickness of the first Ti metal layer is 1000Å~2000Å, the thickness of the Al metal layer is 10000Å~150000Å, the thickness of the second Ti metal layer is 1000Å~2000Å, the thickness of the Pt metal layer is 1000Å~2000Å, the thickness of the Ni metal layer is 8000Å~12000Å, and the thickness of the Au metal layer is 300Å~600Å.

[0072] Accordingly, see Figure 12 and Figure 13 As shown, the present invention also discloses a flip-chip silver mirror light-emitting diode chip, which is prepared by the above-described method for preparing a flip-chip silver mirror light-emitting diode chip, including a substrate 10, an epitaxial layer 11, a Bragg reflective layer 14, a metal reflective layer 15 and a first insulating layer 16. The epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113. The active light-emitting layer 112 is stacked on the surface of a predetermined region of the N-type semiconductor layer 111. An N-type conductive step 1111 is formed in the region of the N-type semiconductor layer 111 not covered by the active light-emitting layer 112. The P-type semiconductor layer 113 covers the surface of the active light-emitting layer 112. A Bragg reflector layer 14 is stacked on the surface of a P-type semiconductor layer 113 and an N-type conductive step 1111. The Bragg reflector layer 14 is provided with a first annular groove 143. The area of ​​the Bragg reflector layer 14 surrounded by the first annular groove 143 forms a first protrusion 144. The metal reflective layer 15 covers the surface of the predetermined area of ​​the Bragg reflective layer 14, and the metal reflective layer 15 forms a second annular groove 151 at the position corresponding to the first annular groove 143 and a second protrusion 152 at the position corresponding to the first protrusion 144, and the metal reflective layer 15 is partially electrically connected to the P-type semiconductor layer 113 through the Bragg reflective layer 14. The first insulating layer 16 covers the surfaces of the metal reflective layer 15 and the Bragg reflective layer 14 not covered by the metal reflective layer 15. The first insulating layer 16 has a P-type first insulating layer through-hole 161 and an N-type first insulating layer through-hole 162. The position of the P-type first insulating layer through-hole 161 corresponds to the position of the second protrusion 152, and the edge of the P-type first insulating layer through-hole 161 is located within the second annular groove 151 (e.g., Figure 13 (As shown in the enlarged view of the part); the N-type first insulating layer through-hole 162 extends to the N-type conductive step 1111.

[0073] Preferably, the Bragg reflector layer 14 is further provided with a P-type Bragg reflector conductive via 141 and an N-type Bragg reflector conductive via 142, and the metal reflector layer 15 is partially electrically connected to the P-type semiconductor layer 113 through the P-type Bragg reflector conductive via 141.

[0074] In one embodiment, the flip-chip light-emitting diode chip further includes a current spreading layer 12, a current blocking layer 13, a P-type connection metal layer 181, an N-type connection metal layer 182, a second insulating layer 19, a P-type pad layer 201, and an N-type pad layer 202. A current spreading layer 12 covers the surface of the P-type semiconductor layer 113; The current blocking layer 13 covers the current spreading layer 12 and the surface of the P-type semiconductor layer 113 and the N-type conductive step 1111 that are not covered by the current spreading layer 12; A portion of the metal reflective layer 15 is electrically connected to the current spreading layer 12 via the Bragg reflective layer 14 and the current blocking layer 13 in sequence. P-type connecting metal layer 181 and N-type connecting metal layer 182 respectively cover the surface of the first insulating layer 16; P-type connecting metal layer 181 contacts the metal reflective layer 15 through P-type first insulating layer through-hole 161, thereby achieving electrical connection between P-type connecting metal layer 181 and metal reflective layer 15; N-type connecting metal layer 182 contacts the N-type conductive step 1111 through N-type first insulating layer through-hole 162, thereby achieving electrical connection between N-type connecting metal layer 182 and N-type semiconductor layer 111; The second insulating layer 19 covers the surfaces of the P-type connecting metal layer 181, the N-type connecting metal layer 182, and the first insulating layer 16 not covered by the P-type connecting metal layer 181 and the N-type connecting metal layer 182, and the second insulating layer 19 provides insulation between the P-type connecting metal layer 181 and the N-type connecting metal layer 182. P-type pad layer 201 and N-type pad layer 202 respectively cover the surface of the second insulating layer 19. The P-type pad layer 201 is partially in contact with the P-type connection metal layer 181 through the second insulating layer 19, thereby achieving an electrical connection between the P-type pad layer 201 and the P-type connection metal layer 181. The N-type pad layer 202 is partially in contact with the N-type connection metal layer 182 through the second insulating layer 19, thereby achieving an electrical connection between the N-type pad layer 202 and the N-type connection metal layer 182.

[0075] In one embodiment, the current blocking layer 13 is provided with a P-type current blocking layer conductive via 131 and an N-type current blocking layer conductive via 132. The P-type current blocking layer conductive via 131 is located below the P-type Bragg reflector conductive via 141. A portion of the metal reflector layer 15 is electrically connected to the current extension layer 12 through the P-type Bragg reflector conductive via 141 and the P-type current blocking layer conductive via 131 in sequence. The N-type current blocking layer conductive via 132 is located below the N-type Bragg reflector conductive via 142, and the N-type first insulating layer via 162 is located inside the N-type current blocking layer conductive via 132.

[0076] In one embodiment, the second insulating layer 19 is provided with a P-type second insulating layer opening 191 and an N-type second insulating layer opening 192; the P-type pad layer 201 is partially in contact with the P-type connection metal layer 181 through the P-type second insulating layer opening 191, thereby achieving an electrical connection between the P-type pad layer 201 and the P-type connection metal layer 181; the N-type pad layer 202 is partially in contact with the N-type connection metal layer 182 through the N-type second insulating layer opening 192, thereby achieving an electrical connection between the N-type pad layer 202 and the N-type connection metal layer 182.

[0077] It should also be noted that there is a gap between the P-type pad layer 201 and the N-type pad layer 202 to achieve insulation between them.

[0078] The technical solution of the present invention will be further described below through embodiments and comparative examples.

[0079] Example 1 This embodiment provides a method for fabricating a flip-chip silver mirror light-emitting diode, including the following steps: (1) Provide a substrate having an epitaxial layer; (2) A Bragg reflector layer is formed on the epitaxial layer; (3) A first annular groove is formed at a predetermined position on the Bragg reflector; wherein, the area surrounded by the first annular groove in the Bragg reflector forms a first protrusion; the thickness of the Bragg reflector is 8000 Å, the depth of the first annular groove is 80% of the thickness of the Bragg reflector, the top width of the first annular groove is 5 μm, and the bottom width of the first annular groove is 3 μm. (4) A metal reflective layer is deposited on the surface of the Bragg reflective layer, wherein a second annular groove is formed at the position corresponding to the first annular groove and a second protrusion is formed at the position corresponding to the first protrusion. (5) A first insulating layer is deposited on the surface of the metal reflective layer and the Bragg reflective layer not covered by the metal reflective layer; a third annular groove is formed on the first insulating layer at the position corresponding to the second annular groove, and a third protrusion is formed at the position corresponding to the second protrusion, so that there is a height difference between the bottom end of the third annular groove and the top end of the third protrusion; wherein, the material of the first insulating layer is Al2O3 and the thickness is 1000Å. (6) Photoresist is applied to the surface of the first insulating layer and the third annular groove to form a photoresist layer. The upper surface of the photoresist layer is a flat surface so that the thickness of the photoresist on the third annular groove is greater than the thickness of the photoresist on the surface of the third protrusion. (7) A P-type photoresist layer opening is formed in the photoresist layer to expose the top surface of the third protrusion, and the third annular groove surrounds the outer periphery of the P-type photoresist layer opening; wherein, the distance between the edge of the bottom opening of the P-type photoresist layer opening and the edge of the top surface of the third protrusion is 10nm, and the edge of the bottom opening of the P-type photoresist layer opening is located inside the edge of the top surface of the third protrusion; (8) The third protrusion exposed in the opening of the P-type photoresist layer is removed by inductively coupled plasma etching process, the photoresist is removed, and a P-type first insulating layer through hole is formed, and the edge of the P-type first insulating layer through hole is located in the second annular groove; wherein, the etching gas is CF4, the flow rate of CF4 is 20 sccm; the upper etching power is 450W, and the lower etching power is 220W.

[0080] Example 2 This embodiment provides a method for fabricating a flip-chip silver mirror light-emitting diode (LED). The fabrication method of the flip-chip silver mirror LED in this embodiment is basically the same as that in Embodiment 1, except that: In Example 2, the depth of the first annular groove is 100% of the thickness of the Bragg reflective layer, that is, the depth of the first annular groove in Example 2 is equal to the thickness of the Bragg reflective layer, and the first annular groove penetrates the Bragg reflective layer; at the same time, in Example 2, the distance between the edge of the bottom opening of the P-type photoresist layer aperture and the edge of the top surface of the third protrusion is 3nm.

[0081] Comparative Example 1 This comparative example provides a method for fabricating a flip-chip silver mirror light-emitting diode (LED). The fabrication method of the flip-chip silver mirror LED in this comparative example is basically the same as that in Example 1, except that: Comparative Example 1 does not have a first annular groove in the Bragg reflector layer.

[0082] Comparative Example 2 This comparative example provides a method for fabricating a flip-chip silver mirror light-emitting diode (LED). The fabrication method of the flip-chip silver mirror LED in this comparative example is basically the same as that in Example 1, except that: In Comparative Example 2, the depth of the first annular groove is 50% of the thickness of the Bragg reflective layer, and the distance between the edge of the bottom opening of the P-type photoresist layer aperture and the edge of the top surface of the third protrusion is 70 nm.

[0083] Performance testing The flip-chip silver mirror light-emitting diode chips prepared in Example 1 and Comparative Example 1 were subjected to AOI inspection, and the AOI inspection yield was calculated. The results are shown in Table 1 below: Table 1 Performance Test Results

[0084] As can be seen from the test results in Table 1, the fabrication method of the flip-chip silver mirror light-emitting diode chip of the present invention can effectively improve the AOI detection yield of the flip-chip silver mirror light-emitting diode chip.

[0085] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-described technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for fabricating a flip-chip silver mirror light-emitting diode, characterized in that, Includes the following steps: (1) Provide a substrate having an epitaxial layer; (2) A Bragg reflector layer is formed on the epitaxial layer; (3) A first annular groove is formed at a predetermined position on the Bragg reflector layer, and the area surrounded by the first annular groove forms a first protrusion; (4) A metal reflective layer is deposited on the surface of the Bragg reflective layer, wherein a second annular groove is formed at the position corresponding to the first annular groove and a second protrusion is formed at the position corresponding to the first protrusion. (5) A first insulating layer is deposited on the surface of the metal reflective layer and the Bragg reflective layer not covered by the metal reflective layer; the first insulating layer forms a third annular groove at the position corresponding to the second annular groove and a third protrusion at the position corresponding to the second protrusion, so that there is a height difference between the bottom end of the third annular groove and the top end of the third protrusion. (6) Photoresist is applied to the surface of the first insulating layer and the third annular groove to form a photoresist layer. The upper surface of the photoresist layer is a flat surface so that the thickness of the photoresist on the third annular groove is greater than the thickness of the photoresist on the surface of the third protrusion. (7) A P-type photoresist layer opening is formed in the photoresist layer to expose the top surface of the third protrusion, and the third annular groove surrounds the outer periphery of the P-type photoresist layer opening; (8) Etch away the third protrusion exposed in the opening of the P-type photoresist layer, remove the photoresist, and form a P-type first insulating layer through hole; In step (7), the shape of the bottom opening of the P-type photoresist layer corresponds to the shape of the top surface of the third protrusion; The distance between the edge of the bottom opening of the P-type photoresist layer aperture and the edge of the top surface of the third protrusion is ≤50nm; The depth of the first annular groove is ≥ 80% of the thickness of the Bragg reflective layer.

2. The method for fabricating a flip-chip silver mirror light-emitting diode according to claim 1, characterized in that, The top width of the first annular groove is 3μm~5μm, and the bottom width of the first annular groove is 2μm~4μm.

3. The method for fabricating a flip-chip silver mirror light-emitting diode according to claim 1, characterized in that, The angle between the sidewall of the first annular groove and the horizontal plane is 30°~60°.

4. The method for fabricating a flip-chip silver mirror light-emitting diode according to claim 1, characterized in that, In step (8), the third protrusion exposed in the opening of the P-type photoresist layer is removed by inductively coupled plasma etching process to form a P-type first insulating layer via; wherein, the etching gas is CF4, the flow rate of CF4 is 10sccm~30sccm; the upper etching power is 400W~500W, and the lower etching power is 150W~280W.

5. The method for fabricating a flip-chip silver mirror light-emitting diode according to claim 1, characterized in that, In step (5), the material of the first insulating layer is Al2O3, and the thickness is 600Å~1500Å; The thickness of the Bragg reflector is 5000Å~10000Å.

6. The method for fabricating a flip-chip silver mirror light-emitting diode according to claim 1, characterized in that, The Bragg reflector layer is also provided with P-type Bragg reflector conductive vias and N-type Bragg reflector conductive vias. In step (3), while forming the P-type Bragg reflector conductive via and the N-type Bragg reflector conductive via on the Bragg reflector layer, the first annular groove is formed at a preset position on the Bragg reflector layer.

7. A flip-chip silver mirror light-emitting diode chip, characterized in that, The flip-chip light-emitting diode chip is prepared by any one of claims 1-6, comprising a substrate, an epitaxial layer, a Bragg reflective layer, a metal reflective layer, and a first insulating layer. The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer. The active light-emitting layer is stacked on the surface of a predetermined region of the N-type semiconductor layer, and an N-type conductive step is formed in the region of the N-type semiconductor layer not covered by the active light-emitting layer. The P-type semiconductor layer covers the surface of the active light-emitting layer; The Bragg reflector layer is stacked on the surface of the P-type semiconductor layer and the N-type conductive step. The Bragg reflector layer is provided with a first annular groove, and the area of ​​the Bragg reflector layer surrounded by the first annular groove forms a first protrusion. The metal reflective layer covers the surface of a predetermined area of ​​the Bragg reflective layer, and the metal reflective layer forms a second annular groove at the position corresponding to the first annular groove and a second protrusion at the position corresponding to the first protrusion. The metal reflective layer is partially electrically connected to the P-type semiconductor layer through the Bragg reflective layer. The first insulating layer covers the surface of the metal reflective layer and the Bragg reflective layer not covered by the metal reflective layer. The first insulating layer has a P-type first insulating layer through hole and an N-type first insulating layer through hole. The position of the P-type first insulating layer through hole corresponds to the position of the second protrusion, and the edge of the P-type first insulating layer through hole is located in the second annular groove. The N-type first insulating layer through hole extends to an N-type conductive step.

8. The flip-chip silver mirror light-emitting diode chip according to claim 7, characterized in that, The flip-chip silver mirror light-emitting diode chip also includes a current spreading layer, a current blocking layer, a P-type connection metal layer, an N-type connection metal layer, and a second insulating layer. The current spreading layer covers the surface of the P-type semiconductor layer; The current blocking layer covers the surface of the current spreading layer and the P-type semiconductor layer and N-type conductive step that are not covered by the current spreading layer. A portion of the metal reflective layer passes sequentially through the Bragg reflective layer and the current blocking layer, and is electrically connected to the current spreading layer; The P-type connecting metal layer and the N-type connecting metal layer respectively cover the surface of the first insulating layer; the P-type connecting metal layer contacts the metal reflective layer through the P-type first insulating layer through-hole; the N-type connecting metal layer contacts the N-type conductive step through the N-type first insulating layer through-hole. The second insulating layer covers the surface of the P-type connection metal layer, the N-type connection metal layer, and the surface of the first insulating layer that is not covered by the P-type connection metal layer and the N-type connection metal layer.

9. The flip-chip silver mirror light-emitting diode chip according to claim 8, characterized in that, The flip-chip silver mirror light-emitting diode chip also includes a P-type pad layer and an N-type pad layer; The P-type pad layer and the N-type pad layer respectively cover the surface of the second insulating layer. The P-type pad layer is partially in contact with the P-type connection metal layer through the second insulating layer, and the N-type pad layer is partially in contact with the N-type connection metal layer through the second insulating layer.

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