Data driving apparatus and display apparatus including the same

Abstract

The present invention relates to a data driving apparatus and a display apparatus including the same, the data driving apparatus including a voltage selection part receiving pixel data and outputting a first voltage, a second voltage, and an interpolation code of a predetermined number of bits, and an output buffer having a first input terminal to which the first voltage is applied, a second input terminal to which the second voltage is applied, a third input terminal connected to an output terminal through a feedback node, and a control terminal to which the interpolation code is input. The output buffer outputs an interpolation voltage, a voltage of which is changed according to a current controlled by the interpolation code.

Description

TECHNICAL FIELD

[0001] The present application relates to a data driving device and a display device including the same. BACKGROUND

[0002] There are known various flat panel display devices such as a liquid crystal display (LCD), an electroluminescence display (ELD) such as an organic light emitting diode display (OLED Display), a field emission display (FED), a plasma display panel (PDP), and an electrophoresis display (EPD).

[0003] A display device includes a display panel configured with pixels for displaying an input image, and a display panel driving circuit that writes data to the pixels of the display panel. The display panel driving circuit includes a data driving circuit that supplies a data signal of pixel data to a data line of the display panel, and a gate driving circuit that supplies a gate signal to a gate line of the display panel.

[0004] In order to reproduce a high-quality image in a display device, various circuit technologies are applied to the display device. For example, by increasing the number of bits of pixel data transmitted to a data driving circuit in the form of a digital signal, a data signal that further subdivides a gray scale is supplied to the pixels of the display panel, and it is possible to improve the gray scale expressiveness and color reproduction characteristics. SUMMARY

[0005] Problems to be Solved by the Invention

[0006] The present application aims to solve the aforementioned necessity and / or problems.

[0007] The present application provides a data driving device capable of reducing the circuit area occupied by an interpolation circuit and improving the gray scale expressiveness and color reproduction characteristics, and a display device including the same.

[0008] The problems of the present application are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0009] Means for Solving the Problems

[0010] An embodiment of the data driving device of the present invention includes: a voltage selection unit that receives pixel data and outputs a first voltage, a second voltage, and an interpolation code of a predetermined number of bits; and an output buffer having a first input terminal to which the first voltage is applied, a second input terminal to which the second voltage is applied, a third input terminal connected to an output terminal via a feedback node, and a control terminal for inputting the interpolation code. The output buffer outputs an interpolation voltage, the voltage of which changes according to the current controlled by the interpolation code.

[0011] With the first voltage and the second voltage fixed, the interpolation voltage can be changed.

[0012] The pixel data includes j bits, where j is a positive integer greater than k. The interpolation code, when jk bits are n, can include 2^k bits. n n bits, where n is a positive integer greater than or equal to 2.

[0013] The voltage selection unit may include: a first decoder that receives a high-order k-bit image code separated from the pixel data and p allocated voltages, and selects the first voltage and the second voltage, wherein k is a positive integer greater than or equal to 2 and p is a positive integer greater than or equal to 3; and a second decoder that receives a low-order jk-bit image code separated from the pixel data and outputs the interpolation code.

[0014] The output buffer may include: a plurality of input transistors to which the first voltage and the second voltage are applied; a plurality of bias transistors to generate bias current; and a current control unit connected between the plurality of input transistors and the plurality of bias transistors and receiving the interpolation code. The current control unit may include a plurality of switching elements that, in response to the interpolation code, adjust the number of current paths conducted between the plurality of bias transistors and the plurality of input transistors.

[0015] The output buffer may further include: a current amplification and output section connected to the plurality of input transistors to amplify and output current; and a plurality of output transistors connected to the current amplification and output section.

[0016] An embodiment of the display device of the present invention includes: a display panel having a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, and a plurality of pixels; and a data driving unit electrically connected to the plurality of data lines to supply data voltages generated in the form of interpolation voltages to the plurality of data lines. The data driving unit includes: a voltage selection unit that receives pixel data and outputs a first voltage, a second voltage, and an interpolation code of a predetermined number of bits; and an output buffer having a first input terminal to which the first voltage is applied, a second input terminal to which the second voltage is applied, a third input terminal connected to the output terminal via a feedback node, and a control terminal for inputting the interpolation code. The output buffer includes an output buffer that outputs the interpolation voltage, the voltage of which changes according to the current controlled by the interpolation code.

[0017] The effects of the invention

[0018] Since the present invention performs interpolation in a current-controlled manner in the interpolation circuit of the data driving device, it can reduce the number of high-capacity input transistors to which the input voltage is applied, thus making efficient use of the circuit area.

[0019] Even when the input voltage range of the interpolation circuit is widened, the present invention can ensure the linearity of the current based on the input transistor, thereby reducing interpolation error and improving grayscale performance and color reproduction characteristics.

[0020] The more bits the interpolation code has, the better the resolution of voltage interpolation.

[0021] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. Attached Figure Description

[0022] Figure 1 A block diagram illustrating a display device according to an embodiment of the present invention.

[0023] Figure 2 A block diagram illustrating the circuit configuration of the data drive unit is provided.

[0024] Figure 3 To show in detail Figure 2 The circuit diagram of the interpolation circuit shown in the figure is as follows.

[0025] Figure 4 To show Figure 2 The diagram shows an example of the input and output signals of the second decoder.

[0026] Figure 5This diagram illustrates an example of the voltage interpolated based on a digital signal input to an interpolation circuit.

[0027] Figure 6 and Figure 7 To show in detail Figure 3 The diagram shows the circuit diagram of the output buffer. Detailed Implementation

[0028] The advantages and features of the present invention, as well as the methods of implementing them, will become clear with reference to the accompanying drawings and detailed embodiments described below. The present invention is not limited to the embodiments disclosed below, but is provided only to facilitate implementation in various different forms. These embodiments are provided solely to make the disclosure of the invention more complete and to fully inform those skilled in the art of the scope of the invention; the invention is defined only by the scope of the claims.

[0029] The shapes, sizes, proportions, angles, quantities, etc., disclosed in the accompanying drawings are illustrative for the purpose of illustrating embodiments of the present invention, and therefore the present invention is not limited to the items shown in the drawings. Throughout the specification, the same reference numerals substantially refer to the same constituent elements. Furthermore, in describing the present invention, detailed descriptions of related prior art will be omitted where it is determined that such detailed descriptions might unnecessarily obscure the spirit of the invention.

[0030] In this specification, when terms such as "provided with," "including," "having," or "consisting of" are used, other parts may be added unless "only" is used. When a constituent element is referred to in the singular, it may be interpreted as plural unless otherwise explicitly stated.

[0031] When interpreting constituent elements, even if there is no separate explicit statement, it is interpreted as including the range of error.

[0032] In describing the positional relationship and interconnection between two constituent elements, terms such as “on top of”, “above”, “below”, “next to”, “connected or coupled with”, and “crossing” are used. Unless “adjacent” or “direct” is mentioned, more than one other constituent element may be inserted between the constituent elements.

[0033] When using phrases like "after," "next," "before," or "before" to describe temporal sequence, the sequence may be discontinuous on the timeline unless "immediately adjacent" or "directly" is used.

[0034] To distinguish the constituent elements, terms such as "first," "second," etc., may be used, but the function or structure of these constituent elements is not limited by the ordinal number or name attached to the constituent element.

[0035] The following embodiments can be combined or integrated with each other in part or in whole, and can be technically linked and driven in various ways. Each embodiment can be implemented independently of each other, or it can be implemented together in a related manner.

[0036] In the following embodiments, the transistor is a three-electrode device including a gate, a source, and a drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, the current flows from the drain to the source. In the case of a p-channel transistor, since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. The source and drain of the transistor are not fixed. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0037] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 A block diagram illustrating a display device according to an embodiment of the present invention.

[0039] Reference Figure 1 The display device of an embodiment of the present invention includes a display panel 100 and a display panel driving circuit, wherein the display panel driving circuit is used to write pixel data to pixels 101 of the display panel 100. Pixel data (Sourcedata) can be interpreted as pixel data.

[0040] The substrate of the display panel 100 can be a plastic substrate, a thin glass substrate, or a metal substrate, but is not limited to these. The display panel 100 can be a rectangular panel with a width in a first direction, a length in a second direction, and a thickness in a third direction, but is not limited to these. Figure 1 In this context, X, Y, and Z can represent the first direction, the second direction, and the third direction, respectively.

[0041] In the case of a liquid crystal display device, a backlight unit (BLU) may be arranged below the display panel 100. In the case of a self-emissive display device such as an electroluminescent display device, since the light-emitting elements are arranged in each pixel, a separate light source like a backlight unit is not required.

[0042] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 connected to the data lines 102 and the gate lines 103.

[0043] Pixels 101 can be configured in a matrix within the display area AA. To achieve color, each pixel 101 can be divided into red subpixels, green subpixels, and blue subpixels. Each pixel may further include a white subpixel. In a liquid crystal display device, a pixel includes a liquid crystal cell. In an electroluminescent display device, a pixel includes a light-emitting element such as an OLED (organic light-emitting diode). Each subpixel includes pixel circuitry for driving the liquid crystal cell or the light-emitting element.

[0044] Under the control of the timing controller 130, the display panel driving circuit writes pixel data of the input image to the pixels of the display panel 100. The display panel driving circuit includes a data driving unit 110 and a gate driving unit 120 for driving the pixels 101. The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensor. Figure 1 The touch sensor driver is omitted in this example. In mobile or wearable terminals, the timing controller 130, data driver 110, touch sensor driver, etc., can be integrated into a single driver IC.

[0045] The data drive unit 110 receives pixel data of the input image received in digital signal form from the timing controller 130, and outputs a data voltage. The data voltage of the pixel data is supplied to the pixel 101 through the data line 102.

[0046] The circuitry of the gate driving unit 120 can be configured in a non-display area NA other than the display area AA in the display panel 100, or at least a portion of the circuitry of the gate driving unit 120 can be configured in the display area AA. The gate driving unit 120 can be integrated into a separate gate driving IC and electrically connected to the gate line 103 of the display panel 100. Under the control of the timing controller 130, the gate driving unit 120 sequentially outputs pulses of the gate signal to the gate line. The gate driving unit 120 can shift the pulses of the gate signal using a shift register, thereby sequentially supplying the pulses of the gate signal to the gate line 103.

[0047] The timing controller 130 receives pixel data of the input image and timing signals synchronized with that data from an external host system 200. These timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a master clock. Since the vertical and horizontal periods can be determined by counting the data enable signal, the vertical and horizontal synchronization signals (Hsync) can be omitted. The vertical synchronization signal has a period of one frame. The horizontal synchronization signal and the data enable signal have a period of one horizontal period. The data enable signal defines the effective pixel data range of the input image.

[0048] The timing controller 130 controls the operation timing of the display panel drive circuits 110 and 120 based on the timing signals (Vsync, Hsync, DE) received from the host system 200. The host system 200 can scale the image signal from the video source according to the resolution of the display panel 100 and transmit it to the timing controller 130 along with the timing signals.

[0049] Figure 2 A block diagram illustrating the circuit configuration of the data drive unit is provided.

[0050] Reference Figure 2 The data driving unit 110 may include: a receiving unit 111, a logic control unit 112, a shift register 113, a first latch 114, a second latch 115, a grayscale voltage generation unit 116, and an interpolation circuit 117.

[0051] The receiving unit 111 receives the digital signal DATA serially received from the timing controller 130, recovers the clock from the digital signal DATA, and uses the recovered clock to sample control data and pixel data of the input image from the digital signal DATA and provides them to the logic control unit 112. The timing controller 130 can convert the clock and data into low-voltage differential signals and transmit them to the data driving unit 110 through a high-speed serial interface.

[0052] The logic control unit 112 rearranges the pixel data in units of sub-pixels. The logic control unit 112 can supply the start pulse and clock to the shift register 113 using the recovered clock and control data, and control the output timing of the first latch unit and the second latch units 114, 115 and the output buffer 118.

[0053] Shift register 113, first latch 114, and second latch 115 convert serial data into parallel data. Shift register 113 shifts the clock and outputs it to the channel of first latch 114 upon receiving a start pulse. First latch 114, in response to clock signals sequentially input from shift register 113, samples pixel data input from receiving unit 111 via logic control unit 112. When pixel data is latched in all channels of first latch 114, the latched data is simultaneously output to the channel of second latch 115. Second latch 115 latches the data simultaneously received from first latch 114 and, in response to an output enable signal from logic control unit 112, outputs the latched data to interpolation circuit 117.

[0054] The grayscale voltage generation unit 116 can receive gamma tap voltages from a gamma voltage generation circuit (omitted in the figures), such as a programmable gamma circuit. The gamma tap voltages can be interpreted as gamma reference voltages. The grayscale voltage generation unit 116 can distribute the input voltage using a voltage divider circuit comprising a plurality of resistors connected in series.

[0055] The data driving unit 110 may further include a level shifter (omitted in the figures). The level shifter may be connected between the second latch 115 and the interpolation circuit 117, thereby shifting the voltage of the pixel data output from the second latch 115 to the operating voltage of the interpolation circuit 117 and supplying it to the interpolation circuit 117.

[0056] Interpolation circuit 117 selects a voltage in response to pixel data input from second latch 115, and interpolates that voltage to output a data voltage. For example... Figure 3 As shown, the interpolation circuit 117 receives j bits (j is a positive integer greater than k) of pixel data and p (p is a positive integer greater than 3) of allocation voltages VG1 to VGp from the grayscale voltage generation unit 116. The voltage levels of the allocation voltages VG1 to VGp are different from each other. In response to the image code (hereinafter referred to as "image code") of the high-order k bits (k is a positive integer greater than 2) separated from the pixel data, the interpolation circuit 117 selects two voltages with a potential difference from the p allocation voltages VG1 to VGp and outputs a first input voltage and a second input voltage VINH and VINL.

[0057] Interpolation circuit 117 generates an interpolation code STH in response to the low-order jk bits of the pixel data, used to control the current of the output buffer. Interpolation circuit 117 uses a bias current selected according to the interpolation code STH to generate an interpolation voltage VOUT between the first input voltage and the second input voltages VINH and VINL. The interpolation voltage VOUT is the data voltage of the pixel data. Therefore, the interpolation voltage VOUT output from output buffer 320 is a data voltage that varies according to the grayscale value of the pixel data.

[0058] Interpolation circuit 117 controls the current of the input transistor when the input voltages VINH and VINL are fixed. This can be achieved through the transconductance g of the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). m Let me explain.

[0059]

[0060] Here, V GS V is the gate-source voltage of the transistor. TH The threshold voltage is denoted as Ids. Ids is the current flowing through the transistor channel.

[0061] Interpolation circuit 117 in the above formula in V GS -V TH In a fixed state, the interpolated voltage is output by controlling the current. Because this interpolation circuit 117 can reduce the number of high-capacity transistors, the area occupied by the interpolation circuit can be significantly reduced. Furthermore, even when the input voltage range widens, the interpolation circuit 117 can compensate for the linearity (gm linearity) caused by the current of the input transistor, thereby reducing interpolation error.

[0062] Figure 3 To show in detail Figure 2 The circuit diagram of the interpolation circuit shown is shown.

[0063] Reference Figure 3 The interpolation circuit 117 includes: a voltage selection unit 310, which selects a voltage and generates an interpolation code STH based on pixel data input in the form of a j-bit digital signal; and an output buffer 320, which uses the current controlled according to the interpolation code STH to generate an interpolation voltage using the voltage selected by the voltage selection unit 310.

[0064] The voltage selection unit 310 includes: a first decoder 312, which selects a first input voltage and a second input voltage VINH and VINL in response to an image code obtained from the high k bits of the pixel data; and a second decoder 314, which generates an interpolation code STH in response to the low jk bits of the pixel data.

[0065] The first decoder 312, in response to a k-bit image code, selects two voltages from p allocation voltages VG1 to VGp. The first decoder 312 may select a higher voltage when the image code value is higher, but is not limited to this. For example, depending on the pixel driving method, a higher image code value is more likely to allow the selection of a relatively lower voltage from the allocation voltages VG1 to VGp.

[0066] The second decoder 314 generates an n-bit interpolation code STH (n is a positive integer greater than 2) by decoding the jk-bit input signal. When the jk-bit value is n (n is a positive integer greater than 2), the interpolation code STH can be generated as 2. n The code can be bit-based, but is not limited to this. For example, the second decoder 314 can respond to a 3-bit input signal as follows: Figure 4 The diagram shows the generation of 8-bit interpolation code STH. (As shown...) Figure 4 As shown, the second decoder 314 can generate the interpolation code STH as 00000000 when the jk bits are 000, and as 111111111 when the jk bits are 111. The interpolation code STH generated by the second decoder 314 interpolates the input voltages VINH and VINL by controlling the bias current of the output buffer. The interpolation code STH generated by the second decoder 314 can be changed according to the current distribution method of the output buffer 320. The more bits the interpolation code STH has, the more finely the intermediate voltage between the first input voltage VINH and the second input voltage VINL can be distinguished, thereby improving the resolution of voltage interpolation.

[0067] Output buffer 320 receives a first input voltage and a second input voltage VINH, VINL selected according to an image code, and an n-bit interpolation code STH. Output buffer 320 includes: a first input terminal (+) to which the first input voltage VINH is applied, a second input terminal (+) to which the second input voltage VINH is applied, a third input terminal (-) connected to an output terminal via a feedback node, and a control terminal for inputting the n-bit interpolation code STH. The first input voltage VINH can be a voltage higher than the second input voltage VINL. Output buffer 320 can output an interpolated voltage VOUT, whose voltage is changed by a bias current controlled according to the interpolation code STH, within the voltage range between the first input voltage and the second input voltages VINH, VINL.

[0068] Figure 5 This diagram illustrates an example of the voltage interpolated based on a digital signal input to an interpolation circuit. Figure 5 In the text, Ids represents the number of streams. Figure 6 The diagram illustrates the drain-source channel current of the bias transistor. The voltage of the output buffer VOUT can be calculated based on the jk-bit digital signal. Figure 5 Interpolation can be performed as in the example, but is not limited to this. For example, when the jk bits are 000, VINL can be set to 8. IDs ， And VOUT = VINL. When the jk bits are 011, VINL can be set to 5. Ids, VINH=3 Ids, and VOUT = (5 VINL + 3 VINH) / 8. When jk bits are 100, VINL can be 4. Ids, VINH=4 Ids, and VOUT = (4 VINL + 4 VINH) / 8. When the jk bits are 111, VINL can be 1. Ids, VINH=8 Ids, and VOUT = (1 VINL + 7 VINH) / 8.

[0069] Figure 6 and Figure 7 To show in detail Figure 3 The diagram shows the circuit diagram of the output buffer. Figure 6 In this diagram, AVDDH is the high-potential drive voltage applied to the wiring at node 55, and VSS is the low-potential reference voltage or ground voltage applied to the wiring at node 68. VBP is a second bias voltage lower than the high-potential drive voltage AVDDH and is applied to node 56. STHB is the inverted code of the interpolation code STH obtained by an inverter omitted in the diagram and is applied to node 57. STH is the non-inverted interpolation code and is applied to node 56. VBN is a first bias voltage lower than the second input voltage VINL and higher than the low-potential reference voltage VSS and is applied to node 67. Node 51, to which the first input voltage VINH is applied, can be connected to... Figure 6 The first input terminal is shown in the diagram. The second node 52, to which the second input voltage VINL is applied, can be connected... Figure 6 The second input terminal shown in the diagram. The thirteenth node 63 can be...Figure 6 The diagram shows the feedback node between the output terminal and the third input terminal. Figure 7 It shows Figure 6 The diagram shows the current amplification and output section.

[0070] Reference Figure 6 The output buffer 320 includes a plurality of input transistors M1 to M8, a plurality of bias transistors PM1 to PMn, NM1 to NMn, current control units 40 and 42, current amplification and output unit 70, and output transistors PMO and NMO.

[0071] A first input voltage VINH and a second input voltage VINL are applied to input transistors M1 to M8. The first to fourth input transistors M1 to M4 can be implemented using n-channel MOSFETs. The first input transistor M1 includes a gate electrode connected to a first node 51 where the first input voltage VINH is applied, a first electrode connected to a third node 53, and a second electrode connected to a fourteenth node 64. When the first input transistor M1 is turned on, the third node 53 can be electrically connected to the fourteenth node 64. The second input transistor M2 includes a gate electrode connected to a thirteenth node 63, a first electrode connected to a fourth node 54, and a second electrode connected to the fourteenth node 64. When the second input transistor M2 is turned on, the fourteenth node 54 can be electrically connected to the fourth node 64.

[0072] The third input transistor M3 includes: a gate electrode connected to a second node 52 where a second input voltage VINL is applied, a first electrode connected to a third node 53, and a second electrode connected to a fifteenth node 65. When the third input transistor M3 is turned on, the third node 53 can be electrically connected to the fifteenth node 65. The fourth input transistor M4 includes: a gate electrode connected to a thirteenth node 63, a first electrode connected to a fourth node 54, and a second electrode connected to the fifteenth node 65. When the fourth input transistor M4 is turned on, the fourth node 54 can be electrically connected to the fifteenth node 65.

[0073] The fifth to eighth input transistors M5 to M8 can be implemented using p-channel MOSFETs. The fifth input transistor M5 includes a gate electrode connected to the first node 51, a first electrode connected to the eighth node 58, and a second electrode connected to the eleventh node 61. When the first input transistor M1 is turned on, the eighth node 58 can be electrically connected to the eleventh node 61. The sixth input transistor M6 includes a gate electrode connected to the thirteenth node 63, a first electrode connected to the eighth node 58, and a second electrode connected to the twelfth node 62. When the sixth input transistor M6 is turned on, the eighth node 58 can be electrically connected to the twelfth node 62.

[0074] The seventh input transistor M7 includes a gate electrode connected to the second node 52, a first electrode connected to the ninth node 59, and a second electrode connected to the eleventh node 61. When the seventh input transistor M7 is turned on, the ninth node 59 can be electrically connected to the eleventh node 61. The eighth input transistor M8 includes a gate electrode connected to the thirteenth node 63, a first electrode connected to the ninth node 59, and a second electrode connected to the twelfth node 62. When the eighth input transistor M8 is turned on, the ninth node 59 can be electrically connected to the twelfth node 62.

[0075] Bias transistors NM1 to NMn generate bias current Ids. The n-channel bias transistors NM1 to NMn can be implemented using n-channel MOSFETs. The n-channel bias transistors NM1 to NMn are connected between the corresponding switching element in the first current control unit 42 and the eighteenth node 68. Each of the n-channel bias transistors NM1 to NMn includes: a gate electrode connected to the seventeenth node 67 where a first bias voltage VBN is applied; a first electrode connected to the corresponding switching element in the first current control unit 42; and a second electrode connected to the eighteenth node 68 where a low-potential reference voltage VSS is applied. Each of the n-channel bias transistors NM1 to NMn can be electrically connected to the fourteenth node 64 or the fifteenth node 65 through the first current control unit 42.

[0076] The p-channel bias transistors PM1 to PMn can be implemented using p-channel MOSFETs. The p-channel bias transistors PM1 to PMn are connected between the corresponding switching element in the second current control unit 40 and the eighteenth node 68. Each p-channel bias transistor PM1 to PMn includes: a gate electrode connected to the sixth node 56 where a second bias voltage VBP is applied; a first electrode connected to the fifth node 55 where a high-potential drive voltage AVDDH is applied; and a second electrode connected to the corresponding switching element in the second current control unit 40. Each p-channel bias transistor PM1 to PMn can be electrically connected to the eighth node 58 or the ninth node 59 via the second current control unit 40.

[0077] The first current control unit 42 connects the corresponding n-channel bias transistors NM1 to NMn to the fourteenth node 64 or the fifteenth node 65 in response to the interpolation code STH. The first current control unit 42 includes a plurality of switching elements that are switched in response to the voltage of the corresponding bit of the interpolation code STH. The number of current paths turned on by the first current control unit 42 may vary depending on the interpolation code STH. Based on the current paths formed by the first current control unit 42, it is possible to... Figure 5The bias current Ids flowing through the n-channel transistor NM1 is adjusted as shown, thereby changing the interpolation voltage VOUT. For example, when the first bit of the interpolation code STH is 0, the first n-channel transistor NM1 is connected to the fifteenth node 65; conversely, when the first bit of the interpolation code STH is 1, the first n-channel transistor NM1 can be connected to the fourteenth node 64.

[0078] The second current control unit 40 connects the corresponding p-channel bias transistors PM1 to PMn to the eighth node 58 or the ninth node 59 in response to the inverted interpolation code STHB. The second current control unit 40 includes a plurality of switching elements that are switched in response to the voltage of the corresponding bit of the inverted interpolation code STHB. The number of current paths turned on by the first current control unit 42 may vary depending on the inverted interpolation code STHB. Based on the current path formed by the first current control unit 42, the bias current Ids flowing through the n-channel transistor NM1 can be adjusted, thereby changing the interpolation voltage VOUT. For example, when the first bit of the inverted interpolation code STHB is 0, the first p-channel transistor PM1 is connected to the ninth node 59; conversely, when the first bit of the inverted interpolation code STHB is 1, the first p-channel transistor PM1 can be connected to the eighth node 58.

[0079] Reference Figure 6 and Figure 7 The current amplification and output section 70 can amplify the current using a current mirror.

[0080] The current amplification and output section 70 includes a plurality of transistors T1 to T12. The current amplification and output section 70 is connected to output transistors PMO and NMO. The first to fourth, sixth, and eighth transistors T1, T2, T3, T4, T6, and T8, as well as the first output transistor PMO, can be implemented using p-channel MOSFETs. The fifth, seventh, ninth to twelfth transistors T5, T7, T9, T10, T11, and T12, as well as the second output transistor NMO, can be implemented using n-channel MOSFETs.

[0081] The first transistor T1 includes a gate electrode connected to node 71, a first electrode connected to node 55, and a second electrode connected to node 53. The second transistor T2 includes a gate electrode connected to node 71, a first electrode connected to node 55, and a second electrode connected to node 54. The third transistor T3 includes a gate electrode connected to node 72, a first electrode connected to node 53, and a second electrode connected to node 71. The fourth transistor T4 includes a gate electrode connected to node 72, a first electrode connected to node 54, and a second electrode connected to node 73. The sixth transistor T6 includes a gate electrode to which a fourth bias voltage Vb is applied, a first electrode connected to node 71, and a second electrode connected to node 74. The eighth transistor T8 includes a gate electrode to which a sixth bias voltage Vd is applied, a first electrode connected to node 73, and a second electrode connected to node 76. The first output transistor PMO includes a gate electrode connected to node 73, a first electrode connected to node 55, and a second electrode connected to node 63.

[0082] The fifth transistor T5 includes a gate electrode to which a third bias voltage Va is applied, a first electrode connected to the twenty-first node 71, and a second electrode connected to the twenty-fourth node 74. The seventh transistor T7 includes a gate electrode to which a fifth bias voltage Vc is applied, a first electrode connected to the twenty-third node 73, and a second electrode connected to the twenty-sixth node 76. The ninth transistor T9 includes a gate electrode connected to the twenty-fifth node 75, a first electrode connected to the twenty-fourth node 74, and a second electrode connected to the eleventh node 61. The tenth transistor T10 includes a gate electrode connected to the twenty-fifth node 75, a first electrode connected to the twenty-sixth node 76, and a second electrode connected to the twelfth node 62. The eleventh transistor T11 includes a gate electrode connected to the twenty-fourth node 72, a first electrode connected to the eleventh node 11, and a second electrode connected to the eighteenth node 68. The twelfth transistor T12 includes a gate electrode connected to the twenty-fourth node 74, a first electrode connected to the twelfth node 62, and a second electrode connected to the eighteenth node 68. The second output transistor NMO includes: a gate electrode connected to the twenty-sixth node 76, a first electrode connected to the thirteenth node 63, and a second electrode connected to the eighteenth node 68.

[0083] The current amplification and output section 70 may further include capacitors C connected to the thirteenth node 63. These capacitors C are able to suppress ripple and stabilize the interpolated voltage VOUT.

[0084] In the interpolation circuit 117 of the present invention, the interpolation voltage VOUT can be adjusted between the two input voltages VINH and VINL by adjusting the bias current Id, while the two input voltages VINH and VINL to the output buffer 720 are fixed. Since interpolation is performed in a current-controlled manner, the number of high-capacity input transistors to which the input voltage is applied can be reduced. On the other hand, since the transistors constituting the current control units 40 and 42 are switching elements, they can be implemented in a much smaller size than the input transistors. Therefore, the circuit area of ​​the output buffer 72 can be significantly reduced.

[0085] As the contents of the specification describing the problem to be solved, the means to solve the problem, and the effect are not used to limit the essential features of the claims, the scope of the claims is not limited by the matters described in the specification.

[0086] Although embodiments of the present invention have been described in more detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in this invention are not intended to limit the technical spirit of the present invention, but are intended to illustrate that the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it must be understood that the embodiments described above are exemplary and not restrictive in all respects.

Claims

1. A data-driven device, wherein, include: The voltage selection unit receives pixel data and outputs a first voltage, a second voltage, and an interpolation code of a predetermined number of bits. as well as The output buffer has a first input terminal to which the first voltage is applied, a second input terminal to which the second voltage is applied, a third input terminal connected to the output terminal via a feedback node, and a control terminal for inputting the interpolation code; The output buffer outputs an interpolated voltage, the voltage of which changes according to the current controlled by the interpolation code.

2. The data driving device according to claim 1, wherein, With the first voltage and the second voltage fixed, the interpolation voltage is changed.

3. The data driving device according to claim 1, wherein, The pixel data includes j bits, where j is a positive integer greater than k; The interpolation code includes 2 when jk bits are n. n n bits, where n is a positive integer greater than or equal to 2.

4. The data driving device according to claim 3, wherein, The voltage selection unit includes: A first decoder receives a high-order k-bit image code separated from the pixel data and p assigned voltages, and selects the first voltage and the second voltage, where k is a positive integer greater than or equal to 2 and p is a positive integer greater than or equal to 3; and The second decoder receives the low-order jk bits separated from the pixel data and outputs the interpolation code.

5. The data driving device according to claim 4, wherein, The output buffer includes: A plurality of input transistors to which the first voltage and the second voltage are applied; A plurality of bias transistors that generate bias current; and A current control unit is connected between the plurality of input transistors and the plurality of bias transistors and receives the interpolation code; The current control unit includes a plurality of switching elements that, in response to the interpolation code, adjust the number of current paths that are turned on between the plurality of bias transistors and the plurality of input transistors.

6. The data driving device according to claim 5, wherein, The output buffer also includes: A current amplification and output section is connected to the plurality of input transistors to amplify and output the current; and A plurality of output transistors are connected to the current amplification and output section.

7. A display device, wherein, include: The display panel is configured with a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, and a plurality of pixels; as well as A data driving unit is electrically connected to the plurality of data lines to supply data voltage generated in the form of interpolated voltage to the plurality of data lines; The data driving unit includes: The voltage selection unit receives pixel data and outputs a first voltage, a second voltage, and an interpolation code of a predetermined number of bits. as well as The output buffer has a first input terminal to which the first voltage is applied, a second input terminal to which the second voltage is applied, a third input terminal connected to the output terminal via a feedback node, and a control terminal for inputting the interpolation code; The output buffer includes an output buffer for an interpolated voltage, the voltage of which changes according to the current controlled by the interpolation code.

8. The display device according to claim 7, wherein, With the first voltage and the second voltage fixed, the interpolation voltage is changed.

9. The display device according to claim 7, wherein, The pixel data includes j bits, where j is a positive integer greater than k; The interpolation code consists of n bits, where n is a positive integer greater than or equal to 2.

10. The display device according to claim 9, wherein, The voltage selection unit includes: A first decoder receives a high-order k-bit image code separated from the pixel data and p assigned voltages, and selects the first voltage and the second voltage, where k is a positive integer greater than or equal to 2 and p is a positive integer greater than or equal to 3; and The second decoder receives the low-order jk bits separated from the pixel data and outputs the interpolation code.

11. The display device according to claim 10, wherein, The output buffer includes: A plurality of input transistors to which the first voltage and the second voltage are applied; A plurality of bias transistors that generate bias current; and A current control unit is connected between the plurality of input transistors and the plurality of bias transistors and receives the interpolation code; The current control unit includes a plurality of switching elements that, in response to the interpolation code, adjust the number of a plurality of current paths that are turned on between the plurality of bias transistors and the plurality of input transistors.

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