Display device and pixel IC

By optimizing the pixel IC structure and circuit through series connection, the problems of synchronous control and data transmission difficulties in large-scale display devices are solved, achieving high-frequency bandwidth and good display characteristics, which is suitable for displays with a high number of pixels.

CN122228539APending Publication Date: 2026-06-16JAPAN DISPLAY INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
JAPAN DISPLAY INC
Filing Date
2024-10-29
Publication Date
2026-06-16

AI Technical Summary

Technical Problem

In large-scale display devices, existing technologies struggle to achieve synchronous control in both row and column directions, resulting in poor display characteristics and difficulties in data transmission when a large number of LEDs are connected.

Method used

The first and second pixel ICs are connected in series. By serially transmitting clock signals and image data, combined with buffer circuits and trigger circuits, the synchronous and stable transmission of signals is ensured. The circuit design is optimized by connecting the power supply and reference potential in parallel.

Benefits of technology

It improves the display characteristics of display devices, reduces signal delay and voltage fluctuation, and enables high-frequency bandwidth signal transmission, making it suitable for high-pixel-count displays such as full HD and 4K displays.

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    Figure CN122228539A_ABST
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Abstract

A display device has a plurality of display elements, a plurality of pixel ICs, and a driving IC, the plurality of pixel ICs each has a clock signal input terminal to which a clock signal is input, an image data input terminal to which image data is input, a clock signal output terminal that outputs a clock signal, an image data output terminal that outputs image data, and a connection terminal that is connected to at least one display element, the plurality of pixel ICs includes a first pixel IC and a second pixel IC that are connected in series, the clock signal input terminal and the image data input terminal of the first pixel IC are connected to the driving IC, the clock signal output terminal of the first pixel IC is connected to the clock signal input terminal of the second pixel IC, and the image data output terminal of the first pixel IC is connected to the image data input terminal of the second pixel IC.
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