A chip sidewall defect detection method and apparatus

Abstract

This invention discloses a method and device for detecting chip sidewall defects, belonging to the field of semiconductor testing technology. The method includes: acquiring the outer contour information of the chip under test, and dividing the inner side of the chip under test along the boundary direction into multiple boundary detection units, each boundary detection unit including a first detection sub-region, a second detection sub-region, and a third detection sub-region; selecting target boundary detection units according to a preset scanning order; applying thermal excitation under first boundary conditions and second boundary conditions respectively and collecting thermal response data for each detection sub-region; extracting thermal response parameters based on the thermal response data and determining the order of thermal response dominance; comparing the thermal response dominance order with a preset normal model to determine whether a chip sidewall defect exists at the corresponding position of the target boundary detection unit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to a method and device for detecting chip sidewall defects. Background Technology

[0002] During chip cutting, handling, packaging, and subsequent assembly, localized defects such as cracks, chipping, and microcracks are prone to occur at the edges and sidewalls. These defects can affect the chip's mechanical reliability, thermal conductivity stability, and subsequent packaging quality. Therefore, effective inspection of chip edges and sidewall areas is of great significance.

[0003] In existing technologies, the detection of chip sides or edges mainly includes optical side imaging detection and thermal excitation combined with infrared thermal imaging detection. Optical side imaging can detect visible anomalies on the sidewall surface, but its detection capability is limited for defects such as tiny cracks, hidden structural anomalies, or abnormal heat conduction paths that are not easily imaged directly. Although thermal imaging detection can identify cracks or holes, it focuses more on the analysis of overall thermal image features, temperature distribution characteristics, or local response differences, and is easily affected by factors such as boundary heat transfer fluctuations, local non-uniform heating, emissivity differences, and transient thermal noise, resulting in insufficient stability and reliability in the determination of local defects at chip boundaries or sidewalls.

[0004] Therefore, it is still necessary to provide a new chip sidewall defect detection scheme in the existing technology to establish a more stable thermal response comparison and judgment mechanism for chip boundaries or local areas of sidewalls, thereby reducing the impact of boundary heat transfer fluctuations, local non-uniform heating, emissivity differences and transient thermal noise on defect judgment results. Summary of the Invention

[0005] This invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one object of this invention is to provide a chip sidewall defect detection method, comprising: acquiring the outer contour information of a chip under test, and dividing a plurality of boundary detection units along the boundary direction on the inner side of the boundary of the chip under test, each boundary detection unit including a first detection sub-region, a second detection sub-region, and a third detection sub-region, wherein the first detection sub-region is disposed along the inner side of the chip's outer contour, the second detection sub-region is located on the side of the first detection sub-region facing the inner side of the chip, and the third detection sub-region extends tangentially along the chip boundary; selecting a target boundary detection unit according to a preset scanning order; applying thermal excitation to the target boundary detection unit under a first boundary condition, and collecting first thermal response data of the first detection sub-region, the second detection sub-region, and the third detection sub-region; applying thermal excitation to the target boundary detection unit under a second boundary condition, and collecting first thermal response data of the first detection sub-region, the second detection sub-region, and the third detection sub-region. The second thermal response data of the second detection sub-region and the third detection sub-region, wherein the equivalent heat transfer capacity of the chip boundary side under the first boundary condition is greater than the equivalent heat transfer capacity of the chip boundary side under the second boundary condition; based on the first thermal response data and the second thermal response data, the thermal response parameters of the first detection sub-region, the second detection sub-region, and the third detection sub-region are extracted, and the thermal response dominance order of each detection sub-region within a preset time window is determined accordingly; the thermal response dominance order is compared with a preset normal model, and when the comparison result shows that the thermal response dominance order deviates from the preset normal model, it is determined that there is a chip sidewall defect at the corresponding position of the target boundary detection unit; when the comparison result shows that the thermal response dominance order does not deviate from the preset normal model, it is determined that there is no chip sidewall defect at the corresponding position of the target boundary detection unit.

[0006] In one possible implementation, the thermal response parameters include at least one of the following: peak temperature rise, time to reach peak temperature, temperature rise rate, response duration, response integral value, and response difference between adjacent detection sub-regions; the dominant thermal response region is a detection sub-region that meets at least one of the following conditions within the preset time window: peak temperature rise is higher than other detection sub-regions and exceeds a first threshold, peak temperature rise time is earlier than other detection sub-regions and less than a second threshold, temperature rise rate is higher than other detection sub-regions and exceeds a third threshold, and response integral value is higher than other detection sub-regions and exceeds a fourth threshold.

[0007] In one possible implementation, the preset normal model is established based on at least one of the following: the detection results of a defect-free standard sample, and the detection results of a defect-free adjacent boundary detection unit in the same chip under test.

[0008] In one possible implementation, the deviation of the thermal response dominance order from the preset normal model includes at least one of the following situations: the third detection sub-region becomes the thermal response dominance region before the second detection sub-region within the preset time window; at the end of the preset time window, the first detection sub-region is still the thermal response dominance region while the second detection sub-region has not become the thermal response dominance region; within the preset time window, the second detection sub-region and the third detection sub-region alternately become the thermal response dominance region.

[0009] In one possible implementation, the first boundary condition and the second boundary condition are achieved by at least one of the following methods: switching the cooling intensity on the boundary side, switching the thermally conductive contact state, and switching the boundary clamping state.

[0010] In one possible implementation, before outputting the determination result that a chip sidewall defect exists at the location corresponding to the target boundary detection unit, the method further includes: at the same target boundary detection unit location, swapping the application order of the first boundary condition and the second boundary condition, while maintaining the same or equivalent thermal input energy before and after the swap, and comparing the defect determination results before and after the swap; when the defect determination results before and after the swap are consistent and both indicate the presence of a chip sidewall defect, outputting the determination result that a chip sidewall defect exists at the location corresponding to the target boundary detection unit; when the defect determination results before and after the swap are inconsistent, marking the location corresponding to the target boundary detection unit as a location to be re-inspected.

[0011] In one possible implementation, the same or equivalent thermal input energy means that at least one of the thermal excitation power, thermal excitation duration, and total thermal excitation energy is the same before and after the sequence is interchanged, or the baseline temperature rise deviation obtained in the preset reference area is less than a preset threshold.

[0012] In one possible implementation, after completing the detection under the second boundary condition, the method further includes: stopping the boundary condition switching and waiting for the thermal responses of the first detection sub-region, the second detection sub-region, and the third detection sub-region to recover to a preset initial range; applying thermal excitation again and collecting verification thermal response data after returning to the position corresponding to the target boundary detection unit; comparing the verification thermal response data with the thermal response data corresponding to the first detection, the comparison including the order of thermal response dominance and at least one thermal response parameter; when the order of thermal response dominance obtained by comparison is consistent and the deviation of the at least one thermal response parameter is less than a preset threshold, it is determined that the consistency recovery condition is met, and the original judgment result of the position corresponding to the target boundary detection unit is maintained; when the order of thermal response dominance obtained by comparison is inconsistent, or the deviation of the at least one thermal response parameter is not less than the preset threshold, the position corresponding to the target boundary detection unit is marked as a position to be re-inspected.

[0013] The present invention also provides a chip sidewall defect detection device, comprising: a stage unit for carrying a chip under test; a motion execution unit for driving a detection module to move relative to the chip under test; a thermal excitation unit for applying thermal excitation to a target boundary detection unit; a boundary condition modulation unit for selectively applying a first boundary condition and a second boundary condition to the chip boundary side to change the equivalent heat transfer capacity of the chip boundary side, wherein the equivalent heat transfer capacity of the chip boundary side under the first boundary condition is greater than the equivalent heat transfer capacity of the chip boundary side under the second boundary condition; and a data processing unit for dividing multiple boundary detection units according to the outer contour of the chip under test and determining the position of the target boundary detection unit, and dividing the target boundary detection unit into a first boundary detection unit arranged along the inner side of the outer contour of the chip. The system comprises a detection sub-region, a second detection sub-region located on the chip-inward side of the first detection sub-region, and a third detection sub-region extending tangentially along the chip boundary. Thermal response parameters of each detection sub-region are extracted to determine the dominant order of thermal response within a preset time window. This dominant order is then compared with a preset normal model to determine whether a chip sidewall defect exists at the corresponding location of the target boundary detection unit. An infrared imaging module is used to collect thermal response data from the first, second, and third detection sub-regions. A control unit is used to control the motion execution unit, the thermal excitation unit, the boundary condition modulation unit, and the infrared imaging module to work collaboratively. A result output unit is used to output the chip sidewall defect determination result.

[0014] In one possible implementation, the system further includes a two-dimensional visible light imaging module and a re-inspection positioning unit; the two-dimensional visible light imaging module is used to acquire a front image of the chip under test and determine the front detection position; the re-inspection positioning unit is used to return the front detection position corresponding to the abnormal position based on the defect mapping information, so as to perform a re-inspection.

[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Based on the above technical solution, this invention constructs a partitioned detection basis for the local region of the chip boundary by dividing the inner side of the chip under test along the boundary direction into multiple boundary detection units, and setting a first detection sub-region, a second detection sub-region, and a third detection sub-region within each boundary detection unit. On this basis, thermal excitation is applied to the target boundary detection unit under first boundary conditions and second boundary conditions with different equivalent heat transfer capabilities, and thermal response data is collected to construct thermal response differences under different boundary conditions. Furthermore, by extracting the thermal response parameters of the first detection sub-region, the second detection sub-region, and the third detection sub-region, and determining the order of thermal response dominance of each detection sub-region within a preset time window, the order of thermal response dominance is compared with a preset normal model to form a comparative judgment mechanism for chip sidewall defects, thereby achieving effective detection of chip sidewall defects. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a chip sidewall defect detection method. Figure 2 A schematic diagram showing the division of the outer contour and boundary detection units of the chip under test; Figure 3 A schematic diagram of the boundary detection unit and the first, second and third detection sub-regions; Figure 4 This is a schematic diagram illustrating the detection execution under two boundary conditions; Figure 5 This diagram illustrates the order of thermal response dominance and deviation modes. Figure 6 This is a schematic diagram of the device structure used to implement the chip sidewall defect detection method. Figure 7 This is a system block diagram of a chip sidewall defect detection device.

[0018] Explanation of reference numerals in the attached figures: 10. Chip under test; 11. Chip boundary; 20. Boundary detection unit; 211. First detection sub-area; 212. Second detection sub-area; 213. Third detection sub-area; 100. Chip sidewall defect detection equipment; 110. Stage unit; 120. Motion execution unit; 130. Thermal excitation unit; 140. Boundary condition modulation unit; 150. Infrared imaging module; 160. Data processing unit; 170. Control unit; 180. Result output unit; 190. Two-dimensional visible light imaging module; 195. Re-inspection positioning unit; B. Chip inner direction; C. Boundary tangential direction. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, features defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0021] In this embodiment, the "equivalent heat transfer capacity of the chip boundary 11 side" refers to the comprehensive ability of the chip boundary 11 side to transfer heat to the external environment, thermally conductive contact structure, clamping structure, or cooling medium under unit temperature difference conditions. The equivalent heat transfer capacity can be characterized by at least one of the following factors: boundary side cooling flow rate, type of cooling medium, thermally conductive contact area, contact pressure, contact thermal resistance, thermal conductivity of clamping structure, and clamping contact area. It can also be indirectly characterized by at least one of the following thermal proxy quantities: temperature decay rate of preset reference region, thermal recovery time constant, temperature drop per unit time, or boundary side temperature response slope.

[0022] In this embodiment, the term "preset time window" refers to the analysis time range used to characterize the thermal propagation process of the target boundary detection unit 20, starting from the initial moment of thermal excitation. The preset time window can be determined based on at least one of the following factors: chip material, chip thickness, thermal diffusion feature length, thermal excitation method, 150 frame rate of the infrared imaging module, and target defect scale.

[0023] In this embodiment, "thermal response data" refers to the collective thermal response data acquired by the infrared imaging module 150. The original form of the thermal response data can be a temperature response data sequence; a temperature response curve can be formed based on the temperature response data sequence, and thermal response parameters can be further extracted.

[0024] In this embodiment, the term "thermal response dominant region" refers to a detection sub-region that preferentially exhibits dominant thermal response characteristics relative to other detection sub-regions within a preset time window. The dominant thermal response characteristics can be characterized by at least one of the following: peak temperature rise, time to peak, temperature rise rate, response duration, response integral value, response difference between adjacent detection sub-regions, and combinations thereof.

[0025] In this embodiment, the term "thermal response dominance sequence" refers to the temporal relationship in which the first detection sub-region 211, the second detection sub-region 212, and the third detection sub-region 213 successively become the thermal response dominance regions at different time points or different time segments within a preset time window.

[0026] In this embodiment, the "preset normal model" refers to a reference model used to characterize the heat propagation law of each detection sub-region within the boundary detection unit 20 under a defect-free state within a preset time window. The preset normal model may include at least one normal dominant sequence template, and may further include parameter tolerance interval, sequence offset tolerance interval, dominant switching time interval, and parameter fluctuation tolerance interval.

[0027] In this embodiment, the term "preset initial range" refers to the allowable deviation range of the thermal baseline state of the area corresponding to the target boundary detection unit 20 before the detection begins. The preset initial range can be determined based on at least one of the following: the initial baseline temperature before detection, the preset reference area temperature, the ambient temperature compensation value, or the steady-state temperature before detection.

[0028] The various preset parameters involved in this embodiment, including but not limited to preset scanning order, preset time window, first threshold, second threshold, third threshold, fourth threshold, preset normal model, parameter tolerance range, establishment threshold, consistency judgment threshold, and allowable deviation range, can be determined by at least one of the following methods: calibration results of defect-free standard samples, statistical results of historical inspection data, process experience parameters, allowable error settings, and online adaptive update results. Preferably, a basic parameter group can be established first based on defect-free standard samples, and then the parameters can be locally corrected based on the adjacent normal boundary detection units 20 in the actual inspection batch.

[0029] Please see Figures 1-5 In one specific embodiment, a method for detecting chip sidewall defects is provided. The method takes a localized boundary region of the chip 10 under test as the detection object, and determines whether a chip sidewall defect exists at the corresponding location of the target boundary detection unit 20 by collecting and comparing the thermal responses of the same target boundary detection unit 20 under two different boundary thermal constraint conditions. The method includes at least the following steps.

[0030] Step S1: Obtain the outer contour information of the chip under test 10 First, the chip to be tested 10 is placed on the stage unit 110 and kept in a preset positioning state relative to the detection system. The stage unit 110 can fix the chip to be tested 10 by vacuum adsorption, mechanical clamping, electrostatic adsorption, or a combination thereof, so as to reduce the positioning error caused by chip displacement during the detection process.

[0031] Subsequently, the outer contour information of the chip under test 10 is acquired. This outer contour information can be obtained by acquiring a frontal image of the chip under test 10 using a two-dimensional visible light imaging module 190, and then extracting it using edge extraction, contour fitting, template matching, or boundary recognition algorithms; alternatively, it can be obtained through pre-stored chip layout data, CAD contour data, platform positioning data, historical contour template data, or infrared image-assisted boundary extraction. The outer contour information can be represented as a closed boundary curve, a discrete contour point set, a vector contour, or a set of pixel boundaries.

[0032] The outer contour information is used to determine the shape, position, extension direction and coordinate range of the chip boundary 11, and serves as the basis for the subsequent boundary detection unit 20 division and target boundary detection unit 20 selection.

[0033] Step S2: Divide the boundary detection units 20 based on the outer contour information, and divide them into three detection sub-regions; like Figure 3As shown, B represents the inner direction of the chip, and C represents the tangential direction of the boundary extending along the chip boundary 11; the second detection sub-region 212 is located on the side of the first detection sub-region 211 along the B direction towards the inner side of the chip, and the third detection sub-region 213 is extended along the C direction.

[0034] Based on the outer contour information obtained in step S1, multiple boundary detection units 20 are divided along the direction of the chip boundary 11 inside the boundary of the chip 10 under test. The multiple boundary detection units 20 can be distributed continuously or at intervals to cover the sidewall area to be detected. Each boundary detection unit 20 corresponds to a local boundary segment of the chip boundary 11 and is used to independently detect that local position.

[0035] The length of the boundary detection units 20 in the direction of the chip boundary 11 can be the same, or it can be adaptively adjusted according to the chip corner position, edge curvature change, local high-risk areas, or detection resolution requirements. The width of the boundary detection units 20 in the direction towards the inside of the chip can be determined according to the chip thickness, thermal diffusion feature length, spatial resolution of the infrared imaging module 150, target defect scale, or empirical parameters. Preferably, each boundary detection unit 20 can cover no less than a preset number of effective pixels under the infrared imaging module 150; or the width can be no less than a preset multiple of the target defect feature scale; or it can be determined based on the ability of each detection sub-region to be stably distinguished in the pre-experiment of a defect-free standard sample. Adjacent boundary detection units 20 can partially overlap or be set independently of each other.

[0036] Each boundary detection unit 20 is further divided into a first detection sub-region 211, a second detection sub-region 212, and a third detection sub-region 213. The first detection sub-region 211 is located adjacent to the chip boundary 11 and is used to characterize the thermal response of the boundary-adjacent region. The second detection sub-region 212 is located on the side of the first detection sub-region 211 facing inwards from the chip and is used to characterize the thermal response when heat diffuses into the chip interior. The third detection sub-region 213 extends tangentially along the local boundary segment and is used to characterize the thermal response when heat propagates along the direction of the chip boundary 11. This division allows for the characterization of the thermal propagation characteristics of the boundary-adjacent region, the internal diffusion region, and the tangential propagation region within the same boundary detection unit 20, thereby improving the ability to identify changes in local heat flow distribution paths.

[0037] In some embodiments, the first detection sub-region 211 and the second detection sub-region 212 are arranged adjacent to each other in the direction toward the inside of the chip. The third detection sub-region 213, together with the first detection sub-region 211 and the second detection sub-region 212, corresponds to the local boundary segment corresponding to the same boundary detection unit 20, so as to ensure that the three detection sub-regions reflect the thermal response characteristics of the same local boundary position in different propagation directions. The first detection sub-region 211 and the second detection sub-region 212 can be configured as strip-shaped regions extending along the direction of the chip boundary 11, and the third detection sub-region 213 can be configured as a comparison region extending tangentially along the local boundary segment. The widths of the first detection sub-region 211 and the second detection sub-region 212 can be the same or different; the tangential length of the third detection sub-region 213 can be the same as the length of the boundary detection unit 20, or it can be a part of the length of the boundary detection unit 20. The shape of the detection sub-region can be rectangular, arc-shaped, trapezoidal, or a deformed region that matches the curvature of the boundary.

[0038] Step S3: Select target boundary detection unit 20 according to the preset scanning order. After the boundary detection unit 20 is divided, the target boundary detection unit 20 is selected according to a preset scanning order. The preset scanning order can be scanning clockwise or counterclockwise along the outer contour of the chip, or scanning according to a preset partition order. The preset scanning order can be set by a fixed program, or it can be dynamically adjusted according to contour coordinate sorting rules, high-risk area priority strategy, historical abnormal hot zone distribution, or pre-scan results.

[0039] The target boundary detection unit 20 can be the currently detected unit, or it can be a unit preferentially determined based on risk assessment, pre-scan results, visible light appearance anomaly prompts, or other screening conditions. After determining the target boundary detection unit 20, the data processing unit 160 can call the motion execution unit 120 to move the thermal excitation unit 130 and the infrared imaging module 150 to the position corresponding to the target boundary detection unit 20.

[0040] Step S4: Apply thermal excitation under the first boundary condition and collect the first thermal response data. Under the first boundary condition, thermal excitation is applied to the target boundary detection unit 20, and the first thermal response data of the first detection sub-region 211, the second detection sub-region 212 and the third detection sub-region 213 are collected simultaneously.

[0041] The first boundary condition refers to the boundary constraint condition where the chip boundary 11 is in a state of high equivalent heat transfer capacity. The first boundary condition can be established through boundary-side cooling enhancement, thermally conductive contact enhancement, boundary clamping enhancement, or a combination thereof. The thermal excitation can employ pulsed thermal excitation, laser thermal excitation, focused photothermal excitation, local micro-heat flow excitation, micro-resistive heating excitation, or other controllable thermal input methods. The infrared imaging module 150 preferably continuously samples the target boundary detection unit 20 at a preset frame rate, with the sampling time preferably covering both the heating and cooling phases to form a temperature response data sequence corresponding to the first thermal response data.

[0042] In some implementations, the initial temperature of a preset reference area and the area corresponding to the target boundary detection unit 20 can be collected before applying thermal excitation to serve as a baseline for subsequent temperature rise calculation. Preferably, the infrared imaging module 150 and the thermal excitation unit 130 are synchronously triggered by the control unit 170 to ensure that the time coordinate of the first thermal response data corresponds to the start time of thermal excitation.

[0043] Step S5: Apply thermal excitation under the second boundary condition and collect the second thermal response data. After completing the first round of detection under the first boundary conditions, a second boundary condition is established for the same target boundary detection unit 20, and thermal excitation is applied again and the second thermal response data is collected synchronously.

[0044] The second boundary condition refers to the boundary constraint condition where the chip boundary 11 is in a state of lower equivalent heat transfer capacity, and the equivalent heat transfer capacity of the chip boundary 11 under the first boundary condition is greater than that under the second boundary condition. The purpose of setting the first and second boundary conditions is to construct two sets of different thermal boundary constraints for the same target boundary detection unit 20, so that the influence of local structural anomalies on the heat flow distribution path, heat diffusion rate, and heat dissipation mode is manifested under the two sets of conditions respectively.

[0045] In some preferred embodiments, the success of establishing two boundary conditions can be verified by the thermal response of a preset reference region. When the temperature decay rate of the preset reference region under the first boundary condition is higher than that under the second boundary condition, and the difference exceeds a preset establishment threshold, the first and second boundary conditions can be considered successfully established. Alternatively, when the difference between the thermal recovery time constant, temperature drop per unit time, or boundary-side temperature response slope corresponding to the preset reference region under the two boundary conditions exceeds the corresponding threshold, the first and second boundary conditions can also be considered successfully established.

[0046] Step S6: Extract thermal response parameters and determine the order of thermal response dominance. After obtaining the first and second thermal response data, the two sets of thermal response data are first preprocessed. The preprocessing may include at least one of the following: background subtraction, temperature baseline correction, noise filtering, time alignment, bad pixel correction, regional averaging, regional peak extraction, or weighted statistical processing, to improve the stability of subsequent parameter extraction.

[0047] Subsequently, the thermal response parameters of the first detection sub-region 211, the second detection sub-region 212, and the third detection sub-region 213 are extracted from the first thermal response data and the second thermal response data, respectively. For each detection sub-region, a representative thermal response value can be calculated based on the temperature data of multiple pixels within that sub-region. The representative thermal response value can be the region's average temperature rise, the region's peak temperature rise, or a feature response value after filtering, smoothing, fitting, or statistical processing.

[0048] Preferably, the order of dominance of the first thermal response under the first boundary condition can be determined based on the first thermal response data, and the order of dominance of the second thermal response under the second boundary condition can be determined based on the second thermal response data. Then, a thermal response dominance order for defect determination can be formed according to the correspondence between the first thermal response dominance order and the second thermal response dominance order.

[0049] In other embodiments, two sets of thermal response parameters can be extracted separately first, and then the two sets of thermal response parameters can be normalized, weighted or combined according to a preset fusion method to form fused thermal response parameters, and the order of thermal response dominance can be determined based on the fused thermal response parameters.

[0050] Preferably, the thermal response data can be discretized into multiple time points according to the sampling time, or the preset time window can be divided into multiple continuous time segments. Within each time point or time segment, the order in which the three detection sub-regions reach their peak values ​​is first compared; when the peak values ​​of multiple detection sub-regions are the same or the difference is less than a preset threshold, the temperature rise rate is then compared; when the temperature rise rate comparison result still cannot distinguish them, the peak temperature rise or response integral value is then compared; when the comparison result is still the same, the detection sub-region with the larger response integral value can be determined as the thermal response dominant region of that time segment. By arranging the thermal response dominant regions of each time segment in chronological order, the thermal response dominance order of the target boundary detection unit 20 within the preset time window can be formed.

[0051] When a detection sub-region consistently meets the dominant criterion for a continuous time segment not less than a preset number of sampling periods, it can be determined that the detection sub-region stably constitutes the dominant thermal response region within the corresponding time period. The response duration can be used as an auxiliary thermal response parameter to correct or verify the consistency of the determination results for the dominant thermal response region.

[0052] Step S7: Compare with the preset normal model and determine the defects. After obtaining the thermal response dominance sequence corresponding to the target boundary detection unit 20, it is compared with a preset normal model. When the comparison result shows that the thermal response dominance sequence deviates from the preset normal model, it is determined that there is a chip sidewall defect at the location corresponding to the target boundary detection unit 20; when the comparison result shows that the thermal response dominance sequence does not deviate from the preset normal model, it is determined that there is no chip sidewall defect at the location corresponding to the target boundary detection unit 20.

[0053] In some implementations, the comparison includes not only whether the dominant sequence templates are consistent, but also whether the dominant switching node falls within the tolerance range, whether the duration of the dominant region in each time segment falls within the tolerance range, and whether the corresponding thermal response parameters are within the parameter tolerance range of the preset normal model. When the dominant sequence of thermal response is consistent with the preset normal model, and the corresponding thermal response parameters fall within the parameter tolerance range of the preset normal model, it can be determined that the corresponding position of the target boundary detection unit 20 is in a normal state; when the dominant sequence of thermal response deviates from the preset normal model, or although the sequence is consistent, the corresponding parameters exceed the parameter tolerance range, it can be further determined that there is an abnormality in thermal propagation.

[0054] In summary, this embodiment establishes first and second boundary conditions at the same target boundary detection unit 20, collects the thermal responses of three detection sub-regions, and determines chip sidewall defects based on the deviation between the dominant order of thermal responses in each detection sub-region within a preset time window and a preset normal model. Compared with methods that rely solely on a single temperature amplitude or a single point-in-time thermal response, this embodiment can characterize the impact of local anomalies on heat flow distribution paths, heat diffusion rates, and heat dissipation methods, thereby improving the reliability of identifying chip sidewall cracks, edge chipping, and micro-defects.

[0055] Please see Figure 5 In one specific embodiment, the thermal response parameters include at least one of the following: peak temperature rise, time to peak, temperature rise rate, response duration, response integral value, and response difference between adjacent detection sub-regions. These thermal response parameters characterize the temperature response changes of the first detection sub-region 211, the second detection sub-region 212, and the third detection sub-region 213 under thermal excitation, and serve as the basis for determining the dominant thermal response region.

[0056] Specifically, after obtaining the thermal response data of each detection sub-region, the temperature response curve of each detection sub-region within a preset time window can be extracted, and the corresponding thermal response parameters can be calculated based on the temperature response curve. Specifically, the peak temperature rise can be determined by the difference between the highest temperature value and the initial temperature value of the corresponding detection sub-region within the preset time window; the time to reach the peak temperature can be determined by the time interval from the start of thermal excitation to the occurrence of the peak temperature rise; the temperature rise rate can be determined based on the slope of the temperature response curve during the heating phase; the response duration can be determined based on the duration for which the temperature response is above a preset baseline or above a preset proportional threshold; the response integral value can be obtained by integrating the temperature rise curve within the preset time window; and the response difference between adjacent detection sub-regions can be determined by the difference in thermal response parameters between adjacent detection sub-regions at the same time or within the same time period.

[0057] In some implementations, for the same detection sub-region, the temperature rise of all valid pixels within the sub-region can be statistically analyzed using a regional averaging method; alternatively, a regional peak method can be used to extract the temperature rise features corresponding to the most significant hotspots; or a preset weighting method can be used to assign higher weights to pixels near local boundary segments. For cases with noise fluctuations or occasional abnormal pixels, median filtering, moving average, curve smoothing, or fitting processing can be performed before parameter calculation to improve the stability of the parameter extraction results.

[0058] Based on the above thermal response parameters, it can be determined which detection sub-region constitutes the dominant thermal response region within a preset time window. The dominant thermal response region is a detection sub-region that meets at least one of the following conditions within the preset time window: the peak temperature rises higher than other detection sub-regions and exceeds a first threshold; the peak temperature is reached earlier than other detection sub-regions and less than a second threshold; the temperature rise rate is higher than other detection sub-regions and exceeds a third threshold; the response integral value is higher than other detection sub-regions and exceeds a fourth threshold.

[0059] When multiple detection sub-regions meet at least one dominant condition in the same time period, a parameter priority determination method can be adopted, that is, first compare the time to reach the peak, then compare the temperature rise rate, and then compare the peak temperature rise or response integral value; or a preset comprehensive determination method can be adopted, which combines different thermal response parameters according to preset weights, and identifies the detection sub-region with the best combination result as the dominant thermal response region in that time period.

[0060] The first, second, third, and fourth thresholds can be preset based on the chip material, chip size, thermal excitation method, sampling conditions, and testing environment, or they can be obtained through pre-experimental calibration of defect-free standard samples. Specifically, multiple defect-free samples can be tested under the same thermal excitation conditions, the same boundary conditions, and the same sampling conditions. The mean, variance, range, or confidence interval of the corresponding thermal response parameters can be statistically analyzed, and each threshold can be set accordingly. Alternatively, each threshold can be adjusted based on historical testing data, false positive rate control requirements, false negative rate control requirements, or classification performance optimization principles.

[0061] Please see Figure 5 In one specific implementation, the preset normal model is established based on at least one of the following methods: the detection results of a defect-free standard sample and the detection results of a defect-free adjacent boundary detection unit 20 in the same chip under test 10. The preset normal model is used to characterize the thermal response change law of each detection sub-region within the boundary detection unit 20 in a defect-free state within a preset time window, and serves as a comparison benchmark for defect judgment.

[0062] In one implementation, the preset normal model can be established based on defect-free standard samples. Specifically, multiple standard samples confirmed to be free of sidewall defects can be selected. Under the same thermal excitation conditions, the same boundary condition switching method, and the same acquisition parameters, multiple boundary detection units 20 of the standard samples are detected, the corresponding thermal response parameters are extracted, and the order of thermal response dominance of each detection sub-region within a preset time window is determined, thereby establishing the preset normal model. The preset normal model may include a representative normal dominance sequence or a template set composed of multiple normal sequence templates.

[0063] In another implementation, a preset normal model can be established based on defect-free adjacent boundary detection units 20 within the same chip under test 10. Specifically, multiple boundary detection units 20 of the chip under test 10 can be preliminarily inspected, and reference boundary detection units 20 can be selected using at least one of the following methods: no abnormalities are found at the corresponding position in visible light appearance inspection, historical inspection, or pre-scan results; the deviation between the thermal response dominance order at the corresponding position and the defect-free standard sample model is less than a first preset threshold; the corresponding position and its adjacent multiple boundary detection units 20 all exhibit consistent normal thermal response characteristics. Reference boundary detection units 20 that meet the above conditions can serve as local normal reference areas, and a local preset normal model can be established based on their thermal response parameters and thermal response dominance order.

[0064] In some implementations, the preset normal model further includes a parameter tolerance range corresponding to the normal dominant sequence. The parameter tolerance range may include at least one of the following: peak temperature rise tolerance range, peak time tolerance range, temperature rise rate tolerance range, response integral value tolerance range, dominant switching time tolerance range, and sequence offset tolerance range.

[0065] When both offline standard sample models and online neighboring normal cell models exist, the offline standard sample model can be used as the basic judgment template, and the online neighboring normal cell model can be used to locally correct the tolerance range of relevant parameters. Alternatively, the two types of models can be weighted and fused based on their credibility scores, the number of reference cells, or data stability.

[0066] Please see Figure 4 , Figure 5 In one specific implementation, the deviation of the thermal response dominance order from the preset normal model includes at least one of the following situations: the third detection sub-region 213 becomes the thermal response dominance region before the second detection sub-region 212 within a preset time window; at the end of the preset time window, the first detection sub-region 211 is still the thermal response dominance region while the second detection sub-region 212 has not become the thermal response dominance region; within the preset time window, the second detection sub-region 212 and the third detection sub-region 213 alternately become the thermal response dominance region.

[0067] In the first scenario, when the third detection sub-region 213 becomes the dominant thermal response region before the second detection sub-region 212 within a preset time window, it indicates an abnormal enhancement or preferential triggering of heat propagation along the chip boundary 11 relative to heat propagation towards the chip interior. Normally, heat typically diffuses from the region near the boundary into the chip interior first, followed by significant tangential propagation along the boundary. If the third detection sub-region 213 becomes the dominant thermal response region prematurely, it indicates that local heat flow exhibits bypass propagation, abnormal deflection, or obstructed internal diffusion along the chip boundary 11. This anomaly may be related to heat flow redistribution caused by sidewall cracks, edge chipping, local voids, or sudden changes in local thermal resistance.

[0068] In the second scenario, if the first detection sub-region 211 remains the dominant thermal response region at the end of the preset time window while the second detection sub-region 212 does not, it indicates a significant heat retention phenomenon near the chip boundary 11, suggesting an abnormal blockage, delay, or attenuation in heat diffusion into the chip. Normally, heat should gradually transfer into the chip over time, and the second detection sub-region 212 would typically become the dominant thermal response region within the preset time window. If this dominant shift does not occur, it indicates a structural anomaly near the boundary that hinders heat propagation inward. This anomaly could correspond to sidewall cracks, interlayer separation, localized low thermal conductivity areas, or micro-defects causing thermal diffusion blockage.

[0069] In the third scenario, when the second detection sub-region 212 and the third detection sub-region 213 alternately become the dominant regions of thermal response within a preset time window, it indicates that the propagation of heat between the direction towards the chip interior and along the chip boundary 11 exhibits an unstable switching state. This phenomenon suggests that the local heat flow path does not propagate along a single stable path, but rather competes or repeatedly switches between different propagation directions. This abnormal mode may be related to complex defect morphology, discontinuous boundary damage, local contact disturbances, or the combined effect of multiple micro-defects.

[0070] In addition to the examples above, any instance where the dominant relationship among the first detection sub-region 211, the second detection sub-region 212, and the third detection sub-region 213 deviates from the preset normal model in terms of being earlier, later, reversed, alternating, missing, or abnormally persistent. These deviations are merely illustrative and do not constitute an exhaustive limitation on the ways in which the dominant relationship of the thermal response can deviate; the same sidewall defect may correspond to one or more deviations.

[0071] Please see Figure 4 In one specific implementation, the first boundary condition and the second boundary condition are implemented through at least one of the following methods: switching the cooling intensity on the boundary side, switching the thermally conductive contact state, and switching the boundary clamping state. The difference between the first boundary condition and the second boundary condition is that the equivalent heat transfer capacity on the chip boundary 11 side corresponding to the two conditions is different. Specifically, the equivalent heat transfer capacity on the chip boundary 11 side under the first boundary condition is greater than the equivalent heat transfer capacity on the chip boundary 11 side under the second boundary condition.

[0072] In one embodiment, the first and second boundary conditions can be achieved by switching the cooling intensity on the boundary side. For example, under the first boundary condition, the chip boundary 11 side is subjected to a stronger cooling state by increasing the airflow of the air-cooled nozzle, the micro-jet flow rate, the cooling medium flow rate, or the power of the thermoelectric refrigeration unit; under the second boundary condition, the chip boundary 11 side is subjected to a weaker cooling state by reducing the cooling intensity, closing some cooling channels, or stopping boundary-side cooling. This creates a distinguishable difference in the equivalent heat transfer capacity of the chip boundary 11 side.

[0073] In another embodiment, the first and second boundary conditions can be achieved by switching the thermally conductive contact state. For example, under the first boundary condition, the thermally conductive contact block is controlled to form contact with the chip boundary 11, or the contact area or contact pressure is increased, or a thermally conductive pad with lower contact thermal resistance is used to enhance the heat dissipation capability of the chip boundary 11 side; under the second boundary condition, the thermally conductive contact block is separated from the chip boundary 11, or the contact area is reduced, the contact pressure is lowered, or a thermally conductive pad with higher contact thermal resistance is used to reduce the heat dissipation capability of the chip boundary 11 side.

[0074] In another embodiment, the first and second boundary conditions can also be achieved by switching the boundary clamping state. For example, under the first boundary condition, the chip boundary 11 is clamped with a higher clamping force, a larger contact area, or a higher thermal conductivity material, so that a stronger heat conduction path is formed on the chip boundary 11 side; under the second boundary condition, the chip boundary 11 is clamped with a lower clamping force, a smaller contact area, or a lower thermal conductivity material, or even the clamping is released, thereby changing the contact thermal resistance on the chip boundary 11 side and reducing the equivalent heat transfer capacity.

[0075] In some implementations, the above methods can be used alone or in combination. Preferably, the establishment effect of the two boundary conditions can be verified by the thermal response of a preset reference region. When the temperature decay rate of the preset reference region under the first boundary condition is higher than that under the second boundary condition, and the difference exceeds a preset establishment threshold, the first and second boundary conditions can be considered successfully established; or, when the difference between the corresponding thermal recovery time constant, the temperature drop per unit time, or the slope of the boundary side temperature response exceeds the corresponding threshold, the first and second boundary conditions can also be considered successfully established.

[0076] Please see Figure 1 In one specific implementation, as a preferred measure to improve the stability of the test results and the reliability of the verification, the preliminary judgment results can be further subjected to sequential interchange verification.

[0077] Specifically, before outputting the final defect determination result indicating the presence of a chip sidewall defect at the corresponding position of the target boundary detection unit 20, the method further includes: at the same target boundary detection unit 20 position, swapping the application order of the first boundary condition and the second boundary condition, while maintaining the same or equivalent thermal input energy before and after the swap, and comparing the defect determination results before and after the swap; when the defect determination results before and after the swap are consistent and both indicate the presence of a chip sidewall defect, maintaining the original determination result; when the defect determination results before and after the swap are inconsistent, marking the corresponding position of the target boundary detection unit 20 as a position to be re-inspected.

[0078] In some implementations, during the initial detection, a first boundary condition may be applied first, followed by a second boundary condition, and a preliminary judgment result may be obtained. Subsequently, the detection is re-executed at the same target boundary detection unit 20, but the second boundary condition is applied first, followed by the first boundary condition. By verifying the sequence interchange, false anomalies caused by heat accumulation sequence effects, contact state hysteresis effects, and the order of boundary condition switching can be eliminated.

[0079] In some implementations, to avoid the residual heat from the previous test affecting the sequential interchange verification, a preset interval can be set between two sequential interchange tests, or the temperature of the corresponding area of ​​the preset reference area and the target boundary detection unit 20 can be required to recover to the preset initial range before the next round of sequential interchange tests is performed.

[0080] Please see Figure 1 In one specific implementation, the same or equivalent thermal input energy means that at least one of the thermal excitation power, thermal excitation duration and total thermal excitation energy is the same before and after the sequence is interchanged, and the remaining parameters are within the allowable deviation range; or the baseline temperature rise deviation obtained in the preset reference area is less than the preset threshold.

[0081] In one implementation, the thermal input before and after the sequence interchange can be kept consistent by controlling at least one of the thermal excitation power, thermal excitation duration, and total thermal excitation energy. For example, the same excitation power, the same pulse width, and the same number of excitations can be used in both rounds of detection; or, if the thermal excitation methods are not exactly the same, the thermal input energy applied in the two rounds of detection can be made equivalent by controlling the total cumulative thermal input within the allowable deviation range.

[0082] In another embodiment, the same or equivalent thermal input energy can also be verified by the baseline temperature rise deviation of a preset reference region. The preset reference region can be selected as a reference region far from the target boundary detection unit 20 and not easily affected by local sidewall defects, such as a thermally relatively uniform region in the middle of the chip, a reference boundary unit region confirmed to be defect-free, or other temperature-response-stable regions. If at least one of the average baseline temperature rise deviation, peak temperature rise deviation, or temperature rise curve integral deviation of the preset reference region before and after sequential interchange is less than a preset threshold, then the thermal input applied in the two detections can be considered to be in the same or equivalent state.

[0083] The preset threshold can be set based on the results of repeated experiments on defect-free standard samples, statistical results of historical test data, or allowable errors. Preferably, during the system calibration stage, thermal excitation can be applied to the same defect-free sample multiple times, the fluctuation range of the response parameters in the preset reference area can be statistically analyzed, and this fluctuation range can be used as the basic threshold for thermal input equivalent verification.

[0084] Please see Figure 1In one specific implementation, after completing the detection under the second boundary condition, the method further includes: stopping the boundary condition switching and waiting for the thermal responses of the first detection sub-region 211, the second detection sub-region 212, and the third detection sub-region 213 to recover to a preset initial range; applying thermal excitation again and collecting verification thermal response data after returning to the corresponding position of the target boundary detection unit 20; comparing the verification thermal response data with the thermal response data corresponding to the first detection, the comparison includes the order of thermal response dominance and at least one thermal response parameter; when the order of thermal response dominance obtained by comparison is consistent and the deviation of the at least one thermal response parameter is less than a preset threshold, it is determined that the consistency recovery condition is met and the original judgment result is maintained; when the order of thermal response dominance obtained by comparison is inconsistent, or the deviation of the at least one thermal response parameter is not less than the preset threshold, the corresponding position of the target boundary detection unit 20 is marked as a position to be re-inspected.

[0085] In some implementations, "recovering to the preset initial range" can be determined as follows: the absolute value of the average temperature rise of the first detection sub-region 211, the second detection sub-region 212, and the third detection sub-region 213 does not exceed the allowable deviation range of the initial baseline before detection, and this state is maintained for a preset duration; or the temperature change rate is lower than the preset threshold for several consecutive frames; or both of the above criteria are met simultaneously.

[0086] In some implementations, the comparison between the verified thermal response data and the corresponding thermal response data from the initial test can be performed using either a parameter-by-parameter comparison method or a preset consistency judgment method. In the parameter-by-parameter comparison method, parameters such as the order of thermal response dominance, peak temperature rise, time to peak, temperature rise rate, or response integral value can be compared separately. In the preset consistency judgment method, a comprehensive consistency score can be set based on the results of pre-experiment calibration or statistical results of historical test data. When the comprehensive consistency score reaches the preset requirements, it is determined that the conditions for restoring consistency are met.

[0087] Please see Figure 6 , Figure 7 In one specific embodiment, a chip sidewall defect detection device 100 is provided for performing the chip sidewall defect detection method in any of the above embodiments. The device includes: a stage unit 110, a motion execution unit 120, a thermal excitation unit 130, a boundary condition modulation unit 140, a data processing unit 160, an infrared imaging module 150, a control unit 170, and a result output unit 180.

[0088] The stage unit 110 is used to carry the chip under test 10 and to position and support the chip under test 10 so that the chip under test 10 maintains a preset position during the testing process. The stage unit 110 may have a positioning reference structure, and preferably can be fixed by vacuum adsorption, mechanical clamping, electrostatic adsorption or a combination thereof.

[0089] The motion execution unit 120 is used to drive the detection module to move relative to the chip under test 10, so that the thermal excitation unit 130 and the infrared imaging module 150 can sequentially complete the detection corresponding to the positions of multiple boundary detection units 20. The motion execution unit 120 may include a two-dimensional moving platform, a linear module, a rotating platform, a robotic arm or a combination thereof, to realize two-dimensional translation, rotation or multi-axis positioning functions.

[0090] The thermal excitation unit 130 is used to apply thermal excitation to the target boundary detection unit 20. The thermal excitation unit 130 may include a pulsed laser, a focused photothermal excitation head, a miniature resistance heating head, a micro heat flow applicator, or other controllable heat sources. The infrared imaging module 150 is used to acquire thermal response data of the first detection sub-region 211, the second detection sub-region 212, and the third detection sub-region 213, and form corresponding temperature response data sequences.

[0091] Boundary condition modulation unit 140 is used to selectively apply a first boundary condition and a second boundary condition to the chip boundary 11 side to change the equivalent heat transfer capacity of the chip boundary 11 side, wherein the equivalent heat transfer capacity of the chip boundary 11 side under the first boundary condition is greater than the equivalent heat transfer capacity of the chip boundary 11 side under the second boundary condition. In a preferred embodiment, boundary condition modulation unit 140 includes at least one of a boundary side cooling component, a switchable thermally conductive contact component, and an adjustable clamping component. The boundary side cooling component may include at least one of a local air cooling component, a micro-jet cooling component, and a thermoelectric cooling component; the switchable thermally conductive contact component may include a thermally conductive contact block, a thermally conductive pad, and a driving mechanism; the adjustable clamping component may include a boundary clamping block, a pressure adjustment mechanism, and a position adjustment mechanism.

[0092] The data processing unit 160 is used to divide multiple boundary detection units 20 according to the outer contour information of the chip under test 10 and determine the position of the target boundary detection unit 20, and divide the target boundary detection unit 20 into a first detection sub-region 211, a second detection sub-region 212, and a third detection sub-region 213. The data processing unit 160 is also used to receive thermal response data collected by the infrared imaging module 150, extract thermal response parameters of each detection sub-region, determine the order of thermal response dominance, and compare the order of thermal response dominance with a preset normal model to determine whether there is a chip sidewall defect at the corresponding position of the target boundary detection unit 20. The data processing unit 160 can also be used to output the boundary detection unit 20 division result, thermal response parameters, thermal response dominance order, preliminary judgment result, original judgment result, final defect judgment result, and a mark of the position to be re-inspected.

[0093] The control unit 170 is used to control the coordinated operation of the motion execution unit 120, the thermal excitation unit 130, the boundary condition modulation unit 140, and the infrared imaging module 150. Specifically, the control unit 170 can control the outer contour acquisition, boundary detection unit 20 segmentation, target boundary detection unit 20 positioning, first boundary condition detection, second boundary condition detection, parameter extraction, dominant sequence generation, and defect judgment process. The result output unit 180 is used to output the defect judgment result, abnormal location, re-inspection mark, or re-inspection prompt information.

[0094] Please see Figure 7 In one specific embodiment, the chip sidewall defect detection device 100 further includes a two-dimensional visible light imaging module 190 and a re-inspection positioning unit 195. The two-dimensional visible light imaging module 190 is used to acquire a frontal image of the chip 10 under test and determine the frontal detection position; the re-inspection positioning unit 195 is used to return the frontal detection position corresponding to the abnormal position according to the defect mapping information, so as to perform a re-inspection.

[0095] Specifically, the two-dimensional visible light imaging module 190 can acquire a frontal image of the chip under test 10 before detection begins, which is used to extract the outer contour information of the chip under test 10, establish the frontal coordinate system of the chip under test 10, and form the positional mapping relationship of the boundary detection units 20 in the frontal image. The data processing unit 160 can establish the coordinate association relationship between each boundary detection unit 20 and the coordinates of the frontal image based on the frontal image and the outer contour information of the chip under test 10.

[0096] The re-inspection positioning unit 195, after the inspection is completed, converts the position of the abnormal boundary detection unit 20 into a corresponding front detection position based on the defect mapping information output by the data processing unit 160. The defect mapping information may include at least one of the following: the abnormal boundary detection unit 20 number, boundary position coordinates, anomaly type marker, and its correspondence with the front coordinate system. The re-inspection positioning unit 195 can receive the abnormal boundary detection unit 20 number, boundary position coordinates, and its mapping relationship with the front coordinate system, and convert them into a front detection position so that the motion execution unit 120 or the auxiliary positioning mechanism can return to the front detection position to perform re-inspection, local magnification imaging, manual confirmation, or other subsequent verification operations.

[0097] In some implementations, the re-inspection positioning unit 195 can also output the corresponding front detection position coordinates, movement commands, or local magnified imaging area information for use by the motion execution unit 120 or the auxiliary positioning mechanism. Through the above settings, coordinate transformation and closed-loop backtracking from the abnormal position on the sidewall to the chip's front re-inspection position can be achieved, thereby improving the efficiency of abnormal position verification.

[0098] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0099] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for detecting sidewall defects in a chip, characterized in that, include: The outer contour information of the chip under test is obtained, and multiple boundary detection units are divided along the boundary direction inside the boundary of the chip under test. Each boundary detection unit includes a first detection sub-region, a second detection sub-region, and a third detection sub-region. The first detection sub-region is arranged along the inner side of the outer contour of the chip, the second detection sub-region is located on the side of the first detection sub-region facing the inside of the chip, and the third detection sub-region extends tangentially along the chip boundary. Select target boundary detection units according to the preset scanning order; Thermal excitation is applied to the target boundary detection unit under the first boundary condition, and first thermal response data of the first detection sub-region, the second detection sub-region, and the third detection sub-region are collected; Thermal excitation is applied to the target boundary detection unit under the second boundary condition, and second thermal response data of the first detection sub-region, the second detection sub-region, and the third detection sub-region are collected, wherein the equivalent heat transfer capacity of the chip boundary side under the first boundary condition is greater than the equivalent heat transfer capacity of the chip boundary side under the second boundary condition. Based on the first thermal response data and the second thermal response data, the thermal response parameters of the first detection sub-region, the second detection sub-region, and the third detection sub-region are extracted, and the order of thermal response dominance of each detection sub-region within a preset time window is determined accordingly. The thermal response dominance sequence is compared with a preset normal model. If the comparison result shows that the thermal response dominance sequence deviates from the preset normal model, it is determined that there is a chip sidewall defect at the corresponding position of the target boundary detection unit. If the comparison result shows that the thermal response dominance sequence does not deviate from the preset normal model, it is determined that there is no chip sidewall defect at the corresponding position of the target boundary detection unit.

2. The chip sidewall defect detection method according to claim 1, characterized in that, The thermal response parameters include at least one of the following: peak temperature rise, time to reach peak temperature, temperature rise rate, response duration, response integral value, and response difference between adjacent detection sub-regions; The dominant thermal response region is a detection sub-region that meets at least one of the following conditions within the preset time window: the peak temperature rises higher than the other detection sub-regions and exceeds the first threshold; the peak temperature is reached earlier than the other detection sub-regions and less than the second threshold; the temperature rise rate is higher than the other detection sub-regions and exceeds the third threshold; and the response integral value is higher than the other detection sub-regions and exceeds the fourth threshold.

3. The chip sidewall defect detection method according to claim 1, characterized in that, The preset normal model is established based on at least one of the following: the detection results of a defect-free standard sample, and the detection results of a defect-free adjacent boundary detection unit in the same chip under test.

4. The chip sidewall defect detection method according to claim 1, characterized in that, The deviation of the dominant order of thermal response from the preset normal model includes at least one of the following situations: The third detection sub-region becomes the thermal response dominant region before the second detection sub-region within the preset time window; At the end of the preset time window, the first detection sub-region is still the thermal response-dominant region while the second detection sub-region has not become the thermal response-dominant region. Within the preset time window, the second detection sub-region and the third detection sub-region alternately become the dominant regions for thermal response.

5. The chip sidewall defect detection method according to claim 1, characterized in that, The first boundary condition and the second boundary condition are achieved by at least one of the following methods: switching the cooling intensity on the boundary side, switching the thermally conductive contact state, and switching the boundary clamping state.

6. The chip sidewall defect detection method according to claim 1, characterized in that, Before outputting the determination result that there is a chip sidewall defect at the corresponding position of the target boundary detection unit, the method further includes: at the same target boundary detection unit position, swapping the application order of the first boundary condition and the second boundary condition, while keeping the thermal input energy before and after the swap the same or equivalent, and comparing the defect determination results before and after the swap; when the defect determination results before and after the swap are consistent and both indicate the presence of a chip sidewall defect, outputting the determination result that there is a chip sidewall defect at the corresponding position of the target boundary detection unit; when the defect determination results before and after the swap are inconsistent, marking the corresponding position of the target boundary detection unit as a position to be re-inspected.

7. The chip sidewall defect detection method according to claim 6, characterized in that, The same or equivalent thermal input energy means that at least one of the thermal excitation power, thermal excitation duration and total thermal excitation energy is the same before and after the sequence is interchanged, or the baseline temperature rise deviation obtained in the preset reference area is less than a preset threshold.

8. The chip sidewall defect detection method according to claim 1, characterized in that, After completing the detection under the second boundary condition, the process further includes: stopping the boundary condition switching and waiting for the thermal responses of the first detection sub-region, the second detection sub-region, and the third detection sub-region to recover to a preset initial range; applying thermal excitation again and collecting verification thermal response data after returning to the corresponding position of the target boundary detection unit; comparing the verification thermal response data with the thermal response data corresponding to the first detection, the comparison including the order of thermal response dominance and at least one thermal response parameter; when the order of thermal response dominance obtained by comparison is consistent and the deviation of the at least one thermal response parameter is less than a preset threshold, it is determined that the consistency recovery condition is met, and the original judgment result of the corresponding position of the target boundary detection unit is maintained; when the order of thermal response dominance obtained by comparison is inconsistent, or the deviation of the at least one thermal response parameter is not less than the preset threshold, the corresponding position of the target boundary detection unit is marked as a position to be re-inspected.

9. A chip sidewall defect detection device, characterized in that, include: The stage unit is used to support the chip under test; A motion execution unit is used to drive the detection module to move relative to the chip under test. The thermal excitation unit is used to apply thermal excitation to the target boundary detection unit. A boundary condition modulation unit is used to selectively apply a first boundary condition and a second boundary condition to the chip boundary side to change the equivalent heat transfer capability of the chip boundary side, wherein the equivalent heat transfer capability of the chip boundary side under the first boundary condition is greater than the equivalent heat transfer capability of the chip boundary side under the second boundary condition. The data processing unit is used to divide multiple boundary detection units according to the outer contour of the chip under test and determine the position of the target boundary detection unit. The target boundary detection unit is divided into a first detection sub-region set along the inner side of the outer contour of the chip, a second detection sub-region located on the side of the first detection sub-region facing the inner side of the chip, and a third detection sub-region extended tangentially along the chip boundary. The thermal response parameters of each detection sub-region are extracted, the thermal response dominance order of each detection sub-region within a preset time window is determined, and the thermal response dominance order is compared with a preset normal model to determine whether there is a chip sidewall defect at the corresponding position of the target boundary detection unit. An infrared imaging module is used to collect thermal response data of the first detection sub-region, the second detection sub-region, and the third detection sub-region; The control unit is used to control the motion execution unit, the thermal excitation unit, the boundary condition modulation unit, and the infrared imaging module to work together. The result output unit is used to output the chip sidewall defect determination result.

10. The chip sidewall defect detection device according to claim 9, characterized in that, It also includes a two-dimensional visible light imaging module and a re-inspection positioning unit; The two-dimensional visible light imaging module is used to acquire a front image of the chip under test and determine the front detection position. The re-inspection and positioning unit is used to return the front detection position corresponding to the abnormal position based on the defect mapping information, so as to perform a re-inspection.

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