Interrupt information processing system, method, chip and electronic device

Abstract

This application discloses an interrupt information processing system, method, chip, and electronic device, belonging to the field of integrated circuit technology. The interrupt information processing system includes M processor cores, a routing unit, and N interrupt proxy units. The routing unit is connected to the M processor cores and the N interrupt proxy units, and the N interrupt proxy units are connected one-to-one with N acceleration units. A target acceleration unit generates first interrupt information. A target interrupt proxy unit receives the first interrupt information, converts its format to obtain second interrupt information, and sends the second interrupt information to the routing unit. The routing unit routes the second interrupt information to the target processor core, which then processes it. By having the processor core process the interrupt information generated by the acceleration unit, stable system operation is ensured.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an interrupt information processing system, method, chip, and electronic device. Background Technology

[0002] An interrupt is a mechanism in a computer system for handling emergency events. Normally, an interrupt source in a computer system sends an interrupt message to the CPU (Central Processing Unit). Upon receiving the interrupt message, the CPU suspends the execution of the current program and executes the interrupt routine. After the interrupt routine is completed, execution of the original program resumes. Through the interrupt mechanism, the computer system can respond promptly to emergency events, ensuring the stable operation of the computer system. Summary of the Invention

[0003] This application provides an interrupt information processing system, method, chip, and electronic device. This system can process interrupt information generated by the acceleration unit through the processor core, ensuring stable system operation. The technical solution includes the following:

[0004] On the one hand, an interrupt information processing system is provided, the system including M processor cores, a routing unit and N interrupt proxy units, the routing unit is connected to the M processor cores and the N interrupt proxy units, the N interrupt proxy units are connected to N acceleration units in a one-to-one correspondence, and M and N are positive integers greater than or equal to 1; The target interrupt proxy unit among the N interrupt proxy units is used to receive the first interrupt information generated by the target acceleration unit among the N acceleration units, convert the format of the first interrupt information to obtain the second interrupt information, and send the second interrupt information to the routing unit. The target acceleration unit is connected to the target interrupt proxy unit. The routing unit is used to route the second interrupt information to the target processor core among the M processor cores; The target processor core is used to process the second interrupt information.

[0005] On the other hand, a method for processing interrupt information is provided. This method is executed by an interrupt information processing system, which includes M processor cores, a routing unit, and N interrupt proxy units. The routing unit is connected to the M processor cores and the N interrupt proxy units. The N interrupt proxy units are connected one-to-one with N acceleration units. M and N are positive integers greater than or equal to 1. The method includes: The target interrupt proxy unit receives the first interrupt information generated by the target acceleration unit among the N acceleration units, converts the format of the first interrupt information to obtain the second interrupt information, and sends the second interrupt information to the routing unit. The target acceleration unit is connected to the target interrupt proxy unit. The routing unit routes the second interrupt information to the target processor core among the M processor cores. The second interrupt information is processed by the target processor core.

[0006] On the other hand, a chip is provided that includes the interrupt information processing system described above.

[0007] On the other hand, an electronic device is provided, which includes the chip described above.

[0008] The technical solution provided in this application brings at least the following beneficial effects: The technical solution provided in this application includes an interrupt information processing system comprising M processor cores, a routing unit, and N interrupt proxy units. The routing unit is connected to the M processor cores and the N interrupt proxy units, and the N interrupt proxy units are connected to the N acceleration units in a one-to-one correspondence.

[0009] After the target acceleration unit generates the first interrupt information, the target interrupt proxy unit receives the first interrupt information, converts its format to obtain the second interrupt information, and sends the second interrupt information to the routing unit. The routing unit routes the second interrupt information to the target processor core, which then processes it. In this way, interrupt information generated by the target acceleration unit is processed by the target processor core, enabling the system to respond to emergencies in a timely manner and ensuring stable system operation.

[0010] Furthermore, the routing unit and interrupt proxy unit enable the connection of any type of acceleration unit to the processor core, reducing connection complexity and improving the applicability of the interrupt information processing system. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of an interrupt information processing system provided in an embodiment of this application; Figure 2 This is a schematic diagram of another interrupt information processing system provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of another interrupt information processing system provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of another interrupt information processing system provided in the embodiments of this application; Figure 5 This is a flowchart illustrating the transmission of interruption information provided in an embodiment of this application; Figure 6 This is another flowchart of interrupt information transmission provided in an embodiment of this application; Figure 7 This is a flowchart illustrating a method for processing interruption information provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a chip provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0014] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0015] In the field of integrated circuit technology, the interrupt information processing system is an important system. This system can process the received interrupt information so that the computer system can respond to emergency events in a timely manner, thus ensuring the stable operation of the computer system.

[0016] In related technologies, the interrupt information processing system includes a processor core, a root complex, an I / O APIC (Input / Output Advanced Programmable Interrupt Controller), a switch, and a PCI (Peripheral Component Interconnect) bridge. The processor core is connected to the root complex, which in turn is connected to the I / O APIC, the switch, and the PCI bridge. The root complex is then connected to different types of acceleration units via the I / O APIC, the switch, and the PCI bridge.

[0017] The aforementioned technologies involve multiple devices in the interrupt information processing system, resulting in complex connection methods. To address this, this application provides an interrupt information processing system that reduces connection complexity and improves applicability.

[0018] like Figure 1 As shown, Figure 1 This is a schematic diagram of an interrupt information processing system provided in an embodiment of this application. The interrupt information processing system 10 includes M processor cores 101, a routing unit 102, and N interrupt proxy units 103, where M and N are positive integers greater than or equal to 1. In practical applications, M can be greater than, equal to, or less than N; for example, M=4, N=8, or M=N=2. For ease of distinction, in... Figure 1 In this, the M processor cores 101 are referred to as processor cores 1 to M, and similarly, the N interrupt proxy units 103 are referred to as interrupt proxy units 1 to N, and the N acceleration units 20 are referred to as acceleration units 1 to N.

[0019] The processor core 101 is the basic physical unit inside the processor that performs calculations and processes instructions. Typically, a processor includes at least one processor core. Each processor core is an independent working unit within the processor, capable of autonomously reading, decoding, and executing program instructions to perform arithmetic and logical operations.

[0020] Optionally, such as Figure 2 As shown, processor core 101 includes a CPU (Central Processing Unit) core and an interrupt controller. Typically, the CPU core and the interrupt controller are integrated together to form processor core 101.

[0021] The CPU core is a hardware unit capable of executing instructions and performing operations, including a computation unit, registers, a level 1 cache, and a controller. The computation unit is the core functional module responsible for performing arithmetic and logical operations, including addition, subtraction, multiplication, and division, as well as logical operations such as AND, OR, and NOT. Optionally, the computation unit includes an ALU (Arithmetic Logic Unit) and a FPU (Floating Point Unit). The ALU is primarily responsible for performing integer arithmetic operations (such as addition, subtraction, multiplication, and division) and logical operations (such as AND, OR, NOT, XOR, and shift operations), while the FPU is specifically designed for handling floating-point operations, such as high-precision calculations in scientific computing and graphics processing.

[0022] The interrupt controller is a module used to manage interrupt information, responsible for receiving, filtering, and distributing interrupt information. Optionally, the interrupt controller is a LAPIC (Local Advanced Programmable Interrupt Controller).

[0023] The routing unit 102 is a hardware unit responsible for path selection, forwarding, and transmission control of data, instructions, or interrupt information. Optionally, such as Figure 2 As shown, the routing unit 102 includes a Network on Chip (NOC), which is a network-based communication subsystem used for transmitting data, interrupt information, etc. It is understood that the NOC may have other functions besides those of the routing unit 102, which will not be elaborated here.

[0024] Interrupt proxy unit 103 is a hardware unit responsible for relaying, distributing, and coordinating interrupt information, and uniformly managing interrupt routing. Optionally, interrupt proxy unit 103 includes an interrupt interface, through which it connects to an external device. In this embodiment, the external device includes acceleration unit 20.

[0025] Acceleration unit 20 is a dedicated hardware acceleration unit used to offload and accelerate specific computing tasks in scenarios such as artificial intelligence, image processing, big data, and network storage.

[0026] Optionally, such as Figure 2As shown, the acceleration unit 20 includes an XPU (Accelerated Processing Unit). In practical applications, XPUs include GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), NPUs (Neural Network Processing Units), DPUs (Data Processing Units), DPUs (Deep Learning Processing Units), APUs (Accelerated Processing Units), BPUs (Brain Processing Units), IPUs (Intelligence Processing Units), IPUs (Image Processing Units), VPUs (Vector Processing Units), MPUs (Micro Processing Units), FPGAs (Field Programmable Gate Arrays), and GPGPUs (General-Purpose computing on Graphics Processing Units), etc. Different types of XPUs undertake core computing acceleration tasks in scenarios such as Artificial Intelligence (AI) and high-performance computing, and adapt to different application scenario requirements based on their respective hardware architectures and computing characteristics.

[0027] In this embodiment, the processor core 101 and the acceleration unit 20 are heterogeneous devices. Heterogeneous devices are devices with different computing architectures. Through interconnection and communication, heterogeneous devices can overcome the power consumption and performance bottlenecks of homogeneous devices, allowing different types of devices with their own strengths to work together to process different computing tasks more efficiently. Generally, the processor core 101 is a "general-purpose processor," and the acceleration unit 20 is a "dedicated accelerator," together forming a heterogeneous computing system.

[0028] The routing unit 102 and the interrupt proxy unit 103 are unified standard interfaces for heterogeneous device interconnection, which can solve the compatibility issues of heterogeneous device interconnection. The protocol conforming to the routing unit 102 and the interrupt proxy unit 103 is a general term for the protocol standard that defines the data interaction and instruction control between the processor core and different types of acceleration units. It has a complete functional system, such as supporting standard operations such as memory access, interrupts, control and atomic operations between the CPU core and the XPU, ensuring the collaborative operation between heterogeneous devices. It also supports functions customized for artificial intelligence computing power systems, such as address translation, unified memory and virtualization, providing core technical support for corresponding scenarios.

[0029] In this embodiment, the routing unit 102 is connected to M processor cores 101 and N interrupt proxy units 103, and the N interrupt proxy units 103 are connected to N acceleration units 20 in a one-to-one correspondence. The connection method between any two units or between any unit and a processor core is not limited here. In practical applications, any two units or between any unit and a processor core can be directly connected by wires, connected via a bus, or connected via interfaces, connecting devices, etc. For example, the routing unit 102 is connected to the M processor cores 101 and N interrupt proxy units 103 by wires. Each interrupt proxy unit 103 includes an interrupt interface and is connected to an acceleration unit 20 through the interrupt interface.

[0030] Among them, the target interrupt proxy unit in the N interrupt proxy units 103 is used to receive the first interrupt information generated by the target acceleration unit in the N acceleration units 20, convert the format of the first interrupt information to obtain the second interrupt information, and send the second interrupt information to the routing unit 102. The target acceleration unit is connected to the target interrupt proxy unit.

[0031] In this embodiment, the target acceleration unit can generate first interrupt information. The first interrupt information carries data and status information involved in the occurrence, processing, and return of the interrupt. The first interrupt information may conform to a fixed format; this embodiment does not limit the fixed format. For example, the routing unit 102 and the interrupt proxy unit 103 conform to a protocol that enables heterogeneous devices to interconnect. This protocol specifies a fixed format for interrupt information, and the first interrupt information generated by the target acceleration unit must conform to this fixed format.

[0032] Optionally, the first interrupt information includes at least one of the following: interrupt vector, message type, trigger mode, interrupt destination, and destination mode.

[0033] An interrupt vector is an identifier or address pointer used to quickly locate and jump to the entry address of the corresponding interrupt handler function. Interrupt vectors, also called interrupt priorities, indicate the importance of the interrupt information. After receiving an interrupt message, the processor core enters different interrupt handler functions according to the interrupt priority.

[0034] Message types are used to identify the type of interrupt information. Different message types can be defined according to the needs of actual applications, thereby formulating different interrupt handling schemes. In practical applications, interrupt information of the same message type can be assigned different interrupt priorities to indicate their respective importance.

[0035] Trigger mode indicates how the interrupt source is triggered. Generally, trigger modes include edge triggering and pulse triggering. Edge triggering means that the interrupt information is triggered on the rising or falling edge, while pulse triggering means that the interrupt information is triggered on a high or low level.

[0036] The interrupt destination is used to indicate the destination to which the interrupt information needs to be sent. In practical applications, the interrupt destination can be customized according to the needs of the application scenario. Optionally, the interrupt destination is used to indicate the target processor core among M processor cores. Alternatively, each processor core includes a CPU core and an interrupt controller, and the interrupt destination is used to indicate the interrupt controller in the target processor core.

[0037] Destination mode is information used to interpret the meaning of the interrupt destination. In practical applications, the destination mode can be customized according to the needs of the application scenario. Optionally, destination mode includes physical mode and logical mode. Physical mode means that the destination address carried by the interrupt information is the processor core ID (Identification Number), that is, the physical mode indicates that the interrupt destination directly corresponds to the processor core. Logical mode means that the destination address carried by the interrupt information needs to be logically mapped to obtain the processor core ID, that is, the logical mode indicates that the interrupt destination indirectly corresponds to the processor core.

[0038] Optionally, each processor core has its corresponding ID, or each processor core includes a CPU core and an interrupt controller, with the interrupt controller having its corresponding ID. During the generation of the first interrupt information, the target acceleration unit can configure the interrupt vector, message type, and interrupt destination. It can configure the destination mode according to the actual application requirements, select the trigger mode according to the triggering method of the interrupt source, and encapsulate the first interrupt information based on the interrupt vector, message type, interrupt destination, destination mode, and trigger mode.

[0039] The target acceleration unit is connected to the target interrupt proxy unit and can send the first interrupt information to the target interrupt proxy unit. For example, in Figure 2In this process, XPU 2 can generate a first interrupt message and send it to the interrupt interface connected to it. Interrupt proxy unit 2 receives the first interrupt message sent by XPU 2 through the interrupt interface.

[0040] The target interrupt proxy unit can convert the format of the first interrupt information to obtain the second interrupt information. The target interrupt proxy unit is connected to the routing unit 102 and can send the second interrupt information to the routing unit 102. The format of the second interrupt information conforms to the protocol of the routing unit 102, enabling the routing unit 102 to recognize the second interrupt information. The content of the format conversion is not limited here; it can be configured according to the application scenario in practical applications.

[0041] The routing unit 102 is used to route the second interrupt information to the target processor core among the M processor cores 101.

[0042] The second interrupt information carries the interrupt destination, which indicates the target processor core. The routing unit 102 can identify the interrupt destination from the second interrupt information and route the second interrupt information to the target processor core based on the interrupt destination. In practical applications, there can be one or more target processor cores.

[0043] like Figure 2 As shown, each interrupt controller corresponds to an identifier (i.e., ID). The second interrupt information carries the identifier of at least one interrupt controller, and each interrupt controller's identifier is an interrupt destination. The on-chip network can identify each identifier from the second interrupt information and route the second interrupt information to the interrupt controller corresponding to each identifier. For example, the second interrupt information carries the identifier 0001 of interrupt controller 1, the identifier 0002 of interrupt controller 2, and the identifier 0005 of interrupt controller 5. By identifying each identifier, the on-chip network routes the second interrupt information to interrupt controller 1, interrupt controller 2, and interrupt controller 5, thereby routing the second interrupt information to the target processor core.

[0044] The target processor core is used to process the second interrupt information.

[0045] This application does not limit the method by which the target processor core processes the second interrupt information. For example, the target processor core performs format conversion on the second interrupt information to obtain third interrupt information, so that the third interrupt information conforms to the format required by the target processor core, thereby facilitating the target processor core's processing of the third interrupt information.

[0046] Generally, the target processor core can call the interrupt handling function corresponding to the interrupt vector carried by the second interrupt information to process the second interrupt information. Optionally, the target processor core includes registers for storing status bits. When the target processor core begins processing the second interrupt information, it changes the status bits in the registers from indicating that the second interrupt information has not been processed to indicating that the second interrupt information is being processed. For example, if the status bit is 0 indicating that the second interrupt information has not been processed and the status bit is 1 indicating that the second interrupt information is being processed, the target processor core changes the status bit from 0 to 1 when it begins processing the second interrupt information. Optionally, after successfully processing the second interrupt information, the status bits in the registers are cleared so that the status bits corresponding to the interrupt information can be re-stored when subsequent interrupt information is received.

[0047] In this embodiment, the processor core 101 and the acceleration unit 20 are heterogeneous devices. The routing unit 102 and the interrupt proxy unit 103 are a unified standard interface for interconnecting heterogeneous devices, which can solve the compatibility problem of heterogeneous device interconnection. Based on this, the interrupt information processing system can establish a universal high-speed interrupt transmission network between heterogeneous devices, freeing it from the limitations of ecological differences. The acceleration unit 20 can use the unified standard interface to quickly report interrupt information to the processor core 101. The processor core 101 can quickly sense and process the interrupt information, achieving rapid response to device interrupts, reducing the delay in interrupt response between heterogeneous devices, and improving the processing efficiency of interrupt information.

[0048] In one possible implementation, each processor core 101 corresponds to an identifier for indicating the processor core 101, and the second interrupt information includes a destination identifier (i.e., interrupt destination) for indicating the target processor core 101. A routing unit 102 is used to broadcast the second interrupt information to M processor cores 101; the target processor core is used to process the second interrupt information if it is determined that the identifier of the target processor core matches the destination identifier.

[0049] In this embodiment, after receiving the second interrupt information, the routing unit 102 broadcasts the second interrupt information to M processor cores 101. Each processor core 101, upon receiving the second interrupt information, extracts the destination identifier from the second interrupt information and compares it with its own identifier. If the two are inconsistent, no processing of the second interrupt information is required; otherwise, processing of the second interrupt information is performed.

[0050] Optionally, such as Figure 2As shown, the processor core 101 includes a CPU core and an interrupt controller, and the interrupt controller has its corresponding identifier. The routing unit 102 broadcasts second interrupt information to interrupt controllers 1 to M. After receiving the second interrupt information, each interrupt controller compares the destination identifier carried in the second interrupt information with its own identifier. If the two do not match, the second interrupt information is discarded; if the two match, the second interrupt information is temporarily stored and waits for the CPU core to process the second interrupt information.

[0051] For example, the identifier of interrupt controller 1 is 0001, the identifier of interrupt controller 2 is 0002, and so on, with the identifier of interrupt controller M being 000M. Assuming the second interrupt information carries a destination identifier 0002, then: after interrupt controller 1 receives the second interrupt information, it discards the second interrupt information because the destination identifier 0002 is inconsistent with its own identifier 0001; after interrupt controller 2 receives the second interrupt information, it temporarily stores the second interrupt information because the destination identifier 0002 is consistent with its own identifier 0002, waiting for CPU core 2 to process the second interrupt information; and so on, for each interrupt controller from interrupt controller 3 to M, the second interrupt information is discarded because the destination identifier 0002 is inconsistent with its own identifier.

[0052] It is understandable that the processor core indicated by the destination identifier is the target processor core. By broadcasting a second interrupt message to each processor core, the target processor core can receive and process the second interrupt message. Furthermore, broadcasting interrupt messages can reduce the routing time and improve routing efficiency.

[0053] Optionally, such as Figure 3 As shown, the routing unit 102 includes multiple routing nodes 1021, each routing node 1021 being connected to at least one processor core 101 from M processor cores 101 and at least one interrupt proxy unit 103 from N interrupt proxy units 103. Assuming the number of routing nodes 1021 is L (L is a positive integer), for ease of distinction, in... Figure 3 In this context, the L routing nodes are represented sequentially as routing node 1 to routing node L.

[0054] Each routing node 1021 is connected to at least one processor core 101. Different routing nodes 1021 may be connected to the same number or different numbers of processor cores 101. For example, in Figure 3 In the process, routing node 1 is connected to processor core 1, routing node 2 is connected to processor cores 2 through 4, and routing node L is connected to processor core M.

[0055] Similarly, each routing node 1021 is connected to at least one interrupt proxy unit 103. Different routing nodes 1021 may be connected to the same or different number of interrupt proxy units 103. For example, in... Figure 3 In the middle, routing node 1 is connected to interrupt agent units 1 to 3, routing node 2 is connected to interrupt agent unit 4, and routing node L is connected to interrupt agent unit N.

[0056] Furthermore, every two routing nodes 1021 are interconnected. Optionally, the routing unit 102 includes an internal bus, and every two routing nodes 1021 are interconnected via the internal bus. The interrupt information processing system may include an external bus located outside the routing unit 102, and the interrupt proxy unit, routing unit, and processor core may be interconnected via the external bus.

[0057] Optionally, the routing unit 102 includes an on-chip network, such as... Figure 4 As shown, the on-chip network comprises L on-chip network nodes. In this example, each routing node includes one on-chip network node. For ease of distinction, the L on-chip network nodes are sequentially designated as on-chip network node 1 to on-chip network node L, with each pair of on-chip network nodes interconnected. Each on-chip network node is connected to at least one processor core and at least one interrupt proxy unit. Optionally, each processor core includes a CPU core and an interrupt controller, and each on-chip network node is connected to one interrupt controller and one interrupt proxy unit. In this example, L=M=N.

[0058] The first routing node is used to receive the second interrupt information sent by the target interrupt proxy unit, broadcast the second interrupt information to each processor core 101 connected to the first routing node, and transmit the second interrupt information to other routing nodes among the multiple routing nodes other than the first routing node. The first routing node is connected to the target interrupt proxy unit. Other routing nodes are used to broadcast the second interrupt information to each processor core 101 connected to other routing nodes.

[0059] In this embodiment, the target acceleration unit and the target interrupt proxy unit are connected, and the target interrupt proxy unit is connected to the first routing node. Based on this, after generating first interrupt information, the target acceleration unit can send the first interrupt information to the target interrupt proxy unit. The target interrupt proxy unit converts the first interrupt information into second interrupt information and then sends the second interrupt information to the first routing node.

[0060] like Figure 4As shown, assuming interrupt proxy unit 2 is the target interrupt proxy unit, then: after receiving the first interrupt information, interrupt proxy unit 2 converts the first interrupt information into second interrupt information and sends the second interrupt information to on-chip network node 2. In this example, the first routing node is on-chip network node 2.

[0061] The first routing node is connected to at least one processor core 101 and can broadcast a second interrupt message to each connected processor core 101. For example, in Figure 4 In the middle, the on-chip network node 2 is connected to the interrupt controller 2 and can broadcast the second interrupt information to the interrupt controller 2.

[0062] Furthermore, since any two routing nodes are interconnected, the first routing node can transmit second interrupt information to other routing nodes, which in turn broadcast the second interrupt information to each connected processor core 101. For example, in Figure 4 In this configuration, on-chip network node 2 can transmit second interrupt information to on-chip network nodes 1, 3, and L. On-chip network node 1 is connected to interrupt controller 1 and can broadcast the second interrupt information to interrupt controller 1; on-chip network node 3 is connected to interrupt controller 3 and can broadcast the second interrupt information to interrupt controller 3; and so on. On-chip network node L is connected to interrupt controller M and can broadcast the second interrupt information to interrupt controller M.

[0063] Optionally, such as Figure 5 As shown, the target interrupt proxy unit transmits the second interrupt information to the first routing node. Upon receiving the second interrupt information, the first routing node broadcasts the second interrupt information to each interrupt controller connected to it, and also transmits it to other routing nodes. Other routing nodes, upon receiving the second interrupt information, broadcast it to each interrupt controller connected to them. Each interrupt controller, upon receiving the second interrupt information, extracts the destination identifier from it and compares it with its own identifier. If they match, the controller transmits the second interrupt information to the CPU core connected to it. The CPU core, upon receiving the second interrupt information, can then process it.

[0064] By transmitting the second interrupt information from the first routing node to other routing nodes, each routing node can obtain the second interrupt information and broadcast it to the connected processor cores, thus ensuring that all processor cores receive the second interrupt information. Subsequently, the target processor core can identify and process the second interrupt information, guaranteeing that the interrupt information is handled correctly by the processor core.

[0065] In another possible implementation, each processor core 101 corresponds to an identifier for indicating the processor core 101, and the second interrupt information includes a destination identifier for indicating the target processor core. The routing unit 102 is used to obtain the identifiers of each processor core 101, determine the target processor core whose identifier matches the destination identifier from the M processor cores 101, and send the second interrupt information to the target processor core.

[0066] In this embodiment, the routing unit 102 may include a storage unit, or the routing unit 102 may be connected to a storage unit. The storage unit is used to store the identifiers of each processor core 101, and the routing unit 102 reads the identifiers of each processor core 101 from the storage unit. After receiving the second interrupt information, the routing unit 102 extracts the destination identifier from the second interrupt information, compares the destination identifier with the identifier of each processor core 101, and if there is a processor core 101 whose identifier matches the destination identifier, the routing unit 102 transmits the second interrupt information to that processor core 101.

[0067] Optionally, such as Figure 2 As shown, the processor core 101 includes a CPU core and an interrupt controller, each with its corresponding identifier. The routing unit 102 reads the identifiers of each interrupt controller from the storage unit. Upon receiving the second interrupt information, it compares the destination identifier carried in the second interrupt information with the identifier of each interrupt controller, and transmits the second interrupt information to the interrupt controller that matches the comparison.

[0068] For example, the identifier of interrupt controller 1 is 0001, the identifier of interrupt controller 2 is 0002, and so on, with the identifier of interrupt controller M being 000M. Assuming the second interrupt information carries a destination identifier of 0002, then: after receiving the second interrupt information, routing unit 102 first compares the destination identifier 0002 with the identifier 0001 of interrupt controller 1. Since they are inconsistent, routing unit 102 then compares the destination identifier 0002 with the identifier 0002 of interrupt controller 2. Since they are consistent, routing unit 102 transmits the second interrupt information to interrupt controller 2.

[0069] By comparing the identifier of each processor core with the destination identifier through the routing unit, and transmitting the second interrupt information to the processor cores that match the identification, the routing unit can accurately identify the target processor core and transmit the second interrupt information only to the target processor core, thereby reducing the consumption of transmission resources.

[0070] Optionally, such as Figure 3As shown, the routing unit 102 includes multiple routing nodes 1021, and each routing node 1021 is connected to at least one processor core 101 among M processor cores 101 and at least one interrupt proxy unit 103 among N interrupt proxy units 103.

[0071] The first routing node is used to receive the second interrupt information sent by the target interrupt proxy unit, obtain the correspondence between each routing node and the identifiers of each connected processor core 101, and determine the second routing node from multiple routing nodes based on the destination identifier and the correspondence. The first routing node is connected to the target interrupt proxy unit, and the second routing node is connected to the target processor core. The first routing node is also used to send the second interrupt information to the second routing node when the second routing node is not the first routing node. The second routing node is used to send the second interrupt information to the target processor core.

[0072] In this embodiment, after the target acceleration unit generates the first interrupt information, it can send the first interrupt information to the target interrupt proxy unit. After the target interrupt proxy unit converts the first interrupt information into second interrupt information, it sends the second interrupt information to the first routing node.

[0073] Each routing node is connected to a storage unit, which can store the identifier of each routing node, the identifier of each processor core 101, and the correspondence between the identifier of each routing node and the identifiers of the processor cores 101 connected to that routing node. Optionally, the storage unit stores data in key-value pairs, where the key in the key-value pair stores the identifier of a routing node, and the value in the key-value pair stores the identifiers of each processor core 101 connected to that routing node.

[0074] The first routing node can read the correspondence between each routing node and the identifiers of each connected processor core 101 from the storage unit. After receiving the second interrupt information, it extracts the destination identifier from the second interrupt information, compares the destination identifier with the identifier of each processor core 101, and if there is a processor core 101 whose identifier matches the destination identifier, it obtains the identifier of the routing node connected to that processor core 101 based on the correspondence.

[0075] In some cases, the identifier of the first routing node is the identifier of the second routing node. In this case, the first routing node is the second routing node, and the second interrupt information is sent to the target processor core through the second routing node.

[0076] For example, in Figure 4In this process, interrupt proxy unit 2 sends a second interrupt message to on-chip network node 2. The destination identifier carried in the second interrupt message is the identifier of interrupt controller 2. On-chip network node 2 determines that the destination identifier is the identifier of interrupt controller 2 by comparing the destination identifier with the identifier of each interrupt controller, and determines the identifier of on-chip network node 2 corresponding to the identifier of interrupt controller 2 based on the correspondence. In this case, on-chip network node 2 is both the first routing node and the second routing node. On-chip network node 2 sends the second interrupt message to interrupt controller 2.

[0077] In some cases, the identifier of the first routing node is the identifier of another routing node, which is the second routing node, and the second routing node is not the first routing node. The first routing node transmits the second interrupt information to the second routing node, and then the second routing node sends the second interrupt information to the target processor core.

[0078] For example, in Figure 4 In this process, interrupt proxy unit 2 sends a second interrupt message to on-chip network node 2. The destination identifier carried in the second interrupt message is the identifier of interrupt controller 1. On-chip network node 2 determines that the destination identifier is the identifier of interrupt controller 1 by comparing the destination identifier with the identifier of each interrupt controller, and determines that the identifier of interrupt controller 1 corresponds to the identifier of on-chip network node 1 based on the correspondence. In this case, on-chip network node 2 is the first routing node, and on-chip network node 1 is the second routing node. On-chip network node 2 transmits the second interrupt message to on-chip network node 1, and then on-chip network node 1 sends the second interrupt message to interrupt controller 1.

[0079] Optionally, the second routing node is connected to at least one processor core. In some cases, the second routing node broadcasts second interrupt information to each processor core, which then identifies and processes the second interrupt information. In other cases, the second routing node extracts a destination identifier from the second interrupt information, compares the destination identifier with the identifier of each connected processor core 101, and sends the second interrupt information to the processor core 101 that passed the comparison (i.e., the target processor core).

[0080] By identifying the second routing node through the first routing node, and having the second routing node transmit the second interrupt information to the target processor core, the second interrupt information is accurately routed to the target processor core, ensuring that the interrupt information can be correctly processed by the processor core.

[0081] In practical applications, the same acceleration unit 20 can generate at least one interrupt message. In some cases, the interrupt messages do not need to be processed in sequence; that is, the interrupt messages generated earlier can be processed first or later, and the interrupt messages generated later can be processed first or later. For interrupt messages that do not need to be processed in sequence, the routing unit 102 can route the interrupt messages at any time and arbitrarily. This application embodiment does not limit the routing method.

[0082] In other cases, the interrupt information needs to be processed sequentially; that is, the interrupt information generated first needs to be processed first, and the interrupt information generated later needs to be processed later. For interrupt information that needs to be processed sequentially, this application provides implementation methods 1 and 2, and the routing unit 102 can route the interrupt information according to implementation method 1 or 2.

[0083] In implementation method 1, the second interrupt information carries a sorting flag, which is used to indicate whether the second interrupt information is sent in sequence. The target interrupt proxy unit is used to send the second interrupt information to the routing unit 102 when the sorting flag of the second interrupt information indicates that it is sent in sequence, and the previous interrupt information of the second interrupt information has been sent to the routing unit 102. The previous interrupt information is obtained by format conversion of the interrupt information generated by the target acceleration unit and carries a sorting flag indicating that it is sent in sequence.

[0084] In this embodiment, each interrupt message generated by the target acceleration unit carries a sorting flag, which indicates whether the interrupt messages are sent in sequence. Optionally, the sorting flag is a first value, indicating that the interrupt messages need to be sent in sequence; or the sorting flag is a second value, indicating that the interrupt messages do not need to be sent in sequence. The first value and the second value are different values; for example, the first value is 1 and the second value is 0.

[0085] Assuming the target acceleration unit generates at least two interrupt messages, and each interrupt message carries a sorting flag indicating that it needs to be sent in sequence, then these interrupt messages are interrupt messages that need to be processed in sequence.

[0086] Optionally, each time the target acceleration unit generates an interrupt message, it transmits the interrupt message to the target interrupt proxy unit. In this case, the order in which the target interrupt proxy unit receives the interrupt messages is the same as the order in which the interrupt messages are generated. The target interrupt proxy unit converts the format of the received interrupt messages sequentially according to the order of reception and transmits the converted interrupt messages to the routing unit 102. The order in which the routing unit 102 receives the converted interrupt messages is the same as the order in which the interrupt messages are generated. Optionally, the target interrupt proxy unit transmits the converted interrupt messages to the first routing node. Based on this, the order in which the first routing node receives the converted interrupt messages is the same as the order in which the interrupt messages are generated.

[0087] Optionally, each interrupt message generated by the target acceleration unit carries a timestamp. The target acceleration unit generates at least two interrupt messages and transmits each interrupt message to the target interrupt proxy unit. The timestamps carried by the interrupt messages can reflect the order in which the interrupt messages were generated. Based on the timestamps carried by each interrupt message, the target interrupt proxy unit sequentially converts the format of each received interrupt message according to the order in which the interrupt messages were generated, and then transmits the converted interrupt messages to the routing unit 102. In this case, the order in which the routing unit 102 receives the converted interrupt messages is the order in which the interrupt messages were generated. Optionally, the target interrupt proxy unit transmits the converted interrupt messages to the first routing node. Based on this, the order in which the first routing node receives the converted interrupt messages is the order in which the interrupt messages were generated.

[0088] Optionally, the routing unit 102 can receive each interrupt information after format conversion and identify the generation order of the interrupt information based on the timestamps carried by each interrupt information after format conversion. Optionally, the target interrupt proxy unit transmits each interrupt information after format conversion to the first routing node, and based on this, the first routing node identifies the generation order of the interrupt information based on the timestamps carried by each interrupt information after format conversion.

[0089] Routing unit 102 (or the first routing node) routes each interrupt message to its corresponding processor core according to the order in which the interrupt messages are generated. It can be understood that any two interrupt messages can be routed to the same processor core or to different processor cores. For simplicity, the following explanation uses two interrupt messages as an example.

[0090] In this example, routing unit 102 (or the first routing node) can receive two interruption messages, both of which are format-converted interruption messages, including the second interruption message and the interruption message preceding the second interruption message (hereinafter referred to as the preceding interruption message).

[0091] Optionally, the routing unit 102 (or the first routing node) receives the previous interrupt information first, and then receives the second interrupt information. The routing unit 102 (or the first routing node) first routes the previous interrupt information to the corresponding processor core, and then routes the second interrupt information to the target processor core. The reception time of the second interrupt information may be earlier or later than the time when the previous interrupt information is routed to the corresponding processor core, and the corresponding processor core may or may not be the target processor core.

[0092] Optionally, routing unit 102 (or the first routing node) receives the previous interrupt information and the second interrupt information, and the order in which they are received is not limited here. Based on the timestamps carried by the previous interrupt information and the second interrupt information, routing unit 102 (or the first routing node) first routes the previous interrupt information to the corresponding processor core, and then routes the second interrupt information to the target processor core. The corresponding processor core may or may not be the target processor core.

[0093] It should be noted that the way the routing unit 102 (or the first routing node) routes the previous interrupt information to the corresponding processor core is the same as the way it routes the second interrupt information to the target processor core. Please refer to the description above, which will not be repeated here.

[0094] For example, in one implementation, such as Figure 6 As shown, the target acceleration unit transmits each interrupt message that needs to be sent sequentially to the target interrupt proxy unit. The target interrupt proxy unit then transmits each interrupt message it receives to the first routing node. In this way, the target interrupt proxy unit can sequentially transmit multiple interrupt messages that need to be sent sequentially to the first routing node.

[0095] The first routing node broadcasts each interrupt message to the respective interrupt controllers in the order they are received. Specifically, for two interrupt messages received sequentially, the first routing node first broadcasts the interrupt message received earlier to the respective interrupt controllers, and then broadcasts the interrupt message received later to the respective interrupt controllers.

[0096] For each interrupt message, each interrupt controller, upon receiving the interrupt message, extracts the destination identifier from it and compares it with its own identifier. If they match, the interrupt message is transmitted to the CPU core connected to that interrupt controller. The CPU core, upon receiving the interrupt message, can then process it.

[0097] By routing the previous interrupt information to the corresponding processor core through the routing unit 102, and then routing the second interrupt information to the target processor core, the interrupt information is routed in the order of interrupt information. This allows the processor core to process the interrupt information that was routed first and then process the interrupt information that was routed later, ensuring that the interrupt information is processed in order.

[0098] In implementation method 2, based on implementation method 1, the routing unit 102 is further configured to route the previous interrupt information to the corresponding processor core among the M processor cores; the corresponding processor core is configured to send response information for the previous interrupt information to the routing unit 102 upon receiving the previous interrupt information; the routing unit 102 is further configured to send the response information for the previous interrupt information to the target interrupt proxy unit; the target interrupt proxy unit is configured to send the second interrupt information to the routing unit 102 upon obtaining the response information for the previous interrupt information.

[0099] In this embodiment, the routing unit 102 (or the first routing node) routes the previous interrupt information to the corresponding processor core. Upon receiving the previous interrupt information, the corresponding processor core (or the corresponding interrupt controller within the processor core) generates response information for the previous interrupt information and transmits this response information to the routing unit 102 (or the first routing node), so that the routing unit 102 (or the first routing node) routes the response information to the target interrupt proxy unit. Upon receiving the response information, the target interrupt proxy unit sends second interrupt information to the routing unit 102 (or the first routing node), so that the routing unit 102 (or the first routing node) routes the second interrupt information to the target processor core.

[0100] This application embodiment does not limit the content of the response information. For example, the response information carries an identifier of the previous interrupt information. The target interrupt proxy unit can send the previous interrupt information to the routing unit 102 (or the first routing node), so that the routing unit 102 (or the first routing node) routes the previous interrupt information to the corresponding processor core. After receiving the previous interrupt information, the corresponding processor core generates response information for the previous interrupt information and sends the response information to the routing unit 102 (or the first routing node), so that the response information is routed to the target interrupt proxy unit through the routing unit 102 (or the first routing node). The target interrupt proxy unit extracts an identifier from the response information. If the identifier is the identifier of the previous interrupt information, it sends the second interrupt information to the routing unit 102 (or the first routing node), so that the second interrupt information is routed to the target processor core through the routing unit 102 (or the first routing node).

[0101] Optionally, the response information carries the identifier of the target interrupt proxy unit. The corresponding interrupt controller transmits the response information to the routing node connected to it (for ease of description, this routing node is referred to as the corresponding routing node). The corresponding routing node identifies the first routing node connected to the target interrupt proxy unit based on the identifier carried in the response information and transmits the response information to the first routing node.

[0102] Optionally, each routing node includes a storage unit, or each routing node is connected to a storage unit. The storage unit stores the mapping relationship between each routing node and each interrupt proxy unit it is connected to. For example, the mapping relationship is a key-value pair, where the key represents the identifier of the routing node, and the value represents the identifier of each interrupt proxy unit connected to the routing node. Based on this mapping relationship and the identifier carried in the response information, the corresponding routing node determines the first routing node connected to the target interrupt proxy unit and transmits the response information to the first routing node.

[0103] The first routing node can identify the target interrupt proxy unit based on the identifier carried in the response information and send the response information of the previous interrupt information to the target interrupt proxy unit. Alternatively, the first routing node is connected to at least two interrupt proxy units and can broadcast the response information of the previous interrupt information to each interrupt proxy unit. The target interrupt proxy unit determines that the received response information is the response information of the previous interrupt information based on its own identifier and the identifier carried in the response information.

[0104] By receiving the response information for the previous interrupt information before sending the second interrupt information, it is ensured that the previous interrupt information is successfully received before the next interrupt information is sent, thus enabling the processor core to process interrupt information in sequence.

[0105] Optionally, the previous interrupt information carries a response mode, which indicates whether to provide feedback on the previous interrupt information. Optionally, the response mode is a third value, indicating that feedback on the previous interrupt information is required; the response mode is a fourth value, indicating that feedback on the previous interrupt information is not required. The third and fourth values ​​are different values, for example, the third value is 1 and the fourth value is 0. The target interrupt proxy unit determines whether to use implementation mode 1 or implementation mode 2 to send the interrupt information based on the response mode carried by the previous interrupt information.

[0106] In the above technical solution, the interrupt information processing system includes M processor cores, a routing unit, and N interrupt proxy units. The routing unit is connected to the M processor cores and the N interrupt proxy units, and the N interrupt proxy units are connected to the N acceleration units in a one-to-one correspondence.

[0107] After the target acceleration unit generates the first interrupt information, the target interrupt proxy unit receives the first interrupt information, converts its format to obtain the second interrupt information, and sends the second interrupt information to the routing unit. The routing unit routes the second interrupt information to the target processor core, which then processes it. In this way, interrupt information generated by the target acceleration unit is processed by the target processor core, enabling the system to respond to emergencies in a timely manner and ensuring stable system operation.

[0108] Furthermore, the routing unit and interrupt proxy unit enable the connection of any type of acceleration unit to the processor core, reducing connection complexity and improving the applicability of the interrupt information processing system.

[0109] This application provides a method for processing interrupt information, which is executed by the interrupt information processing system described above. The interrupt information processing system includes M processor cores, a routing unit, and N interrupt proxy units. The routing unit is connected to the M processor cores and the N interrupt proxy units. The N interrupt proxy units are connected one-to-one with the N acceleration units. M and N are positive integers greater than or equal to 1. Figure 7 As shown, the method includes the following steps.

[0110] Step 701: The target interrupt agent unit among the N interrupt agent units receives the first interrupt information generated by the target acceleration unit among the N acceleration units, performs format conversion on the first interrupt information to obtain the second interrupt information, sends the second interrupt information to the routing unit, and the target acceleration unit connects with the target interrupt agent unit.

[0111] Step 702: The second interrupt information is routed to the target processor core among the M processor cores through the routing unit.

[0112] Step 703: Process the second interrupt information through the target processor core.

[0113] In one possible implementation, each processor core corresponds to an identifier for indicating the processor core, and the second interrupt information includes a destination identifier for indicating the target processor core. The second interrupt information is routed to the target processor core among the M processor cores via the routing unit, including: The second interrupt information is broadcast to M processor cores via the routing unit; The second interrupt information is processed through the target processor core, including: The second interrupt information is processed by the target processor core if the identifier of the target processor core matches the destination identifier.

[0114] In one possible implementation, the routing unit includes multiple routing nodes, each routing node being connected to at least one of the M processor cores and at least one of the N interrupt proxy units. The second interrupt information is broadcast to M processor cores via the routing unit, including: The first routing node receives the second interrupt information sent by the target interrupt proxy unit, broadcasts the second interrupt information to each processor core connected to the first routing node, and transmits the second interrupt information to other routing nodes among multiple routing nodes except the first routing node. The first routing node is connected to the target interrupt proxy unit. The second interrupt information is broadcast by other routing nodes to each processor core connected to other routing nodes.

[0115] In one possible implementation, each processor core corresponds to an identifier for indicating the processor core, and the second interrupt information includes a destination identifier for indicating the target processor core. The second interrupt information is routed to the target processor core among the M processor cores via the routing unit, including: The identifiers of each processor core are obtained through the routing unit. The target processor core whose identifier matches the destination identifier is determined from the M processor cores, and the second interrupt information is sent to the target processor core.

[0116] In one possible implementation, the routing unit includes multiple routing nodes, each routing node being connected to at least one of the M processor cores and at least one of the N interrupt proxy units. The identifiers of each processor core are obtained through the routing unit. From the M processor cores, the target processor core whose identifier matches the destination identifier is determined. A second interrupt message is sent to the target processor core, including: The first routing node receives the second interrupt information sent by the target interrupt proxy unit, obtains the correspondence between the identifiers of each routing node and the identifiers of each connected processor core, and determines the second routing node from multiple routing nodes based on the destination identifier and the correspondence. The first routing node is connected to the target interrupt proxy unit, and the second routing node is connected to the target processor core. If the first routing node sends a second interruption message to the second routing node when the second routing node is not the first routing node; The second interrupt information is sent to the target processor core through the second routing node.

[0117] In one possible implementation, the second interrupt information carries a sorting flag, which is used to indicate whether the second interrupt information is sent in sequence; Send a second interrupt message to the routing unit, including: If the target interrupt proxy unit sends the second interrupt information to the routing unit in the case that the previous interrupt information has been sent to the routing unit, the second interrupt information is sent by the target interrupt proxy unit. The previous interrupt information is obtained by converting the format of the interrupt information generated by the target acceleration unit and carries a sorting mark indicating that it should be sent in order.

[0118] In one possible implementation, the method also includes: The routing unit routes the previous interrupt information to the corresponding processor core among the M processor cores. Upon receiving the previous interrupt information, the corresponding processor core sends a response message to the routing unit in response to the previous interrupt information. The routing unit sends a response message for the previous interrupt information to the target interrupt agent unit. Send a second interrupt message to the routing unit, including: Upon receiving the response information for the previous interrupt information, the target interrupt agent unit sends the second interrupt information to the routing unit.

[0119] In the above method, the interrupt information processing system includes M processor cores, a routing unit, and N interrupt proxy units. The routing unit is connected to the M processor cores and the N interrupt proxy units, and the N interrupt proxy units are connected to the N acceleration units in a one-to-one correspondence.

[0120] After the target acceleration unit generates the first interrupt information, the target interrupt proxy unit receives the first interrupt information, converts its format to obtain the second interrupt information, and sends the second interrupt information to the routing unit. The routing unit routes the second interrupt information to the target processor core, which then processes it. In this way, interrupt information generated by the target acceleration unit is processed by the target processor core, enabling the system to respond to emergencies in a timely manner and ensuring stable system operation.

[0121] Furthermore, the routing unit and interrupt proxy unit enable the connection of any type of acceleration unit to the processor core, reducing connection complexity and improving the applicability of the interrupt information processing system.

[0122] The above-described method and system for processing interrupt information are based on the same inventive concept, and the technical features described in the above description of the interrupt information processing system are also applicable to the above-described method embodiments. For specific details, please refer to the technical features described in the above description of the interrupt information processing system; for the sake of brevity, they will not be repeated here.

[0123] This application also provides a chip that includes the interrupt information processing system mentioned above. The interrupt information processing system is connected to N acceleration units. The contents of the interrupt information processing system and the acceleration units have been described above and will not be repeated here.

[0124] Optionally, such as Figure 8 As shown, the chip also includes an input interface 801 and an output interface 802, which are interconnected with an interrupt information processing system via a bus 803. The input interface is used to receive data sent to the chip, and the output interface is used to output data generated by the chip.

[0125] This application also provides an electronic device, such as... Figure 9 As shown, the electronic device includes the chip mentioned above. Optionally, the electronic device also includes a memory 901, a transceiver 902, and a bus 903, which are interconnected via the bus 903. The memory 901 is used to store data, and the transceiver 902 is used to receive and transmit data.

[0126] Electronic devices may include terminal devices and servers. Terminal devices can be any electronic product capable of human-computer interaction with a user through one or more methods such as a keyboard, touchpad, remote control, voice interaction, or handwriting device. For example, a terminal device can be a mobile phone or a computer, where mobile phones include, but are not limited to, smartphones, foldable phones, slider phones, or flip phones, and computers include, but are not limited to, tablets, laptops, desktop computers, PPCs (Pocket PCs), or PCs (Personal Computers). In practical applications, terminal devices may also include smart speakers, smartwatches, PDAs (Personal Digital Assistants), wearable devices, smart car systems, smart TVs, etc. A server may be a single server or a server cluster consisting of multiple servers; this application embodiment does not limit this. Furthermore, the functions of the terminal device and the server are not limited herein.

[0127] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0128] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0129] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A system for interrupting processing of information, characterized by The system includes M processor cores, a routing unit, and N interrupt proxy units. The routing unit is connected to the M processor cores and the N interrupt proxy units. The N interrupt proxy units are connected to N acceleration units in a one-to-one correspondence. M and N are positive integers greater than or equal to 1. The target interrupt proxy unit among the N interrupt proxy units is used to receive the first interrupt information generated by the target acceleration unit among the N acceleration units, convert the format of the first interrupt information to obtain the second interrupt information, and send the second interrupt information to the routing unit. The target acceleration unit is connected to the target interrupt proxy unit. The routing unit is used to route the second interrupt information to the target processor core among the M processor cores; The target processor core is used to process the second interrupt information.

2. The system of claim 1, wherein, Each processor core corresponds to an identifier for indicating the processor core, and the second interrupt information includes a destination identifier for indicating the target processor core; The routing unit is used to broadcast the second interrupt information to the M processor cores; The target processor core is configured to process the second interrupt information if it is determined that the identifier of the target processor core is consistent with the destination identifier.

3. The system of claim 2, wherein, The routing unit includes multiple routing nodes, and each routing node is connected to at least one processor core among the M processor cores and at least one interrupt proxy unit among the N interrupt proxy units; A first routing node is configured to receive the second interrupt information sent by the target interrupt proxy unit, broadcast the second interrupt information to each processor core connected to the first routing node, and transmit the second interrupt information to other routing nodes among the plurality of routing nodes besides the first routing node. The first routing node is connected to the target interrupt proxy unit. The other routing nodes are used to broadcast the second interrupt information to each processor core connected to the other routing nodes.

4. The system of claim 1, wherein, Each processor core corresponds to an identifier for indicating the processor core, and the second interrupt information includes a destination identifier for indicating the target processor core; The routing unit is used to obtain the identifiers of each processor core, determine the target processor core whose identifier matches the destination identifier from the M processor cores, and send the second interrupt information to the target processor core.

5. The system of claim 4, wherein, The routing unit includes multiple routing nodes, and each routing node is connected to at least one processor core among the M processor cores and at least one interrupt proxy unit among the N interrupt proxy units; A first routing node is configured to receive the second interrupt information sent by the target interrupt proxy unit, obtain the correspondence between each routing node and the identifiers of each connected processor core, and determine a second routing node from the plurality of routing nodes based on the destination identifier and the correspondence. The first routing node is connected to the target interrupt proxy unit, and the second routing node is connected to the target processor core. The first routing node is further configured to send the second interrupt information to the second routing node if the second routing node is not the first routing node; The second routing node is used to send the second interrupt information to the target processor core.

6. The system according to any one of claims 1 to 5, characterized in that The second interrupt information carries a sorting flag, which is used to indicate whether the second interrupt information is sent in sequence; The target interrupt proxy unit is configured to send the second interrupt information to the routing unit when the sorting mark of the second interrupt information indicates that it should be sent in sequence, and the previous interrupt information has been sent to the routing unit. The previous interrupt information is obtained by format conversion of the interrupt information generated by the target acceleration unit and carries a sorting mark indicating that it should be sent in sequence.

7. The system according to claim 6, characterized in that, The routing unit is also used to route the previous interrupt information to the corresponding processor core among the M processor cores; The corresponding processor core is used to send response information for the previous interrupt information to the routing unit upon receiving the previous interrupt information; The routing unit is also configured to send response information for the previous interruption information to the target interruption proxy unit; The target interrupt proxy unit is used to send the second interrupt information to the routing unit when it receives the response information for the previous interrupt information.

8. A method of interrupting processing of information, characterized by The method is executed by an interrupt information processing system, which includes M processor cores, a routing unit, and N interrupt proxy units. The routing unit is connected to the M processor cores and the N interrupt proxy units, and the N interrupt proxy units are connected one-to-one with N acceleration units. M and N are positive integers greater than or equal to 1. The method includes: The target interrupt proxy unit receives the first interrupt information generated by the target acceleration unit among the N acceleration units, converts the format of the first interrupt information to obtain the second interrupt information, and sends the second interrupt information to the routing unit. The target acceleration unit is connected to the target interrupt proxy unit. The routing unit routes the second interrupt information to the target processor core among the M processor cores. The second interrupt information is processed by the target processor core.

9. The method of claim 8, wherein, Each processor core corresponds to an identifier for indicating the processor core, and the second interrupt information includes a destination identifier for indicating the target processor core; The step of routing the second interrupt information to the target processor core among the M processor cores through the routing unit includes: The second interrupt information is broadcast to the M processor cores through the routing unit; The process of processing the second interrupt information through the target processor core includes: The second interrupt information is processed by the target processor core if it determines that the identifier of the target processor core matches the destination identifier.

10. The method of claim 9, wherein, The routing unit includes multiple routing nodes, and each routing node is connected to at least one processor core among the M processor cores and at least one interrupt proxy unit among the N interrupt proxy units; The step of broadcasting the second interrupt information to the M processor cores through the routing unit includes: The first routing node receives the second interrupt information sent by the target interrupt proxy unit, broadcasts the second interrupt information to each processor core connected to the first routing node, and transmits the second interrupt information to other routing nodes among the plurality of routing nodes except the first routing node. The first routing node is connected to the target interrupt proxy unit. The second interrupt information is broadcast to each processor core connected to the other routing node via the other routing node.

11. The method of claim 8, wherein, Each processor core corresponds to an identifier for indicating the processor core, and the second interrupt information includes a destination identifier for indicating the target processor core; The step of routing the second interrupt information to the target processor core among the M processor cores through the routing unit includes: The routing unit obtains the identifiers of each processor core, determines the target processor core whose identifier matches the destination identifier from the M processor cores, and sends the second interrupt information to the target processor core.

12. The method of claim 11, wherein, The routing unit includes multiple routing nodes, and each routing node is connected to at least one processor core among the M processor cores and at least one interrupt proxy unit among the N interrupt proxy units; The step of obtaining the identifiers of each processor core through the routing unit, determining the target processor core whose identifier matches the destination identifier from the M processor cores, and sending the second interrupt information to the target processor core includes: The first routing node receives the second interrupt information sent by the target interrupt proxy unit, obtains the correspondence between each routing node and the identifiers of each connected processor core, and determines the second routing node from the plurality of routing nodes based on the destination identifier and the correspondence. The first routing node is connected to the target interrupt proxy unit, and the second routing node is connected to the target processor core. The first routing node sends the second interrupt information to the second routing node when the second routing node is not the first routing node; The second interrupt information is sent to the target processor core through the second routing node.

13. The method according to any one of claims 8 to 12, characterized in that, The second interrupt information carries a sorting flag, which is used to indicate whether the second interrupt information is sent in sequence; Sending the second interrupt information to the routing unit includes: When the target interrupt proxy unit sends the second interrupt information to the routing unit in accordance with the ordering mark indicating that the second interrupt information should be sent in sequence, and the previous interrupt information has already been sent to the routing unit, the second interrupt information is sent to the routing unit. The previous interrupt information is obtained by format conversion of the interrupt information generated by the target acceleration unit and carries an ordering mark indicating that the second interrupt information should be sent in sequence.

14. The method of claim 13, wherein, The method further includes: The routing unit routes the previous interrupt information to the corresponding processor core among the M processor cores. Upon receiving the previous interrupt information, the corresponding processor core sends a response message to the routing unit in response to the previous interrupt information. The routing unit sends a response message for the previous interruption information to the target interruption proxy unit. Sending the second interrupt information to the routing unit includes: Upon receiving the response information for the previous interruption information, the target interruption proxy unit sends the second interruption information to the routing unit.

15. A chip, characterized by The chip includes the interrupt information processing system according to any one of claims 1 to 7.

16. An electronic device, comprising: The electronic device includes the chip of claim 15.

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