Timing adjustment circuit for integrated circuit bus and electronic device
By introducing a latch module and a control module into the I2C bus, the timing of the serial data signal is adjusted so that it jumps during the low-level period of the serial clock signal, thus solving the communication anomaly problem caused by the I2C bus signal transmission delay and achieving higher reliability and consistency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING TSINGTENG MICROSYSTEM CO LTD
- Filing Date
- 2026-02-12
- Publication Date
- 2026-06-19
AI Technical Summary
The transmission delay of serial data and serial clock signals on the I2C bus can cause communication anomalies. Existing technologies rely on manual adjustment and timing constraints, which increases design cycle and manpower costs, and makes it difficult to ensure the consistency of adjustments.
A timing adjustment circuit for an integrated circuit bus is provided, including a latch module and a control module, which monitors the serial clock signal and the data signal. By adjusting the timing of the serial data signal, the hold time is made greater than or equal to 0, ensuring that the data bit signal jumps during the low level period of the serial clock signal and avoiding misjudgment.
It improves the reliability and stability of signal transmission, reduces manual intervention, lowers labor costs, and ensures the consistency of timing adjustments.
Smart Images
Figure CN122240546A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of electronic communication technology, and in particular to a timing adjustment circuit and electronic device for an integrated circuit bus. Background Technology
[0002] The I2C bus (Inter-Integrated Circuit Bus) is a two-wire serial bus. With its advantages such as two-wire structure, fewer pins, and easy expansion, it is widely used for communication between various microcontrollers, sensors, memories, and other integrated circuits.
[0003] The I2C bus consists of a serial data line (SDA) and a serial clock line (SCL). In some application scenarios, signal transmission delays on the serial data and clock lines can lead to communication anomalies. Related technologies typically rely on manual adjustments and timing constraints to resolve timing delay issues. This approach increases design time and manpower costs, and makes it difficult to ensure consistency in each adjustment.
[0004] Therefore, how to solve the above-mentioned technical problems has become one of the most urgent technical problems to be solved at this stage. Summary of the Invention
[0005] To address the aforementioned technical problems, this disclosure provides a timing adjustment circuit and electronic device for an integrated circuit bus, which improves signal transmission reliability, reduces costs, and ensures consistent adjustment.
[0006] In a first aspect, this disclosure provides a timing adjustment circuit for an integrated circuit bus, comprising: The first input terminal is connected to the serial clock line to receive the serial clock signal, and the second input terminal is connected to the serial data line to receive the serial data signal. A latch module is connected to the first input terminal and the second input terminal respectively. The latch module is configured to receive the serial clock signal and the serial data signal, and adjust the serial data signal according to the serial clock signal and the serial data signal so that the hold time is greater than or equal to 0. A control module is connected to the output of the latch module, and the control module is configured to receive the serial clock signal and the serial data signal processed by the latch module.
[0007] Secondly, based on the same inventive concept, this disclosure provides an electronic device including a timing adjustment circuit for an integrated circuit bus.
[0008] The technical solution provided in this disclosure has the following advantages compared with the prior art: This disclosure provides a timing adjustment circuit and electronic device for an integrated circuit bus. The timing adjustment circuit includes a first input terminal, a second input terminal, a latch module, and a control module. In this disclosure, the latch module monitors the serial clock signal and the serial data signal, and adjusts the timing of the serial data signal. By adjusting the timing of the serial data signal, the hold time is made greater than or equal to 0, and the transition of the data bit signal occurs during the low-level period of the serial clock signal. This helps prevent the data bit signal from being misinterpreted as a start or stop signal, thus ensuring the reliability and stability of data transmission. Furthermore, the timing adjustment circuit provided in this disclosure is physically connected to the device, enabling self-adjustment of timing, which helps reduce manual intervention and lower labor costs. Simultaneously, this disclosure adjusts timing based on hardware circuitry, which, compared to manual adjustment and timing constraints in related technologies, is more conducive to ensuring the consistency of timing adjustment. Attached Figure Description
[0009] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0011] Figure 1 The diagram shown is a schematic of a timing adjustment circuit for an integrated circuit bus provided in an embodiment of this disclosure; Figure 2 The diagram shown is a schematic of a latch module provided in an embodiment of this disclosure; Figure 3 The diagram shown is another schematic diagram of the latch module provided in an embodiment of this disclosure; Figure 4 The figure shown is a timing diagram of an integrated circuit bus timing adjustment circuit provided in an embodiment of this disclosure; Figure 5 The diagram shown is a schematic of a start / stop detection circuit provided in an embodiment of this disclosure; Figure 6 The diagram shown is another schematic diagram of the timing adjustment circuit of the integrated circuit bus provided in the embodiment of this disclosure; Figure 7 The diagram shown is yet another schematic of the timing adjustment circuit for an integrated circuit bus provided in an embodiment of this disclosure; Figure 8 The diagram shown is a schematic representation of an electronic device provided in an embodiment of this disclosure. Detailed Implementation
[0012] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0013] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.
[0014] The inventors discovered in their research that the I2C bus transmits signals according to the I2C protocol. The protocol relies on strict timing between the serial data signal and the serial clock signal to ensure communication reliability. The hold time is defined as the minimum time that the serial data signal must remain stable after the serial clock signal transitions. With the evolution of technology and the increase in bus speed, in high-speed or standard modes, the protocol even specifies that the minimum hold time of the data signal relative to the clock signal can be 0 nanoseconds.
[0015] The I2C bus supports communication between master and slave devices. In an I2C slave device design, its receive port receives signals and transmits them to the slave device's controller for processing. However, in the physical transmission path, the internal trace length and logic gate delay of the signals transmitted on the serial data line and serial clock line from the receive port to the controller are difficult to guarantee to be completely consistent. If the serial clock line path delay is greater than that of the serial data line, when the master device drives according to a 0 nanosecond hold time, the input signal hold-time violation received by the slave device's controller will cause the controller to misinterpret normal data bits as start or end signals, leading to communication abnormalities.
[0016] In related technologies, solving timing delay problems usually relies on manual adjustment and timing constraints. This approach increases design cycle and manpower costs, and makes it difficult to ensure consistency in each adjustment.
[0017] In view of this, the present disclosure provides a timing adjustment circuit and electronic device for an integrated circuit bus, which can improve the reliability of signal transmission, reduce costs, and ensure the consistency of adjustment.
[0018] Figure 1 The diagram shown is a schematic of a timing adjustment circuit for an integrated circuit bus provided in an embodiment of this disclosure. Please refer to it. Figure 1This disclosure provides a timing adjustment circuit 100 for an integrated circuit bus, comprising: a first input terminal 11 and a second input terminal 12, the first input terminal 11 being connected to a serial clock line for receiving a serial clock signal SCL, and the second input terminal 12 being connected to a serial data line for receiving a serial data signal SDA; a latch module 20, the latch module 20 being connected to the first input terminal 11 and the second input terminal 12 respectively, the latch module 20 being configured to at least receive the serial clock signal SCL and the serial data signal SDA, and to adjust the serial data signal SDA according to the serial clock signal SCL and the serial data signal SDA so that the hold time is greater than or equal to 0; and a control module 30 being configured to at least receive the serial clock signal SCL and the serial data signal SDA processed by the latch module 20.
[0019] It should be noted that the timing adjustment circuit 100 provided in this disclosure is installed in the slave device of the I2C transmission system. In the slave device, the serial clock signal SCL and the serial data signal SDA enter the slave device from the input terminal. During the process from when the control module 30 receives the serial clock signal SCL and the serial data signal SDA, there are other modules between the input terminal and the control module 30, and the transmission path delay is uncertain, making it difficult to ensure that the delays of the serial clock signal SCL and the serial data signal SDA are consistent. Therefore, this disclosure provides a timing adjustment circuit 100 to adjust the timing of the serial data signal SDA to improve the delay difference between the serial clock signal SCL and the serial data signal SDA.
[0020] It should also be noted that the accompanying drawings are for illustrative purposes only and do not represent the actual structure of the timing adjustment circuit 100. For example, the first input terminal 11 and the control module 30 may include, but are not limited to, the latch module 20. In some embodiments, other modules may also be included between the first input terminal 11 and the control module 30.
[0021] Specifically, this disclosure provides a timing adjustment circuit 100 for an integrated circuit bus. The timing adjustment circuit 100 includes a first input terminal 11, a second input terminal 12, a latch module 20, and a control module 30. The first input terminal 11 is connected to the serial clock line of the I2C bus and is used to receive the serial clock signal SCL from the master device. The second input terminal 12 is connected to the serial data line of the I2C bus and is used to receive the serial data signal SDA from the master device. The latch module 20 is the core processing unit of the timing adjustment circuit 100. It simultaneously monitors the serial clock signal SCL and the serial data signal SDA, adjusts the timing of the serial data signal SDA to improve the delay between them, and then transmits the processed serial clock signal SCL and serial data signal SDA to the control module 30.
[0022] It should be noted that the I2C protocol stipulates that when the serial clock signal SCL is high, a transition between high and low levels in the serial data signal SDA indicates that one end (master device) is sending a start or end signal of data bits to the other end (slave device) on the I2C bus. Between the start and end of a data bit transmission, the level change of the serial data signal SDA must occur during the low-level period of the serial clock signal SCL. The protocol relies on the strict timing of the serial clock signal SCL and the serial data signal SDA to ensure communication reliability. The protocol also defines a hold time, which is the minimum time that the serial data signal SDA must remain stable after a transition in the serial clock signal SCL. Taking a hold time of 0 nanoseconds as an example, the serial data signal SDA holds for 0 nanoseconds after the serial clock signal SCL transitions before transitioning. However, if the delay of the serial clock signal SCL is greater than that of the serial data signal SDA, and the master device still operates according to the 0 nanosecond hold time, the transition of the serial data signal SDA will occur after the transition of the serial clock signal SCL. This will result in timing violations corresponding to read or write operations in the signals obtained from the control module 30 in the device. In other words, the serial data signal SDA should have transitioned during the low-level period of the serial clock signal SCL after it transitions from high to low. However, because the serial data signal SDA transitions earlier than the serial clock signal SCL, the serial data signal SDA transitions during the high-level period of the serial clock signal SCL. At this time, the hold time becomes negative, causing the control module 30 to misinterpret the normal data bit signal as a start or end signal, thus leading to communication abnormalities.
[0023] Therefore, this disclosure includes a latch module 20 in the timing adjustment circuit 100 to monitor the serial clock signal SCL and the serial data signal SDA, and adjust the timing of the serial data signal SDA. When the monitoring detects that the serial data signal SDA corresponding to the data bit signal flips during the high-level period of the serial clock signal SCL, the signal is latched, and output only when the serial clock signal SCL jumps to a low level. This configuration, by adjusting the timing of the serial data signal SDA, ensures that the hold time is always non-negative, and that the data bit signal transition occurs during the low-level period of the serial clock signal SCL. This helps prevent the data bit signal from being misinterpreted as a start or stop signal, thus ensuring the reliability and stability of data transmission. Furthermore, the timing adjustment circuit 100 provided in this disclosure is physically connected to the device, enabling self-adjustment of timing, which helps reduce manual intervention and lower labor costs. Simultaneously, this disclosure adjusts timing based on hardware circuitry, which, compared to manual adjustment and timing constraints in related technologies, is more conducive to ensuring the consistency of timing adjustments.
[0024] Figure 2 The diagram shown is a schematic of a latch module provided in an embodiment of this disclosure. Please refer to it. Figure 1 and Figure 2 In one optional embodiment of this disclosure, the latch module 20 includes a latch 21, a logic operation circuit 22, and a selector 23. The latch 21 includes a data input terminal Din, an enable terminal EN, and a data output terminal Dout. The data input terminal Din receives a serial data signal SDA, and the enable terminal EN is connected to the selector 23. The latch 21 is configured to transmit the signal of the data input terminal Din to the data output terminal Dout when the signal of the enable terminal EN is at an enable level, and to maintain the output state of the data output terminal Dout at the previous moment when the signal of the enable terminal EN is at an enable level. The logic operation circuit 22 is connected to the data input terminal Din, the data output terminal Dout of the latch 21, and the enable input terminal of the selector 23, respectively. The logic operation circuit 22 also receives a serial clock signal SCL. The logic operation circuit 22 is configured to generate a first control signal Ctrl1 based on the signal of the data input terminal Din (serial data signal SDA), the signal of the data output terminal Dout (adjusted serial data signal SDA_LATCH), and the serial clock signal SCL. Selector 23 is configured to receive a first control signal Ctrl1 and other control signals, and to provide a signal to the enable terminal EN of latch 21 based on the first control signal Ctrl1 and other control signals.
[0025] Specifically, this embodiment provides a specific implementation of a latch module 20, wherein the latch 21 is a level-sensitive storage unit. Its data input terminal Din receives the serial data signal SDA, its enable terminal EN is controlled by the output of selector 23, and its data output terminal Dout provides the adjusted serial data signal SDA_LATCH. When the signal received by the enable terminal EN is at an enable level, the latch 21 is in transparent mode, and the data output terminal Dout follows the changes of the data input terminal Din in real time. When the signal received by the enable terminal EN is at a non-enable level, the latch 21 is in hold mode, and the data output terminal Dout retains the state of the previous moment, unaffected by input changes. By controlling the latch 21 to be in transparent mode or hold mode through selector 23, the serial data signal SDA_LATCH output by the data output terminal Dout can be controlled, thereby adjusting the serial data signal SDA and ensuring that the hold time is always a non-negative value.
[0026] The logic operation circuit 22 receives the serial data signal SDA from the data input terminal Din of the latch 21, the serial data signal SDA_LATCH from the data output terminal Dout, and the serial clock signal SCL. Based on the state of these signals, the logic operation circuit 22 generates a first control signal Ctrl1. The first control signal Ctrl1 provides at least a partial enable signal EN to the latch 21, thereby controlling the operating mode of the latch 21 according to the timing state. For example, when the first control signal Ctrl1 is at the enable level, the latch 21 is in a transparent state; when the first control signal Ctrl1 is at the disable level, the latch 21 is in a holding state.
[0027] Selector 23 receives the first control signal Ctrl1 generated by logic operation circuit 22, as well as other control signals. Figure 2 The middle arrow pointing to selector 23 indicates that the first control signal Ctrl1 and other control signals are input to selector 23. That is, in addition to the first control signal Ctrl1, other control signals are also included to control the working state of latch 21. With this setting, the working state of latch 21 can be controlled by multiple signals, which is beneficial to increasing the flexibility of control.
[0028] This embodiment uses a latch 21, a logic operation circuit 22, and a selector 23 to adjust the serial data signal SDA. The logic operation circuit 22 monitors the states of the serial clock signal SCL and the serial data signal SDA. When a transition is detected in the serial data signal SDA, but the serial clock signal SCL is high at this time, the first control signal Ctrl1 is set to a disabled level, and the latch 21 is in hold mode to prevent the serial data signal SDA from being output. After a transition to a low level is detected in the serial data signal SDA, the first control signal Ctrl1 is set to an enabled signal, the latch 21 is in transparent mode, and the transitioned serial data signal SDA_LATCH is output. This configuration ensures that the serial data signal SDA flips after the serial clock signal SCL transitions, keeping the hold time non-negative. The serial data signal SDA transitions during the low-level period of the serial clock signal SCL, thus preventing the transition from occurring during the high-level phase of the serial clock signal SCL and improving the reliability of signal transmission.
[0029] Figure 3 The diagram shown is another schematic diagram of the latch module provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 1 and Figure 3In one optional embodiment of this disclosure, the logic operation circuit 22 includes a first logic operation unit 221, a second logic operation unit 222, and a third logic operation unit 223. The first logic operation unit 221 is at least configured to receive the signal (serial data signal SDA) from the data input terminal Din of the latch 21 and the signal (serial data signal SDA_LATCH) from the data output terminal Dout, compare whether the signal from the data input terminal Din of the latch 21 and the signal from the data output terminal Dout are different, and output the operation result. The second logic operation unit 222 is at least configured to receive the serial clock signal SCL, perform a logical NOT operation on the serial clock signal SCL, and output the operation result. The third logic operation unit 223 is at least configured to receive the operation result from the first logic operation unit 221 and the operation result from the second logic operation unit 222, perform a logical AND operation on the operation result from the first logic operation unit 221 and the operation result from the second logic operation unit 222, and output the operation result.
[0030] Specifically, the logic operation circuit 22 is used to monitor the serial clock signal SCL and the serial data signal SDA. This disclosure provides a specific implementation of the logic operation circuit 22, wherein the first logic operation unit 221 is used to compare whether the signal at the data input terminal Din (serial data signal SDA) and the signal at the data output terminal Dout (serial data signal SDA_LATCH) are the same. Both the data input terminal Din and the data output terminal Dout transmit serial data signals. The serial data signal SDA represents the serial data signal before processing by the latch 21, and the serial data signal SDA_LATCH represents the serial data signal after processing by the latch 21. Therefore, the first logic operation unit 221 is essentially used to monitor whether the serial data signal SDA has changed. When the serial data signal SDA changes, the first logic operation unit 221 outputs "1"; when the serial data signal SDA does not change, the first logic operation unit 221 outputs "0". The second logic operation unit 222 is used to monitor whether the serial clock signal SCL is at a high level or a low level. When the serial clock signal SCL is high, the second logic operation unit 222 outputs "0"; when the serial clock signal SCL is low, the second logic operation unit 222 outputs "1". The third logic operation unit 223 performs operations based on the states of the first logic operation unit 221 and the second logic operation unit 222. That is, whether the serial data signal SDA changes direction and the high or low level of the serial clock signal SCL determines the output state of the third logic operation unit 223. When the serial data signal SDA changes direction and the serial clock signal SCL is low, the first logic operation unit 221 outputs "1", the second logic operation unit 222 outputs "1", and the third logic operation unit 223 outputs "1". In other words, at this time, the first control signal Ctrl1 is high, the enable terminal EN of the latch 21 receives an enable signal, the latch 21 is in transparent mode, and the serial data signal SDA is output in real time. When the serial data signal SDA transitions and the serial clock signal SCL is high, the first logic unit 221 outputs "1", the second logic unit 222 outputs "0", and the third logic unit 223 outputs "0". At this time, the first control signal Ctrl1 is low, the enable terminal EN of latch 21 receives a disabled signal, and latch 21 is in hold mode. The serial data signal SDA remains in its state before the transition. This setting helps avoid the serial data signal SDA transitioning when the serial clock signal SCL is high, but instead delays the output until the serial data signal SDA transitions to low. This adjusts the hold time from negative to positive, which helps prevent the data signal from being misinterpreted as a start or stop signal, thereby improving the reliability of signal transmission.
[0031] Optionally, the first logic operation unit 221 is an XOR gate, the second logic operation unit 222 is a NOT gate, and the third logic operation unit 223 is an AND gate.
[0032] Please continue to refer to this. Figure 1 and Figure 3 In one optional embodiment of this disclosure, the control signal includes a reset signal RESET, and the selector 23 is further configured to receive the reset signal RESET, providing a signal to the enable terminal EN of the latch 21 based on the first control signal Ctrl1 and the reset signal RESET. In this embodiment, the input terminal of the selector 23 receives not only the first control signal Ctrl1 but also the reset signal RESET. This facilitates controlling the operating state of the latch 21 through multiple signals. Furthermore, the latch module 20 can also reset the serial data signal SDA, increasing control flexibility.
[0033] In another optional embodiment of this disclosure, the control signals include a start signal START and a stop signal STOP. The selector 23 is also configured to receive the start signal START and the stop signal STOP, and to provide a signal to the enable terminal EN of the latch 21 based on the first control signal Ctrl1, the start signal START, and the stop signal STOP. In this embodiment, the input terminal of the selector 23 receives not only the first control signal Ctrl1, but also the start signal START and the stop signal STOP. This facilitates controlling the operating state of the latch 21 through multiple signals. Furthermore, the latch module 20 enables the smooth transmission of the start signal START and the stop signal STOP, further increasing control flexibility.
[0034] It should be noted that in some embodiments, selector 23 receives the first control signal Ctrl1 and the reset signal RESET; in other embodiments, selector 23 receives the first control signal Ctrl1, the start signal START, and the stop signal STOP; in still other embodiments, the input terminal of selector 23 can simultaneously receive the first control signal Ctrl1, the reset signal RESET, the start signal START, and the stop signal STOP. In this way, signal transmission at different stages can be achieved, which is more conducive to stable signal transmission and improves the reliability of signal transmission.
[0035] Figure 4 The diagram shown is a timing schematic of an integrated circuit bus timing adjustment circuit provided in an embodiment of this disclosure. Please refer to it. Figure 1 , Figure 3 and Figure 4 , Figure 1 and Figure 3 The structure of the timing adjustment circuit 100 and the latch module 20 is shown. Figure 4The diagram illustrates a timing sequence of a timing adjustment circuit 100, showing its operation based on four latch enable conditions. The selector 23 includes four enable signal inputs: a first enable input EN1, a second enable input EN2, a third enable input EN3, and a fourth enable input EN4. The first enable input EN1 receives a reset signal RESET, the second enable input EN2 receives a start signal START, the third enable input EN3 receives a first control signal Ctrl1, and the fourth enable input EN4 receives a stop signal STOP.
[0036] The workflow corresponding to the sequence diagram is as follows: Period ①: The system performs initialization and reset. When the reset signal RESET is valid, the first enable input terminal EN1 of selector 23 provides an enable signal to latch 21. The serial data signal SDA_LATCH output by data output terminal Dout has the same state as the serial data signal SDA received by data input terminal Din, both of which are in a high-level state.
[0037] Period ②: After the reset is completed, the master device sends a start signal START. When the start signal START is detected, an enable level of one system clock cycle is generated and transmitted to the second enable input terminal EN2 of selector 23 to provide an enable signal for latch 21. The serial data signal SDA_LATCH output by the data output terminal Dout is latched to a low level.
[0038] Period ③: Serial data signal SDA transition (master device transmits data). Taking the serial data signal SDA transitioning from low to high as an example, after the serial data signal SDA at the data input terminal Din and the serial data signal SDA_LATCH at the data output terminal Dout are XORed, the first logic operation unit 221 outputs "1". At this time, the serial clock signal SCL is low, the second logic operation unit 222 outputs "1", the third logic operation unit 223 also outputs "1", the first control signal Ctrl1 is high, the third enable input terminal EN3 provides the enable level for the latch 21, and the serial data signal SDA_LATCH output from the data output terminal Dout follows the serial data signal SDA input from the data input terminal Din, that is, it follows the transition.
[0039] Time Period ④: Serial data signal SDA transition (master device transmits data). Taking the serial data signal SDA transitioning from high to low as an example, after the serial data signal SDA at the data input terminal Din and the serial data signal SDA_LATCH at the data output terminal Dout are XORed, the first logic operation unit 221 outputs "1". At this time, the serial clock signal SCL is high, the second logic operation unit 222 outputs "0", the third logic operation unit 223 also outputs "0", the first control signal Ctrl1 is low, the third enable input terminal EN3 provides a disabled level to the latch 21, and the data output terminal Dout maintains the state of the previous moment until the serial clock signal SCL transitions to low. Then, the first control signal Ctrl1 becomes high, the third enable input terminal EN3 provides an enable level to the latch 21, and the data output terminal Dout outputs the transitioned serial data signal SDA.
[0040] Period ⑤: The master device starts sending the stop signal STOP. When the stop signal STOP is detected, an enable level of one system clock cycle is generated and transmitted to the fourth enable input terminal EN4 of selector 23 to provide an enable signal for latch 21. The serial data signal SDA_LATCH output by the data output terminal Dout is latched to a high level.
[0041] The above embodiments complete a full I2C communication process, which includes timing calibration. It can be seen that this disclosure can achieve a non-negative hold time for I2C bus data, thus improving the reliability of data transmission.
[0042] It should be noted that, Figure 4 The document also mentions the system clock signal SYS_CLK, which is the clock signal relied upon in the I2C bus communication system and is the core reference for coordinating synchronous communication between master and slave devices.
[0043] Optionally, the timing adjustment circuit 100 further includes a start / stop detection circuit, which is configured to detect and output a start signal START and a stop signal STOP based on the serial data signal SDA and the serial clock signal SCL. Specifically, embodiments of this disclosure also provide a detection circuit for the start signal START and the stop signal STOP, which determines the start signal START and the stop signal STOP by monitoring the states of the serial clock signal SCL and the serial data signal SDA.
[0044] Figure 5 The diagram shown is a schematic of a start / stop detection circuit provided in an embodiment of this disclosure. Please refer to it. Figure 5Furthermore, in an optional embodiment of this disclosure, the start / stop detection circuit includes a shift register module 61 and a comparison module 62; the shift register module 61 is at least configured to receive and store the states of the serial data signal SDA and the serial clock signal SCL over a period of time; the comparison module 62 is connected to the output terminal of the shift register module 61, and the comparison module 62 is at least configured to receive the states of the serial data signal SDA and the serial clock signal SCL stored by the shift register module 61, compare them with the target state, and output a start signal START or a stop signal STOP when a preset condition is met.
[0045] Specifically, Figure 5 A specific implementation of a start / stop detection circuit is provided, wherein the shift register module 61 includes two 3-bit shift registers, namely shift register scl_shifter[2:0] and shift register sda_shifter[2:0]. The input of shift register scl_shifter[2:0] is the serial clock signal SCL, used to receive and monitor the state of the serial clock signal SCL. The input of shift register sda_shifter[2:0] is the serial data signal SDA, used to receive and detect the state of the serial data signal SDA. Through the shift register module 61, the bus state is sampled and monitored for three consecutive cycles in the system clock domain. When the serial clock signal SCL is detected to be high for three consecutive cycles and the serial data signal SDA shows a high-to-low transition and remains low for at least two cycles, it is determined to be a valid start signal START, and the output terminal of the start signal START is set high. The logical expression corresponding to setting the START output terminal high in the comparison module 62 is: START = (scl_shifter[2:0] == 3'b111)&(sda_shifter[2:0] == 3'b001). This setting helps to avoid misjudging the case where the falling edge of the serial data signal SDA precedes the falling edge of the serial clock signal SCL by one clock cycle as the start signal START.
[0046] For the stop signal STOP, the shift register module 61 samples and monitors the bus state for three consecutive clock cycles in the system clock domain. When the serial clock signal SCL is detected to be continuously high for three cycles, and the serial data signal SDA transitions from low to high and maintains a high level for two cycles, it is identified as a valid stop signal STOP, and the output of the stop signal STOP is set high. The logical expression corresponding to setting the output of the stop signal STOP in the comparison module 62 to high is: stop_det = (scl_shifter[2:0] == 3'b111)&(sda_shifter[2:0] == 3'b110). This setting helps to avoid misjudging the case where the rising edge of the serial data signal SDA precedes the falling edge of the serial clock signal SCL by one cycle as the stop signal STOP.
[0047] It should be noted that the system clock domain refers to the set of clock signal sources, frequency ranges, and timing rules that the entire I2C bus communication system relies on. It is the core benchmark for coordinating synchronous communication between master and slave devices.
[0048] Figure 6 The diagram shown is another schematic diagram of the timing adjustment circuit of the integrated circuit bus provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 6 In one optional embodiment of this disclosure, the timing adjustment circuit 100 further includes a transmission module 40, which is connected to the first input terminal 11 and the second input terminal 12 respectively. The transmission module 40 is configured to transmit at least a serial clock signal SCL and a serial data signal SDA.
[0049] It should be noted that after the serial clock signal SCL and the serial data signal SDA enter the device through the first input terminal 11 and the second input terminal 12, they need to be transmitted to multiple modules in the device. Therefore, the timing adjustment circuit 100 also includes a transmission module 40 for multiplexing the serial clock signal SCL and the serial data signal SDA. In some embodiments, the transmission module 40 achieves multiplexing through a selection circuit. The selection circuit can refer to the selection circuits in related technologies, as long as it can achieve signal multiplexing. This disclosure does not make specific limitations.
[0050] Signal glitches may occur when passing through transmission module 40, which may be misinterpreted as signal transitions, leading to timing violations. To address this issue, this disclosure provides an optional implementation method. Figure 7 The diagram shown is yet another schematic of the timing adjustment circuit for the integrated circuit bus provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 7The timing adjustment circuit 100 also includes a synchronization module 50, which is connected between the transmission module 40 and the latch module 20. The synchronization module 50 is configured to synchronize the serial data signal SDA and the serial clock signal SCL to the system clock domain. Specifically, in this embodiment, a synchronization module 50 is provided between the input terminal and the latch module 20. Optionally, the synchronization module 50 includes two two-stage synchronous flip-flops, which are used to filter out glitches in the serial clock signal SCL and the serial data signal SDA, respectively, to achieve the filtering function. This configuration helps to prevent the latch module 20 from misinterpreting glitches in the signal as signal transitions, further improving the reliability of signal transmission.
[0051] Based on the same inventive concept, this disclosure provides an electronic device. Figure 8 The diagram shown is a schematic representation of an electronic device provided in an embodiment of this disclosure. Please refer to it. Figure 8 The electronic device 200 includes a timing adjustment circuit 100 for an integrated circuit bus, which is an embodiment of any timing adjustment circuit 100 provided in the present disclosure.
[0052] It should be noted that the embodiments of the electronic device 200 provided in this disclosure can refer to any embodiment of the timing adjustment circuit 100 provided in this disclosure, and the repeated parts will not be described again.
[0053] As can be seen from the above embodiments, the timing adjustment circuit and electronic device of the integrated circuit bus provided in this disclosure achieve at least the following beneficial effects: This disclosure provides a timing adjustment circuit and electronic device for an integrated circuit bus. The timing adjustment circuit includes a first input terminal, a second input terminal, a latch module, and a control module. In this disclosure, the latch module monitors the serial clock signal and the serial data signal, and adjusts the timing of the serial data signal. By adjusting the timing of the serial data signal, the hold time is made greater than or equal to 0, and the transition of the data bit signal occurs during the low-level period of the serial clock signal. This helps prevent the data bit signal from being misinterpreted as a start or stop signal, thus ensuring the reliability and stability of data transmission. Furthermore, the timing adjustment circuit provided in this disclosure is physically connected to the device, enabling self-adjustment of timing, which helps reduce manual intervention and lower labor costs. Simultaneously, this disclosure adjusts timing based on hardware circuitry, which, compared to manual adjustment and timing constraints in related technologies, is more conducive to ensuring the consistency of timing adjustment.
[0054] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0055] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A timing adjustment circuit for an integrated circuit bus, characterized in that, include: The first input terminal is connected to the serial clock line to receive the serial clock signal, and the second input terminal is connected to the serial data line to receive the serial data signal. A latch module is connected to the first input terminal and the second input terminal respectively. The latch module is configured to receive the serial clock signal and the serial data signal, and adjust the serial data signal according to the serial clock signal and the serial data signal so that the hold time is greater than or equal to 0. A control module is connected to the output of the latch module, and the control module is configured to receive the serial clock signal and the serial data signal processed by the latch module.
2. The timing adjustment circuit for the integrated circuit bus according to claim 1, characterized in that, The latch module includes a latch, a logic operation circuit, and a selector; The latch includes a data input terminal, an enable terminal, and a data output terminal. The data input terminal receives the serial data signal, and the enable terminal is connected to the selector. The latch is configured to transmit the signal of the data input terminal to the data output terminal when the signal of the enable terminal is at an enable level, and to maintain the output state of the previous moment when the signal of the enable terminal is at an enable level. The logic operation circuit is connected to the data input terminal, the data output terminal of the latch, and the enable input terminal of the selector, respectively. The logic operation circuit also receives the serial clock signal. The logic operation circuit is configured to generate a first control signal based on the signal at the data input terminal, the signal at the data output terminal, and the serial clock signal. The selector is configured to receive the first control signal and other control signals, and to provide a signal to the enable terminal of the latch based on the first control signal and the other control signals.
3. The timing adjustment circuit for the integrated circuit bus according to claim 2, characterized in that, The logic operation circuit includes a first logic operation unit, a second logic operation unit, and a third logic operation unit; The first logic operation unit is configured to receive the signal at the data input terminal and the signal at the data output terminal of the latch, compare whether the signal at the data input terminal and the signal at the data output terminal of the latch are different, and output the operation result; The second logic operation unit is configured to at least receive the serial clock signal, perform a logical NOT operation on the serial clock signal, and output the operation result; The third logic operation unit is configured to receive the operation result of the first logic operation unit and the operation result of the second logic operation unit, perform a logical AND operation on the operation result of the first logic operation unit and the operation result of the second logic operation unit, and output the operation result.
4. The timing adjustment circuit for the integrated circuit bus according to claim 2, characterized in that, The control signal includes a reset signal, and the selector is further configured to receive the reset signal and provide a signal to the enable terminal of the latch based on the first control signal and the reset signal.
5. The timing adjustment circuit for the integrated circuit bus according to claim 2, characterized in that, The control signal includes a start signal and a stop signal, and the selector is further configured to receive the start signal and the stop signal, and to provide a signal to the enable terminal of the latch based on the first control signal, the start signal and the stop signal.
6. The timing adjustment circuit for the integrated circuit bus according to claim 5, characterized in that, It also includes a start / stop detection circuit, which is configured to detect and output the start signal and the stop signal based on the serial data signal and the serial clock signal.
7. The timing adjustment circuit for the integrated circuit bus according to claim 6, characterized in that, The start / stop detection circuit includes a shift register module and a comparison module; The shift register module is at least configured to receive and store the state of the serial data signal and the serial clock signal over a period of time; The comparison module is connected to the output of the shift register module. The comparison module is configured to receive the state of the serial data signal and the serial clock signal stored in the shift register module, compare them with the target state, and output the start signal or the stop signal when the preset conditions are met.
8. The timing adjustment circuit for the integrated circuit bus according to claim 1, characterized in that, Also includes: A transmission module is connected to the first input terminal and the second input terminal respectively, and the transmission module is configured to transmit at least the serial clock signal and the serial data signal.
9. The timing adjustment circuit for the integrated circuit bus according to claim 8, characterized in that, Also includes: A synchronization module is connected between the transmission module and the latch module, and the synchronization module is configured to at least synchronize the serial data signal and the serial clock signal to the system clock domain.
10. An electronic device, characterized in that, The timing adjustment circuit of the integrated circuit bus included in any one of claims 1 to 9.