Signal transmission device

Abstract

To reduce current consumption of a signal transmission device.SOLUTION: A signal transmission device 400 includes: a first pulse transmission circuit 411 configured to generate a first transmission pulse signal S42 in synchronization with only one of a rising edge and a falling edge of a first reference clock signal S41; a first pulse reception circuit 421 configured to receive a first reception pulse signal S43 and generate a second reference clock signal S44; a first insulating communication circuit 431 configured to transmit the first transmission pulse signal S42 as a first reception pulse signal S43 while insulating the first pulse transmission circuit 411 and the first pulse reception circuit 421 from each other; and a drive clock signal generation circuit 424 configured to generate a drive clock signal S44 having a predetermined oscillation frequency and a predetermined duty or a predetermined pulse width in synchronization with the second reference clock signal S45.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The present disclosure relates to a signal transmission device.

Background Art

[0002] Conventionally, signal transmission devices that transmit pulse signals while insulating between input and output have been used in various applications (such as power supply devices or motor drive devices).

[0003] As an example of the related prior art, Patent Document 1 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, there has been room for improvement in reducing the current consumption of conventional signal transmission devices.

Means for Solving the Problems

[0006] For example, the signal transmission device disclosed in this specification includes a first pulse transmission circuit configured to generate a first transmission pulse signal in synchronization with a rising edge or a falling edge of a first reference clock signal, a first pulse reception circuit configured to receive a first reception pulse signal and generate a second reference clock signal, a first insulation communication circuit configured to transmit the first transmission pulse signal as the first reception pulse signal while insulating between the first pulse transmission circuit and the first pulse reception circuit, and a drive clock signal generation circuit configured to generate a drive clock signal having a predetermined oscillation frequency, a predetermined duty, or a predetermined pulse width in synchronization with the second reference clock signal.

[0007] Further details regarding other features, elements, steps, advantages, and characteristics will become clearer from the embodiments for carrying out the invention and the accompanying drawings. [Effects of the Invention]

[0008] This disclosure makes it possible to provide a signal transmission device with low current consumption. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows the basic configuration of a signal transmission device. [Figure 2] Figure 2 shows the basic structure of a transformer chip. [Figure 3] Figure 3 is a perspective view of a semiconductor device used as a 2-channel transformer chip. [Figure 4] Figure 4 is a plan view of the semiconductor device shown in Figure 3. [Figure 5] Figure 5 is a plan view showing the layer in the semiconductor device of Figure 3 where the low-potential coil is formed. [Figure 6] Figure 6 is a plan view showing the layer in the semiconductor device of Figure 3 where the high-potential coil is formed. [Figure 7] Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. [Figure 8] Figure 8 shows an enlarged view (separated structure) of region XIII shown in Figure 7. [Figure 9] Figure 9 is a schematic diagram showing an example of a transformer chip layout. [Figure 10] Figure 10 shows a first embodiment of the signal transmission device. [Figure 11] Figure 11 shows the signal transmission operation of the first embodiment. [Figure 12] Figure 12 shows a second embodiment of the signal transmission device. [Figure 13] Figure 13 shows the signal transmission operation of the second embodiment. [Figure 14] Figure 14 is a diagram showing a third embodiment of the signal transmission device. [Figure 15] Figure 15 is a diagram showing a fourth embodiment of the signal transmission device. [Figure 16] Figure 16 is a diagram showing the signal transmission operation of the fourth embodiment. [Figure 17] Figure 17 is a diagram showing a fifth embodiment of the signal transmission device. [Figure 18] Figure 18 is a diagram showing the signal transmission operation of the fifth embodiment.

Embodiments for Carrying Out the Invention

[0010] <Signal Transmission Device (Basic Configuration)> Figure 1 is a diagram showing the basic configuration of the signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p (VCC1 - GND1 system) to the secondary circuit system 200s (VCC2 - GND2 system) while insulating between them, and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by encapsulating a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0011] The controller chip 210 is a semiconductor chip that operates by receiving a supply of the power supply voltage VCC1 (for example, up to 7V with respect to GND1). In the controller chip 210, for example, a pulse transmission circuit 211, buffers 212 and 213 are integrated.

[0012] The pulse transmission circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 according to the input pulse signal IN. More specifically, when notifying that the input pulse signal IN is at a high level, the pulse transmission circuit 211 performs pulse driving (single-shot or multiple-shot transmission pulse output) of the transmission pulse signal S11, and when notifying that the input pulse signal IN is at a low level, it performs pulse driving of the transmission pulse signal S21. That is, the pulse transmission circuit 211 pulse-drives either one of the transmission pulse signals S11 and S21 according to the logic level of the input pulse signal IN.

[0013] The buffer 212 receives the input of the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transchip 230 (specifically, the transformer 231).

[0014] The buffer 213 receives the input of the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transchip 230 (specifically, the transformer 232).

[0015] The driver chip 220 is a semiconductor chip that operates receiving the supply of a power supply voltage VCC2 (for example, up to 30V with respect to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse reception circuit 223, and a driver 224.

[0016] The buffer 221 waveform-shapes the received pulse signal S12 induced in the transchip 230 (specifically, the transformer 231) and outputs it to the pulse reception circuit 223.

[0017] The buffer 222 waveform-shapes the received pulse signal S22 induced in the transchip 230 (specifically, the transformer 232) and outputs it to the pulse reception circuit 223.

[0018] The pulse receiving circuit 223 generates an output pulse signal OUT by driving a driver 224 in response to received pulse signals S12 and S22 input via buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 to raise the output pulse signal OUT to a high level in response to the pulse drive of the received pulse signal S12, and to lower the output pulse signal OUT to a low level in response to the pulse drive of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. For example, an RS flip-flop can be suitably used as the pulse receiving circuit 223.

[0019] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223.

[0020] The transformer chip 230 uses transformers 231 and 232 to DC-isolate the controller chip 210 and the driver chip 220, and outputs the transmitted pulse signals S11 and S21 input from the pulse transmitting circuit 211 as received pulse signals S12 and S22, respectively, to the pulse receiving circuit 223. In this specification, "DC-isolated" means that the objects to be isolated are not connected by a conductor.

[0021] More specifically, transformer 231 outputs a received pulse signal S12 from its secondary coil 231s in response to a transmitted pulse signal S11 input to its primary coil 231p. On the other hand, transformer 232 outputs a received pulse signal S22 from its secondary coil 232s in response to a transmitted pulse signal S21 input to its primary coil 232p.

[0022] Thus, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0023] In this example, the signal transmission device 200 has a separate transformer chip 230 containing only transformers 231 and 232, in addition to the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0024] With this configuration, both the controller chip 210 and the driver chip 220 can be formed using a general low-to-medium voltage process (several volts to tens of volts), eliminating the need to use a dedicated high-voltage process (several kV voltage), and thus reducing manufacturing costs.

[0025] The signal transmission device 200 can be suitably used, for example, in a power supply unit or motor drive unit for in-vehicle equipment mounted on a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (xEVs such as BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV (plug-in hybrid electric vehicle / plug-in hybrid vehicle], or FCEV / FCV (fuel cell electric vehicle / fuel cell vehicle)).

[0026] <Trans-chip (basic structure)> Next, the basic structure of the transformer chip 230 will be described. Figure 2 shows the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that are opposed to each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that are opposed to each other in the vertical direction.

[0027] The primary coils 231p and 232p are both formed in the first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed in the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is positioned directly above the primary coil 231p and faces it. Similarly, the secondary coil 232s is positioned directly above the primary coil 232p and faces it.

[0028] The primary coil 231p is laid in a spiral pattern, starting from its first end connected to internal terminal X21 and surrounding internal terminal X21 in a clockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral pattern, starting from its first end connected to internal terminal X23 and surrounding internal terminal X23 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. Internal terminals X21, X22, and X23 are arranged linearly in the order shown in the figure.

[0029] Internal terminal X21 is connected to external terminal T21 of the second layer 230b via conductive wiring Y21 and via Z21. Internal terminal X22 is connected to external terminal T22 of the second layer 230b via conductive wiring Y22 and via Z22. Internal terminal X23 is connected to external terminal T23 of the second layer 230b via conductive wiring Y23 and via Z23. External terminals T21 to T23 are arranged in a straight line and are used for wire bonding to the controller chip 210.

[0030] The secondary coil 231s is laid in a spiral pattern, starting from its first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. On the other hand, the secondary coil 232s is laid in a spiral pattern, starting from its first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure and are used for wire bonding with the driver tip 220.

[0031] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, respectively, and are DC-isolated from the primary coils 231p and 232p. In other words, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-isolated from the controller chip 210 by the transformer chip 230.

[0032] <Trans-chip (2-channel type)> Figure 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. Figure 4 is a plan view of the semiconductor device 5 shown in Figure 3. Figure 5 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed. Figure 6 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed. Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 8 is an enlarged view of region XIII shown in Figure 7, showing the separation structure 130.

[0033] Referring to Figures 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0034] Wide-bandgap semiconductors consist of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide-bandgap semiconductor is preferably 2.0 eV or greater. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0035] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a laminated structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0036] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a rectangular shape (in this form, a rectangular shape) when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").

[0037] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long side of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and face a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short side of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in a second direction Y and face a first direction X. The chip sidewalls 44A to 44D consist of a ground surface.

[0038] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that aligns with the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0039] The insulating sidewalls 53A to 53D include the first insulating sidewall 53A, the second insulating sidewall 53B, the third insulating sidewall 53C, and the fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form a ground surface that is flush with the chip sidewalls 44A to 44D.

[0040] The insulating layer 51 consists of a multilayer insulating laminate structure including a bottom insulating layer 55, an upper insulating layer 56, and a plurality (11 layers in this embodiment) of interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the upper insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the upper insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0041] Each of the multiple interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the bottom insulating layer 55 side and a second insulating layer 59 on the top insulating layer 56 side. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0042] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0043] The total thickness DT of the insulating layer 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the dielectric strength (dielectric breakdown voltage) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layer 57 are arbitrary and are not limited to any specific insulating material.

[0044] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, more) transformers 21 (corresponding to the transformers mentioned earlier). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51, spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed spaced apart in the first direction X.

[0045] The multiple transformers 21 specifically include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating sidewall 53C to the insulating sidewall 53D in a plan view. The multiple transformers 21A to 21D each have a similar structure. The structure of the first transformer 21A will be used as an example below. The explanation of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D will be omitted, as the explanation of the structure of the first transformer 21A will be applied mutatis mutandis.

[0046] Referring to Figures 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within the insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in the region sandwiched between the bottom insulating layer 55 and the top insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0047] The low-potential coil 22 is formed within the insulating layer 51 on the side of the bottom insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 on the side of the top insulating layer 56 (main insulating surface 52) relative to the low-potential coil 22. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 in between. The placement of the low-potential coil 22 and the high-potential coil 23 is arbitrary. Furthermore, the high-potential coil 23 only needs to face the low-potential coil 22 with one or more interlayer insulating layers 57 in between.

[0048] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulating layer 57) is appropriately adjusted according to the dielectric breakdown voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this configuration, the low-potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55. In this configuration, the high-potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56.

[0049] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 that is spirally routed between the first inner end 24 and the first outer end 25. The first helical portion 26 is spirally routed in an elliptical (long oval) shape in plan view. The portion forming the innermost periphery of the first helical portion 26 defines an elliptical first inner region 66 in plan view.

[0050] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first helical portion 26 is 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction perpendicular to the helical direction. The first turn pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the first turn pitch is 1 μm or more and 3 μm or less. The first turn pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction perpendicular to the helical direction.

[0051] The winding shape of the first helical portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the forms shown in Figure 5, etc. The first helical portion 26 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The first inner region 66 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the first helical portion 26.

[0052] The low-potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a laminated structure including a barrier layer and a main body layer. The barrier layer partitions a recess space within the interlayer insulating layer 57. The barrier layer may contain at least one of titanium and titanium nitride. The main body layer may contain at least one of copper, aluminum, and tungsten.

[0053] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second helical portion 29 that is spirally routed between the second inner end 27 and the second outer end 28. The second helical portion 29 is spirally routed in an elliptical (oval) shape in plan view. In this embodiment, the portion forming the innermost periphery of the second helical portion 29 defines an elliptical second inner region 67 in plan view. The second inner region 67 of the second helical portion 29 faces the first inner region 66 of the first helical portion 26 in the normal direction Z.

[0054] The number of turns of the second helical section 29 may be between 5 and 30. The number of turns of the second helical section 29 relative to the number of turns of the first helical section 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical section 29 exceeds the number of turns of the first helical section 26. Of course, the number of turns of the second helical section 29 may be less than the number of turns of the first helical section 26, or it may be equal to the number of turns of the first helical section 26.

[0055] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction perpendicular to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0056] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions in the second helical portion 29 in a direction perpendicular to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0057] The winding shape of the second helical portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the forms shown in Figure 6, etc. The second helical portion 29 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The second inner region 67 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the second helical portion 29.

[0058] It is preferable that the high-potential coil 23 is formed from the same conductive material as the low-potential coil 22. In other words, it is preferable that the high-potential coil 23 includes a barrier layer and a main body layer, similar to the low-potential coil 22.

[0059] Referring to Figure 4, the semiconductor device 5 includes a plurality (12 in this figure) of low-potential terminals 11 and a plurality (12 in this figure) of high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0060] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed in the region on the insulating side wall 53B side, spaced apart in the second direction Y from the multiple transformers 21A to 21D, and are arranged with spacing in the first direction X.

[0061] The multiple low-potential terminals 11 include a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this configuration, two of each of the multiple low-potential terminals 11A to 11F are formed. The number of multiple low-potential terminals 11A to 11F is arbitrary.

[0062] The first low-potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low-potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low-potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low-potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low-potential terminal 11E is formed in the region between the first low-potential terminal 11A and the second low-potential terminal 11B in a plan view. The sixth low-potential terminal 11F is formed in the region between the third low-potential terminal 11C and the fourth low-potential terminal 11D in a plan view.

[0063] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0064] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0065] Multiple high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51, spaced apart from multiple low-potential terminals 11. Specifically, the multiple high-potential terminals 12 are formed in the region on the insulating side wall 53A side, spaced apart in the second direction Y from the multiple low-potential terminals 11, and are arranged with spacing in the first direction X.

[0066] Multiple high-potential terminals 12 are each formed in a region adjacent to the corresponding transformers 21A to 21D in a plan view. The proximity of the high-potential terminals 12 to the transformers 21A to 21D means that, in a plan view, the distance between the high-potential terminals 12 and the transformer 21 is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0067] Specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D in a plan view. More specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high-potential coil 23 and in the region between adjacent high-potential coils 23 in a plan view. As a result, the multiple high-potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0068] The multiple high-potential terminals 12 include a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this configuration, two of each of the multiple high-potential terminals 12A to 12F are formed. The number of multiple high-potential terminals 12A to 12F is arbitrary.

[0069] The first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23) in a plan view. The second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23) in a plan view. The third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23) in a plan view. The fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23) in a plan view. The fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0070] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0071] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0072] Referring to Figures 5 to 7, the semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, each formed within the insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0073] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this configuration, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0074] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this configuration, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0075] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. Multiple first low-potential wirings 31 have similar structures. Below, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. For descriptions of the structures of other first low-potential wirings 31, the description of the structure of the first low-potential wiring 31 connected to the first transformer 21A will be applied mutatis mutandis, and the description will be omitted.

[0076] The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0077] It is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, it is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The through-wiring 71 penetrates multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this configuration, the through-wiring 71 is formed in the region between the lowest insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through-wiring 71 has an upper end on the side of the uppermost insulating layer 56 and a lower end on the side of the lowest insulating layer 55. The upper end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0079] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0080] The first electrode layer 78 forms the upper end of the through-wiring 71. The second electrode layer 79 forms the lower end of the through-wiring 71. The first electrode layer 78 is formed in an island shape and faces the low-potential terminal 11 (first low-potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0081] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the bottom insulating layer 55 to the top insulating layer 56 so as to be electrically connected to each other, and also electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0082] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this configuration, six wiring plug electrodes 80 are embedded within each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded within each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating multiple interlayer insulating layers 57.

[0083] The low-potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) within the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connection wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. It is preferable that the low-potential connection wiring 72 has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0084] The lead wire 73 is formed in the region between the semiconductor chip 41 and the through-wiring 71 within the interlayer insulating layer 57. In this embodiment, the lead wire 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead wire 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first and second ends. The first end of the lead wire 73 is located in the region between the semiconductor chip 41 and the lower end of the through-wiring 71. The second end of the lead wire 73 is located in the region between the semiconductor chip 41 and the low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip-like manner in the region between the first and second ends.

[0085] The first connecting plug electrode 74 is formed in the region between the through-wiring 71 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the first ends of the through-wiring 71 and the lead-out wiring 73. The second connecting plug electrode 75 is formed in the region between the low-potential connecting wiring 72 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second ends of the low-potential connecting wiring 72 and the lead-out wiring 73.

[0086] Multiple pad plug electrodes 76 are formed in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through-wiring 71 within the uppermost insulating layer 56, and are electrically connected to the upper ends of the low-potential terminal 11 and the through-wiring 71, respectively. Multiple substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the lead-out wiring 73 within the lowermost insulating layer 55. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first end of the lead-out wiring 73, and are electrically connected to the first end of the semiconductor chip 41 and the lead-out wiring 73, respectively.

[0087] Referring to Figures 6 and 7, the multiple first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23), respectively. The multiple first high-potential wirings 33 each have a similar structure. Below, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. For descriptions of the structures of the other first high-potential wirings 33, the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A will be applied mutatis mutandis, and the descriptions will be omitted.

[0088] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, more) pad plug electrodes 82. Preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 are formed of the same conductive material as the low-potential coil 22, etc. That is, preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0089] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulation layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at an interval from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. Thereby, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the breakdown voltage of the insulation layer 51 is enhanced.

[0090] The plurality of pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (the first high-potential terminal 12A) and the high-potential connection wiring 81 within the uppermost insulation layer 56 and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. The plurality of pad plug electrodes 82 each have a planar area less than the planar area of the high-potential connection wiring 81 in a plan view.

[0091] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulation layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. It is preferable that the distance D1 is 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0092] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulation layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0093] The dummy pattern 85 is formed with a different pattern (discontinuous pattern) from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A-21D. In other words, the dummy pattern 85 does not function as a transformer 21A-21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A-21D and suppresses electric field concentration on the high-potential coil 23. In this configuration, the dummy pattern 85 is routed with a line density equal to that of the high-potential coil 23 per unit area. The line density of the dummy pattern 85 being equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 is within ±20% of the line density of the high-potential coil 23.

[0094] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the dummy pattern 85 is formed in a region adjacent to the high-potential coil 23 with respect to the low-potential coil 22 with respect to the normal direction Z. Note that when we say that the dummy pattern 85 is adjacent to the high-potential coil 23 with respect to the normal direction Z, it means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential coil 22 with respect to the normal direction Z.

[0095] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 with respect to the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the dummy pattern 85 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively. The dummy pattern 85 includes a plurality of dummy patterns with different electrical states. The dummy pattern 85 may also include a high-potential dummy pattern.

[0096] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the high-potential dummy pattern 86 is formed in a region adjacent to the high-potential coil 23 with respect to the normal direction Z relative to the low-potential coil 22. The high-potential dummy pattern 86 being adjacent to the high-potential coil 23 with respect to the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22 with respect to the normal direction Z.

[0097] The dummy pattern 85 includes a floating dummy pattern formed electrically in a floating state within the insulating layer 51 so as to be located around the transformers 21A to 21D.

[0098] In this embodiment, the floating dummy pattern is routed in a dense linear fashion so as to partially cover and partially expose the area surrounding the high-potential coil 23 in a plan view. The floating dummy pattern may be formed with ends or without ends.

[0099] The depth position of the floating dummy pattern within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated.

[0100] The number of floating lines is arbitrary and is adjusted according to the electric field to be mitigated. A floating dummy pattern may consist of multiple floating lines.

[0101] Referring to Figure 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using the surface layer of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (bottom insulating layer 55). In Figure 7, the second functional device 60 is simplified by dashed lines shown on the surface layer of the first main surface 42.

[0102] The second functional device 60 is electrically connected to the low-potential terminal 11 via low-potential wiring and to the high-potential terminal 12 via high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 to connect to the second functional device 60. A detailed explanation of the low-potential and high-potential wiring related to the second functional device 60 is omitted.

[0103] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more devices from among the passive device, semiconductor rectifier device, and semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0104] Passive devices may include semiconductor passive devices. Passive devices may include either a resistor or a capacitor, or both. Semiconductor rectifier devices may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. Semiconductor switching devices may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0105] Referring to Figures 5 to 7, the semiconductor device 5 further includes a sealing conductor 61 embedded in the insulating layer 51. In a plan view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating side walls 53A to 53D, and divides the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 suppresses the intrusion of moisture and cracks from the outer region 63 into the device region 62.

[0106] The device region 62 is the region that includes the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. The outer region 63 is the region outside the device region 62.

[0107] The sealing conductor 61 is electrically isolated from the device region 62. Specifically, the sealing conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealing conductor 61 is electrically suspended. The sealing conductor 61 does not form a current path that connects to the device region 62.

[0108] In a plan view, the sealing conductor 61 is formed in a strip shape along the insulating side walls 53-53D. In this configuration, the sealing conductor 61 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the sealing conductor 61 demarcates a rectangular (specifically, rectangular) device region 62 in a plan view. Furthermore, the sealing conductor 61 demarcates the outer rectangular ring (specifically, a rectangular ring shape) region 63 surrounding the device region 62 in a plan view.

[0109] Specifically, the seal conductor 61 has an upper end on the insulating main surface 52 side, a lower end on the semiconductor chip 41 side, and a wall portion extending wall-like between the upper end and the lower end. In this embodiment, the upper end of the seal conductor 61 is formed with a gap from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed with a gap from the semiconductor chip 41 toward the upper end side.

[0110] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side relative to the multiple low-potential terminals 11 and the multiple high-potential terminals 12. Furthermore, within the insulating layer 51, the sealing conductor 61 faces the first functional device 45 (multiple transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Within the insulating layer 51, the sealing conductor 61 may also face a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0111] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, multiple) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 of the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. It is preferable that the seal plug conductors 64 and seal via conductors 65 are made of the same conductive material as the low-potential coil 22. That is, it is preferable that the seal plug conductors 64 and seal via conductors 65 include a barrier layer and a body layer, similar to the low-potential coil 22, etc.

[0112] Multiple seal plug conductors 64 are embedded in multiple interlayer insulating layers 57, and in a plan view, they are each formed in a rectangular ring (specifically, a rectangular ring) surrounding the device region 62. Multiple seal plug conductors 64 are stacked from the bottom insulating layer 55 toward the top insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 corresponds to the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0113] If a single annular seal conductor 61 is formed by an assembly of multiple seal plug conductors 64, it is not necessary for all of the multiple seal plug conductors 64 to be formed in an annular shape. For example, at least one of the multiple seal plug conductors 64 may be formed with ends. Alternatively, at least one of the multiple seal plug conductors 64 may be divided into multiple end-shaped strips. However, considering the risk of moisture and cracks entering the device region 62, it is preferable that the multiple seal plug conductors 64 be formed in an endless (annular) shape.

[0114] Multiple seal via conductors 65 are formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the bottom insulating layer 55. The multiple seal via conductors 65 are formed at intervals from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. If a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area greater than or equal to the planar area of ​​the seal plug conductor 64.

[0115] The width of the seal conductor 61 may be 0.1 μm or more and 10 μm or less. Preferably, the width of the seal conductor 61 is 1 μm or more and 5 μm or less. The width of the seal conductor 61 is defined by the width in the direction perpendicular to the direction in which the seal conductor 61 extends.

[0116] Referring to Figures 7 and 8, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the sealing conductor 61, which electrically isolates the sealing conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 consists of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0117] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 consists of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0118] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion to which the lower end (seal via conductor 65) of the seal conductor 61 bites toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0119] The separation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. The inner end portion 130A demarcates the region where the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end portion 130A may be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0120] The outer end portion 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is connected to the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0121] The main body portion 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in the main body portion 130C at a distance from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can take various forms other than the field insulating film 131.

[0122] Referring to Figure 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52.

[0123] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. Preferably, the first inorganic insulating layer 141 contains USG (undopped silicate glass), which is silicon oxide without impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength on the high-potential coil 23 can be increased.

[0124] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the dielectric breakdown voltage (V / cm) of USG exceeds the dielectric breakdown voltage (V / cm) of silicon nitride. Therefore, when thickening the inorganic insulating layer 140, it is preferable to form the first inorganic insulating layer 141 which is thicker than the second inorganic insulating layer 142.

[0125] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass) as examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable that the first inorganic insulating layer 141 be made of USG in order to increase the dielectric strength on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure consisting of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0126] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed in the area outside the seal conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11, respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that ride up over the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may also have overlapping portions that ride up over the periphery of the high-potential terminals 12.

[0127] The semiconductor device 5 further includes an organic insulating layer 145 formed on an inorganic insulating layer 140. The organic insulating layer 145 may contain a photosensitive resin. The organic insulating layer 145 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0128] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than or equal to the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Also, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. With these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the dielectric strength on the high-potential coil 23 can be appropriately increased by the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0129] The organic insulating layer 145 includes a first portion 146 that covers the low-potential region and a second portion 147 that covers the high-potential region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 in between. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have overlapping portions that ride up on the periphery (overlap portion) of the low-potential pad openings 143.

[0130] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may have overlapping portions that ride up on the periphery (overlap portion) of the high-potential pad openings 144.

[0131] The second section 147 covers the transformers 21A to 21D and the dummy pattern 85 together. Specifically, the second section 147 covers the multiple high-potential coils 23, the multiple high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121 together.

[0132] Embodiments of the present invention can be implemented in yet other forms. In the embodiments described above, an example was described in which a first functional device 45 and a second functional device 60 are formed. However, an embodiment may be adopted in which only the second functional device 60 is present, without the first functional device 45. In this case, the dummy pattern 85 may be removed. With this structure, the second functional device 60 can achieve the same effects as described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0133] In other words, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, unwanted conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed.

[0134] Furthermore, the above-described embodiment described an example in which a second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0135] Furthermore, the above-described embodiment described an example in which a dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0136] Furthermore, in the embodiments described above, an example was given in which the first functional device 45 consists of a multi-channel type including multiple transformers 21. However, a first functional device 45 consisting of a single-channel type including a single transformer 21 may also be employed.

[0137] <Trans arrangement> Figure 9 is a schematic plan view (top view) showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the semiconductor device 5 mentioned earlier). The transformer chip 300 in this figure includes a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0138] In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary coil L1s that forms the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of the secondary coil L2s that forms the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0139] Furthermore, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0140] Note that the primary coils forming the first transformer 301, the second transformer 302, the third transformer 303, and the fourth transformer 304 are not explicitly shown in this figure. However, each primary coil basically has the same configuration as the secondary coils L1s to L4s, and is positioned directly below each of the secondary coils L1s to L4s, facing them respectively.

[0141] Specifically, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Similarly, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0142] Furthermore, pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Similarly, pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0143] However, pads a5-a8, b5-b8, c3 and c4, and d3 and d4 are led from the inside of the trans tip 300 to the surface via vias (not shown).

[0144] Of the above multiple pads, pads a1 to a8 correspond to the first current supply pads, pads b1 to b8 correspond to the first voltage measurement pads, pads c1 to c4 correspond to the second current supply pads, and pads d1 to d4 correspond to the second voltage measurement pads.

[0145] Therefore, with the transformer chip 300 in this configuration example, the series resistance component of each coil can be accurately measured during defective product inspection. Consequently, it becomes possible to appropriately reject not only defective products with open circuits in each coil, but also defective products with abnormal resistance values ​​in each coil (for example, short circuits between coils), and ultimately, to prevent defective products from reaching the market.

[0146] Furthermore, for the transformer chip 300 that has passed the above-mentioned defect inspection, the multiple pads can be used as means of connecting to the primary chip and the secondary chip (for example, the controller chip 210 and driver chip 220 mentioned above).

[0147] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 should be connected to the signal input terminal or signal output terminal of the secondary chip, respectively. Also, pads c1 and d1, and pads c2 and d2 should be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0148] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 should be connected to the signal input terminal or signal output terminal of the primary chip, respectively. Also, pads c3 and d3, and pads c4 and d4 should be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0149] Here, the first transformers 301 to the fourth transformers 304 are arranged in a coupled configuration according to their respective signal transmission directions, as shown in Figure 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary side chip to the secondary side chip, are connected as a first pair by the first guard ring 305. Similarly, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary side chip to the primary side chip, are connected as a second pair by the second guard ring 306.

[0150] The reason for this coupling is to ensure voltage resistance between the primary and secondary coils when the primary and secondary coils forming the first to fourth transformers 301 to 304 are stacked in the vertical direction on the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0151] The first guard ring 305 and the second guard ring 306 can be connected to low-impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0152] Furthermore, in the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between their respective primary coils. By adopting this configuration, it is possible to reduce the number of pads and miniaturize the transformer chip 300.

[0153] Furthermore, as shown in Figure 9, it is desirable that the primary and secondary coils forming the first to fourth transformers 301 to 304 be wound in a rectangular shape (or a track shape with rounded corners) when viewed from above the transformer tip 300. This configuration increases the area of ​​the overlapping portion between the primary and secondary coils, thereby improving the transmission efficiency of the transformer.

[0154] Of course, the transformer arrangement in this diagram is merely an example, and the number, shape, and placement of coils, as well as the placement of pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to semiconductor devices in general that integrate coils on a semiconductor chip.

[0155] <Signal transmission device (first embodiment)> Figure 10 shows a first embodiment of the signal transmission device. The signal transmission device 400 of the first embodiment is an isolated ADC (analog-to-digital converter) and comprises a first chip 410, a second chip 420, and a third chip 430, which are sealed in a single package.

[0156] The first chip 410 is a control-side chip provided in the primary circuit system. The first chip 410 integrates, for example, a first pulse transmission circuit 411, a second pulse reception circuit 412, and an interface 413.

[0157] The first pulse transmission circuit 411 generates the first transmission pulse signal S42 in synchronization with the first reference clock signal S41 (= external input clock signal CLKI).

[0158] The second pulse receiving circuit 412 receives the second received pulse signal S53 and generates the second digital signal S54.

[0159] Interface 413 outputs the external input clock signal CLKI, which is received as an external input, as the first reference clock signal S41 to the first pulse transmission circuit 411. Interface 413 also outputs the second digital signal S54, which is output from the second pulse reception circuit 412, as the digital output signal DO.

[0160] The second chip 420 is a measurement-side chip ADC provided in the secondary circuit system. The second chip 420 integrates, for example, a first pulse receiving circuit 421, a second pulse transmitting circuit 422, and an analog-to-digital conversion circuit 423.

[0161] The first pulse receiving circuit 421 receives the first received pulse signal S43 and generates a second reference clock signal S44.

[0162] The second pulse transmission circuit 422 generates a second transmission pulse signal S52 in synchronization with the second reference clock signal S44, corresponding to the logic level of the first digital signal S51.

[0163] The analog-to-digital conversion circuit 423 converts the externally input analog input signal AI into a first digital signal S51 in synchronization with the second reference clock signal S44. A ΔΣ ADC is preferably used as the analog-to-digital conversion circuit 423.

[0164] The third chip 430 is an isolated communication chip provided between the primary circuit system and the secondary circuit system (i.e., between the first chip 410 and the second chip 420). The third chip 430 integrates, for example, a first isolated communication circuit 431 and a second isolated communication circuit 432.

[0165] The first isolated communication circuit 431 transmits the first transmitted pulse signal S42 as the first received pulse signal S43 while isolating the first pulse transmitting circuit 411 and the first pulse receiving circuit 421.

[0166] The second isolated communication circuit 432 transmits the second transmitted pulse signal S52 as the second received pulse signal S53 while isolating the second pulse transmitting circuit 422 and the second pulse receiving circuit 412.

[0167] Suitable insulation methods for the first isolated communication circuit 431 and the second isolated communication circuit 432 include transformer isolation (coil isolation) or capacitive isolation.

[0168] Furthermore, both the first isolated communication circuit 431 and the second isolated communication circuit 432 are integrated into a third chip 430, which is provided separately and independently from the first chip 410 and the second chip 420. With this configuration, the first chip 410 and the second chip 420 can each be formed using an inexpensive low-to-medium voltage process (several volts to tens of volts).

[0169] However, the configuration shown in this figure is merely an example, and the third chip 430 can be omitted. In that case, the first isolated communication circuit 431 and the second isolated communication circuit 432 may be integrated into the first chip 410 or the second chip 420, respectively.

[0170] Furthermore, the second chip 420 may be divided into, for example, an isolated communication chip equipped with a first pulse receiving circuit 421 and a second pulse transmitting circuit 422, and a measurement chip equipped with an analog / digital conversion circuit 423.

[0171] Figure 11 is a diagram showing the signal transmission operation of the first embodiment, and from top to bottom, it depicts the first reference clock signal S41, the first received pulse signals S43R and S43F, the second reference clock signal S44, the first digital signal S51, and the second transmitted pulse signals S52H and S52L.

[0172] The first received pulse signals S43R and S43F correspond to the first received pulse signal S43 mentioned earlier, respectively. Referring to this figure, the first received pulse signal S43R, which transmits the rising edge of the first reference clock signal S41, is pulse-driven in synchronization with the rising edge of the first reference clock signal S41. On the other hand, the first received pulse signal S43F, which transmits the falling edge of the first reference clock signal S41, is pulse-driven in synchronization with the falling edge of the first reference clock signal S41.

[0173] The second reference clock signal S44 rises to a high level in response to the pulse drive of the first received pulse signal S43R, and falls to a low level in response to the pulse drive of the first received pulse signal S43F. Therefore, the second reference clock signal S44 has the same oscillation frequency and duty cycle as the first reference clock signal S41 (and consequently the external input clock signal CLKI).

[0174] In other words, in the signal transmission device 400 of the first embodiment, the external input clock signal CLKI, which is input to the first chip 410, is transferred to the second chip 420 via the first pulse transmission circuit 411, the first isolated communication circuit 431, and the first pulse receiving circuit 421.

[0175] The analog-to-digital conversion circuit 423 converts the analog input signal AI to the first digital signal S51 by alternately repeating two operating states corresponding to the logic level of the second reference clock signal S44. Therefore, the logic level (=data) of the first digital signal S51 is determined for each cycle of the second reference clock signal S44.

[0176] The second transmission pulse signals S52H and S52L correspond to the previously mentioned second transmission pulse signal S52, respectively. Referring to this figure, during the high-level period of the first digital signal S51, the second transmission pulse signal S52H for high-level transmission is pulse-driven in synchronization with the rising edge of the second reference clock signal S44. On the other hand, during the low-level period of the first digital signal S51, the second transmission pulse signal S52L for low-level transmission is pulse-driven in synchronization with the rising edge of the second reference clock signal S44.

[0177] Although not explicitly shown in this diagram, the second transmission pulse signals S52H and S52L are transmitted to the second pulse receiving circuit 412 via the second isolated communication circuit 432 and used for the generation process of the second digital signal S54. The second digital signal S54 has essentially the same logic level as the first digital signal S51 and is output externally as the digital output signal DO.

[0178] In other words, in the signal transmission device 400 of the first embodiment, the analog input signal AI that is externally input to the second chip 420 is converted from analog to digital, then transferred to the first chip 410 via the second pulse transmission circuit 422, the second isolated communication circuit 432, and the second pulse receiving circuit 412, and output externally as a digital output signal DO.

[0179] Thus, the signal transmission device 400 of the first embodiment can transmit various pulse signals (such as a reference clock signal and digital signals) while insulating the first chip 410 and the second chip 420.

[0180] However, in the signal transmission device 400 of the first embodiment, two pulse drives synchronized with the rising edge and falling edge of the first reference clock signal S41 are performed as the clock transfer process from the first chip 410 to the second chip 420. As a result, the current consumption of the first isolated communication circuit 431 is relatively large.

[0181] <Signal transmission device (second embodiment)> Figure 12 shows a second embodiment of the signal transmission device. The signal transmission device 400 of the second embodiment is based on the first embodiment (Figure 10) described above, with the addition of a drive clock signal generation circuit 424 on the second chip 420.

[0182] The drive clock signal generation circuit 424 is located between the first pulse receiving circuit 421 and the analog / digital conversion circuit 423. The drive clock signal generation circuit 424 generates a drive clock signal S45 having a predetermined oscillation frequency and a predetermined duty cycle or predetermined pulse width, in synchronization with the second reference clock signal S44.

[0183] Furthermore, a phase-locked loop (PLL) or a delay-locked loop (DLL) is preferably used as the drive clock signal generation circuit 424.

[0184] Furthermore, with the addition of the drive clock signal generation circuit 424, the operation of both the first pulse transmission circuit 411 and the analog / digital conversion circuit 423 has also been modified.

[0185] Specifically, the first pulse transmission circuit 411 generates the first transmission pulse signal S42 in synchronization with either the rising edge or the falling edge of the first reference clock signal S41 (= external input clock signal CLKI) output from the interface 413. For example, the first pulse transmission circuit 411 performs pulse driving (single or multiple transmission pulse output) of the first transmission pulse signal S42 at the timing when the first reference clock signal S41 rises from a low level to a high level. In addition, the analog-to-digital conversion circuit 423 converts the analog input signal AI to the first digital signal S51 in synchronization with the drive clock signal S45, not the second reference clock signal S44.

[0186] Figure 13 is a diagram showing the signal transmission operation of the second embodiment, and from top to bottom, it depicts the first reference clock signal S41, the first received pulse signal S43, the second reference clock signal S44, the drive clock signal S45, the first digital signal S51, and the second transmitted pulse signals S52H and S52L.

[0187] The first received pulse signal S43 is pulse-driven in synchronization only with the rising edge of the first reference clock signal S41.

[0188] The second reference clock signal S44 rises to a high level in response to the pulse drive of the first received pulse signal S43, and then falls to a low level at any arbitrary timing. Therefore, the second reference clock signal S44 has the same oscillation frequency as the first reference clock signal S41 (and consequently the external input clock signal CLKI), but it is a signal with a different duty cycle or pulse width.

[0189] The drive clock signal S45 is synchronized with the second reference clock signal S44 and is feedback-controlled to have the same duty cycle or pulse width as the first reference clock signal S41 (and consequently the external input clock signal CLKI).

[0190] The analog-to-digital conversion circuit 423 converts the analog input signal AI into the first digital signal S51 in synchronization with the drive clock signal S45. The subsequent operation is basically the same as in the first embodiment described above (Figure 10).

[0191] Thus, in the signal transmission device 400 of the second embodiment, only timing information related to the rising edge (or falling edge) of the first reference clock signal S41 is transferred as part of the clock transfer process from the first chip 410 to the second chip 420. In other words, only pulse driving synchronized with the rising edge of the first reference clock signal S41 is performed. Therefore, compared to the first embodiment described above (Figure 10), it is possible to reduce the current consumption of the first isolated communication circuit 431.

[0192] <Signal transmission device (third embodiment)> Figure 14 shows a third embodiment of the signal transmission device. The signal transmission device 400 of the third embodiment is based on the second embodiment (Figure 12) described above, with an oscillator 414 added to the first chip 410.

[0193] The oscillator 414 outputs its own internal clock signal as the first reference clock signal S41 to the first pulse transmission circuit 411. Alternatively, the oscillator 414 may output its own internal clock signal S46 as the external output clock signal CLKO via the interface 413.

[0194] Thus, the first reference clock signal S41 does not necessarily have to originate from the external input clock signal CLKI, but may also originate from the internal clock signal of oscillator 414.

[0195] <Signal transmission device (fourth embodiment)> Figure 15 shows a fourth embodiment of the signal transmission device. The signal transmission device 400 of the fourth embodiment is based on the second embodiment (Figure 12) described above, with a latch circuit 425 added to the second chip 420.

[0196] The latch circuit 425 latches and outputs the first digital signal S51 in synchronization with the second reference clock signal S44. For example, the latch circuit 425 captures the logic level of the first digital signal S51 in synchronization with the rising edge of the second reference clock signal S44 and outputs it to the second pulse transmission circuit 422 as the latched first digital signal S51L. A D flip-flop or the like is preferably used as the latch circuit 425.

[0197] The second pulse transmission circuit 422 generates a second transmission pulse signal S52 corresponding to the logic level of the latched first digital signal S51L.

[0198] Figure 16 is a diagram showing the signal transmission operation of the fourth embodiment, and from top to bottom, it depicts the first reference clock signal S41, the first received pulse signal S43, the second reference clock signal S44, the drive clock signal S45, the first digital signal S51, the latched first digital signal S51L, and the second transmitted pulse signals S52H and S52L.

[0199] As shown in this figure, the drive clock signal S45 has jitter due to signal processing (phase synchronization processing or delay synchronization processing, etc.) in the drive clock signal generation circuit 424. Therefore, jitter may also occur in the first digital signal S51 which is generated in synchronization with the drive clock signal S45.

[0200] On the other hand, the second reference clock signal S44 does not undergo signal processing by the drive clock signal generation circuit 424 and therefore does not have the jitter mentioned above. Consequently, by latching the first digital signal S51 in synchronization with the second reference clock signal S44, the drive clock signal S45 (and consequently the first digital signal S51) becomes less susceptible to the effects of jitter.

[0201] <Signal transmission device (5th embodiment)> Figure 17 shows a fifth embodiment of the signal transmission device. The signal transmission device 400 of the fifth embodiment is based on the second embodiment (Figure 12) described above, with the addition of a frequency divider circuit 415 to the first chip 410.

[0202] The frequency divider circuit 415 is located between the interface 413 and the first pulse transmission circuit 411. The frequency divider circuit 415 outputs a divided clock signal S41D, obtained by dividing the first reference clock signal S41 (and consequently the external input clock signal CLKI), to the first pulse transmission circuit 411 in place of the first reference clock signal S41.

[0203] Figure 18 is a diagram showing the signal transmission operation of the fifth embodiment, and from top to bottom, it depicts the first reference clock signal S41, the frequency divider clock signal S41D, the first received pulse signal S43, the second reference clock signal S44, the drive clock signal S45, the first digital signal S51, and the second transmitted pulse signals S52H and S52L.

[0204] The divided clock signal S41D has the same duty cycle as the first reference clock signal S41, but its oscillation frequency is divided by half. Therefore, the first received pulse signal S43 (and consequently the second reference clock signal S44), which is generated in synchronization only with the rising edge of the divided clock signal S41D, has fewer pulses compared to the second embodiment described above (Figure 13). As a result, the current consumption of the first isolated communication circuit 431 can be further reduced.

[0205] Furthermore, if the number of pulses in the second reference clock signal S44 is reduced to half of its original value, the drive clock signal generation circuit 424 should double the second reference clock signal S44 before using it to generate the drive clock signal S45.

[0206] Furthermore, the second transmission pulse signals S52H and S52L are preferably pulse-driven in synchronization with the drive clock signal S45, rather than the second reference clock signal S44. Referring to this figure, during the high-level period of the first digital signal S51, the second transmission pulse signal S52H is pulse-driven in synchronization with the rising edge of the drive clock signal S45. On the other hand, during the low-level period of the first digital signal S51, the second transmission pulse signal S52L is pulse-driven in synchronization with the rising edge of the drive clock signal S45.

[0207] With this configuration, even if the number of pulses in the first received pulse signal S43 (and consequently the second reference clock signal S44) is reduced, it does not cause any problems in the generation operations of the first digital signal S51 and the second transmitted pulse signals S52H and S52L.

[0208] <Combination of Embodiments> Furthermore, the first to fifth embodiments described so far may be combined as appropriate, as long as they do not contradict each other. For example, although not shown again in the diagram, the third embodiment (Figure 14) and the fifth embodiment (Figure 17) may be combined to divide the internal clock signal generated by the oscillator 414 and output it to the first pulse transmission circuit 411.

[0209] <Summary> The various embodiments described above will be summarized below.

[0210] For example, the signal transmission device disclosed herein has a configuration (first configuration) comprising: a first pulse transmitting circuit configured to generate a first transmit pulse signal synchronized with either the rising edge or the falling edge of a first reference clock signal; a first pulse receiving circuit configured to receive a first receive pulse signal and generate a second reference clock signal; a first isolated communication circuit configured to transmit the first transmit pulse signal as the first receive pulse signal while insulating the first pulse transmitting circuit and the first pulse receiving circuit from each other; and a drive clock signal generation circuit configured to generate a drive clock signal having a predetermined oscillation frequency and a predetermined duty cycle or predetermined pulse width synchronized with the second reference clock signal.

[0211] In the signal transmission device according to the first configuration described above, the drive clock signal generation circuit may be configured as a phase-synchronous circuit or a delay-synchronous circuit (second configuration).

[0212] The signal transmission device according to the first or second configuration described above may further include an interface configured to output an external input clock signal as the first reference clock signal (third configuration).

[0213] The signal transmission device according to the first or second configuration described above may further include an oscillator configured to output an internal clock signal as the first reference clock signal (fourth configuration).

[0214] A signal transmission device according to any of the first to fourth configurations described above may further include a frequency divider circuit configured to output a divided clock signal obtained by dividing an external input clock signal or an internal clock signal as the first reference clock signal (a fifth configuration).

[0215] The signal transmission device according to any of the first to fifth configurations described above may further include an analog-to-digital conversion circuit configured to convert an analog input signal into a first digital signal in synchronization with the drive clock signal (sixth configuration).

[0216] The signal transmission device according to the sixth configuration described above may further include (seventh configuration) a second pulse transmission circuit configured to generate a second transmission pulse signal corresponding to the logic level of the first digital signal, a second pulse reception circuit configured to receive a second reception pulse signal and generate a second digital signal, and a second isolated communication circuit configured to transmit the second transmission pulse signal as the second reception pulse signal while insulating the second pulse transmission circuit and the second pulse reception circuit.

[0217] The signal transmission device according to the seventh configuration described above may further include a latch circuit configured to output the first digital signal to the second pulse transmission circuit in a latch state in synchronization with the second reference clock signal (eighth configuration).

[0218] The signal transmission device according to the seventh or eighth configuration described above may further include a first chip configured to integrate the first pulse transmission circuit and the second pulse reception circuit, and a second chip configured to integrate the first pulse reception circuit, the second pulse transmission circuit, the drive clock signal generation circuit, and the analog / digital conversion circuit (the ninth configuration).

[0219] In the signal transmission device according to the ninth configuration described above, the first isolated communication circuit and the second isolated communication circuit may be integrated on the first chip, the second chip, or a separate, independent third chip, respectively (the tenth configuration).

[0220] <Other variations> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure should be defined by the claims and understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0221] 5 Semiconductor Equipment 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformers 22 Low-potential coil (primary coil) 23. High-potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42. First Main Surface 43 Second Main Surface 44A~44D Chip sidewall 45. First Functional Device 51 Insulating layer 52 Insulation main surface 53A~53D Insulating sidewall 55. Bottom insulating layer 56. Top insulating layer 57 Interlayer insulating layer 58 First insulating layer 59 Second insulating layer 60 Second Functional Device 61 Seal conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Sea via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-voltage connection wiring 73 Pull-out wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrodes 77 Circuit board plug electrodes 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrodes 81 High-potential connection wiring 82 Pad plug electrodes 85 Dummy Patterns 86 High-Potential Dummy Pattern 87. First High-Potential Dummy Pattern 88. Second High-Potential Dummy Pattern 89 First area 90 Second area 91 Third area 92 First connection section 93 Pattern 1 94 Pattern 2 95 Pattern 3 96 First outer line 97 Second outer perimeter line 98 First Intermediate Line 99 First connection line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First Inorganic Insulating Layer 142 Second Inorganic Insulating Layer 143 Low-potential pad opening 144 High-potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmission circuit (pulse generator) 212, 213 buffers 220 Driver chip (second chip) 221, 222 buffers 223 Pulse receiving circuit (RS flip-flop) 224 drivers 230 Transchip (Third Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformers 231p, 232p primary coil 231s, 232s Secondary coil 300 Transchips 301 First Transformer 302 Second Transformer 303 Third Transformer 304 4th Transformer 305 First Guard Ring 306 Second Guard Ring 400 Signal transmission device 410 First chip 411 First pulse transmission circuit 412 Second pulse receiving circuit 413 Interface 414 Oscillator 415 frequency divider circuit 420 Second chip 421 First pulse receiving circuit 422 Second pulse transmission circuit 423 Analog / Digital Conversion Circuit 424 Drive Clock Signal Generation Circuit 425 Latch Circuit 430 Third chip 431 First isolated communication circuit 432 Second isolated communication circuit a1~a8 Pads (corresponding to the first current supply pads) b1~b8 Pads (corresponding to the first voltage measurement pads) c1~c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads L1p, L2p primary coil L1s, L2s, L3s, L4s secondary coils T21, T22, T23, T24, T25, T26 External terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 Via

Claims

1. A first pulse transmission circuit configured to generate a first transmission pulse signal synchronized with either the rising edge or the falling edge of a first reference clock signal, A first pulse receiving circuit configured to receive a first received pulse signal and generate a second reference clock signal, A first isolated communication circuit configured to transmit the first transmitted pulse signal as a first received pulse signal while insulating the first pulse transmitting circuit and the first pulse receiving circuit, A drive clock signal generation circuit configured to generate a drive clock signal having a predetermined oscillation frequency and a predetermined duty cycle or predetermined pulse width in synchronization with the second reference clock signal, An analog-to-digital conversion circuit configured to convert an analog input signal into a first digital signal in synchronization with the aforementioned drive clock signal, A second pulse transmission circuit configured to generate a second transmission pulse signal corresponding to the logic level of the first digital signal, A second pulse receiving circuit configured to receive a second received pulse signal and generate a second digital signal, A second isolated communication circuit configured to transmit the second transmitted pulse signal as a second received pulse signal while insulating the second pulse transmitting circuit from the second pulse transmitting circuit and the second pulse receiving circuit, A latch circuit configured to output a latched output to a second pulse transmission circuit of the first digital signal having jitter due to signal processing in the clock signal generation circuit, in synchronization with the second reference clock signal which has no jitter due to signal processing in the clock signal generation circuit, A signal transmission device equipped with the following features.

2. The signal transmission device according to claim 1, wherein the drive clock signal generation circuit is a phase-synchronization circuit or a delay-synchronization circuit.

3. The signal transmission device according to claim 1, further comprising an interface configured to output an external input clock signal as the first reference clock signal.

4. The signal transmission device according to claim 1, further comprising an oscillator configured to output an internal clock signal as the first reference clock signal.

5. The signal transmission device according to claim 1, further comprising a frequency divider circuit configured to output a frequency-divided clock signal obtained by dividing an external input clock signal or an internal clock signal as the first reference clock signal.

6. A first chip configured to integrate the first pulse transmitting circuit and the second pulse receiving circuit, A second chip configured to integrate the first pulse receiving circuit, the second pulse transmitting circuit, the drive clock signal generation circuit, and the analog / digital conversion circuit, The signal transmission device according to claim 1, further comprising:

7. The signal transmission device according to claim 6, wherein the first isolated communication circuit and the second isolated communication circuit are each integrated on the first chip, the second chip, or a separate and independent third chip.

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