Gnn and llm collaborative system for power electronic schematic automatic design

Abstract

This application relates to the field of electronic design automation (EDA) technology and discloses a GNN and LLM collaborative system for automatic schematic design of power electronics. The system includes an iterative update control module, a graph structure modeling module, a dual-channel graph feature encoding module, a semantic prompt construction module, and a large language model inference module. The system generates a component prediction sequence based on the circuit energy flow, extracts node embedding vectors from the masked graph structure data using a dual-channel graph neural network, and constructs natural language prompts containing local topology and design constraints. The large language model performs thought chain inference based on the prompts, generates specific component models and backfills them into the circuit netlist, and triggers the next round of prediction through a chained mask completion mechanism. This invention achieves effective fusion of circuit topology and semantic features, enhances the interpretability of the design process, and ensures dynamic matching of circuit parameters between different stages.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, specifically to a GNN and LLM collaborative system for automatic design of power electronic schematics. Background Technology

[0002] Schematic design of power electronic systems is a complex engineering task involving topology selection, component selection, and parameter calculation. Traditional design processes rely heavily on the expertise of hardware engineers and manual calculations, resulting in long design cycles and susceptibility to parameter mismatch errors due to human negligence. With the development of artificial intelligence technology, using data-driven methods to automate the generation and design of circuit schematics has gradually become a research hotspot in this field.

[0003] Despite advancements in automated circuit design, numerous technical challenges remain in practical applications. Existing automated design methods often struggle to effectively integrate circuit topology with design text constraints. While graph neural network-based methods can handle irregular connections in circuit netlists well, they often struggle to directly interpret unstructured natural language constraints in design specifications, such as input / output voltages and rated power. Conversely, natural language processing-based methods, while capable of parsing textual requirements, struggle to perceive the complex topological connection logic of circuits. This disconnect in data modality processing capabilities makes it difficult for existing automated design tools to accurately meet specific electrical performance specifications while ensuring the correctness of circuit topology connections.

[0004] Existing deep learning-based end-to-end circuit generation models generally suffer from insufficient interpretability. These models typically output predicted results for components directly, without providing specific engineering reasoning processes regarding voltage stress margin, current capacity matching, or frequency response analysis. In the field of power electronics, where reliability requirements are extremely high, design results lacking clear electrical derivation are difficult for engineers to accept and hinder subsequent troubleshooting and design verification.

[0005] Power electronic circuits exhibit significant cascading dependency characteristics; the parameters of upstream components, whether in terms of energy or signal flow, often determine the electrical stress distribution of downstream components. However, existing automatic generation methods mostly employ parallel prediction or independent optimization strategies, neglecting the dynamic coupling relationship between upstream and downstream component parameters. This approach can easily lead to the selection of downstream components in the generated circuit schematic failing to adequately adapt to the actual operating states of upstream components, resulting in system-level parameter mismatches and reducing the electrical reliability and practical value of the generated circuit. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a GNN and LLM collaborative system for automatic design of power electronic schematics, which solves the problem of data mode fragmentation in existing automatic design methods when dealing with irregular circuit topologies and unstructured design text.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] The first aspect of this invention provides a GNN and LLM collaborative system for automatic design of power electronic schematics. This system processes circuit topology data through a graph neural network and collaborates with a large language model to process semantic text data, thereby automating the selection of components from the circuit netlist to specific component models.

[0009] The system includes an iterative update control module, a graph structure modeling module, a dual-channel graph feature encoding module, a semantic prompt construction module, and a large language model inference module.

[0010] The iterative update control module is configured to generate and manage a component prediction sequence. This module sorts the components to be designed in the power electronic circuit according to the signal or energy flow direction. The module determines the current target node to be predicted from the component prediction sequence, and after obtaining the specific component model for that node, writes the specific component model into the netlist file, subsequently triggering the prediction process for the next target node in the sequence.

[0011] The graph structure modeling module is configured to construct circuit graph structure data. This module maps the netlist file of the power electronic circuit into graph structure data containing an adjacency matrix and a node feature matrix. In this graph structure data, each graph node uniquely corresponds to a physical component in the netlist file, and each edge represents two physical components connected to the same electrical network identifier. The module uses a preset mask embedding vector to replace the feature vector in the node feature matrix corresponding to the current target node to be predicted, generating masked graph structure data. During this process, the adjacency matrix values ​​remain unchanged to maintain the circuit topology connections.

[0012] The dual-channel graph feature encoding module is configured to extract node features and output predicted labels using a dual-channel architecture. The first processing channel uses a graph convolutional neural network algorithm to process the adjacency matrix and node feature matrix, aggregating neighbor node features through a message passing mechanism. It then maps and weights the feature vectors of neighbor nodes using a linear transformation weight matrix, finally fusing the feature vectors of the target node to generate a topological structure feature vector representing the connection topology information. The second processing channel uses a multilayer perceptron algorithm to process the node feature matrix, generating attribute feature vectors representing the independent attribute information of the nodes. The feature fusion unit concatenates the topological structure feature vector and the attribute feature vector to generate a node embedding vector. This module further uses a classification prediction unit to perform linear transformation and normalized exponential function operations on the node embedding vector, calculating the probability distribution of the target node belonging to a preset component function category, and selecting the category with the highest probability value as the predicted function category label.

[0013] The semantic prompting construction module is configured to convert graph structure data into natural language prompts. Based on the local topology information of the target node to be predicted and the prediction function category labels, this module constructs a sequence of input prompts in natural language format using a preset text mapping template. The input prompt sequence includes: a task definition fragment containing inference instructions; a circuit state fragment containing component category names and circuit connection relationship text; and a design constraint fragment containing input voltage, output voltage, and rated power values.

[0014] The large language model reasoning module is configured to generate component model numbers using a thought chain strategy. This module inputs a sequence of input prompts into the large language model, first generating intermediate reasoning text fragments. These fragments record numerical analysis of circuit design constraints and matching evaluations of the electrical characteristics of candidate components. The module compares the calculated minimum electrical specification requirements with the parameterized general knowledge stored within the large language model, recording the comparison process as reasoning statements. Subsequently, using the intermediate reasoning text fragments as context, the module generates a final model number text fragment and extracts the specific component model number. Furthermore, the module performs reasoning pruning, retrieving intermediate reasoning text fragments using a pre-defined electrical keyword list, retaining statements containing keywords related to voltage, current, and power, and filtering general descriptive text to generate concise reasoning text.

[0015] In one embodiment of the invention, the system employs a chained mask completion mechanism. The iterative update control module backfills the generated specific component models into the netlist file, updating the state of the target node to be predicted to a determined state. In the prediction process for the next node, the graph structure modeling module regenerates the graph structure data based on the updated netlist file, ensuring that the previously determined nodes provide true physical attribute characteristics in the node feature matrix. This mechanism ensures that the selection of subsequent components in the circuit is matched based on the parameters of the previously determined components.

[0016] A second aspect of this invention provides a method for automatic design of power electronic schematics. The method includes: generating a component prediction sequence based on the signal or energy flow direction of the power electronic circuit, and determining the current target node to be predicted; mapping a netlist file to graph structure data and performing feature masking processing on the target node to be predicted; extracting node embedding vectors using a dual-channel architecture and generating prediction function category labels; constructing a natural language input prompt sequence containing local topology information and design constraints; generating specific component models through thought chain reasoning using a large language model; and updating the specific component models to the netlist file and triggering the next round of prediction.

[0017] A third aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described method.

[0018] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-described method.

[0019] This invention provides a GNN and LLM collaborative system for automatic schematic design in power electronics. It offers the following advantages: 1. This invention achieves an effective fusion of circuit topology features and semantic reasoning features. It extracts the circuit's connection structure features and node attribute features through a dual-channel graph feature encoding module, and combines this with a semantic prompting construction module to convert numerical features into natural language descriptions, enabling collaborative reasoning using a large language model. This architecture solves the problem of traditional automatic design methods struggling to simultaneously handle irregular topology data and unstructured design constraint text in power electronic circuits, ensuring that component selection conforms to both circuit connection logic and specific physical design specifications such as voltage and power.

[0020] 2. This invention enhances the interpretability and reliability of the automated design process. Utilizing a large language model's thought chain reasoning strategy, it generates intermediate reasoning text containing electrical parameter verification processes before outputting the final component model number. This mechanism transforms the implicit feature matching process into explicit natural language logic, clearly recording selection criteria such as voltage stress margin analysis and current capacity requirement matching. This overcomes the technical shortcomings of traditional end-to-end deep learning models, which lack inference process recording and make design results difficult to trace.

[0021] 3. This invention ensures the matching of system-level parameters between preceding and subsequent stages. It employs a chain-like mask completion mechanism based on energy or signal flow direction, continuously backfilling the determined component models into the netlist file and reconstructing the graph structure during iterative prediction. This mechanism ensures that the selection of subsequent cascaded components can be dynamically adjusted based on the actual physical properties of the determined preceding components, conforming to the cascading dependency law in power electronic system design where preceding parameters determine subsequent parameters, thus improving the overall electrical performance consistency of the generated circuit. Attached Figure Description

[0022] Figure 1 This is a system architecture diagram of the present invention; Figure 2 This is a diagram illustrating the overall architecture and workflow of the PE-GLC Agent of the present invention; Figure 3 This is a schematic diagram of the thought chain prompt words of the present invention; Figure 4 This is a schematic diagram of a case study object of the present invention; Figure 5 This is a schematic diagram of the overall process in another case study of the present invention. Detailed Implementation

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Please see the appendix Figure 1 This invention provides a GNN and LLM collaborative system for automatic design of power electronic schematics. The collaborative system 100 can parse the netlist file of power electronic circuits and predict the specific models of undetermined components in the circuit. The collaborative system 100 includes: a graph structure modeling module 110, a dual-channel graph feature encoding module 120, a semantic prompting construction module 130, a large language model inference module 140, and an iterative update control module 150.

[0025] The graph structure modeling module 110 is configured to receive the netlist file of the power electronic circuit. The netlist file contains connection node information and component parameter information for all components in the circuit. The graph structure modeling module 110 parses the netlist file and constructs the graph structure data of the circuit. The graph structure data includes at least: an adjacency matrix describing the electrical connections between components, and a node feature matrix describing the physical properties of the components. When there are components to be designed in the circuit, the graph structure modeling module 110 performs a masking operation on the graph structure data, marking the components to be designed as mask nodes, and transmits the graph structure data containing the mask nodes to the dual-channel graph feature encoding module 120.

[0026] The dual-channel graph feature encoding module 120 is signal-connected to the graph structure modeling module 110. The dual-channel graph feature encoding module 120 internally incorporates a graph neural network algorithm, which includes two parallel processing channels: a topology extraction channel and a component information extraction channel. The topology extraction channel receives an adjacency matrix to extract the connection structure features of the circuit; the component information extraction channel receives a node feature matrix to extract the attribute features of the components. The dual-channel graph feature encoding module 120 fuses the connection structure features and attribute features to generate a high-dimensional embedding vector for the masked nodes. Based on the high-dimensional embedding vector, the dual-channel graph feature encoding module 120 calculates the probability that the masked nodes belong to different component functional categories and outputs the predicted functional category label of the masked nodes.

[0027] The semantic prompting construction module 130 is connected to both the dual-channel graph feature encoding module 120 and the graph structure modeling module 110. The semantic prompting construction module 130 receives the predicted function category labels output by the dual-channel graph feature encoding module 120 and obtains the local circuit topology data directly connected to the mask nodes from the graph structure modeling module 110. The semantic prompting construction module 130 stores a preset natural language conversion template. Using the natural language conversion template, the semantic prompting construction module 130 concatenates the predicted function category labels, local circuit topology data, and preset circuit design constraints into a text sequence that conforms to natural language grammar. The semantic prompting construction module 130 defines the text sequence as structured prompt word data.

[0028] The large language model inference module 140 is connected to the semantic prompting construction module 130 and is used to receive prompt word data. The large language model inference module 140 runs a pre-trained large language model. Based on the prompt word data, the large language model inference module 140 performs multi-step thought chain inference operations. The thought chain inference operations include: first, generating intermediate inference criteria regarding component selection; then, generating the final component model text based on the intermediate inference criteria. The large language model inference module 140 outputs the component model text.

[0029] The iterative update control module 150 is connected to both the large language model inference module 140 and the graph structure modeling module 110. The iterative update control module 150 extracts component model text and fills it back into the corresponding mask node positions in the netlist file, forming an updated netlist file. The iterative update control module 150 checks whether the updated netlist file still contains undesigned components. If it does, the iterative update control module 150 sends a control command to the graph structure modeling module 110, triggering the graph structure modeling module 110 to regenerate graph structure data based on the updated netlist file and initiate the prediction process for the next mask node, until all components in the netlist file are determined.

[0030] An embodiment of the present invention provides an automatic schematic design method for power electronics. This method, applied to the aforementioned collaborative system 100, includes the following steps: Step S1: The graph structure modeling module 110 acquires the initial netlist file of the power electronic circuit and determines the component prediction sequence according to the preset design requirements. Following the component prediction sequence, the graph structure modeling module 110 defines the currently predicted component as the target node and generates a graph structure representation of the target node.

[0031] Step S2: The dual-channel graph feature encoding module 120 receives the graph structure representation and performs convolutional encoding on the topological information and attribute information in the graph structure representation. Based on the encoding results, the dual-channel graph feature encoding module 120 predicts the component function category of the target node.

[0032] Step S3: The semantic prompting construction module 130 extracts the component function categories of the target node and the neighbor connections of the target node in the initial netlist file. The semantic prompting construction module 130 converts the component function categories and neighbor connections into prompt words described in natural language.

[0033] Step S4: The large language model reasoning module 140 receives the prompt words. The large language model reasoning module 140 utilizes the reasoning capabilities of the large language model, combined with the contextual constraints in the prompt words, to generate the specific component model of the target node.

[0034] Step S5: The iterative update control module 150 updates the specific component model to the initial netlist file. The collaborative system 100 determines whether the prediction of all components in the component prediction sequence has been completed; if not, it returns to step S1 and continues to predict the next component using the updated netlist file as input.

[0035] The circuit schematic to graph structure data conversion process provided by this invention is executed by the graph structure modeling module 110, and the process includes: The graph structure modeling module 110 receives the netlist file of the power electronic circuit. The netlist file contains a component list and a network connection list. The component list records the unique identifier, component type, and package parameters of each component in the circuit; the network connection list records the electrical network identifier (NetID) to which each component pin is connected. Based on the component list and network connection list, the graph structure modeling module 110 constructs the graph structure of the circuit. .in, Represents the set of graph nodes. Represents the set of edges in a graph.

[0036] For graph node set In the construction process, the graph structure modeling module 110 performs component mapping operations. The graph structure modeling module 110 traverses the component list, mapping each component in the list to a graph node in the graph structure. The graph structure modeling module 110 counts the total number of components and defines the total number of components as... .

[0037] For graph edge set In the construction of the graph structure modeling module 110, the connection relationship between graph nodes is determined based on the network connection list. When the graph structure modeling module 110 detects that the pins of two components are connected to the same electrical network identifier, the graph structure modeling module 110 establishes an edge between the two graph nodes corresponding to the two components. .

[0038] Graph structure modeling module 110 is based on graph structure Generate an adjacency matrix Adjacency matrix It is a dimension of The matrix. Graph structure modeling module 110 traverses all graph node pairs. If the graph nodes With graph nodes There are edges The graph structure modeling module 110 will use the adjacency matrix The Middle Line number Column elements Assign a value of 1; if no edge exists The graph structure modeling module 110 will use elements Assign a value of 0. Adjacency matrix Numerical representation of circuit topology features.

[0039] The graph structure modeling module 110 extracts attribute data from the component list and constructs a node feature matrix. Node feature matrix The dimension is ,in This represents the dimension of the feature vector. For each graph node... The graph structure modeling module 110 extracts the static physical attributes of the corresponding components from the netlist file. The static physical attributes include package type code, pin count, and component function classification code. The graph structure modeling module 110 combines the static physical attributes into a feature vector and fills the feature vector into the node feature matrix. In the corresponding row.

[0040] The graph structure modeling module 110 performs masking processing during the generation of graph structure data. Based on a preset design sequence, the graph structure modeling module 110 determines the target nodes for model prediction. The graph structure modeling module 110 locates the node feature matrix. The target feature vector corresponding to the target node. The graph structure modeling module 110 replaces the target feature vector with a preset mask vector. The mask vector is a predefined fixed numerical vector used to mask the real model information of the target node.

[0041] The graph structure modeling module 110 outputs processed graph structure data. The graph structure data includes an adjacency matrix. and the masked node feature matrix The graph structure data is configured as input data for the dual-channel graph feature encoding module 120.

[0042] The graph structure data construction process involved in this invention is executed by the graph structure modeling module 110. The graph structure modeling module 110 maps the netlist file of the power electronic circuit into graph structure data. Graph structure data is mathematically represented as an undirected graph. .in, Represents the set of graph nodes. This represents the set of connecting edges.

[0043] Graph structure modeling module 110 constructs a set of nodes. Node set Include A graph node, denoted as .in, This equals the total number of physical components recorded in the netlist file. Each graph node in the set... Each physical component corresponds uniquely to a single physical component in the netlist file. Types of physical components include resistors, capacitors, inductors, diodes, switching transistors, and controller chips.

[0044] Graph structure modeling module 110 constructs edge sets Edge set Includes all existing electrical connections in the circuit, denoted as .in, Represents the connection graph nodes With graph nodes Undirected edges. Graph structure modeling module 110 determines the edges. The logic for determining existence is: when a graph node... Corresponding component pins and diagram nodes When the corresponding component pins are connected to the same electrical network identifier (NetID) in the netlist file, the edge set... Contains edges .

[0045] Graph structure modeling module 110 is based on edge sets. Generate adjacency matrix Adjacency matrix It is a dimension of A binary matrix. Adjacency matrix. elements in Used to numerically represent the connectivity between nodes in a graph. When the edge set... There are edges in At that time, the graph structure modeling module 110 will select elements Assign a value of 1; when the edge set There are no edges in At that time, the graph structure modeling module 110 will select elements Assign a value of 0. Adjacency matrix The mathematical expression that constitutes the circuit topology.

[0046] The graph structure modeling module 110 constructs a node feature matrix based on component attributes. Node feature matrix It is a dimension of A real matrix. Where, The dimension of the node feature vector. Node feature matrix. The first in row vector Corresponding graph nodes The graph structure modeling module 110 will define the graph nodes' attribute characteristics. The corresponding physical component's package code, pin count, and functional classification code combination are grouped into a row vector. For the graph nodes marked as to be predicted, the graph structure modeling module 110 assigns their corresponding row vectors... Replace with a preset mask vector to hide the actual model information of the graph node.

[0047] The masking mechanism provided by this invention is executed by the graph structure modeling module 110. The masking mechanism includes the following steps: The graph structure modeling module 110 determines the component prediction priority sequence based on the signal flow or energy flow direction of the circuit design. The graph structure modeling module 110 then selects components from the graph node set according to the component prediction priority sequence. Select one or more nodes that need to be predicted, and define the selected nodes as the target nodes to be predicted. .

[0048] The graph structure modeling module 110 in the node feature matrix The feature replacement operation is performed. The graph structure modeling module 110 locates the target node to be predicted. In the node feature matrix The corresponding feature row vector Feature row vectors The initial values ​​include the target nodes to be predicted. The original attribute information of the corresponding components. The graph structure modeling module 110 uses a preset mask to embed vectors. Replace feature row vector .

[0049] Mask embedding vector It is a dimension of The numerical vector. In this embodiment, the mask embedding vector. Set as an all-zero vector. In another embodiment, the mask embedding vector... The vector is set to a special label vector containing trainable parameters. By performing a replacement operation, the graph structure modeling module 110 modifies the node feature matrix. Remove the target node to be predicted The original attribute information is retained in the graph structure data, so that only the target nodes to be predicted are preserved. The location information and attribute information of surrounding neighboring nodes.

[0050] The graph structure modeling module 110 maintains the adjacency matrix when performing feature replacement operations. The value remains unchanged. The graph structure modeling module 110 retains the target nodes to be predicted. Connection edges between the circuit and other nodes Preserve the adjacency matrix The invariance ensures the target node to be predicted Connectivity in a graph topology enables the target node to be predicted. It can act as a node in the message passing process of a graph neural network, receiving feature information from neighboring nodes.

[0051] The graph structure modeling module 110 supports region masking. When a specific functional circuit module consisting of multiple components exists in the circuit, the graph structure modeling module 110 simultaneously defines all components within the specific functional circuit module as the set of target nodes to be predicted. The graph structure modeling module 110 uses the node feature matrix... All feature row vectors corresponding to the set of target nodes to be predicted are simultaneously replaced with mask embedding vectors. .

[0052] The graph structure modeling module 110 outputs the processed node feature matrix. and the original adjacency matrix This serves as the mask image structure data. The mask image structure data is transmitted to the dual-channel image feature encoding module 120 to trigger the prediction calculation of component categories.

[0053] The dual-channel graph feature encoding process provided by this invention is executed by the dual-channel graph feature encoding module 120. The dual-channel graph feature encoding module 120 receives mask graph structure data as input. The mask graph structure data includes an adjacency matrix. and the masked node feature matrix The dual-channel image feature encoding module 120 is based on mask image structure data and operates the first and second processing channels in parallel.

[0054] The first processing channel is configured as a topology extraction channel. The first processing channel receives the adjacency matrix. and node feature matrix The first processing channel employs a Graph Convolutional Neural Network (GCN) algorithm. The first processing channel utilizes an adjacency matrix. The defined connection relationships are used to perform message passing operations on the graph structure. Message passing operations include aggregating the feature vectors of each graph node's neighboring nodes and transforming and fusing the aggregated feature vector with the node's own feature vector. The first processing channel generates a topology feature matrix through iterative operations across multiple graph convolutional layers. The first processing channel then extracts the target node to be predicted from the topology feature matrix. The corresponding vector is defined as the topological feature vector. Topological feature vectors Characterize the target node to be predicted Connection topology information in the circuit.

[0055] The second processing channel is configured as a component information extraction channel. The second processing channel receives the node feature matrix. The second processing channel employs a multilayer perceptron (MLP) algorithm. The second processing channel processes the node feature matrix... Each row vector in the algorithm undergoes an independent nonlinear feature transformation, without involving the aggregation of information from neighboring nodes. The second processing channel outputs an attribute feature matrix. The second processing channel extracts the target node to be predicted from the attribute feature matrix. The corresponding vector is defined as the attribute feature vector. Attribute feature vector Characterize the target node to be predicted The node-independent attribute characteristics.

[0056] The dual-channel graph feature encoding module 120 utilizes the feature fusion unit to process the topological feature vector. and attribute feature vector The feature fusion unit performs a concatenation operation, combining the topological feature vectors. With attribute feature vector Connect along the feature dimension to generate node embedding vectors. Node embedding vector It integrates circuit topology semantics and node attribute semantics.

[0057] The dual-channel image feature encoding module 120 utilizes the classification prediction unit to embed the node vectors. Decoding is then performed. The classification prediction unit contains a fully connected layer and a softmax function. The classification prediction unit embeds node vectors. This is a probability distribution mapped to the functional categories of components. Each value in the probability distribution represents the target node to be predicted. The possibility of belonging to a certain preset component function category.

[0058] The dual-channel image feature encoding module 120 determines the target node to be predicted based on the probability distribution. The predicted function category labels are provided. Preset component function categories include resistors, capacitors, inductors, diodes, switches, and integrated circuits. The dual-channel graph feature encoding module 120 outputs the predicted function category labels.

[0059] The message passing and aggregation mechanism provided by this invention is executed by the first processing channel in the dual-channel graph feature encoding module 120. The first processing channel performs feature propagation on graph structure data based on the computational logic of a graph convolutional neural network. The first processing channel receives graph structure data, which includes an adjacency matrix. and node feature matrix The first processing channel contains multiple graph convolutional layers stacked together.

[0060] The first processing channel performs node state update operations in each graph convolutional layer. For any current node in the graph structure... The first processing channel is based on the adjacency matrix. Determine the current node The set of neighboring nodes Neighbor node set Includes the current node There are directly connected edges. All nodes.

[0061] The first processing channel performs feature aggregation and linear transformation. The first processing channel obtains the current node. and the set of neighboring nodes Each node in the current layer eigenvectors The first processing channel uses a preset aggregation function to process the current node. and neighbor node set The eigenvectors are weighted and summed. The first processing channel utilizes a learnable weight matrix. A linear mapping is applied to the weighted summation result. The first processing channel inputs the linearly mapped result into the nonlinear activation function. .

[0062] The first processing channel calculates the current node according to the following formula. On the next floor Update feature vector :

[0063] in, Represents a node In the The feature vector of the layer; Indicates the first Layer weight matrix; Represents the normalized coefficient. Based on adjacency matrix Calculated; Indicates that it includes the current node. Its own neighborhood set; This represents the modified linear unit (ReLU) activation function.

[0064] The first processing channel expands the current node through iterative operations of multiple graph convolutional layers. The feature extraction range. The first processing channel defines the updated feature vector output from the last graph convolutional layer as the topological structure feature vector. Topological feature vectors Represents the current node Local connection mode and global topology location information The classification prediction unit provided by this invention is located in the dual-channel image feature encoding module 120. The classification prediction unit is configured to embed node vectors... Decode the data to generate the target node to be predicted. The component category prediction results.

[0065] The classification prediction unit receives the node embedding vectors output by the feature fusion unit. The classification prediction unit is configured with a linear classification layer. The linear classification layer contains a weight matrix. and bias vector The classification prediction unit embeds nodes into vectors. The input is fed into a linear classification layer. The linear classification layer processes the node embedding vectors. Perform a linear transformation operation to embed the nodes into a vector. Mapped to dimension The output vector of . Where, This indicates the total number of preset component function categories.

[0066] The classification prediction unit is equipped with a Softmax normalization function. The unit uses this function to process the output vector and calculate the target node to be predicted. The probability of belonging to each component's functional category. The classification prediction unit generates the predicted probability distribution vector according to the following formula. :

[0067] in, For dimension is The vector, Each element in the array represents the predicted probability value for the corresponding category; Embed vectors for nodes; This is the weight matrix of the linear classification layer; This is the bias vector for the linear classification layer.

[0068] The classification prediction unit performs the category determination operation. The classification prediction unit traverses the prediction probability distribution vector. Determine the predicted probability distribution vector The index corresponding to the element with the largest value in the middle. The classification prediction unit determines the component function category corresponding to the index as the target node to be predicted. Predicted category labels.

[0069] The dual-channel image feature encoding module 120 is equipped with a loss calculation unit during the training phase. The loss calculation unit is used to calculate the model prediction error and guide parameter updates. The loss calculation unit receives the prediction probability distribution vector. and the true class label vector of the target node to be predicted Real category label vector It is a one-hot encoding format.

[0070] The loss calculation unit uses the cross-entropy loss function to calculate the classification loss value. Classification loss value The calculation formula is as follows:

[0071] in, This indicates the total number of component functional categories; Represents the true category label vector The Middle The value of each element; Represents the predicted probability distribution vector The Middle The value of each element. The dual-channel image feature encoding module 120 utilizes the classification loss value. Calculate the gradient and use the backpropagation algorithm to update the trainable parameters in the first processing channel, the second processing channel, and the linear classification layer.

[0072] The training objective calculation and parameter optimization process provided by this invention is executed by the dual-channel image feature encoding module 120. During the training phase, the dual-channel image feature encoding module 120 uses the loss calculation unit to calculate the model prediction error and update the model parameters.

[0073] The dual-channel graph feature encoding module 120 acquires the training dataset. The training dataset contains graph structure data of multiple completed power electronic circuit schematics. The dual-channel graph feature encoding module 120 determines the target node to be predicted for the current training batch from the training dataset. The dual-channel graph feature encoding module 120 extracts the true component category labels for the target node to be predicted. The true component category labels are defined as vectors. .vector One-hot encoding format is used, with dimensions of .in, This indicates the total number of preset component function categories. (In the vector...) In the code, elements corresponding to the actual functional category are assigned a value of 1, while the rest are assigned a value of 0.

[0074] The dual-channel image feature encoding module 120 obtains the predicted probability distribution vector output by the classification prediction unit. Predicted probability distribution vector The dimension is Predicted probability distribution vector The element values ​​in the table represent the predicted probability that the target node to be predicted belongs to the corresponding component functional category.

[0075] The dual-channel image feature encoding module 120 constructs the training target using the cross-entropy loss function. The dual-channel image feature encoding module 120 calculates the total classification loss value for all target nodes to be predicted in the current training batch. Total classification loss value The calculation formula is as follows:

[0076] in, This indicates the total number of target nodes to be predicted in the current training batch; Indicates the first The real component category label vector of the target node to be predicted The Middle The value of each element; Indicates the first The prediction probability distribution vector of each target node to be predicted The Middle The value of each element.

[0077] The dual-channel image feature encoding module 120 is based on the total classification loss value. Perform backpropagation. The dual-channel image feature encoding module 120 calculates the total classification loss. The gradient is relative to the trainable parameters in the dual-channel image feature encoding module 120. The trainable parameters include the weight matrix of the image convolutional layer in the first processing channel, the weight matrix of the multilayer perceptron in the second processing channel, and the weight matrix of the linear classification layer in the classification prediction unit. The dual-channel image feature encoding module 120 updates the trainable parameters using the gradient descent algorithm and the calculated gradient to minimize the total classification loss. .

[0078] The prompt word construction process provided by this invention is executed by the semantic prompt construction module 130. The semantic prompt construction module 130 converts the numerical graph neural network output into textual sequence data to adapt to the input interface of large language models.

[0079] The semantic prompting construction module 130 receives the predicted function category label output by the dual-channel graph feature encoding module 120. Simultaneously, the semantic prompting construction module 130 obtains the target node to be predicted from the graph structure modeling module 110. The local topology data includes the target node to be predicted. The circuit netlist includes identifiers of directly connected neighboring components, pin connection network identifiers, and overall circuit design parameters. Design parameters include input voltage values, output voltage values, and rated power values.

[0080] The semantic prompting construction module 130 performs data format conversion. The semantic prompting construction module 130 stores a preset category mapping table and a topology description template. Using the category mapping table, the semantic prompting construction module 130 maps the prediction function category labels in numerical encoding format to component category names in natural language format. The semantic prompting construction module 130 uses the topology description template to convert local topology data into circuit connection relationship text. The topology description template is configured as a sentence structure of "component pin-network". For example, when local topology data indicates the target node to be predicted... When the first pin is connected to the input power network, the semantic hint building module 130 generates circuit connection relationship text that characterizes the connection relationship.

[0081] The semantic prompting construction module 130 constructs an input prompt word sequence. The input prompt word sequence is composed of four text fragments concatenated in a preset order: task definition fragment, circuit state fragment, design constraint fragment, and example reference fragment.

[0082] The semantic prompting construction module 130 generates a task definition fragment. This task definition fragment contains natural language instructions to guide the large language model in performing inference. The task definition fragment explicitly requires the large language model to infer the target node to be predicted based on the input circuit information. The specific manufacturing model.

[0083] The semantic prompting construction module 130 generates circuit state fragments. The semantic prompting construction module 130 fills the circuit state fragments with component category names and circuit connection relationship text, reconstructing the target node to be predicted in text form. The local circuit environment.

[0084] Semantic suggestion building module 130 generates design constraint fragments. Semantic suggestion building module 130 extracts circuit design parameters and converts them into numerical constraint condition text. The design constraint fragments are used to limit the electrical stress range of component selection.

[0085] Semantic hint building module 130 generates example reference fragments. Semantic hint building module 130 retrieves a pre-stored few-sample example library. The few-sample example library contains multiple sets of text pairs of "circuit description-reasoning process-correct model". Semantic hint building module 130 selects few-sample examples that match the predicted function category label and populates the example reference fragment with these few-sample examples.

[0086] The semantic prompting construction module 130 generates output format instructions. The output format instructions require that the output of the large language model must include inference step fields and result fields. The semantic prompting construction module 130 combines the task definition fragment, circuit state fragment, design constraint fragment, example reference fragment, and output format instructions into an input prompt word sequence, and sends the input prompt word sequence to the large language model inference module 140.

[0087] The thought chain reasoning process provided by this invention is executed by the large language model reasoning module 140. The large language model reasoning module 140 uses the thought chain strategy to generate the target node to be predicted. The component model number. The thought chain strategy requires the large language model inference module 140 to generate text data containing the logical derivation process before outputting the prediction conclusion.

[0088] The large language model inference module 140 receives the input prompt word sequence transmitted by the semantic prompt construction module 130. The large language model inference module 140 performs text generation processing based on the input prompt word sequence. The large language model inference module 140 first generates intermediate inference text fragments. The content of the intermediate inference text fragments includes numerical analysis of the circuit constraints in the input prompt word sequence, and matching analysis of the electrical characteristics of candidate components.

[0089] The large language model inference module 140 performs electrical parameter verification during the generation of intermediate inference text fragments. Based on the local topological connectivity and voltage / current parameters in the input prompt word sequence, the large language model inference module 140 calculates the target node to be predicted. The minimum electrical specification requirements are determined. The large language model reasoning module 140 compares the minimum electrical specification requirements with the parameterized general knowledge stored internally in the large language model. The large language model reasoning module 140 records the comparison process as reasoning steps in natural language form and includes them in the intermediate reasoning text fragments.

[0090] After generating intermediate inference text fragments, the large language model inference module 140 generates a final model text fragment. The final model text fragment contains the specific component manufacturer's model number. The large language model inference module 140 uses the intermediate inference text fragments as the context for generation, calculates the output probability of the final model text fragment, and generates the final model text fragment.

[0091] The large language model inference module 140 performs inference optimization based on prompt word instructions. Inference optimization limits the length of generated intermediate inference text fragments to improve inference efficiency. Based on the output format instructions in the input prompt word sequence, the large language model inference module 140 generates only summary-level inference text containing key decision evidence. Key decision evidence includes conclusions from voltage stress analysis, current capacity demand analysis, and frequency response analysis. The large language model inference module 140 filters out generic descriptive text irrelevant to the key decision evidence.

[0092] The large language model inference module 140 parses the generated complete text sequence. It locates the final model text fragment based on preset format identifiers. The module then extracts the component model string from this text fragment. Finally, it defines the component model string as the target node to be predicted. The prediction results are obtained and transmitted to the iterative update control module 150.

[0093] The inference pruning strategy provided by this invention is executed by the large language model inference module 140. The inference pruning strategy is used to filter and compress the intermediate text generated by the large language model.

[0094] The Large Language Model Inference Module 140 generates initial inference text based on the input prompt word sequence. This initial inference text contains a complete record of the Large Language Model's thought chain inference process. The content of the initial inference text covers circuit parameter analysis, candidate component comparison, electrical stress calculation, and statements of general circuit knowledge.

[0095] The large language model reasoning module 140 performs keyword retrieval on the initial reasoning text. The large language model reasoning module 140 internally stores a preset list of electrical parameter keywords. This list includes "voltage," "current," "power," "frequency," "package," and "withstand voltage." The large language model reasoning module 140 traverses the initial reasoning text, identifying statements containing electrical parameter keywords. The large language model reasoning module 140 marks these statements as key reasoning statements.

[0096] The large language model inference module 140 performs text filtering operations. The large language model inference module 140 removes text fragments from the initial inference text that are not marked as key inference statements. The large language model inference module 140 removes general descriptive statements from the initial inference text that do not contain specific numerical calculations or parameter comparisons.

[0097] The large language model inference module 140 reconstructs a simplified inference text based on the retained key inference statements. The simplified inference text only contains statements related to the target node to be predicted. The selection of components is directly related to the electrical basis.

[0098] The large language model inference module 140 outputs a simplified inference text and the final component model number. Compared to outputting the complete initial inference text, outputting a simplified inference text reduces the amount of data transmission within the collaborative system 100. The large language model inference module 140 utilizes inference pruning strategies to improve the execution efficiency of the component prediction process while preserving the interpretability of component selection.

[0099] The chain-style mask completion process provided by this invention is led by the iterative update control module 150 and executed in conjunction with the graph structure modeling module 110, the dual-channel graph feature encoding module 120, the semantic prompt construction module 130, and the large language model inference module 140. The chain-style mask completion process is used to determine the specific model of each component to be designed in the circuit netlist one by one according to the preset topology order.

[0100] The iterative update control module 150 generates a component prediction sequence. It analyzes the signal or energy flow direction in the circuit netlist. Based on the signal or energy flow direction, the iterative update control module 150 sorts all components to be designed in the circuit netlist, forming a component prediction sequence. For example, in a Buck converter circuit, the order is input capacitor, power switch, filter inductor, and output capacitor. Initially, none of the components in the component prediction sequence are assigned a specific model. The iterative update control module 150 selects the first component in the component prediction sequence as the current target node to be predicted.

[0101] The graph structure modeling module 110 constructs graph structure data based on the current circuit netlist. For the target node to be predicted, the graph structure modeling module 110 performs masking processing. The graph structure modeling module 110 then converts the node feature matrix... The feature vector corresponding to the current target node to be predicted is replaced with a mask embedding vector. At this time, for other components in the component prediction sequence that are ranked after the current target node to be predicted, the graph structure modeling module 110 also keeps their corresponding feature vectors in a masked state or a state of all zeros.

[0102] The dual-channel graph feature encoding module 120, the semantic prompt construction module 130, and the large language model reasoning module 140 sequentially perform calculations on the current target node to be predicted. The collaborative system 100 generates the specific component model of the current target node to be predicted through dual-channel feature encoding, prompt word construction, and thought chain reasoning steps.

[0103] The iterative update control module 150 obtains the specific component model and performs a netlist update operation. The iterative update control module 150 writes the specific component model into the attribute field corresponding to the current target node to be predicted in the circuit netlist. The netlist update operation changes the state of the current target node to be predicted from a pending state to a determined state.

[0104] The iterative update control module 150 detects whether there are still undetermined components in the component prediction sequence. If so, the iterative update control module 150 selects the next component in the component prediction sequence as the new current target node to be predicted and triggers the next prediction cycle.

[0105] In the next prediction cycle, the graph structure modeling module 110 reads the updated circuit netlist and regenerates the graph structure data. In the regenerated graph structure data, the nodes that have already been predicted in the previous cycle are represented in the node feature matrix. The vector in the image corresponds to a feature vector containing real physical attributes, rather than a mask embedding vector. When performing graph convolution operations, the dual-channel graph feature encoding module 120 uses the real physical attributes of previously predicted nodes to aggregate features for the new target node to be predicted.

[0106] The collaborative system 100 repeats the above prediction, update, and reconstruction steps until all components in the component prediction sequence have been assigned specific component models. The chained mask completion process ensures that the selection of subsequent components in the circuit can be matched based on the parameters of the previously determined components. The graph neural network and large language model collaborative system 100 provided by this invention executes an automatic design process using a multi-channel Buck buck converter circuit as input. The design parameters of the multi-channel Buck buck converter circuit include: an input DC voltage of 17V, three output voltages of 3.3V, 1.8V, and 1.1V respectively, and a load current capacity range of 0.5A to 1A. The multi-channel Buck buck converter circuit uses the TPS6216x series chip as the core control device.

[0107] The iterative update control module 150 parses the circuit netlist of the multi-channel Buck buck converter circuit and generates a component prediction sequence. Taking the 3.3V output voltage branch as an example, the iterative update control module 150 determines the order of the component prediction sequence based on the energy flow from the input port to the output port as follows: input filter capacitor, Buck buck controller chip, power inductor, output filter capacitor, and voltage divider feedback resistor. Before the prediction process begins, the specific model attributes of the above components in the circuit netlist are empty.

[0108] The collaborative system 100 executes the prediction process for the input filter capacitor. The graph structure modeling module 110 defines the input filter capacitor as the target node to be predicted and generates graph structure data containing a mask vector. The dual-channel graph feature encoding module 120 performs calculations on the graph structure data and outputs the functional category label of the target node to be predicted as "ceramic capacitor". The semantic prompt construction module 130 constructs an input prompt word sequence. The local topology information in the input prompt word sequence indicates that the target node to be predicted is connected to the "VIN_17V" network and the "GND" network. The large language model inference module 140 receives the input prompt word sequence and generates intermediate inference text. The content of the intermediate inference text is: "The input voltage is 17V. According to the voltage derating rule, the capacitor withstand voltage must be higher than 1.2 times the input voltage. A 25V withstand voltage rating is selected; to filter out high-frequency switching noise, a capacitance value of 10uF is selected." Based on the intermediate inference text, the large language model inference module 140 outputs the specific component model "CL31B106KAHNNNE". The iterative update control module 150 updates the specific component model "CL31B106KAHNNNE" to the circuit netlist.

[0109] The collaborative system 100 executes the prediction process for the Buck buck controller chip. The graph structure modeling module 110 regenerates the graph structure data based on the updated circuit netlist. At this point, the node feature vector corresponding to the input filter capacitor contains the attribute feature "10uF / 25V". The dual-channel graph feature encoding module 120 uses the attribute feature of the input filter capacitor to predict the functional category label of the target node to be predicted as "power management chip". The semantic prompt construction module 130 constructs an input prompt word sequence, which includes the design constraints of an input voltage of 17V and a target output voltage of 3.3V. The large language model inference module 140 generates intermediate inference text: "Input 17V, output 3.3V, consistent with high differential buck application scenario; based on design constraints and 1A output current requirement, match TPS62160DSG from the TPS6216x series". The large language model inference module 140 outputs the specific component model "TPS62160DSG". The iterative update control module 150 updates the specific component model "TPS62160DSG" to the circuit netlist.

[0110] The collaborative system 100 executes the prediction process for the power inductor. The graph structure modeling module 110 regenerates the graph structure data. The semantic prompting construction module 130 extracts the switching frequency parameter, which is 2.25MHz, from the properties of the determined Buck buck controller chip "TPS62160DSG". The large language model inference module 140 calculates the inductance value based on the switching frequency parameter and the load current, generating intermediate inference text: "At a switching frequency of 2.25MHz, to control the ripple current, the recommended inductance value is 2.2uH, and the inductor saturation current must be greater than 1A". The large language model inference module 140 outputs the specific component model "VLF302512MT-2R2M".

[0111] The collaborative system 100 executes a prediction process for the voltage divider feedback resistors. The large language model inference module 140 obtains the internal reference voltage of 0.8V and the target output voltage of 3.3V for the TPS62160DSG. The large language model inference module 140 calculates the voltage divider resistor ratio and selects a matching resistor combination from a standard resistor value sequence. After completing the model filling for all components, the iterative update control module 150 outputs a complete schematic diagram of the multi-channel Buck buck converter circuit.

[0112] Furthermore, in this invention, since power electronic schematics themselves have a graphical structure, by modeling the components in the schematic as graphical nodes, the task of automated schematic design can be represented as a graph node classification problem. This constitutes a self-supervised learning task, where unknown components are predicted based on the known types of components and the connections between them. For example, a CLLC converter can be represented in a graph-based form, where each component is treated as a node. This graphical representation enables the application of graph neural networks (GNNs) to facilitate the design process.

[0113] However, graph neural networks (GNNs) can suffer from oversmoothing during computation. Oversmoothing refers to the phenomenon where, after several layers of message passing, node embeddings lose their discriminative ability, making it difficult for the model to distinguish between different types of nodes. This severely limits the predictive performance of traditional GNNs in tasks involving highly imbalanced component distributions, as is commonly seen in power electronics schematics. Furthermore, simple GNNs cannot directly generate the specific model number of the device to be predicted; therefore, the fundamental capabilities of large language models are still needed to achieve specific component selection.

[0114] To address the challenges of overfitting in graph neural networks and the limitations of large language models in directly processing graph-structured data, this invention proposes the PE-GLC Agent. This agent leverages the graph-structured data modeling capabilities of GNNs to capture feature representations of target nodes and their neighboring nodes, thereby inferring the component types of the target nodes. Building upon this, it utilizes the powerful expressive capabilities of LLMs and combines CoT (Co-Order) reasoning to derive accurate component models for the target nodes. The overall architecture and workflow of PE-GLC Agent are as follows: Figure 2 As shown.

[0115] In this agent, the input consists of an adjacency matrix derived from the schematic netlist (converted to a graphical representation) and corresponding node-level component information. To further support practical schematic design, a large-scale language model for backend inference is introduced. While the GNN captures structure- and feature-based patterns, the large language model performs semantic induction in the natural language space based on predicted component types and topological information. Utilizing common-sense knowledge from a large-scale corpus, combinatorial reasoning is performed to provide more reliable classifications and interpretable explanations under complex or fuzzy decision boundaries. By integrating these two stages, the information efficiency of the graph representation is preserved, while additional reasoning capabilities and interpretability provided by the language model are gained.

[0116] For each target node, the predicted component type is first obtained from the GNN, and the corresponding topological information is extracted from the netlist. These numerical and symbolic descriptors are then converted into a natural language summary using a predefined template. The summary, task description, output format constraints, and a small set of examples are provided to DeepSeek as input hints. In this way, target inference is performed in the language space, generating structured results. To improve the reliability of the parsing, DeepSeek's output needs to follow a fixed and compact format, containing the predicted component model, along with optional confidence descriptions and brief principles to facilitate relevant parsing and evaluation.

[0117] To encourage verifiable reasoning before generating the final classification, a thought chain cues strategy was employed, such as... Figure 3 As shown in the diagram, a few examples are presented to demonstrate step-by-step reasoning, and the model is instructed to list the reasoning points before providing a conclusion. Experimental results show that using thought chains significantly improves discriminative accuracy and interpretability in cases of scattered or semantically ambiguous evidence. However, thought chains have also been observed to increase token overhead and reasoning latency, and in some cases, introduce false or irrelevant reasoning (illusions). To address these limitations, a compromise design is adopted: during the production of reasoning, only simplified reasons (two to three key pieces of evidence) are retained, while full thought chain reasoning is only used for low-confidence predictions, which are subsequently manually reviewed.

[0118] To automate the design of power electronics schematics, this invention proposes a hierarchical intelligent agent and its construction scheme. This agent integrates a dual-channel graph learning model with a large-scale language model. This framework fully leverages the data modeling capabilities of graph neural networks for graph-structured data, as well as the powerful reasoning and expressive capabilities of large-scale language models, thereby predicting specific component models based on design objectives.

[0119] To fully verify the effectiveness of the proposed intelligent agent, this invention conducted an evaluation at two levels. At the qualitative level, a case study of a three-input / output Buck converter visually demonstrated the agent's reasoning ability and adaptability under practical power electronic topologies and diverse operating conditions.

[0120] To more intuitively demonstrate the working principle of this intelligent agent, this invention selects a reference design schematic from Texas Instruments (TI) as a case study object. For example... Figure 4 As shown, the selected schematic is actually a multi-channel Buck power supply circuit with an input voltage of 17V. It can output 3.3V, 1.8V, and 1.1V digital logic power, with a current capacity of approximately 0.5-1A, suitable for the power supply needs of digital systems such as FPGAs, DSPs, and MCUs. This circuit uses the TI TPS6216x series buck converter chip as the core component, employs a standard LC filter design and a well-designed power indicator circuit, and follows standardized design methods.

[0121] To closely resemble the actual circuit schematic drawing process, this invention first masks the core component TPS6216 and its peripheral components (such as filter capacitors and pull-up resistors) in the 3.3V output circuit to simulate the incomplete state during circuit schematic drawing. Subsequently, when completing the schematic, the workflow is set to a "chain-like working mode"—that is, specific components are configured sequentially, with the selection of each subsequent component based on the results of the preceding steps. Although this mode may introduce error accumulation, it is crucial for simulating the actual design process.

[0122] In practical implementation, this invention predicts components step-by-step based on the energy flow from input to output: First, starting with the filter capacitor at the input end (mask position MASK1), the circuit schematic after masking is converted into a netlist file and bill of materials format, and a graph structure storage file is constructed; the graph learning module generates the predicted type of circuit components at MASK1; then, the predicted component types and circuit netlist are input into the large language model module to infer the specific component models. After completing MASK1, the subsequent completion processes of MASK2 and MASK3 are executed, and the entire process is as follows: Figure 5 As shown.

[0123] By comparing the output values ​​of the large language model with the original component specifications, it is evident that this agent can effectively complete the component prediction task: except for a difference between the predicted capacitor model at MASK1 and the original model, the results generated by the large language model are highly consistent with the original component specifications. It should be noted that using a higher capacitance value capacitor at this location can still achieve comparable or even better filtering performance. This invention demonstrates that the proposed agent can accurately predict the specific component models in engineering schematics, thereby effectively assisting and enhancing the circuit design process.

[0124] At the quantitative level, the proposed agent was subjected to extensive comparative experiments with several representative GNN baseline models to rigorously evaluate the performance differences. As shown in Table 1, the experimental results show that the TOP-5 accuracy of the proposed method can be improved by up to 28.5% compared with the baseline method, which fully demonstrates its excellent accuracy and robustness.

[0125] Table 1

[0126] The graph neural network and large language model collaborative system 100 for automatic design of power electronics schematics provided by this invention can be implemented on an electronic device 600. The electronic device 600 includes a processor 601, a memory 602, a communication interface 603, and a bus 604.

[0127] The processor 601, memory 602, and communication interface 603 are connected via bus 604 to enable communication between them. Bus 604 includes an address bus, a data bus, and a control bus.

[0128] Processor 601 is configured to execute computer program instructions. Processor 601 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices. Given that this invention relates to graph neural network operations and large language model inference, in one embodiment, processor 601 includes a graphics processing unit (GPU), a tensor processor (TPU), or a neural network processor (NPU) to provide parallel computing capabilities.

[0129] The memory 602 is used to store computer programs and data. The memory 602 includes volatile memory, such as random access memory (RAM); the memory 602 also includes non-volatile memory, such as read-only memory (ROM), flash memory, hard disk (HDD), or solid-state drive (SSD).

[0130] The memory 602 stores the functional modules of the graph neural network and large language model collaborative system 100. These functional modules include: a graph structure modeling module 110, a dual-channel graph feature encoding module 120, a semantic prompting construction module 130, a large language model inference module 140, and an iterative update control module 150. The processor 601 executes the automatic schematic design method for power electronics described in this embodiment of the invention by calling the functional modules stored in the memory 602.

[0131] The memory 602 stores data generated during the operation of the graph neural network and large language model collaborative system 100. This data includes: the netlist file of the circuit to be designed, and graph structure data (including the adjacency matrix). and node feature matrix The input includes a sequence of prompt words, a thought chain reasoning text, a component prediction sequence, and a completed circuit schematic file.

[0132] Communication interface 603 is used by electronic device 600 to interact with other external devices or communication networks. Communication interface 603 includes a wired communication interface or a wireless communication interface. Wired communication interfaces include Ethernet interfaces or Universal Serial Bus (USB) interfaces. Wireless communication interfaces include Wireless Local Area Network (WIFI) interfaces or cellular mobile communication interfaces. Electronic device 600 receives initial circuit netlist input by the user through communication interface 603 and outputs the final designed circuit schematic through communication interface 603.

[0133] The processor 601 executes the following steps by running a computer program in memory 602: parsing the circuit netlist to construct graph structure data; masking the graph structure data; extracting node features using a dual-channel graph neural network; constructing cue words containing circuit semantics; generating component models using a large language model; and updating the circuit netlist based on the generated component models.

[0134] This invention provides a computer-readable storage medium. The computer-readable storage medium stores computer program instructions. When executed by a processor 601, the computer program instructions cause the processor 601 to perform the automatic schematic design method for power electronics described in this embodiment of the invention.

[0135] Computer-readable storage media can be either non-volatile or volatile. Specific forms of computer-readable storage media include random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD).

[0136] The computer program instructions include a sequence of instructions for performing circuit netlist parsing and graph structure construction. When processor 601 executes the instruction sequence, it maps the netlist file of the power electronic circuit into graph structure data. The graph structure data consists of a set of nodes. Edge set Adjacency matrix and node feature matrix Composition. The processor 601 determines the current target node to be predicted based on a preset component prediction sequence. Processor 601 pairs node feature matrices The middle corresponds to the current target node to be predicted. The row vectors are subjected to mask replacement.

[0137] The computer program instructions include a sequence of instructions for performing dual-channel graph feature encoding. When the processor 601 executes the instruction sequence, it simultaneously starts the first processing channel and the second processing channel. The processor 601 utilizes the graph convolutional neural network in the first processing channel to extract the circuit topology feature vector. The processor 601 uses the multilayer perceptron in the second processing channel to extract node attribute feature vectors. Processor 601 will process the topological feature vector. With attribute feature vector By splicing and merging, node embedding vectors are generated. .

[0138] The computer program instructions include a sequence of instructions for performing semantic cue construction and thought chain reasoning. When the processor 601 executes the instruction sequence, it embeds the node vectors. The corresponding prediction function category labels and local topological connections are converted into a sequence of input prompt words in natural language format. The processor 601 calls the large language model to process the input prompt word sequence, generating intermediate reasoning text containing the logical deduction process and the final component model number.

[0139] The computer program instructions include a sequence of instructions for performing iterative updates. When the processor 601 executes the instruction sequence, it writes the component models into the circuit netlist. The processor 601 determines whether there are any unpredicted components in the component prediction sequence. If so, the processor 601 triggers a regeneration operation of the graph structure data and uses the updated circuit netlist information to predict the next target node to be predicted, until the component prediction sequence has been traversed.

[0140] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A GNN and LLM collaborative system for automatic design of power electronic schematics, characterized in that, include: The iterative update control module is configured to generate a component prediction sequence based on the signal flow or energy flow of the power electronic circuit, and to determine the target node to be predicted at the current moment from the component prediction sequence. The graph structure modeling module is configured to map the netlist file of the power electronic circuit into graph structure data, which includes an adjacency matrix and a node feature matrix. The feature vectors corresponding to the target node to be predicted in the node feature matrix are replaced with mask embedding vectors to generate mask graph structure data. The dual-channel graph feature encoding module is configured to extract node embedding vectors based on the mask graph structure data using a dual-channel architecture, and generate the prediction function category label of the target node to be predicted based on the node embedding vectors. The semantic prompting construction module is configured to construct a sequence of input prompt words in natural language format based on the local topological information of the target node to be predicted and the prediction function category label, using a preset text mapping template. The large language model inference module is configured to input the input prompt word sequence into the large language model and generate the specific component model of the target node to be predicted through thought chain inference; the iterative update control module is further configured to update the specific component model to the netlist file and trigger the prediction process for the next target node to be predicted in the component prediction sequence.

2. The GNN and LLM collaborative system for automatic design of power electronics schematics according to claim 1, characterized in that, When constructing the graph structure data, the graph structure modeling module is specifically configured to perform the following operations: A node set containing multiple graph nodes is constructed, where each graph node uniquely corresponds to a physical component in the netlist file; a set of connecting edges is constructed, and when the physical components corresponding to two graph nodes are connected to the same electrical network identifier in the netlist file, an undirected edge is established between the two graph nodes; the adjacency matrix is ​​generated based on the set of connecting edges, and the node feature matrix is ​​constructed based on the package code, pin count, and functional classification code of the physical component; When generating the mask graph structure data, the graph structure modeling module keeps the value of the adjacency matrix unchanged and only replaces the row vectors in the node feature matrix that correspond to the target node to be predicted.

3. The GNN and LLM collaborative system for automatic design of power electronics schematics according to claim 1, characterized in that, The dual-channel image feature encoding module includes a first processing channel, a second processing channel, and a feature fusion unit; The first processing channel is configured to process the adjacency matrix and the node feature matrix using a graph convolutional neural network algorithm, and aggregate the features of neighboring nodes through a message passing mechanism to generate a topological feature vector representing the connection topology information. The second processing channel is configured to independently process the node feature matrix using a multilayer perceptron algorithm to generate an attribute feature vector representing the independent attribute information of the node; the feature fusion unit is configured to concatenate the topology feature vector and the attribute feature vector along the feature dimension to generate the node embedding vector.

4. The GNN and LLM collaborative system for automatic design of power electronics schematics according to claim 3, characterized in that, When the first processing channel executes the message passing mechanism, it is specifically configured to: determine the set of neighboring nodes corresponding to the target node to be predicted in the adjacency matrix; perform linear mapping on the feature vector of each neighboring node in the set of neighboring nodes using a linear transformation weight matrix; perform weighted summation on the linearly mapped feature vector using an aggregation function to generate a neighborhood aggregation feature vector; fuse the neighborhood aggregation feature vector with the feature vector of the target node to be predicted itself, and generate an updated feature vector through a nonlinear activation function.

5. The GNN and LLM collaborative system for automatic design of power electronics schematics according to claim 3, characterized in that, The dual-channel graph feature encoding module further includes a classification prediction unit; the classification prediction unit is configured to perform a linear transformation operation on the node embedding vector, mapping the node embedding vector to an output vector with a dimension equal to the total number of preset component functional categories. The classification prediction unit is configured to process the output vector using a normalized exponential function to calculate the probability distribution of the target node to be predicted belonging to each preset component functional category. The classification prediction unit is configured to select the category corresponding to the element with the largest value in the probability distribution as the category label of the prediction function.

6. The GNN and LLM collaborative system for automatic design of power electronics schematics according to claim 1, characterized in that, When constructing the input prompt word sequence, the semantic prompt construction module is specifically configured to: generate a task definition fragment, which contains natural language instructions that guide the large language model to infer the specific component model. Generate a circuit state fragment, which includes component category names obtained by converting the predicted function category labels using a category mapping table, and circuit connection relationship text obtained by converting the local topology information using a topology description template. Generate a design constraint fragment, which includes text that converts the input voltage, output voltage, and rated power parameters of the power electronic circuit into numerical constraints; combine the task definition fragment, the circuit state fragment, and the design constraint fragment in a preset order to form the input prompt word sequence.

7. The GNN and LLM collaborative system for automatic design of power electronics schematics according to claim 1, characterized in that, When generating the specific component model, the large language model inference module adopts the following thought chain strategy: Based on the input prompt word sequence, an intermediate inference text fragment is generated. The intermediate inference text fragment includes a process for verifying the electrical parameters of the target node to be predicted. The electrical parameter verification process compares the calculated minimum electrical specification requirements with the parameterized general knowledge stored inside the large language model. Based on the intermediate inference text fragment as context, a final model text fragment containing the specific component model is generated. The large language model inference module extracts the component model string from the final model text fragment as the prediction result.

8. The GNN and LLM collaborative system for automatic design of power electronics schematics according to claim 7, characterized in that, The large language model inference module is also configured to perform inference pruning operations; the inference pruning operations include: retrieving the intermediate inference text fragments using a preset electrical keyword list, the electrical keyword list containing at least voltage, current and power keywords; identifying key inference statements containing the electrical keyword list, and filtering out general descriptive text in the intermediate inference text fragments that do not contain the key inference statements; and reorganizing the retained key inference statements to generate simplified inference text for the large language model to generate the final model text fragment.

9. The GNN and LLM collaborative system for automatic design of power electronics schematics according to claim 1, characterized in that, The iterative update control module is specifically configured to execute the following chained mask completion logic: The specific component model is entered into the netlist file, and the state of the target node to be predicted is updated from the pending state to the determined state; it is determined whether there are any components with undetermined models in the component prediction sequence; If it exists, the next component in the component prediction sequence is set as the new target node to be predicted; the graph structure modeling module is triggered to regenerate the graph structure data based on the updated netlist file, wherein the node that has been in a determined state in the previous sequence corresponds to a feature vector containing real physical attributes in the node feature matrix, and the real physical attributes are used to perform feature aggregation on the new target node to be predicted.

10. The GNN and LLM collaborative system for automatic design of power electronics schematics according to claim 1, characterized in that, The system also includes a loss calculation unit during the training phase; The loss calculation unit is configured to obtain the real component category label of the target node to be predicted in the current training batch, and the real component category label adopts a one-hot encoding format. The loss calculation unit is configured to use the cross-entropy loss function to calculate the total classification loss value between the probability distribution output by the dual-channel graph feature encoding module and the real component category label; The system is configured to update the weight parameters in the dual-channel graph feature encoding module using the backpropagation algorithm and the total classification loss value.

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