A path balance based post-mapping optimization method for RSFQ circuits
By constructing a Supergate library and an optimization method for mapping RSFQ circuits with node-level perturbations, the problem of inconsistent path depths in RSFQ circuits was solved, resulting in a reduction in circuit area and number of JJs, and improved design efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NINGBO UNIV
- Filing Date
- 2026-05-22
- Publication Date
- 2026-06-19
AI Technical Summary
The existing RSFQ circuit mapping has the problem of inconsistent path depth, which leads to the need to insert a large number of D flip-flops, increasing the circuit area and JJ overhead. Existing methods are difficult to effectively reduce the total number of nodes and JJs.
A path-balanced RSFQ circuit mapping post-optimization method is adopted. By constructing a Supergate library and performing P-class transformation, combined with node-level perturbation and retiming optimization, D flip-flops are inserted to achieve path balancing. Equivalent structures are matched in the Supergate library, and the circuit netlist is replaced to reduce the number of JJs.
It effectively reduces the total number of JJs and nodes in RSFQ circuits, improves design efficiency, reduces implementation costs, expands the optimization space, and improves circuit design efficiency.
Smart Images
Figure CN122242398A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of automated design technology for superconducting digital circuits, specifically to a post-mapping optimization method for RSFQ circuits based on path balancing. Background Technology
[0002] With the development of superconducting digital circuit technology, superconducting digital circuits based on Rapid Single-Flux Quantum (RSFQ) have significant application value in high-performance computing and superconducting electronic systems due to their ultra-high speed and low power consumption characteristics. Unlike traditional CMOS circuits, RSFQ circuit units are composed of Josephson junctions (JJs), and their logic units require clock triggering. During signal propagation, RSFQ circuits must strictly meet timing synchronization requirements. Therefore, path balancing (PB) processing is required during the logic synthesis stage to ensure that all input signals of the same logic gate arrive within the same clock cycle.
[0003] In practical design processes, logic netlists generated after process mapping using traditional logic synthesis tools often exhibit inconsistent path depths. To meet the timing constraints of RSFQ circuits, it is often necessary to insert a large number of D-flip-flops (DFFs) on shorter paths to achieve path balancing. However, the insertion of a large number of DFFs significantly increases the circuit area and introduces additional jig overhead, thereby affecting the overall circuit performance and implementation cost. Therefore, reducing the total number of nodes and jigs in the circuit while satisfying path balancing constraints has become one of the key issues in the logic synthesis and optimization of RSFQ circuits.
[0004] The core challenge in solving the above problems lies in how to balance the depth and area of the circuit while ensuring path balance and reducing the number of DFFs; and how to explore the optimization space of the circuit structure in order to find an equivalent structure with fewer total JJs. In addition, the mapped logic netlist structure is complex, and there are strong dependencies between nodes. When making local structural adjustments, it is easy to destroy the original path balance structure or introduce new timing inconsistencies.
[0005] To address the aforementioned issues, most existing path balancing methods directly balance the given mapped netlist or use algorithms to minimize the number of DFFs after path balancing. They lack the ability to further optimize the netlist structure and often fail to effectively explore the structural optimization space within the circuit, thus limiting further reductions in the total number of nodes and nodes (JJs). Specifically, existing methods have the following limitations: First, they cannot balance circuit depth and area: While path-balancing-based process mappers can generate more balanced circuit structures to reduce DFF insertion compared to traditional process mappers, they are insufficient in reducing circuit logic depth and node count. Second, the optimization space is limited: The mapped circuit structure is fixed, and once the algorithm reaches the optimal number of DFFs for the current circuit netlist, further optimization is impossible. Third, the path balancing framework is rigid and incomplete: Existing methods either directly map to a path-balanced circuit or only optimize the number of DFFs for the current mapped netlist, failing to form a progressive, dynamic, and comprehensive optimization framework.
[0006] Therefore, there is an urgent need for an efficient post-mapping optimization method for RSFQ circuits, which can further reduce the total number of nodes and the number of JJs in the circuit while ensuring path balance constraints, so as to improve the overall implementation efficiency of superconducting digital circuits. Summary of the Invention
[0007] The technical problem this invention aims to solve is to provide a path-balancing-based post-mapping optimization method for RSFQ circuits, addressing the shortcomings of existing technologies. Compared with traditional methods, this invention offers significant advantages in reducing the number of junction objects (JJs), minimizing DFF overhead, and improving the optimization space and efficiency of the mapped RSFQ circuit netlist. This provides an efficient and scalable technical solution for the automated design of superconducting digital circuits.
[0008] The technical solution adopted by this invention to solve the above-mentioned technical problems is: a post-mapping optimization method for RSFQ circuits based on path balancing, comprising the following steps: S1. Read the standard cell library file of the RSFQ circuit and the RSFQ circuit netlist after process mapping, parse the topological connection relationship of the nodes in the circuit netlist, and preset the number of iterations; S2. Based on the standard unit library, enumerate the logical unit combination to construct a candidate Supergate with the first constraint condition, calculate the truth table of the P class (Permutation-Class) of the candidate Supergate, classify and store it after P class transformation, and each P class truth table only stores the candidate Supergate with the fewest Josephson nodes to form a Supergate library. S3. Perform node-level perturbation on the circuit netlist, randomly assign logic levels while maintaining the topology order, and insert D flip-flops to achieve path balance. S4. Traverse the nodes in the circuit netlist in reverse topological order, extract the fanout-free cones (FFCs) that satisfy the second constraint, calculate their Boolean function truth table and perform P-type transformation, match the equivalent structure in the Supergate library, and if the number of Josephson nodes in the library is smaller, perform the inverse P-type transformation and replace it in the circuit netlist. S5. Perform Retiming optimization on the replaced circuit netlist with the goal of minimizing the number of D flip-flops. Depending on the preset number of iterations or the optimization effect, decide whether to delete the D flip-flops and return to S3 to continue the iteration, or output the final netlist.
[0009] The method of this invention optimizes the RSFQ circuit by combining path balancing, structural rewriting, and DFF minimization algorithms, effectively reducing the total number of JJs and nodes in the RSFQ circuit. Compared with traditional DFF optimization methods, this method can achieve better area while ensuring the path balance and logic depth of the RSFQ circuit remain unchanged. It has good scalability and optimization effect, and can be widely used in the post-mapping path balancing stage of the RSFQ circuit logic synthesis process, thereby reducing the implementation cost of the RSFQ circuit and improving the design efficiency of the RSFQ circuit.
[0010] Preferably, in step S1, the standard cell library contains the logic function information of various logic gates in the RSFQ circuit and the corresponding number of gates (JJs). The open-source logic synthesis tool ABC is used to read the process-mapped RSFQ circuit netlist. As a currently advanced mapper, ABC can obtain a process-mapped RSFQ circuit netlist with optimal area and depth. Based on this, by combining logic rewriting and hierarchical perturbation methods, the circuit structure is locally optimized, reducing the number of JJs while ensuring path balance constraints.
[0011] Preferably, the first constraint in step S2 includes: the number of inputs to the candidate Supergate does not exceed 6, the logic level does not exceed 3, and the path balance constraint is satisfied, that is, any input-to-output path of the candidate Supergate passes through the same number of logic units; wherein, D flip-flops participate in the construction of the candidate Supergate as basic units. Unlike traditional Supergates, in this invention, the first constraint limits the number of inputs to the candidate Supergate to no more than 6 and the logic level to no more than 3, to balance the coverage of structural matching and search efficiency; it also restricts each candidate Supergate to ensure path balance, to ensure the consistency of timing within the candidate Supergate; and D flip-flops also participate in the construction of the candidate Supergate as basic units, so that the Supergate library contains combinational structures with timing functions. The Supergate library constructed based on the above first constraint can match common substructures in the mapped netlist and ensure that the timing characteristics of the circuit before and after replacement remain unchanged, avoiding the trouble of needing to adjust the flip-flop positions after replacement.
[0012] Preferably, the P-class transformation in step S2 specifically involves: performing input variable substitution on the Boolean functions; forming a set of mutually reachable equivalent functions after the P-class transformation; taking the truth table of one function in this set as a unified representative, which is called the P-class truth table; and storing only the candidate Supergate with the fewest Josephson junction implementations in the Supergate library for each P-class truth table. The above P-class transformation, through input variable substitution, groups structures with the same logical function but different input arrangements into the same equivalence class, and stores only the candidate Supergate with the fewest Josephson junction implementations in the Supergate library for each equivalence class. This significantly reduces the storage size of the Supergate library and transforms the matching problem of fan-out free cones in the netlist into an equivalence class search problem, improving the matching efficiency during structure replacement.
[0013] Preferably, step S3 involves the following steps: traversing the nodes in the circuit netlist in topological order, calculating the maximum and minimum logical levels achievable by each node, and defining the interval formed by the maximum and minimum logical levels as the node's level perturbation range; without disrupting the circuit topology, randomly assigning values to the logical levels of each node within the level perturbation range in topological order, with restrictions placed on the level perturbation of nodes closer to the main input to reduce the probability of them perturbing to higher levels; after assigning levels to all nodes, inserting D flip-flops to achieve path balancing. By restricting the level perturbation of nodes closer to the main input, the probability of them being assigned higher levels is reduced, thus allowing subsequent nodes to retain perturbation space. This level perturbation strategy effectively breaks the fixed node level distribution in the original netlist structure, thereby improving the optimization space for subsequent structures.
[0014] Preferably, the second constraint in step S4 includes: the logical level of the fan-out free cone does not exceed 3, and the number of inputs does not exceed 6; the fan-out free cone is a logical substructure with the current node as the root node, and the fan-out of internal nodes is only used by this structure. The above-defined extraction conditions for the fan-out free cone are consistent with the construction conditions of the Supergate library, which helps to control the search space for each structure matching and improve optimization efficiency. At the same time, it ensures that the extracted fan-out free cone is comparable to the structure in the library in terms of scale and form, so that the replacement operation can be completed without destroying the circuit topology and path balance constraints. If the node satisfies the second constraint, its Boolean function truth table is calculated, and a P-type transformation is performed on the truth table. Subsequently, an equivalent structure with the same P-type truth table is searched in the constructed Supergate library, and the number of JJs of this structure is compared with that of the current FFC structure. When the number of JJs required by the structure in the Supergate library is less than the current FFC structure, a P-type inverse transform is performed on the structure to restore the original input arrangement, and the structure after the P-type inverse transform is used to replace the corresponding FFC in the circuit netlist, thereby achieving local structural optimization while ensuring path balance.
[0015] Preferably, in step S5, after performing Retiming optimization on the replaced circuit netlist with the goal of minimizing the number of D flip-flops, if the total number of Josephson nodes in the current netlist decreases compared to the previous iteration but has not reached the preset number of iterations, the D flip-flops in the current netlist are deleted and the process returns to step S3; otherwise, the current netlist is output as the final netlist. The above steps use the decrease in the total number of Josephson nodes as the criterion for continuing optimization, and combine this with the preset number of iterations to control the algorithm's runtime, thereby avoiding the waste of computational resources caused by unlimited iterations. Simultaneously, it automatically enters the next round of optimization when there is still room for optimization of the circuit area, ensuring that the method can obtain a better final netlist within an acceptable time cost.
[0016] Compared with existing technologies, this invention has the following advantages: The method of this invention achieves fast function-level matching by pre-constructing a constrained Supergate library and combining it with P-type transformations, thereby efficiently discovering logical substructures with optimization potential in the mapped netlist. During the structure replacement process, the local optimal implementation is selected by comparing the number of Logic Components (JJs), effectively reducing the implementation cost of the RSFQ circuit. Simultaneously, this invention introduces a node-level perturbation strategy, enabling the optimization process to explore more possible structural rewriting schemes while maintaining functional equivalence of the circuit. This provides more optimization space for subsequent retiming optimization to minimize the number of Logic Components (DFFs), further reducing the number of DFFs used for path balancing and the total number of JJs in the circuit. Compared with traditional methods, this invention has significant advantages in reducing the number of JJs, reducing DFF overhead, and improving the optimization space and efficiency of the mapped RSFQ circuit netlist, providing an efficient and scalable technical solution for the automated design of superconducting digital circuits. This invention can be widely applied to the post-mapped path balancing stage in the logic synthesis process of RSFQ circuits, thereby reducing the implementation cost of RSFQ circuits and improving the design efficiency of RSFQ circuits. Attached Figure Description
[0017] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is a combination of two connections based on the logic cell enumeration in the open-source RSFQ standard cell library Cold Flux. Detailed Implementation
[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0019] The circuits listed in Table 1 are used as test cases, including classic combinational logic circuits from the ISCAS, MCNC, and EPFL benchmark sets. Optimization is performed using the path-balanced RSFQ circuit mapping optimization method of this invention, such as... Figure 1 As shown, the optimization method includes the following steps: S1. Read the standard cell library file of the RSFQ circuit. This standard cell library contains the logic function information of various logic gates in the RSFQ circuit and the corresponding number of JJs. Use the open-source logic synthesis tool ABC to read the RSFQ circuit netlist after process mapping. Analyze the topological connection relationship of the nodes in the circuit netlist and preset the number of iterations to control the duration of subsequent iteration optimization.
[0020] S2. Based on the standard cell library, enumerate the connection combinations between various logic units (i.e., logic unit combinations) to generate candidate logic structures. In traditional logic synthesis, this structure is generally called a Supergate. Unlike traditional Supergates, this invention constructs candidate Supergates with first constraints. These first constraints include: the number of inputs to the candidate Supergate does not exceed 6, the logic level does not exceed 3, and it satisfies path balance constraints, meaning that any input-to-output path of the candidate Supergate passes through the same number of logic units. D flip-flops are used as basic units in the construction of candidate Supergates to ensure the timing consistency of the structure. The Supergates are categorized and stored using P-class transformations. Each P-class truth table stores only the candidate Supergate with the fewest Josephson nodes, forming a Supergate library.
[0021] In step S2, the P-type transformation specifically involves: performing input variable substitution on the Boolean function; forming a set of equivalent functions that are mutually reachable through the P-type transformation, and taking the truth table of one function in this set as a unified representative, which is called the P-type truth table; for each P-type truth table, only the candidate Supergate with the fewest Josephson nodes is retained and stored in the Supergate library.
[0022] Figure 2 This is a combination of two connections based on the logic cell enumeration in the open-source RSFQ standard cell library Cold Flux. Figure 2 (a) and Figure 2 In (b), there are two different structures with the same P-class truth table, namely candidate Supergates, both with 3 inputs and 2 logical levels. Figure 2 In the code, the number marked on the logic unit is its corresponding JJ number in the standard cell library Cold Flux. Specifically, Figure 2 In (a), the DFF unit consists of 7 JJs, the AND gate consists of 15 JJs, and the XOR gate consists of 19 JJs; Figure 2 In (b), the NOT gate consists of 8 JJs, the AND gate consists of 15 JJs, and the XOR gate consists of 11 JJs. (Compare) Figure 2 (a) and Figure 2 In (b), it was found that the logical functions of the two candidate Supergates are equivalent, but Figure 2 The total number of penises in (a) is 41. Figure 2 The total number of penises in (b) is 34. Figure 2 (b) has a smaller total number of JJs, so it is stored in the Supergate library as a candidate Supergate with a better number of JJs.
[0023] S3. Perturb the node level of the circuit netlist, randomly assign logic levels while maintaining the topology order, and insert D flip-flops to achieve path balance.
[0024] Step S3 is as follows: Traverse the nodes in the circuit netlist in topological order, calculate the maximum and minimum logic levels achievable by each node, and define the interval formed by the maximum and minimum logic levels as the node's level perturbation range. Without disrupting the circuit topology, randomly assign values to the logic levels of each node within the level perturbation range according to the topological order. Limit the level perturbation of nodes closer to the main input to reduce the probability of them perturbing to higher levels. After determining the logic level of the current node, the minimum logic level achievable by its fan-out nodes may have changed, therefore, the level perturbation range of its fan-out nodes needs to be redefined. After assigning values to the level of all nodes, insert D flip-flops to achieve path balancing.
[0025] S4. Traverse the nodes in the circuit netlist in reverse topology order, extracting fan-out free cones that satisfy the second constraint condition. The second constraint condition includes: the logic level of the fan-out free cone does not exceed 3, and the number of inputs does not exceed 6; the fan-out free cone is a logic substructure with the current node as the root node, and the fan-out of the internal nodes is only used by this structure; calculate the Boolean function truth table of the extracted fan-out free cone and perform a P-type transformation, while recording the process of this P-type transformation, that is, recording the change in the arrangement of input variables. Subsequently, match equivalent supergates with the same P-type truth table in the Supergate library. If the number of Josephson nodes in the supergate in the library is smaller, then perform an inverse P-type transformation on the fan-out free cone according to the previously recorded change in the arrangement of input variables to restore its original input variable arrangement relationship, and replace the corresponding FFC in the circuit netlist with the structure after the inverse P-type transformation, thereby achieving local structural optimization while ensuring path balance. Since the structures stored in the Supergate library are all balanced, the above structural replacement can be performed while keeping the circuit topology relationship and path balance constraints unchanged.
[0026] S5. After attempting to enumerate the FFC structure of all nodes and replacing valid FFCs, perform retiming optimization on the replaced circuit netlist with the goal of minimizing the number of D flip-flops. Since the structural replacement in step S4 changed the circuit netlist structure, it provided new optimization space for retiming optimization, thereby further reducing the number of DFFs and the total number of JJs in the circuit netlist. Subsequently, determine whether to enter the next round of optimization based on whether the number of JJs in the current netlist has decreased compared with the preset number of iterations or the current number of JJs; if the total number of Josephson nodes in the current netlist has decreased compared with the previous iteration but has not reached the preset number of iterations, delete the D flip-flops in the current netlist and return to step S3, and re-execute steps S3-S5; otherwise, output the current netlist as the final netlist.
[0027] For the test circuits listed in Table 1, the method of this invention was compared with two existing RSFQ circuit DFF number optimization methods (i.e., existing method 1 and existing method 2). The test results are shown in Table 1. Existing method 1 is the method proposed in the literature "PBMap: A PathBalancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits", and existing method 2 is the method proposed in the literature "An Optimal DFF-Oriented TechnologyLegalization Algorithm for Rapid Single-Flux-Quantum Circuits". To ensure experimental fairness, the method of this invention uses the same open-source RSFQ standard cell library, Cold Flux, as both methods. Furthermore, to demonstrate the optimization effect of the method of this invention independent of the open-source logic synthesis tool ABC, Table 1 also provides data using the open-source logic synthesis tool ABC as the test benchmark, showing the data results of using only the open-source logic synthesis tool ABC for process mapping and direct DFF insertion. This invention focuses on optimizing circuit area; therefore, the logic depth is consistent with the open-source logic synthesis tool ABC. As shown in Table 1, the open-source logic synthesis tool ABC can produce a mapped netlist with better depth and area. Based on this, the method of this invention can further optimize the number of JSON objects (JJs) while maintaining the same logic depth. In summary, compared with the two existing DFF number optimization methods, the method of this invention achieves optimizations in both logic depth and total number of JJs.
[0028] Table 1
[0029] To demonstrate the ability of the method of this invention to provide more optimization space for algorithms that minimize the number of decoys (DFFs), a comparative experiment was conducted between the method of this invention and Mockturtle's Retiming algorithm (i.e., the DFF minimization Retiming algorithm in the open-source logic synthesis library Mockturtle). The test results are shown in Table 2. The test cases were all selected from the combinational logic benchmark circuit set released by the Swiss Federal Institute of Technology in Lausanne (EPFL). To demonstrate the application capability of the method of this invention to more complex standard cell libraries, this experiment used the open-source standard cell library mcnc, where the area of the logic cells was uniformly used as the number of junction cells (JJs) for calculation. As shown in Table 2, Mockturtle's Retiming algorithm cannot be further optimized after performing minimum DFF optimization on a given circuit netlist; however, the method of this invention can provide new optimization space for the algorithm while reducing the number of JJs. Furthermore, as shown in Table 2, the method of this invention optimizes both the number of JJs and the total number of nodes while maintaining the logic depth and path balance constraints, thus reducing the implementation cost of the RSFQ circuit.
[0030] Table 2
[0031] This invention proposes a path-balanced post-mapping optimization method for RSFQ circuits. By constructing and using a structurally balanced Supergate library and combining it with a hierarchical perturbation strategy, it achieves efficient structural rewriting and optimization of the mapped netlist. Compared to traditional DFF number optimization methods, this invention introduces path-balanced constraints during the Supergate construction stage, ensuring that candidate Supergates meet timing consistency requirements, thus eliminating the need for additional complex balance correction operations during subsequent replacements. Simultaneously, by performing P-type transformations on Boolean functions, it achieves a unified representation and efficient matching of different input permutation structures, significantly reducing the structure search space and improving matching efficiency. Furthermore, by introducing an iterative optimization framework based on hierarchical perturbation, this invention effectively breaks the fixed structure in the original netlist, maintaining the netlist logic depth and reducing the total number of JJs while expanding the search space of the minimum DFF number optimization algorithm. This method exhibits good scalability and stability and can be widely applied to the logic synthesis and post-optimization processes of superconducting RSFQ circuits, providing an efficient solution for high-performance, low-overhead superconducting digital circuit design.
Claims
1. A post-mapping optimization method for RSFQ circuits based on path balancing, characterized in that, Includes the following steps: S1. Read the standard cell library file of the RSFQ circuit and the RSFQ circuit netlist after process mapping, parse the topological connection relationship of the nodes in the circuit netlist, and preset the number of iterations; S2. Based on the standard unit library, enumerate the logical unit combination to construct a candidate Supergate with the first constraint condition, calculate the P-class truth table of the candidate Supergate, classify and store it after P-class transformation, and store only the candidate Supergate with the fewest Josephson nodes in each P-class truth table to form a Supergate library. S3. Perform node-level perturbation on the circuit netlist, randomly assign logic levels while maintaining the topology order, and insert D flip-flops to achieve path balance. S4. Traverse the nodes in the circuit netlist in reverse topological order, extract the fan-out free cones that satisfy the second constraint condition, calculate their Boolean function truth table and perform P-type transformation, match the equivalent structure in the Supergate library, and if the number of Josephson nodes in the structure in the library is smaller, perform the inverse P-type transformation and replace it in the circuit netlist. S5. Perform Retiming optimization on the replaced circuit netlist with the goal of minimizing the number of D flip-flops. Depending on the preset number of iterations or the optimization effect, decide whether to delete the D flip-flops and return to S3 to continue the iteration, or output the final netlist.
2. The RSFQ circuit mapping optimization method based on path balancing according to claim 1, characterized in that, In step S1, the standard cell library contains the logic function information of various logic gates in the RSFQ circuit and the corresponding number of JJs; the open-source logic synthesis tool ABC is used to read the RSFQ circuit netlist after the process mapping.
3. The RSFQ circuit mapping optimization method based on path balancing according to claim 1, characterized in that, The first constraint in step S2 includes: the number of inputs to the candidate Supergate does not exceed 6, the number of logic levels does not exceed 3, and the path balance constraint is satisfied, that is, any input-to-output path of the candidate Supergate passes through the same number of logic units; wherein, D flip-flops participate in the construction of the candidate Supergate as basic units.
4. The RSFQ circuit mapping optimization method based on path balancing according to claim 1, characterized in that, The P-type transformation mentioned in step S2 specifically involves: performing input variable substitution on the Boolean function; forming a set of equivalent functions that are mutually reachable through the P-type transformation, and taking the truth table of one function in the set as a unified representative, which is called the P-type truth table; for each P-type truth table, only the candidate Supergate with the fewest Josephson nodes is retained and stored in the Supergate library.
5. The RSFQ circuit mapping optimization method based on path balancing according to claim 1, characterized in that, The specific process of step S3 is as follows: traverse the nodes in the circuit netlist in topological order, calculate the maximum and minimum logic levels that each node can reach, and set the interval formed by the maximum and minimum logic levels as the level perturbation range of the node; without disrupting the circuit topological order, randomly assign values to the logic levels of each node within the level perturbation range in topological order, wherein the level perturbation of nodes closer to the main input is limited to reduce the probability of them perturbing to higher levels; after completing the level assignment of all nodes, insert D flip-flops to achieve path balancing.
6. The RSFQ circuit mapping optimization method based on path balancing according to claim 1, characterized in that, The second constraint in step S4 includes: the logical level of the fan-out free cone does not exceed 3 and the number of inputs does not exceed 6; the fan-out free cone is a logical substructure with the current node as the root node and the fan-out of the internal nodes is only used by this structure.
7. The RSFQ circuit mapping optimization method based on path balancing according to claim 1, characterized in that, In step S5, after performing Retiming optimization on the replaced circuit netlist with the goal of minimizing the number of D flip-flops, if the total number of Josephson nodes in the current netlist has decreased compared to the previous iteration and has not reached the preset number of iterations, the D flip-flops in the current netlist are deleted and the process returns to step S3; otherwise, the current netlist is output as the final netlist.