Clock gating circuit, clock signal control method, chip and electronic device

Abstract

This invention relates to the field of integrated circuit technology and discloses a clock gating circuit, a clock signal control method, a chip, and an electronic device. By adding a feedback circuit based on a first reverse voltage signal generation module and a first OR gate unit to a conventional clock gating circuit, when the second register group needs to operate, a second enable signal corresponding to the second gating unit is generated to control the second gating unit to open. Based on the second enable signal, the feedback circuit then controls the first gating unit to open, thereby controlling the second register group to enter the working state. Therefore, this invention only needs to generate a second enable signal to simultaneously control the opening of the first and second gating units, eliminating the need to generate separate first and second enable signals to control the opening of the first and second gating units. This avoids the process of determining which gating units need to be opened based on the second gating unit, effectively improving the working efficiency of the clock gating circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a clock gating circuit, a clock signal control method, a chip, and an electronic device. Background Technology

[0002] With the rapid development of chip technology, the design of clock gating circuits in chips has become increasingly complex, and the design of clock gating circuits directly affects the performance of chips. Currently, conventional clock gating circuits typically connect multiple clock gating units in series. Each gating clock unit controls a different register group (each register group can hold tens of thousands to hundreds of thousands of registers). When one register group needs to work, one or more clock gating units usually need to be turned on to send the clock signal to the specified register group so that the register group can start working.

[0003] Then, when one of the register groups needs to operate, it is usually necessary to first determine which cascaded clock gates need to be activated based on the corresponding clock gates for that register group to enable clock signal transmission to that register group. Then, corresponding enable signals are sent to these clock gates respectively, so that after these clock gates are activated, clock signals are sent to the designated register group through these activated clock gates, thus enabling that register group to start operating. Therefore, existing clock gating circuits suffer from low operating efficiency. Summary of the Invention

[0004] This invention provides a clock gating circuit, a clock signal control method, a chip, and an electronic device to solve the problem of low operating efficiency in existing clock gating circuits.

[0005] A clock gating circuit, the clock gating circuit comprising multiple register groups, multiple clock gating units, a clock generation unit, a first OR gate unit, and a first reverse voltage signal generation module; The plurality of clock gating units include a first gating unit and a second gating unit, wherein the output terminal of the first gating unit is connected to the input terminal of the second gating unit; The plurality of register groups include a first register group corresponding to the first gating unit and a second register group corresponding to the second gating unit. The output terminal of the first gating unit is connected to the input terminal of the first register group, the output terminal of the second gating unit is connected to the input terminal of the second register group, and the output terminal of the clock generation unit is connected to the input terminal of the first gating unit. The first input terminal of the first OR gate unit is used to receive a first enable signal, the second input terminal of the first OR gate unit is connected to the first output terminal of the first reverse pressure signal generation module, and the output terminal of the first OR gate unit is connected to the control terminal of the first gate control unit. The input terminal of the first reverse pressure signal generation module is used to receive the second enable signal, and the second output terminal of the first reverse pressure signal generation module is connected to the control terminal of the second gate control unit.

[0006] The aforementioned clock gating circuit is optional. When the first register group needs to enter the working state, the first input terminal of the first OR gate unit receives the first enable signal, and the output terminal of the first OR gate unit outputs the first enable signal to the control terminal of the first gate control unit to control the first gate control unit to open. After the first gating unit is turned on, the clock generating unit sends a clock signal to the input of the first register group through the first gating unit to control the first register group to enter the working state.

[0007] The aforementioned clock gating circuit is optional. When the second register group needs to enter the working state, the input terminal of the first reverse pressure signal generation module receives the second enable signal; The first output terminal of the first reverse pressure signal generation module outputs a first reverse pressure signal generated based on the second enable signal to the second input terminal of the first OR gate unit, so that the output terminal of the first OR gate unit outputs the first reverse pressure signal to the control terminal of the first gate control unit to control the first gate control unit to open. The second output terminal of the first reverse pressure signal generation module outputs the second enable signal to the control terminal of the second gate control unit to control the second gate control unit to open; After the first gating unit and the second gating unit are turned on, the clock generating unit sends a clock signal to the input of the second register group through the first gating unit and the second gating unit to control the second register group to enter the working state.

[0008] The aforementioned clock gating circuit is optional. When the first register group and the second register group need to enter the working state, the first input terminal of the first OR gate unit receives the first enable signal, and the second input terminal of the first OR gate unit receives the first reverse voltage signal generated based on the received second enable signal output by the first output terminal of the first reverse voltage signal generation module. The output terminal of the first OR gate unit outputs the first reverse voltage signal and / or the first enable signal to the control terminal of the first gate control unit to control the first gate control unit to open; The second output terminal of the first reverse pressure signal generation module outputs the second enable signal to the control terminal of the second gate control unit to control the second gate control unit to open; After the first gating unit and the second gating unit are turned on, the clock generating unit sends clock signals to the first register group and the second register group through the first gating unit and the second gating unit respectively, so as to control the first register group and the second register group to enter the working state respectively.

[0009] Optionally, the above clock gating circuit may also include a second OR gate unit and a second reverse voltage signal generation module; the plurality of clock gating units may also include a third gating unit, and the plurality of register groups may also include a third register group; The input terminal of the third gating unit is connected to the output terminal of the second gating unit, and the input terminal of the third register group is connected to the output terminal of the third gating unit; The first input terminal of the second OR gate unit is used to receive the second enable signal, the second input terminal of the second OR gate is connected to the first output terminal of the second reverse voltage signal generation module, and the output terminal of the second OR gate unit is connected to the input terminal of the first reverse voltage signal generation module. The input terminal of the second reverse pressure signal generation module is used to receive a third enable signal, and the second output terminal of the second reverse pressure signal generation module is connected to the control terminal of the third gate unit; wherein, the first output terminal of the second reverse pressure signal generation module is used to output a second reverse pressure signal generated based on the third enable signal to the second input terminal of the second OR gate unit, and the first output terminal of the first reverse pressure signal generation module is used to output a first reverse pressure signal generated based on the second reverse pressure signal to the second input terminal of the first OR gate unit.

[0010] The aforementioned clock gating circuit is optional. When the third register group needs to enter the working state, the input terminal of the second reverse pressure signal generation module receives the third enable signal; The first output terminal of the second reverse pressure signal generation module outputs a second reverse pressure signal generated based on the third enable signal to the second input terminal of the second OR gate unit, so that the output terminal of the second OR gate unit outputs the second reverse pressure signal to the input terminal of the first reverse pressure signal generation module; The first output terminal of the first reverse pressure signal generation module outputs the first reverse pressure signal generated based on the second reverse pressure signal to the second input terminal of the first OR gate unit, so that the output terminal of the first OR gate unit outputs the first reverse pressure signal to the control terminal of the first gate control unit to control the first gate control unit to open. The second output terminal of the first reverse pressure signal generation module outputs the second reverse pressure signal to the control terminal of the second gate control unit to control the second gate control unit to open; The second output terminal of the second reverse pressure signal generation module outputs the third enable signal to the control terminal of the third gate control unit to control the third gate control unit to open; After the first gating unit, the second gating unit, and the third gating unit are turned on, the clock generating unit sends a clock signal to the third register group through the first gating unit, the second gating unit, and the third gating unit to control the third register group to enter the working state.

[0011] A clock signal control method, applied to the clock gating circuit described in any one of the above claims, the method comprising: Determine whether the first register group and the second register group need to enter the working state respectively; When the first register group needs to enter the working state, the first enable signal is acquired and sent to the first gating unit to control the first gating unit to open. After the first gating unit is opened, the clock generation unit sends a clock signal to the first register group through the first gating unit to control the first register group to enter the working state.

[0012] The above methods are optional. When the second register group needs to enter the working state, the second enable signal is obtained, and the first reverse voltage signal is generated based on the second enable signal; The second enable signal is sent to the second gate control unit to control the second gate control unit to open, and the first reverse voltage signal is sent to the first gate control unit to control the first gate control unit to open. After the first gate control unit and the second gate control unit are opened, the clock generation unit sends a clock signal to the first register group through the first gate control unit and the second gate control unit to control the first register group to enter the working state.

[0013] A chip comprising the clock gating circuit described in any of the preceding claims.

[0014] An electronic device comprising at least one of the chips described above.

[0015] The aforementioned clock gating circuit, clock signal control method, chip, and electronic device, by adding a feedback circuit based on a first reverse voltage signal generation module and a first OR gate unit to a conventional clock gating circuit, allows the generation of a second enable signal corresponding to the second gating unit to control its activation when the second register group needs to operate. The feedback circuit, based on the second enable signal, then controls the activation of the first gating unit. This enables the clock signal output by the clock generation unit to be sent to the second register group through both the first and second gating units, thus controlling the second register group to enter the operating state. Therefore, the clock gating circuit of this invention only needs to generate a second enable signal to simultaneously control the activation of both the first and second gating units when the second register group needs to start operating. This eliminates the need to generate both the first and second enable signals separately to control the activation of the first and second gating units, avoiding the process of determining which gating units need to be activated based on the second gating unit, effectively improving the operating efficiency of the clock gating circuit. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a clock gating circuit disclosed in an embodiment of the present invention; Figure 2 This is a schematic diagram of another structure of a clock gating circuit disclosed in one embodiment of the present invention; Figure 3 This is a flowchart illustrating an implementation of a clock signal control method disclosed in an embodiment of the present invention; Figure 4 This is a partial implementation flowchart of a clock signal control method disclosed in an embodiment of the present invention; Among them, 100 is the clock generation unit, 101 is the first OR gate unit, 102 is the first reverse voltage signal generation module, 103 is the first gating unit, 104 is the second gating unit, 105 is the first register group, 106 is the second register group, 107 is the second OR gate unit, 108 is the second reverse voltage signal generation module, 109 is the third gating unit, and 110 is the third register group. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0020] It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0021] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0022] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0023] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0024] This invention discloses a clock gating circuit, a clock signal control method, a chip, and an electronic device. By adding a feedback circuit based on a first reverse voltage signal generation module and a first OR gate unit to a conventional clock gating circuit, when the second register group needs to operate, a second enable signal corresponding to the second gating unit is generated to control the second gating unit to open. Based on the second enable signal, the feedback circuit controls the first gating unit to open, thereby allowing the clock signal output by the clock generation unit to be sent to the second register group through the first and second gating units, controlling the second register group to enter the working state. Therefore, when the clock gating circuit of this invention needs to control the second register group to start operating, it only needs to generate a second enable signal to simultaneously control the first and second gating units to open, eliminating the need to generate both the first and second enable signals separately to control the first and second gating units. This avoids the process of determining which gating units need to be opened based on the second gating unit, effectively improving the working efficiency of the clock gating circuit. Specific embodiments are described below.

[0025] like Figure 1 The diagram shown is a schematic diagram of a clock gating circuit disclosed in an embodiment of the present invention. The schematic diagram of the clock gating circuit includes multiple register groups, multiple clock gating units, a clock generation unit 100, a first OR gate unit 101, and a first reverse voltage signal generation module 102.

[0026] Multiple clock gating units include a first gating unit 103 and a second gating unit 104, with the output terminal of the first gating unit 103 connected to the input terminal of the second gating unit 104; Multiple register groups include a first register group 105 corresponding to the first gate unit 103 and a second register group 106 corresponding to the second gate unit 104. The output terminal of the first gate unit 103 is connected to the input terminal of the first register group 105, the output terminal of the second gate unit 104 is connected to the input terminal of the second register group 106, and the output terminal of the clock generation unit 100 is connected to the input terminal of the first gate unit 103. The first input terminal of the first OR gate unit 101 is used to receive the first enable signal, the second input terminal of the first OR gate unit 101 is connected to the first output terminal of the first reverse pressure signal generation module 102, and the output terminal of the first OR gate unit 101 is connected to the control terminal of the first gate control unit 103. The input terminal of the first reverse pressure signal generation module 102 is used to receive the second enable signal, and the second output terminal of the first reverse pressure signal generation module 102 is connected to the control terminal of the second gate control unit 104.

[0027] The first OR gate unit 101 can be an OR gate logic unit. Therefore, the first OR gate unit 101 has two input terminals. When at least one input terminal of the first OR gate unit 101 has a signal input, both output terminals of the first OR gate unit 101 have a signal output. When the first input terminal of the first OR gate unit 101 receives the first enable signal, the second input terminal of the first OR gate unit 101 is used to receive the signal output from the output terminal of the first reverse voltage signal generation module 102. The first gating unit 103 and the second gating unit 104 are two integrated clock gating units. Cell (ICG), wherein the input terminals of the first gate unit 103 and the second gate unit 104 are the clock input terminals (CLK) of the clock gate unit, used to receive the clock signal sent by the clock generation unit 100. The output terminals of the first gate unit 103 and the second gate unit 104 are the clock output terminals (GCLK / ENCLK) of the clock gate unit, outputting the clock signal passed through the clock gate unit. The control terminals of the first gate unit 103 and the second gate unit 104 are the clock enable input terminals (EN) of the clock gate unit, used to receive enable signals to control whether the clock signal can pass through the clock gate unit. When the clock enable input terminal receives an enable signal (e.g., when the enable signal is high), it controls the clock gate unit to open so that the clock signal can pass through the clock gate unit. When the enable signal is closed, the clock enable input terminal no longer receives an enable signal (e.g., when the enable signal is low), the clock gate unit is closed, and the clock signal cannot pass through the clock gate unit.

[0028] In addition, the first register group 105 and the second register group 106 can be loaded with tens of thousands to hundreds of thousands of registers. In this embodiment, the number of registers in the register group is not limited. The first reverse voltage signal generation module 102 includes, but is not limited to, hardware modules or software modules with reverse voltage signal generation capabilities. In this embodiment, no limitation is made. The clock generation unit 100 includes, but is not limited to, a phase-locked loop circuit. The clock generation unit 100 is used to generate a clock signal that acts on each register group. After receiving the clock signal, the register group enters the working state.

[0029] In summary, this invention discloses a clock gating circuit. By adding a feedback circuit based on the first reverse voltage signal generation module 102 and the first OR gate unit 101 to a conventional clock gating circuit, when the second register group 106 needs to work, a second enable signal corresponding to the second gating unit 104 is generated to control the second gating unit 104 to turn on. Based on the second enable signal, the feedback circuit controls the first gating unit 103 to turn on, thereby enabling the clock signal output by the clock generation unit 100 to be sent to the second register group 106 through the first gating unit 103 and the second gating unit 104, controlling the second register group 106 to enter the working state. As can be seen, when the clock gating circuit of the present invention needs to control the second register group 106 to start working, it only needs to generate a second enable signal to simultaneously control the first gating unit 103 and the second gating unit 104 to open. It is not necessary to generate a first enable signal and a second enable signal to control the first gating unit 103 and the second gating unit 104 to open respectively. This avoids the process of determining which gating units need to be opened based on the second gating unit 104, and effectively improves the working efficiency of the clock gating circuit.

[0030] In one embodiment, when the first register group 105 needs to enter the working state, the first input terminal of the first OR gate unit 101 receives the first enable signal, and the output terminal of the first OR gate unit 101 outputs the first enable signal to the control terminal of the first gate control unit 103 to control the first gate control unit 103 to open.

[0031] After the first gating unit 103 is turned on, the clock generating unit 100 sends a clock signal to the input of the first register group 105 through the first gating unit 103 to control the first register group 105 to enter the working state.

[0032] refer to Figure 1 As shown, the first gating unit 103 is directly connected to the clock generation unit 100. Therefore, the clock generation unit 100 can send a clock signal to the first register unit simply by opening the first gating unit 103. Thus, it is only necessary to obtain the first enable signal and send it to the first input terminal of the first OR gate unit 101, and then send the first enable signal to the control terminal of the first gating unit 103 through the output terminal of the first OR gate unit 101. The first gating unit 103 responds to the first enable signal and controls the first gating unit 103 to open. After the first gating unit 103 is opened, the input and output terminals of the first gating unit 103 are connected, so that the clock generation unit 100 can send the clock signal to the first register group 105 through the input and output terminals of the first gating unit 103 to control the first register group 105 to enter the working state.

[0033] In one embodiment, when the second register group 106 needs to enter the working state, the input terminal of the first reverse voltage signal generation module 102 receives a second enable signal. The first output terminal of the first reverse pressure signal generation module 102 outputs a first reverse pressure signal generated based on the second enable signal to the second input terminal of the first OR gate unit 101, so that the output terminal of the first OR gate unit 101 outputs the first reverse pressure signal to the control terminal of the first gate control unit 103, thereby controlling the first gate control unit 103 to open. The second output terminal of the first reverse pressure signal generation module 102 outputs a second enable signal to the control terminal of the second gate control unit 104 to control the second gate control unit 104 to open.

[0034] After the first gating unit 103 and the second gating unit 104 are turned on, the clock generating unit 100 sends a clock signal to the input terminal of the second register group 106 through the first gating unit 103 and the second gating unit 104 to control the second register group 106 to enter the working state.

[0035] refer to Figure 1 As shown, the second gate unit 104 is not directly connected to the clock generation unit 100. The second gate unit 104 can only be connected to the clock generation unit 100 after the first gate unit 103 is turned on. Therefore, it is necessary to control the first gate unit 103 and the second gate unit to turn on at the same time.

[0036] In this specific implementation, the second enable signal is acquired and input into the first reverse pressure signal generation module 102, so that the first output terminal of the first reverse pressure signal generation module 102 outputs the first reverse pressure signal generated based on the second enable signal to the second input terminal of the first OR gate unit 101, so that the output terminal of the first OR gate unit 101 outputs the first reverse pressure signal to the control terminal of the first gate control unit 103, controlling the first gate control unit 103 to open. At the same time, the second output terminal of the first reverse pressure signal generation module 102 can output the second enable signal to the control terminal of the second gate control unit 104, controlling the second gate unit to open. Thus, the first gate control unit 103 and the second gate control unit 104 can be opened simultaneously. As can be seen, in this embodiment, only a second enable signal is generated. Then, when the input terminal of the first reverse voltage signal generation module 102 receives the second enable signal, it simultaneously sends the second enable signal to the control terminal of the second gating unit 104 at the second output terminal of the first reverse voltage signal generation module 102, and also generates a first reverse voltage signal based on the second enable signal. This signal is then sent to the second input terminal of the first OR gate unit 101 through the first output terminal of the first OR gate unit 101, so that the first reverse voltage signal is sent to the control terminal of the first gating unit 103 through the output terminal of the first OR gate unit 101. Thus, the purpose of simultaneously opening the first gating unit 103 and the second gating unit 104 based on the second enable signal can be achieved. Then, the clock generation unit 100 sends a clock signal to the second register group 106 through the input and output terminals of the first gating unit 103 and the output and input terminals of the second gating unit 104 to control the second register group 106 to start working.

[0037] The first reverse voltage signal can be the same as or different from the second enable signal. When the first reverse voltage signal is the same as the second enable signal, the first reverse voltage signal can be obtained by copying the second enable signal. The copied second enable signal is used as the first reverse voltage signal, and the second enable signal and the first reverse voltage signal are transmitted in two paths.

[0038] In summary, the improved clock gating circuit in this embodiment can simultaneously control the second gating unit 104 and the first gating unit 103 to open when the second register group 106 needs to enter the working state, by acquiring the corresponding second enable signal. This eliminates the need to determine whether the first gating unit 103 needs to be opened and to acquire the corresponding first enable signal of the first gating unit 103. Compared with the prior art, this effectively improves the working efficiency of the clock gating unit.

[0039] In one embodiment, when the first register group 105 and the second register group 106 need to enter the working state, the first input terminal of the first OR gate unit 101 receives the first enable signal, and the second input terminal of the first OR gate unit 101 receives the first reverse voltage signal generated based on the received second enable signal output by the first output terminal of the first reverse voltage signal generation module 102.

[0040] The output terminal of the first OR gate unit 101 outputs a first reverse voltage signal and / or a first enable signal to the control terminal of the first gate control unit 103 to control the first gate control unit 103 to open.

[0041] The second output terminal of the first reverse pressure signal generation module 102 outputs a second enable signal to the control terminal of the second gate control unit 104 to control the second gate control unit 104 to open.

[0042] After the first gating unit 103 and the second gating unit 104 are turned on, the clock generating unit 100 sends clock signals to the first register group 105 and the second register group 106 through the first gating unit 103 and the second gating unit 104 respectively, so as to control the first register group 105 and the second register group 106 to enter the working state respectively.

[0043] Understandably, when both the first register group 105 and the second register group 106 need to enter the working state, since the first enable signal and the second enable signal will be acquired simultaneously, the two input terminals of the first OR gate unit 101 will simultaneously receive the first enable signal and the first reverse voltage signal. In this case, the output terminal of the first OR gate unit 101 can output the first enable signal to the control terminal of the first gate control unit 103 to control the first gate control unit 103 to open; or, the output terminal of the first OR gate unit 101 can output the first reverse voltage signal to the control terminal of the first gate control unit 103 to control the first gate control unit 103 to open; or, the output terminal of the first OR gate unit 101 can simultaneously output the first enable signal and the first reverse voltage signal to the control terminal of the first gate control unit 103 to control the first gate control unit 103 to open. This embodiment does not impose any limitations.

[0044] In one embodiment, such as Figure 2 As shown, the clock gating circuit in this embodiment also includes a second OR gate unit 107 and a second reverse voltage signal generation module 108; the multiple clock gating units also include a third gating unit 109, and the multiple register groups also include a third register group 110.

[0045] The input terminal of the third gating unit 109 is connected to the output terminal of the second gating unit 104, and the input terminal of the third register group 110 is connected to the output terminal of the third gating unit 109.

[0046] The first input terminal of the second OR gate unit 107 is used to receive the second enable signal. The second input terminal of the second OR gate is connected to the first output terminal of the second reverse voltage signal generation module 108. The output terminal of the second OR gate unit 107 is connected to the input terminal of the first reverse voltage signal generation module 102.

[0047] The input terminal of the second reverse pressure signal generation module 108 is used to receive the third enable signal, and the second output terminal of the second reverse pressure signal generation module 108 is connected to the control terminal of the third gate control unit 109; wherein, the first output terminal of the second reverse pressure signal generation module 108 is used to output the second reverse pressure signal generated based on the third enable signal to the second input terminal of the second OR gate unit 107, and the first output terminal of the first reverse pressure signal generation module 102 is used to output the first reverse pressure signal generated based on the second reverse pressure signal to the second input terminal of the first OR gate unit 101.

[0048] It is understood that the clock gating circuit in this embodiment may include multiple clock gating units, including the third gating unit 109. Referring to the connection method between the second gating unit 104 and the third gating unit 109 based on the second reverse voltage signal generation module 108, the second OR gate unit 107 and the first reverse voltage signal generation module 102, the clock gating circuit in this embodiment may also include a fourth gating unit, a fifth gating unit, etc., which will not be listed here. Therefore, the number of clock gating units in the clock gating circuit is not limited in this embodiment.

[0049] In one embodiment, when the third register group 110 needs to enter the working state, the input terminal of the second reverse voltage signal generation module 108 receives a third enable signal.

[0050] The first output terminal of the second reverse voltage signal generation module 108 outputs a second reverse voltage signal generated based on a third enable signal to the second input terminal of the second OR gate unit 107, so that the output terminal of the second OR gate unit 107 outputs a second reverse voltage signal to the input terminal of the first reverse voltage signal generation module 102.

[0051] The first output terminal of the first reverse pressure signal generation module 102 outputs a first reverse pressure signal generated based on the second reverse pressure signal to the second input terminal of the first OR gate unit 101, so that the output terminal of the first OR gate unit 101 outputs the first reverse pressure signal to the control terminal of the first gate control unit 103, thereby controlling the first gate control unit 103 to open.

[0052] The second output terminal of the first reverse pressure signal generation module 102 outputs a second reverse pressure signal to the control terminal of the second gate control unit 104 to control the second gate control unit 104 to open.

[0053] The second output terminal of the second reverse pressure signal generation module 108 outputs a third enable signal to the control terminal of the third gate control unit 109 to control the third gate control unit 109 to open.

[0054] After the first gating unit 103, the second gating unit 104 and the third gating unit 109 are turned on, the clock generating unit 100 sends a clock signal to the third register group 110 through the first gating unit 103, the second gating unit 104 and the third gating unit 109 to control the third register group 110 to enter the working state.

[0055] refer to Figure 2 It is understood that when the third register group 110 needs to enter the working state, simply opening the third gating unit 109 is insufficient for the clock generation unit 100 to send a clock signal to the third register group 110; both the first gating unit 103 and the first gating unit 104 need to be opened simultaneously. Furthermore, in this embodiment, the first reverse voltage signal generation unit can generate the first reverse voltage signal not only based on the second enable signal but also based on the second reverse voltage signal.

[0056] In a specific implementation, when the input terminal of the second reverse pressure signal generation module 108 in this embodiment receives the third reverse pressure signal, it can generate a second reverse pressure signal based on the acquired third enable signal. The second reverse pressure signal is then sent to the second input terminal of the second OR gate unit 107 through the first output terminal of the second reverse pressure signal generation module 108. This causes the output terminal of the second OR gate unit 107 to output the second reverse pressure signal to the input terminal of the first reverse pressure signal generation module 102. The first output terminal of the first reverse pressure signal outputs the first reverse pressure signal generated based on the second reverse pressure signal to the second input terminal of the first OR gate unit 101. This causes the output terminal of the first OR gate unit 101 to output the first reverse pressure signal to the control terminal of the first gate control unit 103, controlling the first gate control unit 103 to open. The second output terminal of the first reverse pressure signal generation module 102 outputs the second reverse pressure signal to the control terminal of the second gate control unit 104, controlling the second gate control unit 104 to open. The second output terminal of the second reverse pressure signal generation module 108 outputs the third enable signal to the control terminal of the third gate control unit 109, controlling the third gate control unit 109 to open. Therefore, after the first gate control unit 103, the second gate control unit 104 and the third gate control unit 109 are turned on, the clock generation unit 100 sends a clock signal to the third register group 110 through the first gate control unit 103, the second gate control unit 104 and the third gate control unit 109 to control the third register group 110 to enter the working state.

[0057] In summary, the clock gating circuit in this embodiment only needs to generate the enable signal for the corresponding clock gating unit when any register group needs to enter the working state, and stops generating the enable signal for the corresponding clock gating unit when any register group needs to exit the working state. This effectively improves the working efficiency of the clock gating circuit. Furthermore, since no additional enable signals need to be generated, the register groups can be used immediately after being stopped, thus reducing the power consumption of the clock gating circuit.

[0058] In one embodiment, such as Figure 3 The diagram shown is a flowchart of a clock signal control method disclosed in this invention. This method is applicable to chips designed based on gated clock circuits, and specifically includes the following steps: S301: Determine whether the first register group and the second register group need to enter the working state respectively.

[0059] It should be understood that the register types in the first register group and the second register group can be different. Register types include segment registers, instruction pointer registers, flag registers, stack pointer registers, and base pointer registers, etc. Different types of registers are used to store different types of data. Therefore, the need for the first register group and the second register group to work can be determined based on the type of data to be processed. It should be noted that the first register group and the second register group in this embodiment are merely illustrative examples and are not intended to limit this embodiment to only having a first register group and a second register group. The number of register groups is not limited in this embodiment.

[0060] S302: When the first register group needs to enter the working state, the first enable signal is obtained and sent to the first gating unit to control the first gating unit to open. After the first gating unit is opened, the clock generation unit sends a clock signal to the first register group through the first gating unit to control the first register group to enter the working state.

[0061] The first enable signal can be generated by internal logic circuitry or software control signal. In this embodiment, the source of the first enable signal is not limited.

[0062] refer to Figure 1As shown, the first gating unit is directly connected to the clock generation unit. Therefore, the clock generation unit can send a clock signal to the first register unit simply by opening the first gating unit. Thus, it is only necessary to obtain the first enable signal and send it to the first input terminal of the first OR gate unit. Then, the first enable signal is sent to the control terminal of the first gating unit through the output terminal of the first OR gate unit. The first gating unit responds to the first enable signal and controls the first gating unit to open. After the first gating unit is opened, the input and output terminals of the first gating unit are connected, so that the clock generation unit can send the clock signal to the first register group through the input and output terminals of the first gating unit to control the first register group to enter the working state.

[0063] In one embodiment, the method in this embodiment includes the following steps, such as... Figure 4 As shown: S303: When the second register group needs to enter the working state, obtain the second enable signal and generate the first reverse voltage signal based on the second enable signal.

[0064] The first reverse pressure signal and the second enable signal can be the same or different. When the first reverse pressure signal and the second enable signal are the same, the second enable signal can be directly copied, and the copied second enable signal is the first reverse pressure signal. When the first reverse pressure signal and the second enable signal are different, the second reverse pressure signal can be set according to actual needs. This embodiment does not impose any restrictions.

[0065] S304: Send a second enable signal to the second gate control unit to control the second gate control unit to open, and send a first reverse pressure signal to the first gate control unit to control the first gate control unit to open.

[0066] When the first gating unit and the second gating unit are activated, the clock generating unit sends a clock signal to the first register group through the first gating unit and the second gating unit to control the first register group to enter the working state.

[0067] refer to Figure 1 As shown, the second gating unit is not directly connected to the clock generating unit. The second gating unit can only be connected to the clock generating unit after the first gating unit is turned on. Therefore, it is necessary to control the first gating unit and the second gating unit to turn on at the same time.

[0068] In a specific implementation, a second enable signal is sent to the second gate control unit to control the second gate control unit to open, and a first reverse pressure signal is sent to the first gate control unit to control the first gate control unit to open.

[0069] In summary, the improved clock gating circuit in this embodiment can simultaneously control the second gating unit and the first gating unit to open when the second register group needs to enter the working state, by acquiring the corresponding second enable signal. It eliminates the need to determine whether the first gating unit needs to be opened and to acquire the corresponding first enable signal of the first gating unit. Compared with the prior art, this simplifies the control logic of the clock gating circuit and helps to improve the working efficiency of the clock gating unit.

[0070] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0071] This application also discloses a chip that includes the clock gating circuit disclosed in any of the above embodiments.

[0072] In one embodiment, a chip is provided, wherein the clock gating circuit in the chip includes multiple register groups, multiple clock gating units, a clock generation unit, a first OR gate unit, and a first reverse voltage signal generation module; Multiple clock gating units include a first gating unit and a second gating unit, with the output of the first gating unit connected to the input of the second gating unit; Multiple register groups include a first register group corresponding to a first gating unit and a second register group corresponding to a second gating unit. The output of the first gating unit is connected to the input of the first register group, the output of the second gating unit is connected to the input of the second register group, and the output of the clock generation unit is connected to the input of the first gating unit. The first input terminal of the first OR gate unit is used to receive the first enable signal, the second input terminal of the first OR gate unit is connected to the first output terminal of the first reverse voltage signal generation module, and the output terminal of the first OR gate unit is connected to the control terminal of the first gate control unit. The input terminal of the first reverse pressure signal generation module is used to receive the second enable signal, and the second output terminal of the first reverse pressure signal generation module is connected to the control terminal of the second gate control unit.

[0073] In one implementation, When the first register group needs to enter the working state, the first input terminal of the first OR gate unit receives the first enable signal, and the output terminal of the first OR gate unit outputs the first enable signal to the control terminal of the first gate control unit to control the first gate control unit to open. After the first gating unit is turned on, the clock generation unit sends a clock signal to the input of the first register group through the first gating unit to control the first register group to enter the working state.

[0074] In one implementation, When the second register group needs to enter the working state, the input terminal of the first reverse voltage signal generation module receives the second enable signal; The first output terminal of the first reverse pressure signal generation module outputs a first reverse pressure signal generated based on the second enable signal to the second input terminal of the first OR gate unit, so that the output terminal of the first OR gate unit outputs the first reverse pressure signal to the control terminal of the first gate control unit to control the first gate control unit to open. The second output terminal of the first reverse pressure signal generation module outputs a second enable signal to the control terminal of the second gate control unit to control the second gate control unit to open. After the first and second gating units are turned on, the clock generation unit sends a clock signal to the input of the second register group through the first and second gating units to control the second register group to enter the working state.

[0075] In one implementation, When the first register group and the second register group need to enter the working state, the first input terminal of the first OR gate unit receives the first enable signal, and the second input terminal of the first OR gate unit receives the first reverse voltage signal generated based on the received second enable signal output by the first output terminal of the first reverse voltage signal generation module. The output terminal of the first OR gate unit outputs a first reverse voltage signal and / or a first enable signal to the control terminal of the first gate control unit to control the first gate control unit to open. The second output terminal of the first reverse pressure signal generation module outputs a second enable signal to the control terminal of the second gate control unit to control the second gate control unit to open. After the first gating unit and the second gating unit are turned on, the clock generating unit sends clock signals to the first register group and the second register group through the first gating unit and the second gating unit respectively, so as to control the first register group and the second register group to enter the working state respectively.

[0076] In one implementation, it also includes a second OR gate unit and a second reverse voltage signal generation module; the multiple clock gating units also include a third gating unit, and the multiple register groups also include a third register group; The input terminal of the third gating unit is connected to the output terminal of the second gating unit, and the input terminal of the third register group is connected to the output terminal of the third gating unit; The first input terminal of the second OR gate unit is used to receive the second enable signal. The second input terminal of the second OR gate is connected to the first output terminal of the second reverse voltage signal generation module. The output terminal of the second OR gate unit is connected to the input terminal of the first reverse voltage signal generation module. The input terminal of the second reverse pressure signal generation module is used to receive the third enable signal, and the second output terminal of the second reverse pressure signal generation module is connected to the control terminal of the third gate unit; wherein, the first output terminal of the second reverse pressure signal generation module is used to output the second reverse pressure signal generated based on the third enable signal to the second input terminal of the second OR gate unit, and the first output terminal of the first reverse pressure signal generation module is used to output the first reverse pressure signal generated based on the second reverse pressure signal to the second input terminal of the first OR gate unit.

[0077] In one implementation, When the third register group needs to enter the working state, the input terminal of the second reverse voltage signal generation module receives the third enable signal; The first output terminal of the second reverse voltage signal generation module outputs a second reverse voltage signal generated based on a third enable signal to the second input terminal of the second OR gate unit, so that the output terminal of the second OR gate unit outputs a second reverse voltage signal to the input terminal of the first reverse voltage signal generation module; The first output terminal of the first reverse pressure signal generation module outputs a first reverse pressure signal generated based on the second reverse pressure signal to the second input terminal of the first OR gate unit, so that the output terminal of the first OR gate unit outputs the first reverse pressure signal to the control terminal of the first gate control unit to control the first gate control unit to open. The second output terminal of the first reverse pressure signal generation module outputs a second reverse pressure signal to the control terminal of the second gate control unit to control the second gate control unit to open. The second output terminal of the second reverse pressure signal generation module outputs a third enable signal to the control terminal of the third gate control unit to control the third gate control unit to open. After the first gating unit, the second gating unit, and the third gating unit are turned on, the clock generation unit sends a clock signal to the third register group through the first gating unit, the second gating unit, and the third gating unit to control the third register group to enter the working state.

[0078] This application also discloses an electronic device that includes at least the chips disclosed above.

[0079] In one embodiment, an electronic device is provided in which a chip, when executing a computer program, performs the following steps: Determine whether the first register group and the second register group need to enter the working state respectively; When the first register group needs to enter the working state, it acquires the first enable signal and sends the first enable signal to the first gating unit to control the first gating unit to open. After the first gating unit is opened, the clock generation unit sends a clock signal to the first register group through the first gating unit to control the first register group to enter the working state.

[0080] When the second register group needs to enter the working state, the second enable signal is obtained, and the first reverse voltage signal is generated based on the second enable signal; A second enable signal is sent to the second gating unit to control the second gating unit to open, and a first reverse voltage signal is sent to the first gating unit to control the first gating unit to open. After the first gating unit and the second gating unit are opened, the clock generation unit sends a clock signal to the first register group through the first gating unit and the second gating unit to control the first register group to enter the working state.

[0081] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0082] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0083] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0084] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0085] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A clock-gated circuit, characterized in that, The clock gating circuit includes multiple register groups, multiple clock gating units, a clock generation unit, a first OR gate unit, and a first reverse voltage signal generation module; The plurality of clock gating units include a first gating unit and a second gating unit, wherein the output terminal of the first gating unit is connected to the input terminal of the second gating unit; The plurality of register groups include a first register group corresponding to the first gating unit and a second register group corresponding to the second gating unit. The output terminal of the first gating unit is connected to the input terminal of the first register group, the output terminal of the second gating unit is connected to the input terminal of the second register group, and the output terminal of the clock generation unit is connected to the input terminal of the first gating unit. The first input terminal of the first OR gate unit is used to receive a first enable signal, the second input terminal of the first OR gate unit is connected to the first output terminal of the first reverse pressure signal generation module, and the output terminal of the first OR gate unit is connected to the control terminal of the first gate control unit. The input terminal of the first reverse pressure signal generation module is used to receive the second enable signal, and the second output terminal of the first reverse pressure signal generation module is connected to the control terminal of the second gate control unit.

2. The clock gating circuit as described in claim 1, characterized in that, When the first register group needs to enter the working state, the first input terminal of the first OR gate unit receives the first enable signal, and the output terminal of the first OR gate unit outputs the first enable signal to the control terminal of the first gate control unit to control the first gate control unit to open. After the first gating unit is turned on, the clock generating unit sends a clock signal to the input of the first register group through the first gating unit to control the first register group to enter the working state.

3. The clock gating circuit as described in claim 1, characterized in that, When the second register group needs to enter the working state, the input terminal of the first reverse pressure signal generation module receives the second enable signal; The first output terminal of the first reverse pressure signal generation module outputs a first reverse pressure signal generated based on the second enable signal to the second input terminal of the first OR gate unit, so that the output terminal of the first OR gate unit outputs the first reverse pressure signal to the control terminal of the first gate control unit to control the first gate control unit to open. The second output terminal of the first reverse pressure signal generation module outputs the second enable signal to the control terminal of the second gate control unit to control the second gate control unit to open; After the first gating unit and the second gating unit are turned on, the clock generating unit sends a clock signal to the input of the second register group through the first gating unit and the second gating unit to control the second register group to enter the working state.

4. The clock gating circuit as described in claim 1, characterized in that, When the first register group and the second register group need to enter the working state, the first input terminal of the first OR gate unit receives the first enable signal, and the second input terminal of the first OR gate unit receives the first reverse voltage signal generated based on the received second enable signal output by the first output terminal of the first reverse voltage signal generation module. The output terminal of the first OR gate unit outputs the first reverse voltage signal and / or the first enable signal to the control terminal of the first gate control unit to control the first gate control unit to open; The second output terminal of the first reverse pressure signal generation module outputs the second enable signal to the control terminal of the second gate control unit to control the second gate control unit to open; After the first gating unit and the second gating unit are turned on, the clock generating unit sends clock signals to the first register group and the second register group through the first gating unit and the second gating unit respectively, so as to control the first register group and the second register group to enter the working state respectively.

5. The clock gating circuit as described in claim 1, characterized in that, It also includes a second OR gate unit and a second reverse voltage signal generation module; the plurality of clock gating units also include a third gating unit, and the plurality of register groups also include a third register group; The input terminal of the third gating unit is connected to the output terminal of the second gating unit, and the input terminal of the third register group is connected to the output terminal of the third gating unit; The first input terminal of the second OR gate unit is used to receive the second enable signal, the second input terminal of the second OR gate is connected to the first output terminal of the second reverse voltage signal generation module, and the output terminal of the second OR gate unit is connected to the input terminal of the first reverse voltage signal generation module. The input terminal of the second reverse pressure signal generation module is used to receive a third enable signal, and the second output terminal of the second reverse pressure signal generation module is connected to the control terminal of the third gate unit; wherein, the first output terminal of the second reverse pressure signal generation module is used to output a second reverse pressure signal generated based on the third enable signal to the second input terminal of the second OR gate unit, and the first output terminal of the first reverse pressure signal generation module is used to output a first reverse pressure signal generated based on the second reverse pressure signal to the second input terminal of the first OR gate unit.

6. The clock gating circuit as described in claim 5, characterized in that, When the third register group needs to enter the working state, the input terminal of the second reverse pressure signal generation module receives the third enable signal; The first output terminal of the second reverse pressure signal generation module outputs a second reverse pressure signal generated based on the third enable signal to the second input terminal of the second OR gate unit, so that the output terminal of the second OR gate unit outputs the second reverse pressure signal to the input terminal of the first reverse pressure signal generation module; The first output terminal of the first reverse pressure signal generation module outputs the first reverse pressure signal generated based on the second reverse pressure signal to the second input terminal of the first OR gate unit, so that the output terminal of the first OR gate unit outputs the first reverse pressure signal to the control terminal of the first gate control unit to control the first gate control unit to open. The second output terminal of the first reverse pressure signal generation module outputs the second reverse pressure signal to the control terminal of the second gate control unit to control the second gate control unit to open; The second output terminal of the second reverse pressure signal generation module outputs the third enable signal to the control terminal of the third gate control unit to control the third gate control unit to open; After the first gating unit, the second gating unit, and the third gating unit are turned on, the clock generating unit sends a clock signal to the third register group through the first gating unit, the second gating unit, and the third gating unit to control the third register group to enter the working state.

7. A clock signal control method, characterized in that, The method, applied to the clock gating circuit according to any one of claims 1-6, comprises: Determine whether the first register group and the second register group need to enter the working state respectively; When the first register group needs to enter the working state, the first enable signal is acquired and sent to the first gating unit to control the first gating unit to open. After the first gating unit is opened, the clock generation unit sends a clock signal to the first register group through the first gating unit to control the first register group to enter the working state.

8. The clock signal control method as described in claim 7, characterized in that, When the second register group needs to enter the working state, the second enable signal is obtained, and the first reverse voltage signal is generated based on the second enable signal; The second enable signal is sent to the second gate control unit to control the second gate control unit to open, and the first reverse voltage signal is sent to the first gate control unit to control the first gate control unit to open. After the first gate control unit and the second gate control unit are opened, the clock generation unit sends a clock signal to the first register group through the first gate control unit and the second gate control unit to control the first register group to enter the working state.

9. A chip, characterized in that, The chip includes the clock gating circuit as described in any one of claims 1 to 6.

10. An electronic device, characterized in that, The electronic device includes at least one chip as described in claim 9.

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