Transient radiation effect behavior level fault injection simulation system and method based on SiP chip

Abstract

This invention discloses a simulation system and method for transient radiation effect behavior-level fault injection based on SiP chips, belonging to the field of chip analysis technology. The simulation system includes an ADC simulation module, a DAC simulation module, an FPGA simulation module, a voltage comparator simulation module, a level driver simulation module, a signal generation module, and a fault injection module. The output of the signal generation module is connected to the inputs of the ADC, voltage comparator, FPGA, and DAC simulation modules. The outputs of the ADC and voltage comparator simulation modules are connected to the input of the FPGA simulation module. The output of the FPGA simulation module is connected to the inputs of the DAC and level driver simulation modules. The output of the fault injection module is connected to the input of the fault injection target module. This invention provides a fast and accurate simulation system and method for studying the transient dose rate effect of SiP chips, and is a useful supplement to the experimental study of SiP using transient radiation effects.

Description

Technical Field

[0001] This invention belongs to the field of chip analysis technology, specifically relating to a transient radiation effect behavior-level fault injection simulation system and method based on SiP chips. Background Technology

[0002] System-in-Package (SiP) technology, as one of the two major development paths beyond Moore's Law, has received widespread attention and application in the field of semiconductor technology development. As a novel technology, SiP achieves miniaturization of electronic systems by encapsulating multiple bare semiconductor chips within a single chip package. Compared to traditional PCB circuit systems, SiP offers advantages such as miniaturization, lightweight design, low power consumption, and powerful functionality, making it suitable for a wide range of applications in the aerospace field.

[0003] However, in these applications, SiP (System-in-Package) chips face the impact of transient radiation in the environment. Transient radiation can generate transient radiation effects inside semiconductor devices. When electronic devices are exposed to transient radiation, a large number of free electron-hole pairs are generated inside the device. Under the influence of the built-in electric field inside the semiconductor device, these electron-hole pairs generate transient currents through drift and diffusion, causing transient radiation effects. The presence of transient currents can interfere with the normal operation of the chip, such as causing disturbances in internal signal waveforms, data flipping, etc., and in severe cases, even causing the chip to burn out.

[0004] Previous research on transient radiation effects primarily involved irradiating semiconductor chips with radiation pulses generated by linear accelerators. However, this accelerator-based approach has several drawbacks: first, the limited experimental time makes it unsuitable for most research needs; second, accelerator irradiation is accompanied by strong electromagnetic interference, affecting effect monitoring; third, SiP (System-in-Package) microsystems, as electronic microsystems, contain both digital and analog circuits, and include both low-frequency and high-frequency signals, making experimental study of transient radiation effects extremely difficult; and fourth, the lack of simulation methods for transient radiation effects hinders system-level simulation. Summary of the Invention

[0005] This invention provides a simulation system and method for transient radiation effect behavior-level fault injection based on SiP chips, which provides a fast and accurate simulation system and method for studying the transient dose rate effect of SiP chips, and makes up for the shortcomings of using only transient radiation effect experiments to study SiP.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A transient radiation effect behavior-level fault injection simulation system based on SiP chip is characterized by comprising an ADC (Analog-to-Digital Converter) simulation module, a DAC (Digital-to-Analog Converter) simulation module, an FPGA (Field Programmable Gate Array) simulation module, a voltage comparator simulation module, a level driver simulation module, a signal generation module, and a fault injection module. The output of the signal generation module is connected to the input of the ADC simulation module, voltage comparator simulation module, FPGA simulation module, and DAC simulation module. The outputs of the ADC simulation module and voltage comparator simulation module are connected to the input of the FPGA simulation module. The output of the FPGA simulation module is connected to the input of the DAC simulation module and the input of the level driver simulation module. The output of the fault injection module is connected to the input of the fault injection target module.

[0007] Furthermore, the ADC simulation module is used to convert the input analog signal into a first digital signal and transmit it to the FPGA simulation module; the voltage comparator simulation module is used to compare the input analog signal with a reference voltage, thereby outputting a second digital signal and transmitting it to the FPGA simulation module. The FPGA simulation module performs bit-width expansion and frequency domain transformation on the first digital signal to generate the third digital signal; it performs frequency division on the clock signal of the FPGA simulation module to generate the fourth digital signal; and it performs logic inversion on the second digital signal; the FPGA simulation module sends the third digital signal to the DAC simulation module and the fourth digital signal to the level driver simulation module. The DAC simulation module is used to receive the clock signal generated by the DAC simulation module and the third digital signal sent by the FPGA simulation module, and convert the third digital signal sent by the FPGA into an analog signal. The level driver simulation module is used to receive the fourth digital signal input from the FPGA and perform voltage conversion based on the fourth digital signal; The signal generation module is used to provide input excitation for the ADC simulation module and the voltage comparator simulation module, and to provide clock signals for the ADC simulation module, the DAC simulation module and the FPGA simulation module; The fault injection module is used to inject transient radiation effect behavioral level faults into the target simulation module.

[0008] Furthermore, the signal generation module includes an analog input signal generation submodule, a clock signal generation submodule, and a signal scheduling and synchronization control submodule; The analog input signal generation submodule is used to provide analog input excitation for the ADC simulation module and the voltage comparator simulation module; The clock signal generation submodule is used to provide clock signals for the ADC simulation module, FPGA simulation module, and DAC simulation module. The signal scheduling and synchronization control submodule is used to achieve coordination and synchronization between different types of signals.

[0009] Furthermore, both the signal generation module and the fault injection module are built using the Python programming language.

[0010] Furthermore, the FPGA simulation module includes a data receiving module, a preprocessing module, an arithmetic logic module, and a result output module connected in sequence; The data receiving module is used to receive the first digital signal generated by the ADC simulation module and the second digital signal generated by the voltage comparator simulation module for sampling and synchronization processing. The preprocessing module is used to format and extend the bit width of the first digital signal, and to perform logical inversion on the second digital signal. The arithmetic logic module is used to control the preprocessed first digital signal to enter the fast Fourier transform and inverse transform arithmetic logic for frequency domain and inverse transform processing; at the same time, this module independently performs frequency division processing on the clock signal of the FPGA simulation module. The output module is used to extract the valid data bits from the Fast Fourier Transform / Fast Fourier Inverter operation output, generate and output the third digital signal to the DAC simulation module; at the same time, the clock signal of the FPGA simulation module after frequency division is output as the fourth digital signal to the level driver simulation module for level conversion and drive control; the synchronized second digital signal is logically inverted and then directly output to the graphical interface to display the waveform.

[0011] Furthermore, it also includes a graphical interface. The ADC simulation module, FPGA simulation module, DAC simulation module, voltage comparator simulation module, level driver simulation module, signal generation module, and fault injection module are all linked to the graphical interface. The graphical interface is used to select and set relevant parameters of the signal generation module and the fault injection module, and to view the input / output signal waveforms.

[0012] A transient radiation effect behavior-level fault injection simulation method based on SiP chip includes the following steps: Step 1: Build behavioral simulation models of each module within the SiP to simulate its logical and analog behavioral characteristics; the behavioral simulation models include FPGA simulation module, ADC simulation module, DAC simulation module, level driver simulation module, and voltage comparator simulation module. Step 2: Based on the interconnection structure of the actual internal circuit of SiP, connect the input and output ports of the behavioral simulation models of each module to form a simulation system. Step 3: Build a signal generation module using the Python programming language; Step 4: Use the Python programming language to build the fault injection module of the simulation system; Step 5: Use the Python programming language to build the graphical interface of the simulation system; Step 6: Based on the graphical interface, set the signal type and signal parameters of the signal generated by the signal generation module and the fault signal generated by the fault injection module. Call the signal generation module to generate the corresponding signal and input it into the corresponding module. Control the fault injection module to inject the set fault signal into the target module selected by the user in the simulation system at the time node set by the user. At the same time, call the behavioral simulation model to perform the simulation operation. After the simulation is completed, display the waveform of the simulation results in the graphical interface.

[0013] Furthermore, in step 1, an FPGA simulation module is established using the Verilog hardware description language, and an ADC simulation module, a DAC simulation module, and a voltage comparator simulation module are established using the Verilog Analog and Mixed Signal Extended Language.

[0014] Furthermore, in step 3, the signal generation module allows users to set the clock signal frequency of the ADC simulation module, the clock signal frequency of the DAC simulation module, the clock signal frequency of the FPGA simulation module, and to customize the input stimulus. The input stimulus includes the signal parameters of the input stimulus of the ADC simulation module and the input stimulus of the voltage comparator simulation module. The input excitation signal parameters of the ADC simulation module include the waveform type of the input excitation. The waveform type of the input excitation of the ADC simulation module includes a sine wave or a custom waveform. If a sine wave is selected, the bias, amplitude and frequency of the sine wave are set; if a custom waveform is selected, the waveform file of the custom waveform is imported. The input excitation signal parameters of the voltage comparator simulation module include the waveform type of the input excitation. The waveform types of the input excitation of the voltage comparator simulation module include constant 0, constant 1, square wave, or custom waveform. If a square wave is selected, the high and low level magnitude, frequency magnitude, duration, and period of the square wave are set. If a custom waveform is selected, the waveform file of the custom waveform is imported.

[0015] Furthermore, in step 6, the simulation process of the FPGA simulation module is as follows: The system receives the first digital signal generated by the ADC simulation module and the second digital signal generated by the voltage comparator simulation module, and performs sampling and synchronization processing on them. The module performs formatting and bit-width expansion on the first digital signal, and performs logical inversion on the second digital signal. It controls the preprocessed first digital signal to enter the Fast Fourier Transform and Inverse Transform operation logic for frequency domain and inverse transform processing. At the same time, this module independently performs frequency division processing on the clock signal from the FPGA simulation module of the signal generation module. The valid data bits of the Fast Fourier Transform / Fast Fourier Inverter operation output are extracted to generate and output a third digital signal to the DAC simulation module; at the same time, the clock signal of the FPGA simulation module after frequency division is output as a fourth digital signal to the level driver simulation module for level conversion and drive control; the synchronized second digital signal is logically inverted and then directly output to the graphical interface to display the waveform.

[0016] Compared with the prior art, the present invention has at least the following beneficial technical effects: This invention takes a domestically produced SiP (System-in-Package) as the research object and its basic structure as a simulation modeling reference. Based on the Verilog digital circuit behavioral simulation model and the Verilog-AMS circuit behavioral simulation model, a behavioral simulation model including each chip module inside the SiP is established. By inputting signals to the behavioral simulation model, the functional simulation output signals of each module inside the SiP and the SiP as a whole can be obtained. In order to conduct simulation research on the transient radiation effect of the SiP, a transient radiation effect fault injection module is established in this simulation system. Through this module, transient radiation effect behavioral faults can be injected into the input and output signals of the established behavioral simulation model to study the failure mechanism of the SiP under transient radiation environment and the propagation law of faults inside the SiP.

[0017] Furthermore, this simulation system utilizes the Python programming language to build a visual graphical interface for simulating transient radiation effects in a SiP (System-in-Package) system. This interface allows for customized settings and simulations of the operational functions, input / output signals, and transient radiation effect fault injection parameters of various modules within the SiP. The graphical interface also provides a simple and intuitive way to plot and display the output signal waveforms of the SiP simulation system. This enables users to easily grasp the various settings and parameters of the simulation system, and to more readily understand and analyze the simulation results, thereby improving system usability and user experience.

[0018] This behavioral-level simulation system platform boasts advantages such as fast simulation speed, customizable fault types, customizable system functions, and the ability to replace and upgrade models. A single simulation takes only a few minutes, and the injected fault type and time point can be randomly selected. The system's functional modules can be added, removed, or upgraded to circuit-level models, achieving higher simulation accuracy. This simulation system can conduct preliminary research on the transient radiation effects of this domestically produced SiP chip and similar SiP chips. Extensive simulations can be performed before accelerator irradiation experiments to identify sensitive components in the system, allowing for focused research on these components during the experiment. It can also interpret and simulate experimental results, enabling a better understanding of the propagation patterns of transient radiation-induced faults within SiP chips. Attached Figure Description

[0019] Figure 1 This is a diagram of the internal system architecture of a domestically produced SiP (System-in-Package). Figure 2 Framework diagram of a simulation system for behavioral-level fault injection and propagation of transient radiation effects in SiP; Figure 3 A diagram showing the clock signal settings page for the FPGA simulation module in the interface of a SiP transient radiation effect behavioral-level fault injection and propagation simulation system. Figure 4 A diagram of the ADC signal input and fault injection settings page in the interface of the SiP transient radiation effect behavioral level fault injection and propagation simulation system; Figure 5 A diagram showing the input and fault injection settings of the voltage comparator in the interface of a SiP transient radiation effect behavioral-level fault injection and propagation simulation system. Figure 6 This is a diagram of the FPGA signal fault injection and SiP output settings page in the interface of the SiP transient radiation effect behavioral level fault injection and propagation simulation system interface. Detailed Implementation

[0020] To make the objectives and technical solutions of this invention clearer and easier to understand, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. The specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0021] A transient radiation effect behavior-level fault injection simulation system for a SiP chip (hereinafter referred to as the SiP simulation system) is based on a certain SiP chip (the chip's internal architecture is as follows). Figure 1 The internal architecture of the SiP simulation system (as shown) is established using Verilog and Verilog-AMS behavioral-level simulation models of the corresponding modules. Figure 2As shown, the SiP simulation system includes eight modules: a graphical interface, a signal generation module, a fault injection module, and a behavioral simulation model. The behavioral simulation model includes an ADC simulation module, a DAC simulation module, an FPGA simulation module, a voltage comparator simulation module, and a level driver simulation module. Each model corresponds to an actual circuit module with a specific function in the SiP chip.

[0022] The simulation modules for ADC, DAC, FPGA, voltage comparator, and level driver correspond to the functional units within the actual SiP chip. The ADC, DAC, voltage comparator, and level driver modules are modeled using Verilog and Verilog-AMS, while the FPGA simulation module is modeled using Verilog. These behavioral models, driven by input signals, simulate the functional behavior of the semiconductor circuits within the ADC, DAC, FPGA, voltage comparator, and level driver modules of the SiP chip and output corresponding signals, without requiring attention to the specific functions and operating states of their internal structures. This modeling method features simplified structure and fast simulation speed, making it suitable for rapid verification and testing of the functions of various modules within a SiP chip.

[0023] After the behavioral-level model is built, the operation of the ADC simulation module, DAC simulation module, FPGA simulation module, and voltage comparator simulation module requires input signal drive, including external input stimuli or clock signals. A signal generation module for the SiP simulation system was built using the Python programming language. This module can provide input stimuli or clock signals to the ADC, DAC, FPGA, and voltage comparator simulation modules within the SiP simulation system. Through the signal generation module, the input stimuli for the ADC and voltage comparator simulation modules, as well as the input clock signals for the ADC, DAC, and FPGA simulation modules, can be generated.

[0024] Since the behavioral-level model does not include a transient radiation effect model, the constructed model cannot be used to simulate and analyze the model's response under transient radiation effects. Therefore, a fault injection module for transient radiation effects in the SiP simulation system was developed using the Python programming language. Transient radiation effects can cause data faults in semiconductor circuits, such as data loss and data flipping. The fault injection module can inject fault types such as data loss and data flipping into signals from user-selected modules (optional ADC simulation module, DAC simulation module, FPGA simulation module, voltage comparator simulation module, and level driver simulation module). The parameters for fault injection (injection time point and duration) can also be defined by the user. The definition of the fault signal can be selected based on previous experimental results. This is used to simulate data loss and data flipping faults caused by transient radiation effects within the SiP system.

[0025] Finally, a graphical user interface platform for SiP system-level transient radiation effect behavioral fault injection simulation was built on the Windows platform using the Python programming language. This platform provides a graphical user interface, allowing users to customize the input parameters of the established signal generation and fault injection modules. These parameters include the frequency of the clock signal in the signal generation module, the waveform type, frequency, bias, and amplitude of the input excitation in the ADC simulation module, and the high / low level, duration, and period of the input excitation in the voltage comparator simulation module. Simultaneously, the platform also allows users to set relevant parameters for transient radiation effect behavioral fault injection in each module, including fault type, fault parameters (start and end times), and the selected fault injection module. The simulation results generated by the system simulation can be displayed through a visual interface, facilitating result analysis and verification by users.

[0026] A simulation method for transient radiation effect behavior-level fault injection in SiP chips includes the following steps. Step 1: First, build simulation models for each module within the SiP. Based on the circuit structure and functions of each module within the SiP, use Verilog Hardware Description Language and Verilog Analog and Mixed-Signal (Verilog-AMS) to establish behavioral-level simulation models for each module, used to simulate its logical and analog behavioral characteristics. Specifically: use Verilog Hardware Description Language to build the FPGA simulation module, and use Verilog Analog and Mixed-Signal (Verilog-AMS) to build the ADC simulation module, DAC simulation module, and voltage comparator simulation module. Step 2: After establishing the simulation models of each module inside the SiP, connect the input and output ports of the established behavioral simulation models of each module according to the interconnection structure of the actual circuit inside the SiP to form a simulation system. Step 3: Establish the signal generation module. Since the constructed ADC simulation module, DAC simulation module, FPGA simulation module, and voltage comparator simulation module require external excitation or clock signals for operation, a signal generation module for the SiP system was built using the Python programming language. This module provides corresponding clock signals for the ADC, DAC, and FPGA simulation modules in the simulation system, and provides respective input excitations for the ADC and voltage comparator simulation modules. The signal generation module supports user-defined settings of the input excitation signal parameters, including the waveform type (e.g., square wave, pulse wave, sine wave, etc.), frequency, amplitude, duty cycle, phase, and duration of the input excitation (analog signal) for the ADC simulation module, as well as the frequency of the clock signal, and the high / low level magnitude, duration, and period of the input excitation (analog signal) for the voltage comparator simulation module. It can also achieve synchronous output of multi-channel signals. This module serves as the front-end input source for system simulation, operating in conjunction with the subsequent fault injection module and behavioral simulation model, providing signal support for system-level simulation. Step 4: Write a fault injection module for the simulation system using Python. Implement fault injection functionality at the ports of various modules within the simulation system established in Step 2 using code. The parameters that need to be set for fault injection mainly include the simulation module selected by the user, the fault type (including signal flipping, signal loss, etc., set individually for each selected module), and fault parameters (start and end times of fault injection, set individually for each selected module). Step 5: Develop a graphical interface for the simulation system using Python. Users can use this interface to configure the input excitation signal type and parameters, clock signal parameters, simulation module selection, fault type, and fault parameters.

[0027] The input excitation signal types and parameters include: waveform type (such as square wave, pulse wave, sine wave, etc.), frequency, amplitude, duty cycle, and phase of the input excitation (analog signal) of the ADC simulation module; high and low level magnitude and period of the input excitation (analog signal) of the voltage comparator simulation module; clock signal parameters include: frequency of the clock signal of the ADC simulation module, frequency of the clock signal of the FPGA simulation module, and frequency of the clock signal of the DAC simulation module; simulation module selection includes the simulation module to be injected with faults, which can be selected from the ADC simulation module, voltage comparator simulation module, FPGA simulation module, DAC simulation module, and level driver simulation module, or multiple modules can be selected simultaneously or none can be selected; fault types include signal inversion and signal loss, which are set individually for each selected simulation module; fault parameters include the start and end times of fault injection, and the fault type and fault parameters are set individually for each selected module.

[0028] After the user completes the settings and clicks "Run," the graphical interface transmits the input excitation signal type and parameters, clock signal parameters, to the signal generation module, and the fault type, fault parameters, and fault selection result to the fault injection module. Upon receiving the parameters, the signal generation module generates the clock signals for the ADC simulation module, FPGA simulation module, DAC simulation module, ADC simulation module input excitation, and voltage comparator simulation module input excitation. Then, it inputs the ADC simulation module's clock signal and input excitation to the ADC simulation module, the FPGA simulation module's clock signal to the FPGA simulation module, the DAC simulation module's clock signal to the DAC simulation module, and the voltage comparator simulation module's input excitation to the voltage comparator simulation module. Upon receiving the parameters, the fault injection module generates a fault and injects it into the output signals of the selected simulation modules (first digital signal, second digital signal, third digital signal, fourth digital signal, first analog signal, and / or second analog signal) for simulation. In addition, after the simulation is completed, the waveform of the simulation results is displayed in the graphical interface. Users can intuitively view the changes in the output signals of each module, which makes it easier for users to observe and analyze the output signals of each module and the whole system within the SiP, and to study the propagation law of transient radiation effect faults between modules in the SiP system. Step 6: After completing the graphical interface setup, the SiP system-level transient radiation effect fault injection simulation platform is now complete. The specific simulation process is as follows.

[0029] First, the user opens the graphical interface and sets parameters on the behavioral-level clock fault injection page. This page has three subpages: one for setting the clock signals of the FPGA simulation module, the other for the ADC simulation module, and the third for the DAC simulation module. Figure 3 Taking the clock signal settings page for the FPGA simulation module as an example, these three sub-pages allow you to set the clock signal for the FPGA simulation module, the clock signal for the ADC simulation module, or the clock signal for the DAC simulation module, as well as the injected fault type (including signal loss and signal flip), and the start and end times of the corresponding fault. Alternatively, you can choose not to inject faults and only set the clock signal frequency, simulation duration, and simulation accuracy. The fault type and the start and end times of the faults in the three sub-pages are independent and do not affect each other. After setting each sub-page, clicking "Run" will input the clock signal frequency, simulation duration, and simulation accuracy into the signal generation module. The signal generation module generates the clock signal for the FPGA simulation module, the clock signal for the ADC simulation module, and the clock signal for the DAC simulation module. Simultaneously, the fault type, start and end times injected into the clock signal for the FPGA simulation module, the clock signal for the ADC simulation module, and the clock signal for the DAC simulation module are input into the fault injection module. The fault is injected into the corresponding signal generated by the signal generation module, and the waveforms of the clock signals for the FPGA simulation module, the ADC simulation module, and the DAC simulation module after fault injection will be displayed on the right side of the graphical interface.

[0030] Next, the user will switch the graphical interface to the ADC and voltage comparator input and fault injection settings page (e.g., Figure 4 This page contains two subpages: one for setting the input and fault injection parameters of the ADC, and the other for setting the input and fault injection parameters of the voltage comparator.

[0031] Users can configure the input and fault injection settings on the ADC (e.g., ...). Figure 4 The setup steps are as follows: First, set the input excitation parameters for the ADC simulation module: select the input waveform type (sine wave or custom waveform). If you choose a sine wave, you need to set the bias, amplitude, and frequency. If you choose a custom waveform, you need to import the waveform file. After setting the ADC input waveform, click "Run." These parameters are input to the signal generation module, which generates the input excitation for the ADC simulation module and inputs it into the ADC simulation module. After the ADC simulation module executes the simulation, it obtains the ADC output signal waveform (i.e., the first digital signal), which is displayed on the right side of the graphical interface.

[0032] Next, set the fault parameters to be injected into the ADC: Because the conversion accuracy of the ADC simulation module is 16 bits, the first digital signal contains 16 bits of digital value. The user needs to select one of the 16 bits for fault injection, and then select the fault type (including signal flip, signal loss) to be injected into that bit of the signal, as well as the start and end times of the corresponding fault. Alternatively, you can choose not to inject a fault. After setting, click Run, which will pass the fault parameters set by the user to the fault injection module, inject the fault into the corresponding signal, and after obtaining the signal after the fault injection, replace the original first digital signal waveform on the right side of the graphical interface.

[0033] Afterwards, the user switches to the voltage comparator input and fault injection settings page (e.g., Figure 5 Setup steps: First, set the input excitation parameters for the voltage comparator simulation module: select the input waveform type (constant 0, constant 1, square wave, or custom waveform). If a square wave is selected, the amplitude and frequency must be set; if a custom waveform is selected, the waveform file must be imported. After setting the input waveform for the voltage comparator, click "Run." These parameters are input to the signal generation module, which generates the input excitation for the voltage comparator simulation module and inputs it into the voltage comparator simulation module. After the voltage comparator simulation module executes the simulation, it obtains the output signal waveform (i.e., the second digital signal) of the voltage comparator, which is displayed on the right side of the graphical interface.

[0034] Next, set the fault parameters to be injected into the voltage comparator: select the type of fault to be injected into the signal (including signal flipping, signal loss), as well as the start and end times of the corresponding fault. Alternatively, you can choose not to inject the fault. After setting, click Run, which will pass the fault parameters set by the user to the fault injection module, inject the fault into the second digital signal, and after obtaining the signal after the fault injection, replace the original second digital signal waveform on the right side of the graphical interface.

[0035] Finally, the user switches to the FPGA signal fault injection and SiP output settings page (e.g.) Figure 6 Setup steps: Select the fault injection channel (optional: third and fourth digital signals, selectable individually, multiple times, or none), select the type of fault to inject into the signal (including signal inversion and signal loss), and the start and end times of the corresponding fault. Alternatively, you can choose not to inject a fault. After setting, click "Run," which will pass the user-defined fault parameters to the fault injection module and inject the fault into the third / fourth digital signal. After obtaining the signal after the fault injection, perform simulation on the DAC simulation module and the level driver simulation module to obtain the first analog signal output by the DAC simulation module and the second analog signal output by the level driver simulation module. The third and fourth digital signals after fault injection, as well as the first and second analog signals, are displayed on the right side of the graphical interface. The simulation ends here.

[0036] In the SiP structure studied, the FPGA simulation module is the main control center and data processing part inside the SiP chip. The FPGA simulation module receives the FPGA clock signal generated by the signal generation module, the first digital signal generated by the ADC simulation module, and the second digital signal generated by the voltage comparator simulation module.

[0037] The first digital signal is the digital signal output by the ADC simulation module. The ADC simulation module has a conversion accuracy of 16 bits and is used to convert the external analog signal into a corresponding 16-bit digital quantity and transmit it to the FPGA. The second digital signal is the digital signal output by the voltage comparator. The second digital signal is a 1-bit digital signal and is used to characterize the comparison result between the compared voltage and the reference voltage.

[0038] In this simulation system, the FPGA simulation module is responsible for performing logical judgments and operational control based on the first and second digital signals. The FPGA simulation module internally uses Verilog to construct signal processing logic, including a data receiving module, a preprocessing module, an arithmetic logic module, and a result output module. The data receiving module samples and synchronizes the first and second digital signals to eliminate the effects of different clock domains or signal delays. The preprocessing module formats and expands the bit width of the first digital signal (e.g., performing zero-padding to adapt to the FFT operation bit width), and simultaneously performs logical inversion on the second digital signal. The arithmetic logic module controls the preprocessed first digital signal to enter the Fast Fourier Transform (FFT) and Inverse IFFT (IFFT) operation logic for frequency domain and inverse transform processing; simultaneously, this module independently performs frequency division processing on the clock signal of the FPGA simulation module (the clock signal of the FPGA simulation module is generated by the signal generation module and sent to the FPGA simulation module). The result output module extracts the effective data bits (e.g., 28 bits) of the FFT / IFFT operation output, generates and outputs the third digital signal; simultaneously, it outputs the frequency-divided clock signal as the fourth digital signal. The third digital signal is digital data used for digital-to-analog conversion, with a bit width of 28 bits. The DAC simulation module converts the received 28-bit third digital signal into a corresponding analog voltage signal for output. The fourth digital signal is a control signal obtained by frequency division of the clock signal, with a logic high voltage of 3.3V and a logic low voltage of 0V. After receiving the fourth digital signal, the level driver simulation module performs voltage level conversion on the input signal, generating corresponding high and low level signals at the output terminal. Its logic high voltage is 5.0V and its logic low voltage is 0V, thereby enabling the drive control of external devices or interface circuits.

[0039] The ADC simulation module receives the input stimulus (analog signal) and ADC clock signal generated by the signal generation module. It samples the input stimulus (analog signal) of the ADC simulation module using the frequency of the ADC clock signal as the sampling frequency, with a conversion accuracy of 16 bits. After sampling and digital conversion of the analog signal, it generates the first digital signal and sends it to the FPGA simulation module.

[0040] The DAC simulation module has 28-bit conversion accuracy. It receives the clock signal from the DAC simulation module generated by the signal generation module and the third digital signal sent by the FPGA simulation module, and converts the digital quantity in the third digital signal sent by the FPGA into an analog signal output.

[0041] The voltage comparator simulation module receives the input excitation (an analog signal) from the signal generation module, compares the analog signal with the reference voltage (ground voltage) at zero crossing, and generates a second digital signal which is then sent to the FPGA simulation module.

[0042] The level driver simulation module receives the fourth digital signal input from the FPGA and performs voltage conversion based on the fourth digital signal sent by the FPGA.

[0043] The signal generation module, after establishing simulation models of various modules within the SiP chip and completing their interconnection, is built using Python. It is mainly responsible for providing input excitation (analog signals) for the ADC simulation module and voltage comparator simulation module, as well as providing clock signals for the ADC simulation module, DAC simulation module, and FPGA simulation module within the SiP. Since each module has a different operating frequency, the signal generation module can generate the clock drive signals required by each module.

[0044] The fault injection module primarily implements the input of transient radiation effect behavioral faults. Using Python, it enables fault injection into the inputs and outputs of various simulation modules within the SiP simulation system. Implementable faults include data flipping and data loss of input / output signals, and the start and end times of the fault signals can be set. Furthermore, it can inject faults into single signals and multiple signals simultaneously.

[0045] The graphical interface, built using Python, encapsulates the established ADC simulation module, FPGA simulation module, DAC simulation module, voltage comparator simulation module, level driver simulation module, signal generation module, and fault injection module. Users can select and set relevant parameters of the signal generation module and fault injection module through the graphical interface, and view the input / output signal waveforms.

[0046] A transient radiation effect behavioral-level fault injection simulation system based on SiP chips includes an ADC simulation module, a DAC simulation module, an FPGA simulation module, a voltage comparator simulation module, a level driver simulation module, a signal generation module, a fault injection module, and a graphical interface. The connections between these modules are as follows: the graphical interface reads the user-set frequencies of the ADC, FPGA, and DAC clocks, the waveform type (e.g., square wave, pulse wave, sine wave), frequency, amplitude, duty cycle, phase, and duration of the input excitation from the ADC simulation module, as well as the high and low level magnitudes, duration, and period of the input excitation from the voltage comparator simulation module, and transmits these values ​​to the signal generation module; the graphical interface also reads the user-set fault type (including signal inversion, signal loss, etc.), fault parameters (e.g., injection time point, fault start and end times), and the user-selected fault injection simulation module, and transmits these values ​​to the fault injection module; the signal generation module and the fault injection module then connect according to the graphical interface... The parameters transmitted from the interface generate corresponding clock signals, input stimuli, or faults, which are then input into the corresponding simulation modules. Upon receiving these signals, the ADC simulation module and the voltage comparator simulation module begin simulation. After the ADC and voltage comparator simulation modules complete their simulations, they generate simulation results (first and second digital signals) and transmit them to the FPGA simulation module. Subsequently, the FPGA simulation module begins simulation processing. After completing its simulation, the FPGA simulation module transmits the simulation results (third and fourth digital signals) to the DAC simulation module and the level driver simulation module, respectively. The DAC and level driver simulation modules then perform their simulations, and after completion, all simulation results are output to the graphical interface for display. Faults can be injected into any output or input signal.

[0047] The input of the signal generation module is linked to the graphical interface, and its output is connected to the inputs of the ADC simulation module, voltage comparator simulation module, FPGA simulation module, and DAC simulation module. The outputs of the ADC simulation module and voltage comparator simulation module are connected to the input of the FPGA simulation module, and the output of the FPGA simulation module is connected to the input of the DAC simulation module and the level driver simulation module. The input of the fault injection module is linked to the graphical interface, and its output is connected to the input or output signal of the fault injection target module selected by the user in the graphical interface (which can be the input or output signal of the ADC simulation module, voltage comparator simulation module, FPGA simulation module, DAC simulation module, and level driver simulation module).

[0048] The specific details of each module are as follows.

[0049] 1. ADC simulation module The ADC simulation module primarily functions to convert analog signals into digital signals. It is a mixed-signal circuit, and its simulation model is built using Verilog and Verilog-AMS. The input signal to the ADC simulation module comes from the signal generation module and can be an analog signal of arbitrary waveform. After passing through the ADC simulation module, it is converted into a first digital signal and output to the FPGA simulation module.

[0050] 2. DAC simulation module The DAC simulation module primarily functions to convert digital signals into analog signals. It is a mixed-signal circuit, and its simulation model was built using Verilog and Verilog-AMS. The DAC simulation module receives a third digital signal from the FPGA simulation module, which is then converted into a first analog signal.

[0051] 3. FPGA simulation module As one of the most important modules in a SiP chip, the FPGA simulation module is used to simulate the FPGA chip within the SiP chip, playing a role in controlling the remaining modules and processing data. As a programmable digital circuit, the FPGA simulation module is implemented in Verilog and can perform different functions, handling signals in various ways. During simulation, the first and second digital signals output from the ADC simulation module and the voltage comparator simulation module serve as input signals to the FPGA simulation module. After processing by the FPGA simulation module, the third and fourth digital signals are generated and passed to the DAC simulation module and the level driver simulation module, respectively, for subsequent simulation by these two modules.

[0052] 4. Voltage comparator behavioral simulation module The voltage comparator simulation module primarily compares an external analog input signal with a reference voltage, thereby outputting a second digital signal. This second digital signal serves as the input signal for the FPGA simulation module. In the simulation system, Verilog and Verilog-AMS are used to build the voltage comparator simulation module. The input signal of the voltage comparator module comes from the signal generation module and can be an analog signal of arbitrary waveform.

[0053] 5. Behavioral simulation module for level drivers Verilog and Verilog-AMS are used to simulate and model the level driver. The main function of the level driver simulation module is to convert the fourth digital signal output by the FPGA simulation module into a voltage to obtain the output signal under different voltage conditions, which is then output as the second analog signal.

[0054] 6. Signal generation module After the simulation models of each module within the SiP are established, the input stimuli for the ADC and voltage comparator simulation modules, as well as the clock signals for the ADC, DAC, and FPGA simulation modules, need to be set for the simulation modules to function correctly. A signal generation module is built using Python. This module provides input stimuli (analog signals) to the ADC and voltage comparator simulation modules and sets the waveform, amplitude, frequency, and other related parameters of the input stimuli. Simultaneously, the signal generation module also provides clock signals to the ADC, DAC, and FPGA simulation modules within the SiP simulation system. Normal simulation of these modules requires clock signals, and since different modules operate at different frequencies, the required clock signal frequencies also differ. The signal generation module can simultaneously provide different frequency clock drive signals to different simulation modules, ensuring the normal operation of the entire simulation system. The signal generation module includes the following three sub-modules: 1) Analog input signal generation submodule This submodule is primarily used to provide input excitation for the ADC simulation module and the voltage comparator simulation module. Supported waveform types include, but are not limited to, sine waves, square waves, triangle waves, sawtooth waves, and single-pulse signals. Users can customize parameters such as amplitude, frequency, bias voltage, and phase of the analog signal according to simulation requirements. The generated signal can be connected to the Verilog-AMS interface via Python and transmitted to the analog behavioral simulation model to simulate external sensor signals or voltage change input scenarios.

[0055] 2) Clock signal generation submodule This submodule provides clock signals for the ADC, DAC, and FPGA simulation modules within the SiP simulation system. Considering the different operating frequency requirements of various modules, this submodule supports multiple independent clock signal outputs. Each clock signal can be configured with its frequency, duty cycle, and phase difference, ensuring that each module performs synchronous or asynchronous simulation at its respective frequency. The generated clock signals can be connected to the digital ports of the Verilog simulation modules to drive the timing of module operation.

[0056] 3) Signal Scheduling and Synchronization Control Submodule To achieve coordination and synchronization among various signal types, this submodule provides a unified scheduling and control mechanism. This submodule allows setting the signal's start time, duration, repetition period, and trigger conditions, enabling time alignment and serialized output of analog signals and clock signals. This module ensures that all types of signals work in coordination on a unified timeline during system-level simulation, thereby preventing signal synchronization issues or simulation logic anomalies.

[0057] The aforementioned signal generation module is linked to the graphical interface via a parameterized interface. Users can select parameter configurations for various signals within the interface, enabling visualized signal setting and automatically generating corresponding signal waveform files or numerical sequences for the simulation system to use. This module possesses high flexibility and scalability, making it an indispensable key component of the SiP system-level transient radiation effect behavioral simulation platform.

[0058] 7. Fault Injection Module Simulation models built with Verilog and Verilog-AMS do not include simulations of radiation effects. Therefore, a fault injection module was built using Python to implement transient radiation effect fault input for the SiP simulation system's response to radiation effects under irradiated conditions. Python is used to implement fault injection functionality for the inputs and outputs of various simulation modules within the SiP simulation system. Faults that can be implemented include data flipping and data loss of input / output signals, and the start and end times of the fault signals can be set. For example, for the input excitation of the ADC simulation module and the voltage comparator simulation module, the fault injection module can cause a brief loss and interference phenomenon in the input excitation. For the output signals of each simulation module (first digital signal, second digital signal, third digital signal, fourth digital signal, first analog signal, and second analog signal), the fault injection module can inject faults such as signal loss, signal flipping, and signal anomalies. Furthermore, the fault injection module can also implement fault injection for a single input / output signal or for multiple input / output signals simultaneously.

[0059] 8. Graphical Interface After completing the construction of the various simulation modules, signal generation module, and fault injection module, a graphical interface platform for the SiP simulation system was built using Python to facilitate use and provide an intuitive understanding of the transient radiation effect response of the SiP simulation system. This platform encapsulates the established circuit simulation module, signal generation module, and fault injection module, adding relevant parameter and circuit setting functions to the interface platform, allowing users to define relevant parameters of the simulation system directly through the interface. Simultaneously, the interface platform includes a signal waveform display window, which provides a visual representation of the input and output signal waveforms.

[0060] The SiP transient radiation effect behavioral-level fault injection simulation system described in this invention can be used to study the transient radiation effect mechanism of SiP chips under radiation environment, obtain the propagation law of transient radiation effect faults in SiP chips and the sensitive modules inside SiP chips. Furthermore, since this system is a behavioral-level simulation system, its simulation time is short and its cost is low, which can greatly accelerate the relevant research on SiP transient radiation effects.

[0061] This invention has been applied to the transient radiation effect study of a domestically produced SiP chip. Before conducting the irradiation experiment on the chip, fault injection simulation was first performed using this simulation system. By comparing and analyzing the output responses of different modules under fault conditions, key functional paths and highly sensitive modules that significantly affect system functionality under specific radiation disturbance conditions were identified. During the irradiation experiment, these circuits were specifically studied, significantly improving the targeting and efficiency of the test, shortening the test cycle, and reducing experimental costs. Furthermore, this system not only provides high-value predictive analysis before the irradiation experiment but also allows for simulation comparison and behavior reproduction of the obtained experimental data after the experiment, assisting in the analysis of the failure mechanism and fault propagation path within the SiP chip. This system has advantages such as rapid modeling, flexible configuration, high visualization, and support for multiple fault type injection and response analysis, making it suitable for radiation-resistant design verification and early evaluation of high-reliability electronic chips.

[0062] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A transient radiation effect behavior-level fault injection simulation system based on SiP chip, characterized in that, It includes an ADC simulation module, a DAC simulation module, an FPGA simulation module, a voltage comparator simulation module, a level driver simulation module, a signal generation module, and a fault injection module; The output of the signal generation module is connected to the input of the ADC simulation module, the voltage comparator simulation module, the FPGA simulation module, and the DAC simulation module. The outputs of the ADC simulation module and the voltage comparator simulation module are connected to the input of the FPGA simulation module. The output of the FPGA simulation module is connected to the input of the DAC simulation module and the input of the level driver simulation module. The output of the fault injection module is connected to the input of the fault injection target module.

2. The transient radiation effect behavior-level fault injection simulation system based on SiP chip according to claim 1, characterized in that, The ADC simulation module is used to convert the input analog signal into a first digital signal and transmit it to the FPGA simulation module; the voltage comparator simulation module is used to compare the input analog signal with a reference voltage, thereby outputting a second digital signal and transmitting it to the FPGA simulation module. The FPGA simulation module is used to perform bit-width expansion and frequency domain transformation processing on the first digital signal to generate a third digital signal; to perform frequency division processing on the clock signal of the FPGA simulation module to generate a fourth digital signal; and to perform logic inversion processing on the second digital signal; the FPGA simulation module sends the third digital signal to the DAC simulation module and the fourth digital signal to the level driver simulation module. The DAC simulation module is used to receive the clock signal of the DAC simulation module generated by the signal generation module and the third digital signal sent by the FPGA simulation module, and convert the third digital signal sent by the FPGA into an analog signal. The level driver simulation module is used to receive the fourth digital signal input from the FPGA and perform voltage conversion based on the fourth digital signal; The signal generation module is used to provide input excitation for the ADC simulation module and the voltage comparator simulation module, and to provide clock signals for the ADC simulation module, the DAC simulation module and the FPGA simulation module; The fault injection module is used to inject transient radiation effect behavioral level faults into the target simulation module.

3. The transient radiation effect behavior-level fault injection simulation system based on SiP chip according to claim 1, characterized in that, The signal generation module includes an analog input signal generation submodule, a clock signal generation submodule, and a signal scheduling and synchronization control submodule. The analog input signal generation submodule is used to provide analog input excitation for the ADC simulation module and the voltage comparator simulation module; The clock signal generation submodule is used to provide clock signals for the ADC simulation module, FPGA simulation module and DAC simulation module; The signal scheduling and synchronization control submodule is used to achieve coordination and synchronization between different types of signals.

4. The transient radiation effect behavior-level fault injection simulation system based on SiP chip according to claim 1, characterized in that, Both the signal generation module and the fault injection module are built using the Python programming language.

5. The transient radiation effect behavior-level fault injection simulation system based on SiP chip according to claim 1, characterized in that, The FPGA simulation module includes a data receiving module, a preprocessing module, an arithmetic logic module, and a result output module connected in sequence. The data receiving module is used to receive the first digital signal generated by the ADC simulation module and the second digital signal generated by the voltage comparator simulation module for sampling and synchronization processing. The preprocessing module is used to format and expand the bit width of the first digital signal, and to perform logical inversion processing on the second digital signal. The arithmetic logic module is used to control the preprocessed first digital signal to enter the fast Fourier transform and inverse transform arithmetic logic for frequency domain and inverse transform processing; at the same time, this module independently performs frequency division processing on the clock signal of the FPGA simulation module. The result output module is used to extract the effective data bits of the Fast Fourier Transform / Fast Fourier Inverter operation output, generate and output a third digital signal to the DAC simulation module; at the same time, the clock signal of the FPGA simulation module after frequency division is output as a fourth digital signal to the level driver simulation module for level conversion and drive control. After the second digital signal is synchronized, it is logically inverted and then directly output to the graphical interface to display the waveform.

6. The transient radiation effect behavior-level fault injection simulation system based on SiP chip according to claim 1, characterized in that, It also includes a graphical interface. The ADC simulation module, FPGA simulation module, DAC simulation module, voltage comparator simulation module, level driver simulation module, signal generation module, and fault injection module are all linked to the graphical interface. The graphical interface is used to select and set relevant parameters of the signal generation module and the fault injection module, and to view the input / output signal waveforms.

7. A simulation method for transient radiation effect behavior-level fault injection based on SiP chip, characterized in that, Includes the following steps: Step 1: Build behavioral simulation models of each module within the SiP to simulate its logical and analog behavioral characteristics; the behavioral simulation models include FPGA simulation module, ADC simulation module, DAC simulation module, level driver simulation module, and voltage comparator simulation module. Step 2: Based on the interconnection structure of the actual internal circuit of SiP, connect the input and output ports of the behavioral simulation models of each module to form a simulation system. Step 3: Build a signal generation module using the Python programming language; Step 4: Use the Python programming language to build the fault injection module of the simulation system; Step 5: Use the Python programming language to build the graphical interface of the simulation system; Step 6: Based on the graphical interface, set the signal type and signal parameters of the signal generated by the signal generation module and the fault signal generated by the fault injection module, call the signal generation module to generate the corresponding signal and input it into the corresponding module, and control the fault injection module to inject the set fault signal into the target module selected by the user in the simulation system at the time node set by the user. At the same time, call the behavioral simulation model to perform simulation operation. After the simulation is completed, display the waveform of the simulation result in the graphical interface.

8. The simulation method for transient radiation effect behavior-level fault injection based on SiP chip according to claim 7, characterized in that, In step 1, the FPGA simulation module is established using the Verilog hardware description language, and the ADC simulation module, DAC simulation module, and voltage comparator simulation module are established using the Verilog Analog and Mixed Signal Extended Language.

9. A simulation method for transient radiation effect behavior-level fault injection based on SiP chip according to claim 7, characterized in that, In step 3, the signal generation module allows users to set the clock signal frequency of the ADC simulation module, the clock signal frequency of the DAC simulation module, the clock signal frequency of the FPGA simulation module, and to customize the input stimulus. The input stimulus includes the signal parameters of the input stimulus of the ADC simulation module and the input stimulus of the voltage comparator simulation module. The signal parameters of the input excitation of the ADC simulation module include the waveform type of the input excitation of the ADC simulation module. The waveform type of the input excitation of the ADC simulation module includes a sine wave or a custom waveform. If a sine wave is selected, the bias, amplitude and frequency of the sine wave are set; if a custom waveform is selected, the waveform file of the custom waveform is imported. The input excitation signal parameters of the voltage comparator simulation module include the waveform type of the input excitation of the voltage comparator simulation module. The waveform type of the input excitation of the voltage comparator simulation module includes constant 0, constant 1, square wave, or custom waveform. If a square wave is selected, the high and low level magnitude, frequency magnitude, duration, and period of the square wave are set. If a custom waveform is selected, the waveform file of the custom waveform is imported.

10. A method for simulating transient radiation effect behavior-level fault injection based on SiP chip according to claim 7, characterized in that, In step 6, the simulation process of the FPGA simulation module is as follows: The system receives the first digital signal generated by the ADC simulation module and the second digital signal generated by the voltage comparator simulation module, and performs sampling and synchronization processing on them. The first digital signal is formatted and its bit width is expanded, while the second digital signal is logically inverted. The preprocessed first digital signal is controlled to enter the Fast Fourier Transform and Inverse Transform operation logic for frequency domain and inverse transform processing; at the same time, this module independently performs frequency division processing on the clock signal from the FPGA simulation module of the signal generation module. The effective data bits of the Fast Fourier Transform / Fast Fourier Inverter operation output are extracted to generate and output a third digital signal to the DAC simulation module; at the same time, the clock signal of the FPGA simulation module after frequency division is output as a fourth digital signal to the level driver simulation module for level conversion and drive control. After the second digital signal is synchronized, it is logically inverted and then directly output to the graphical interface to display the waveform.

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