A layout optimization method and system based on probabilistic bit networks

Abstract

This invention relates to a layout optimization method and system based on probabilistic bit networks, belonging to the field of electronic design automation (EDA) technology. The method includes: acquiring a set of modules to be laid out and boundary constraint parameters, and constructing sequence pairs to represent the layout result; defining a weighted longest common subsequence and defining probabilistic bit variables; mapping the probabilistic bit variables to a probabilistic bit network; constructing a total energy function and initializing its parameters; performing random iterative updates of the probabilistic bit network until a preset termination condition is reached, obtaining the final probabilistic bit variables, and recovering the layout boundary information accordingly and performing layout verification to obtain a non-overlapping physical layout planning result. This invention transforms the layout planning problem into an energy minimization problem, possesses a unified probabilistic computational expression, improves the search efficiency of large-scale layout planning problems, and the output results have engineering recoverability and verifiability; it is applicable to both software simulation and hardware acceleration platforms.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation technology, specifically relating to a layout optimization method and system based on probabilistic bit networks, and more particularly to a solution scheme that maps the layout planning problem to a probabilistic bit network energy minimization problem. Background Technology

[0002] Floor planning is a crucial step in integrated circuit physical design. Its goal is to arrange multiple rectangular modules within a given boundary space to optimize at least one of the following: area, shape, performance, power consumption, or design friendliness. The area optimization-oriented floor planning problem can be abstracted as a rectangular binning problem. Its input is a set of modules with fixed orientation, given width, and height. The objective is to place these modules within the rectangular boundary without overlap, minimizing the boundary area (width W × height H).

[0003] As the number of modules increases, layout planning, as a complex combinatorial optimization problem, experiences a rapid expansion of its solution space. Traditional heuristic, analytical, and learning methods based on the von Neumann architecture generally suffer from high computational overhead, low search efficiency, and long solution times. Especially in large-scale layout scenarios, traditional methods often struggle to simultaneously achieve both search efficiency and solution quality.

[0004] Probabilistic computing utilizes probabilistic bit variables as basic logical computation nodes, providing a new paradigm for solving the aforementioned complex combinatorial optimization problems. The states of probabilistic bit variables can randomly fluctuate between 0 and 1 in time, and their flipping probabilities are modulated by the input. By constructing the energy function of the probabilistic bit network and designing the coupling and interconnection relationships between the probabilistic bit variables, the correct or near-optimal solution to the optimization problem can correspond to the low-energy states of the network, thereby enabling combinatorial optimization solutions using a stochastic search mechanism.

[0005] While probabilistic computation has shown great potential in solving certain conventional combinatorial optimization problems, there is currently no mature solution for its effective application in large-scale layout planning of integrated circuits. Specifically, existing technologies mainly face the following technical bottlenecks:

[0006] (1) There is a lack of a method to directly map the topological representation of the layout planning to probabilistic bit variables; (2) There is a lack of a complete construction method to uniformly map the area target, the rationality of the result and the constraints to the probabilistic bit network energy function; (3) There is a lack of a complete solution process from layout representation, variable definition, energy function construction, probabilistic bit variable state update to result verification; (4) There is a lack of a systematic solution that can take into account the solution efficiency, hardware adaptability and the verifiability of the layout result.

[0007] Therefore, there is an urgent need for a layout optimization method and system based on probabilistic bit networks to fill the above-mentioned technological gaps and improve the solution efficiency and result quality of layout planning problems. Summary of the Invention

[0008] To overcome the shortcomings of existing technologies, such as the difficulty in mapping layout planning problems to probabilistic bit networks, the scattered design of energy functions, and the lack of a complete verification process, this invention provides a layout optimization method and system based on probabilistic bit networks. This scheme represents the layout planning problem as sequence pairs and defines the probabilistic bit variables as binary variables indicating whether the modules to be laid out belong to the corresponding longest common subsequence. It constructs an area objective function, an auxiliary objective function, necessary constraint functions, and boundary constraint functions to form the total energy function, and then uses a probabilistic bit network to perform stochastic iterative solutions.

[0009] The technical solution of the present invention is as follows:

[0010] A layout optimization method based on a probabilistic bit network, wherein the probabilistic bit network includes 2N probabilistic bit variables, and the set of modules to be laid out includes N modules to be laid out, the method comprising the following steps:

[0011] Step 1: Obtain the set of modules to be laid out and the boundary constraint parameters, and construct a sequence pair (Γ) to represent the layout result. + ,Γ - ); where Γ + For a positive sequence, Γ - For negative sequences, both consist of the same set of modules to be laid out, arranged once each; define Γ + R Represents a positive sequence Γ + The reverse sequence; each module to be laid out has a fixed orientation and a preset width w. i and preset height h i , 1≤i≤N;

[0012] Step 2: Based on the sequence pair, define the weighted longest common subsequence related to the layout boundary size, and define the probability bit variable x. i and y i , 1≤i≤N, the x i and y i Let x be the binary optimization variable in the layout planning problem; and let x be the probability bit variable to construct a probability bit network for optimization solution; where x is the binary optimization variable. i =1 indicates that the i-th module to be laid out is located in (Γ). + ,Γ - In the weighted longest common subsequence of ), y i =1 indicates that the i-th module to be laid out is located in (Γ). +R ,Γ - In the weighted longest common subsequence of );

[0013] Step 3: Construct the total energy function for the layout planning problem and initialize the parameters; the total energy function is a weighted sum of multiple energy terms, which include at least the area objective function, auxiliary objective function, necessary constraint function, and boundary constraint function, and each energy term is represented by a probability bit variable x that characterizes the longest common subsequence. i and y i Perform mathematical modeling; simultaneously initialize the probabilistic bit network state, initial temperature T0, annealing coefficient β, total number of iterations, and weight coefficients corresponding to each energy term.

[0014] Step 4: Perform random iterative updates of the probabilistic bit network;

[0015] A target probability bit variable is randomly selected from the probabilistic bit network. The partial derivative of the total energy function with respect to this target probability bit variable is calculated. The update input for the target probability bit variable is obtained based on the partial derivative result. The probability of the corresponding probability bit variable outputting "0" or "1" is controlled according to the update input. The updated value of the probability bit variable is written back to the probabilistic bit network. Simultaneously, a cooling annealing operation is performed on the system in conjunction with the initial temperature T0 and the annealing coefficient β. This update process is repeated until a preset termination condition is reached. After the preset termination condition is reached, the finally converged probability bit variable x is output. i and y i The value of Γ is taken; based on the value of the probability bit variable, (Γ) is calculated respectively. + ,Γ - ), (Γ + R ,Γ - The weighted longest common subsequence of the weighted array is used to recover the physical layout boundary information, thereby determining the set of horizontal boundary modules, the set of vertical boundary modules, and the set of common modules, and thus obtaining the final non-overlapping physical layout planning result.

[0016] Furthermore, calculate (Γ) + ,Γ - The layout width can be obtained by summing the weights of the longest common subsequence of Γ. + R ,Γ - The layout height can be obtained by summing the weights of the longest common subsequence of (Γ); in calculating (Γ) + ,Γ - When calculating the weighted longest common subsequence of Γ, the module width is used as the weight; in calculating (Γ) + R ,Γ -When calculating the weighted longest common subsequence of ), the module height is used as the weight.

[0017] Furthermore, the total energy function E total Represented as:

[0018] ,

[0019] Where I0 represents the coefficient related to the system annealing temperature, E area Let E be the area objective function. longest As an auxiliary objective function, E necessary E is a necessary constraint function. max and E min α1, α2, α3, α4, and α5 represent the weight coefficients corresponding to each energy term.

[0020] Furthermore, the area objective function E area Represented as:

[0021] ,

[0022] The auxiliary objective function E longest Represented as:

[0023] ,

[0024] The necessary constraint function E necessary Represented as:

[0025] ,

[0026] The boundary constraint function E max and E min Represented as:

[0027] ,

[0028] ,

[0029] Where W and H represent the width and height of the layout, respectively; w i h represents the width of the i-th module. i Let x represent the height of the i-th module, N be the total number of modules, and x be the height of the i-th module. i and y i W represents the probability bit variable of whether the i-th module belongs to the longest common subsequence in the corresponding direction. max and H max These are the preset maximum width and maximum height of the layout, respectively; W min and H min These are the preset lower limits for layout width and height, respectively. ih represents the width of the i-th module. i Let N represent the height of the i-th module, and N be the total number of modules.

[0030] Further, based on the horizontal boundary module set, vertical boundary module set, and common module set determined in step 4, layout verification is performed. Specifically, this includes: using the unique module in the common module set as the bottom left anchor point; arranging the modules in the horizontal boundary module set along the bottom edge to restore the maximum width boundary of the layout; arranging the modules in the vertical boundary module set along the left side to restore the maximum height boundary of the layout; then performing filling and greedy placement on the remaining modules to be laid out; and performing non-overlap checks and boundary constraint checks on the overall layout result. If the overall layout verification passes, the final physical layout coordinate result is output. If the layout verification fails, the process of re-executing the initialization parameters and the random iterative update of the probability bit variables is returned to continue solving.

[0031] This invention also provides a layout optimization system based on a probabilistic bit network for running the aforementioned layout optimization method based on a probabilistic bit network. The system includes a storage module, a processor, a peripheral driving circuit, a probabilistic bit calculation array, and an output sampling circuit. The probabilistic bit calculation array is composed of interconnected probabilistic bit units, and each probabilistic bit unit corresponds one-to-one with a probabilistic bit variable in the aforementioned layout optimization method. The storage module is connected to the processor via parameter read / write signals, the processor is connected to the peripheral driving circuit via drive control signals, the peripheral driving circuit is connected to the probabilistic bit calculation array via an analog bias signal, the probabilistic bit calculation array is connected to the output sampling circuit via an updated state, and the processor is connected to the output sampling circuit via a sampling control signal and a sampling result.

[0032] The storage module stores the set of modules to be laid out, module size parameters, boundary constraint parameters, sequence pair information, the state of the current probability bit cell, total energy function parameters, and annealing iteration parameters. The processor reads and writes the parameter information in the storage module via parameter read / write signals, and determines the update input of the target probability bit cell based on the sequence pair information and total energy function parameters. The peripheral driving circuit responds to the driving control signal sent by the processor and outputs a corresponding analog bias signal to the probability bit calculation array. The output sampling circuit samples the updated state output by the probability bit calculation array under the action of the sampling control signal sent by the processor and returns the sampling result to the processor. The processor also updates the state of the current probability bit cell, restores the layout boundary information, performs layout verification, and outputs the final layout result when the verification is successful.

[0033] Furthermore, during the execution of the layout optimization method, the processor first reads the set of modules to be laid out, module size parameters, boundary constraint parameters, sequence pair information, the state of the current probability bit cell, the total energy function parameters, and annealing iteration parameters from the storage module via parameter read / write signals, and accordingly initializes the values ​​of the probability bit variables and constructs the total energy function. During the annealing iteration update process, the processor randomly selects a target probability bit cell, calculates the partial derivative of the total energy function with respect to the corresponding variable of the target probability bit cell, and generates the corresponding update input based on the partial derivative result. Subsequently, the processor sends a drive control signal to the peripheral drive circuit. The peripheral driving circuit outputs a corresponding analog bias signal to the probability bit calculation array, causing the probability bit calculation array to generate an updated state. The processor simultaneously sends a sampling control signal to the output sampling circuit, which samples the updated state and returns the sampling result to the processor. The processor updates the state of the current probability bit unit in the storage module according to the sampling result, and after reaching a preset termination condition, restores the layout boundary information according to the updated state of the probability bit unit, performs layout verification, and outputs the final layout result when the verification passes, and reinitializes the parameters and continues to perform iterative updates when the verification fails.

[0034] The technical effects of this invention are as follows:

[0035] 1. This invention realizes a direct mapping between the definition of layout planning variables and probabilistic bit networks, which facilitates the transformation of the layout planning problem into an energy minimization problem.

[0036] 2. This invention constructs a unified total energy function by using an area objective function, an auxiliary objective function, a necessary constraint function, and a boundary constraint function, thereby enabling the layout planning problem to have a unified probabilistic calculation expression form.

[0037] 3. This invention utilizes the random update mechanism of probabilistic bit networks, which helps to escape local optima and improve the search efficiency of large-scale layout planning problems.

[0038] 4. This invention provides a layout verification process that makes the output results engineering recoverable and verifiable.

[0039] 5. This invention is decoupled from the underlying specific probability bit unit, making it applicable to both software simulation and hardware acceleration platforms based on memristors, magnetic devices, or other probability bit units. Attached Figure Description

[0040] Figure 1This is a schematic diagram of the two-dimensional layout representation based on sequence pairs according to the present invention; the left figure is the relative position boundary partitioning diagram of module b, and the middle figure is the positive sequence Γ. + A schematic diagram of (abdecf), with the right figure showing the negative sequence Γ. - A diagram of (cbfade).

[0041] Figure 2 In this invention, (Γ) + , Γ - ) and (Γ + R , Γ - A schematic diagram for calculating the weighted longest common subsequence.

[0042] Figure 3 This is a flowchart illustrating the process of solving the layout optimization problem based on probabilistic bit networks according to the present invention. It shows the process of inputting the module to be laid out, constructing sequence pairs, mapping probabilistic bit variables, constructing the total energy function, random iterative update, layout recovery, and layout verification.

[0043] Figure 4 This is a schematic diagram of the layout verification steps in this invention.

[0044] Figure 5 The diagram shows the system structure of the layout optimization system based on probabilistic bit networks of this invention, illustrating the connection relationships between the processor, storage module, peripheral driving circuit, output sampling circuit, and probabilistic bit calculation array.

[0045] Figure 6 The results of solving the GSRC n300 problem example are shown in the figure. Detailed Implementation

[0046] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the following specific embodiments are only for explaining the present invention and are not intended to limit the scope of protection of the present invention. Any substitutions, combinations, or equivalent modifications made by those skilled in the art to the parameter settings, module connection relationships, update order, layout recovery strategies, and specific hardware implementations without departing from the concept of the present invention should fall within the scope of protection of the present invention.

[0047] To clarify the mapping relationship between the algorithm logic and the underlying hardware in this invention, the relevant core terms are defined as follows:

[0048] At the algorithmic and logical level, a probabilistic bit variable refers to a binary optimization variable (with a value of 0 or 1) used to mathematically represent layout features; its state flips are driven by the energy function during the algorithm's evolution and iteration; a probabilistic bit network refers to a stochastic optimization computational network composed of multiple probabilistic bit variables and their interaction weights.

[0049] At the physical and hardware level, a probability bit unit refers to a low-level hardware circuit used to physically implement a single probability bit variable, which can output a binary random electrical signal with a specific probability distribution based on the input electrical signal; a probability bit computing array refers to a hardware array composed of multiple probability bit units and their interconnection structures, used as a physical carrier to perform iterative updates and optimization solutions of the probability bit network.

[0050] This invention discloses a layout optimization method based on a probabilistic bit network, wherein the probabilistic bit network includes 2N probabilistic bit variables, and the set of modules to be laid out includes N modules to be laid out. The method includes the following steps:

[0051] Step 1: Obtain the set of modules to be laid out and the boundary constraint parameters, and construct a sequence pair (Γ) to represent the layout result. + ,Γ - ); where Γ + For a positive sequence, Γ - For negative sequences, both consist of the same set of modules to be laid out, arranged once each; define Γ + R Represents a positive sequence Γ + The reverse sequence; each module to be laid out has a fixed orientation and a preset width w. i and preset height h i , 1≤i≤N;

[0052] Step 2: Based on the sequence pair, define the weighted longest common subsequence related to the layout boundary size, and define the probability bit variable x. i and y i , 1≤i≤N, the x i and y i Let x be the binary optimization variable in the layout planning problem; and let x be the probability bit variable to construct a probability bit network for optimization solution; where x is the binary optimization variable. i =1 indicates that the i-th module to be laid out is located in (Γ). + ,Γ - In the weighted longest common subsequence of ), y i =1 indicates that the i-th module to be laid out is located in (Γ). + R ,Γ - In the weighted longest common subsequence of );

[0053] Step 3: Construct the total energy function for the layout planning problem and initialize the parameters; the total energy function is a weighted sum of multiple energy terms, which include at least the area objective function, auxiliary objective function, necessary constraint function, and boundary constraint function, and each energy term is represented by a probability bit variable x that characterizes the longest common subsequence. i and y iPerform mathematical modeling; simultaneously initialize the probabilistic bit network state, initial temperature T0, annealing coefficient β, total number of iterations, and weight coefficients corresponding to each energy term.

[0054] Step 4: Perform random iterative updates of the probabilistic bit network;

[0055] A target probability bit variable is randomly selected from the probabilistic bit network. The partial derivative of the total energy function with respect to this target probability bit variable is calculated. The update input for the target probability bit variable is obtained based on the partial derivative result. The probability of the corresponding probability bit variable outputting "0" or "1" is controlled according to the update input. The updated value of the probability bit variable is written back to the probabilistic bit network. Simultaneously, a cooling annealing operation is performed on the system in conjunction with the initial temperature T0 and the annealing coefficient β. This update process is repeated until a preset termination condition is reached. After the preset termination condition is reached, the finally converged probability bit variable x is output. i and y i The value of Γ is taken; based on the value of the probability bit variable, (Γ) is calculated respectively. + ,Γ - ), (Γ + R ,Γ - The weighted longest common subsequence of the weighted array is used to recover the physical layout boundary information, thereby determining the set of horizontal boundary modules, the set of vertical boundary modules, and the set of common modules, and thus obtaining the final non-overlapping physical layout planning result.

[0056] This invention is used to solve layout planning problems with area optimization as the objective. The layout problem consists of N rectangular modules with fixed orientations, denoted as {m1, m2, ..., m}. N}, where the i-th module has a preset width w i and preset height h i The system also receives layout boundary constraint parameters to limit the allowable range of layout width and height. The goal of layout planning is to determine the placement of each module within the rectangular boundary while minimizing the overall layout area, provided that modules do not overlap and boundary constraints are met.

[0057] To represent the relative topological relationships between modules, this implementation uses sequence pairs (Γ). + ,Γ - ) represents the layout result, where Γ + For a positive sequence, Γ - Both are negative sequences, consisting of the same set of modules to be laid out, arranged once each. + R Represents a positive sequence Γ + The reverse sequence. For example... Figure 1As shown, the sequence pairs do not directly provide the absolute coordinates of each module. Instead, they first determine the relative positional relationship between modules—"which is to the left of which, and which is above which"—by the order in which the modules are placed. For any two modules, if module p is before module q in both the positive and negative sequences, then module p is to the left of module q; if module p is before module q in the positive sequence but after module q in the negative sequence, then module p is above module q; correspondingly, if module p is after module q in both the positive and negative sequences, then module p is to the right of module q; if module p is after module q in the positive sequence but before module q in the negative sequence, then module p is below module q. Figure 1 Taking module b as an example, in the positive sequence Γ + =abdecf and negative sequence Γ - In `=cbfade`, modules d, e, and f all follow module b, therefore they are located to the right of module b. Module a precedes module b in the positive sequence and follows module b in the negative sequence, therefore it is above module b. Module c follows module b in the positive sequence and precedes module b in the negative sequence, therefore it is below module b. This method allows the relative positions of modules to be determined without directly providing specific coordinates, providing a basis for subsequent calculations of layout width and height, as well as layout restoration.

[0058] Building upon this, this implementation further defines a weighted longest common subsequence based on the sequence pairs and utilizes it to determine the layout boundary dimensions. Specifically, as... Figure 2 As shown, assume the current system is given a sequence pair (Γ) + ,Γ - The array is defined as (e da cbf, daebfc), containing 6 rectangular modules. The physical dimensions (width × height) of each module are preset as a (1×4), b (2×3), c (7×4), d (2×5), e (3×3), and f (6×2), respectively. Regarding width calculation, the horizontal relative positions of the layout are determined by the positive sequence Γ. + With negative sequence Γ - With common constraints, the system uses the width value of each module as the weight to solve (Γ). + ,Γ - The weighted longest common subsequence of the path is (d, a, b, f). In this embodiment, the subsequence constituting the horizontal critical constraint path is (d, a, b, f). Therefore, the minimum width of the overall layout is obtained by summing the widths of each module on this path, i.e., 2+1+2+6=11. Regarding height calculation, the vertical relative positions of the layout are determined by the reverse sequence Γ of the forward sequence. + R (i.e., fbcade) and negative sequence Γ- With common constraints, the system uses the height value of each module as the weight to solve for (Γ). + R ,Γ - The weighted longest common subsequence of (d, e) is used; in this embodiment, the subsequence constituting the vertical critical constraint path is (d, e), therefore the minimum height of the overall layout is obtained by summing the heights of each module on this path, i.e., 5 + 3 = 8. Figure 2 As shown in the push-force diagram, the above solution process intuitively reflects the core mechanism of area constraint in a physical sense: modules on the longest common subsequence are closely connected, directly determining the maximum width and height of the layout, and are the most critical elements limiting the overall area; while modules not on the longest common subsequence (such as module c) can slide through internal push-force without expanding the overall boundary. Based on this characteristic, the layout optimization scheme of this invention prioritizes anchoring and determining the physical position of key modules on the longest common subsequence, and then tightly fills the remaining modules into the remaining space within the boundary. The finally calculated 11×8 compact layout boundary and its mapping relationship will serve as the direct basis for subsequent cost function evaluation and simulated annealing iterative optimization.

[0059] To map the above layout planning problem to a probabilistic bit network, this implementation defines a probabilistic bit variable x. i and y i Among them, x i =1 indicates that the i-th module is located in (Γ + ,Γ - In the weighted longest common subsequence of ), y i =1 indicates that the i-th module is located in (Γ + R ,Γ - In the weighted longest common subsequence of x. i and y i As the core binary optimization variables in this problem, they collectively construct an optimization solution space containing 2N probability bit variables. During the physical solution phase, these 2N probability bit variables will be directly mapped to the corresponding 2N probability bit units in the underlying probability bit calculation array, thereby enabling efficient execution of subsequent random iterations and optimization updates via hardware.

[0060] In order to enable the probabilistic bit network to perform layout optimization, this embodiment further constructs a total energy function E. total The total energy function, consisting of a weighted sum of multiple energy terms, can be expressed as:

[0061] ,

[0062] Where I0 is a coefficient related to the annealing temperature, and α1 to α5 are the weighting coefficients for each energy term. The Earea The area objective function is used to drive the minimization of the layout boundary area; the E longest The auxiliary objective function is used to prevent layout degradation and promote compact module arrangement; the E necessary E is a necessary constraint function used to ensure consistency between the probability bit variables and the topological constraints of the sequence pairs; max and E min These are boundary constraint functions used to restrict the layout width and height to meet preset upper and lower limits. The weight of the energy term related to the constraints is greater than the weight of the area objective term, so that the system prioritizes searching for feasible solutions that satisfy the constraints, and then further optimizes the layout area within the feasible solution space. The specific energy terms are as follows:

[0063] Area objective function E area The total area of ​​the rectangular boundary, used to drive the probabilistic bit network to evolve in the direction of minimizing the boundary area, is expressed as:

[0064] ,

[0065] Auxiliary objective function E longest To minimize area while preventing the layout from degenerating to zero area and encouraging compact module arrangement, it is achieved through a penalty term that maximizes the sum of the length and width, expressed as:

[0066] ,

[0067] Necessary constraint function E necessary The values ​​of the probability bit variables are used to constrain the topological constraints of the sequence pairs to ensure the legal logic between the probability bit variables and the topological constraints, thus avoiding the generation of invalid solutions. It is represented as follows:

[0068] ,

[0069] Where W and H represent the width and height of the layout, respectively; w i h represents the width of the i-th module. i Let x represent the height of the i-th module, N be the total number of modules, and x be the height of the i-th module. i and y i The probability bit variable represents whether the i-th module belongs to the longest common subsequence in the corresponding direction.

[0070] Boundary constraint function E max and E min The limits used to constrain the layout result from exceeding the preset upper and lower limits of the layout width and height are expressed as follows:

[0071] ,

[0072] ,

[0073] Among them, W max and H max These are the preset maximum width and maximum height of the layout, respectively; W min and H min These are the preset lower limits for layout width and height, respectively. i h represents the width of the i-th module. i Let x represent the height of the i-th module, N be the total number of modules, and x be the height of the i-th module. i and y i The probability bit variable represents whether the i-th module belongs to the longest common subsequence in the corresponding direction.

[0074] To achieve the above solution process, this implementation method adopts the following approach: Figure 5 The diagram illustrates a layout optimization system based on a probabilistic bit network. The system includes a storage module, a processor, peripheral driving circuits, a probabilistic bit computation array, and an output sampling circuit. The storage module is connected to the processor via parameter read / write signals to enable read / write interaction of parameter and state information. The processor is connected to the peripheral driving circuits via drive control signals to control the output of the peripheral driving circuits. The peripheral driving circuits are connected to the probabilistic bit computation array via analog bias signals to apply the required bias signal for updating the target probabilistic bit unit in the array. The probabilistic bit computation array is connected to the output sampling circuit via the updated state to send the updated output state of the target probabilistic bit unit to the output sampling circuit. The processor is connected to the output sampling circuit via sampling control signals and sampling results to control the sampling time and receive the sampling results. Thus, the system forms a closed-loop update path of "processor—peripheral driving circuit—probabilistic bit computation array—output sampling circuit—processor," while the storage module enables continuous read / write of parameters and states.

[0075] The storage module stores the set of modules to be laid out, module size parameters (such as preset width and height), boundary constraint parameters, sequence pair information, the state of the current probability bit cell, total energy function parameters, and annealing iteration parameters (such as initial temperature, annealing coefficient, and total number of iterations). The processor reads the above parameters from the storage module and calculates the update input of the target probability bit based on the sequence pair, probability bit variables, and total energy function. The peripheral driving circuit converts the update input into a corresponding analog bias signal under the action of a driving control signal and outputs it to the target probability bit cell in the probability bit calculation array. The probability bit calculation array updates the output state of the corresponding probability bit cell under the action of the analog bias signal and provides the updated state to the output sampling circuit. The output sampling circuit samples the updated state under the action of a sampling control signal and returns the sampling result to the processor. In one implementation, the processor can be implemented using a CPU or an FPGA; the probability bit calculation array can be implemented using a hardware probability bit cell array or an equivalent simulated probability bit network. Therefore, this invention is applicable to both software simulation environments and hardware acceleration platforms.

[0076] During system operation, the processor first reads the set of modules to be laid out, module size parameters, boundary constraint parameters, sequence pair information, the state of the current probabilistic bit cell, the total energy function parameters, and annealing iteration parameters from the storage module via parameter read / write signals, and then completes the state initialization of the probabilistic bit cells and the construction of the total energy function accordingly. Subsequently, the system enters the following... Figure 3 The probabilistic bit network is shown in the diagram for a random iterative update process. In each update, the processor randomly selects a target probabilistic bit cell, calculates the partial derivative of the total energy function with respect to the corresponding variable of that target probabilistic bit cell, and generates the corresponding update input based on the partial derivative result. Next, the processor sends a drive control signal to the peripheral drive circuit, which outputs an analog bias signal to the target probabilistic bit cell in the probabilistic bit calculation array, causing the target probabilistic bit cell to generate an updated state. Simultaneously, the processor sends a sampling control signal to the output sampling circuit, which samples the updated state and returns the sampling result to the processor. The processor updates the state of the current probabilistic bit cell in the storage module based on the sampling result. Simultaneously, a system cooling annealing operation is performed using the annealing iteration parameters (initial temperature T0 and annealing coefficient β). This process is repeated until a preset termination condition is met, such as reaching a set total number of updates, the system temperature dropping below a threshold, or the state of the probabilistic bit cell stabilizing. As one implementation, the peripheral drive circuit can provide an input voltage V to the corresponding probabilistic bit cell based on the update input. in This drives the corresponding probability bit unit to generate a new bit output.

[0077] After the preset termination condition is met, the system restores the layout boundary information based on the updated state of the probability bit cells and performs layout verification. This can be done based on the probability bit variable x. i and y i The value of determines the set of horizontal boundary modules X, the set of vertical boundary modules Y, and the set of common modules Z. For example, it can be defined as follows: , , , 1≤i≤N. It should be noted that the necessary constraint function E constructed in the system... necessary This is used to ensure consistency between the state of the probabilistic bit unit and the topological constraints of the sequence pair, thereby strictly ensuring that the common module set Z contains only unique elements. Based on this, according to... Figure 4 The recovery strategy shown executes the following steps sequentially: bottom-edge placement with maximum width, left-side placement with maximum height, and filling verification of the remaining modules. Specifically, a module can be selected from the common module set Z as the bottom-left anchor point; then, modules from set X are placed along the bottom edge to restore the maximum width boundary; modules from set Y are placed along the left edge to restore the maximum height boundary; subsequently, filling and greedy placement are performed on the remaining modules, and finally, non-overlap checks and boundary constraint checks are performed on the overall layout result. If the layout verification passes, the final layout result is output; if the layout verification fails, the process returns to the probabilistic bit network's random iterative update process to continue solving. In this way, the binary state output by the probabilistic bit network is finally transformed into a concrete and verifiable layout coordinate result.

[0078] In a specific solution example, a layout planning problem involving 100 modules can be solved. The initial temperature T0 is set to 300K, with 1000 updates performed at each temperature. The annealing process is performed 1000 times, with an annealing coefficient β set to 0.9999. Cooling is stopped when the system temperature drops to 1K. The parameters in the total energy function can be set as: α1=4, α2=1, α3=5×10⁻⁶. 6 α4 = 5 × 10 5 α5 = 1 × 10 5The larger-order weight parameters (such as α3, α4, and α5) are mainly used to control hard constraints that must be strictly satisfied (such as state validity and non-overlapping constraints), imposing extremely high penalties; while smaller-order weight parameters (such as α1 and α2) are used to control soft optimization objectives such as area or line length. This configuration achieves a good balance between solution time and solution quality. For layout planning problems of different scales, the total number of iterations, annealing parameters, and weight coefficients can be adjusted according to the number of modules, target boundary size, and verification requirements, thus balancing solution efficiency and output quality. For benchmark problems such as n300 (300 modules) in the GSRC (Gigascale Systems Research Center) series, this invention can output layout results that satisfy non-overlapping constraints. Figure 6 A schematic diagram of one set of solution results is shown.

[0079] Although the present invention has been described through preferred embodiments, those skilled in the art should understand that, without departing from the concept of the present invention, adjustments or equivalent substitutions can be made to the energy term weights, parameter settings, update order, and layout verification strategies, and such adjustments or substitutions should all fall within the protection scope defined by the claims of the present invention.

Claims

1. A layout optimization method based on probabilistic bit networks, characterized in that, The probabilistic bit network includes 2N probabilistic bit variables, and the set of modules to be laid out includes N modules to be laid out. The method includes the following steps: Step 1: Obtain the set of modules to be laid out and the boundary constraint parameters, and construct a sequence pair (Γ) to represent the layout result. + ,Γ - ); where Γ + For a positive sequence, Γ - For negative sequences, both consist of the same set of modules to be laid out, arranged once each; define Γ + R Represents a positive sequence Γ + The reverse sequence; each module to be laid out has a fixed orientation and a preset width w. i and preset height h i , 1≤i≤N; Step 2: Based on the sequence pair, define the weighted longest common subsequence related to the layout boundary size, and define the probability bit variable x. i and y i , 1≤i≤N; and a probability bit network for optimization is constructed from the probability bit variables; where x i =1 indicates that the i-th module to be laid out is located in (Γ). + ,Γ - In the weighted longest common subsequence of ), y i =1 indicates that the i-th module to be laid out is located in (Γ). + R ,Γ - In the weighted longest common subsequence of ); Step 3: Construct the total energy function for the layout planning problem and initialize the parameters; the total energy function is a weighted sum of multiple energy terms, which include at least the area objective function, auxiliary objective function, necessary constraint function, and boundary constraint function, and each energy term is represented by a probability bit variable x that characterizes the longest common subsequence. i and y i Perform mathematical modeling; simultaneously initialize the probabilistic bit network state, initial temperature T0, annealing coefficient β, total number of iterations, and weight coefficients corresponding to each energy term. Step 4: Perform random iterative updates of the probabilistic bit network; A target probability bit variable is randomly selected from the probabilistic bit network. The partial derivative of the total energy function with respect to this target probability bit variable is calculated. The update input for the target probability bit variable is obtained based on the partial derivative result. The probability of the corresponding probability bit variable outputting "0" or "1" is controlled according to the update input. The updated value of the probability bit variable is written back to the probabilistic bit network. Simultaneously, a cooling annealing operation is performed on the system in conjunction with the initial temperature T0 and the annealing coefficient β. This update process is repeated until a preset termination condition is reached. After the preset termination condition is reached, the finally converged probability bit variable x is output. i and y i The value of Γ is taken; based on the value of the probability bit variable, (Γ) is calculated respectively. + ,Γ - ), (Γ + R ,Γ - The weighted longest common subsequence of the weighted array is used to recover the physical layout boundary information, thereby determining the set of horizontal boundary modules, the set of vertical boundary modules, and the set of common modules, and thus obtaining the final non-overlapping physical layout planning result.

2. The method as described in claim 1, characterized in that, Calculate (Γ) + ,Γ - The layout width is obtained by summing the weights of the longest common subsequence of Γ. + R ,Γ - The layout height is obtained by summing the weights of the longest common subsequence of (Γ); in calculating (Γ) + ,Γ - When calculating the weighted longest common subsequence of Γ, the module width is used as the weight; in calculating (Γ) + R ,Γ - When calculating the weighted longest common subsequence of ), the module height is used as the weight.

3. The method as described in claim 1, characterized in that, The total energy function E total Represented as: ， Where I0 represents the coefficient related to the system annealing temperature, E area Let E be the area objective function. longest As an auxiliary objective function, E necessary E is a necessary constraint function. max and E min α1, α2, α3, α4, and α5 represent the weight coefficients corresponding to each energy term.

4. The method as described in claim 3, characterized in that, The area objective function E area Represented as: ， The auxiliary objective function E longest Represented as: ， The necessary constraint function E necessary Represented as: ， The boundary constraint function E max and E min Represented as: ， ， Where W and H represent the width and height of the layout, respectively; w i h represents the width of the i-th module. i Let x represent the height of the i-th module, N be the total number of modules, and x be the height of the i-th module. i and y i W represents the probability bit variable of whether the i-th module belongs to the longest common subsequence in the corresponding direction. max and H max These are the preset maximum width and maximum height of the layout, respectively; W min and H min These are the preset lower limits for layout width and height, respectively. i h represents the width of the i-th module. i Let N represent the height of the i-th module, and N be the total number of modules.

5. The method as described in claim 1, characterized in that, Based on the horizontal boundary module set, vertical boundary module set, and common module set determined in step 4, layout verification is performed. Specifically, this includes: using the unique module in the common module set as the bottom left anchor point; arranging the modules in the horizontal boundary module set along the bottom edge to restore the maximum width boundary of the layout; arranging the modules in the vertical boundary module set along the left side to restore the maximum height boundary of the layout; then performing filling and greedy placement on the remaining modules to be laid out; and performing non-overlap checks and boundary constraint checks on the overall layout result. If the overall layout verification passes, the final physical layout coordinate result is output. If the layout verification fails, the process of re-executing the initialization parameters and the random iterative update of the probability bit variables is returned to continue solving.

6. A layout optimization system based on a probabilistic bit network, characterized in that, For running the layout optimization method based on probabilistic bit networks as described in claim 1, the system includes a storage module, a processor, a peripheral driving circuit, a probabilistic bit computing array, and an output sampling circuit; wherein, the probabilistic bit computing array is composed of multiple interconnected probabilistic bit units, and each probabilistic bit unit corresponds one-to-one with the probabilistic bit variables in the layout optimization method; the storage module is connected to the processor via parameter read / write signals, the processor is connected to the peripheral driving circuit via driving control signals, the peripheral driving circuit is connected to the probabilistic bit computing array via analog bias signals, the probabilistic bit computing array is connected to the output sampling circuit via updated state, and the processor is connected to the output sampling circuit via sampling control signals and sampling results; The storage module stores the set of modules to be laid out, module size parameters, boundary constraint parameters, sequence pair information, the state of the current probability bit cell, total energy function parameters, and annealing iteration parameters. The processor reads and writes the parameter information in the storage module via parameter read / write signals, and determines the update input of the target probability bit cell based on the sequence pair information and total energy function parameters. The peripheral driving circuit responds to the driving control signal sent by the processor and outputs a corresponding analog bias signal to the probability bit calculation array. The output sampling circuit samples the updated state output by the probability bit calculation array under the action of the sampling control signal sent by the processor and returns the sampling result to the processor. The processor also updates the state of the current probability bit cell, restores the layout boundary information, performs layout verification, and outputs the final layout result when the verification is successful.

7. The system as described in claim 6, characterized in that, During the implementation of the layout optimization method, the processor first reads the set of modules to be laid out, module size parameters, boundary constraint parameters, sequence pair information, the state of the current probability bit cell, the total energy function parameters, and the annealing iteration parameters from the storage module via parameter read / write signals. Based on this, it initializes the values ​​of the probability bit variables and constructs the total energy function. During the annealing iteration update process, the processor randomly selects a target probability bit cell, calculates the partial derivative of the total energy function with respect to the corresponding variable of the target probability bit cell, and generates the corresponding update input based on the partial derivative result. Subsequently, the processor sends a drive control signal to the peripheral drive circuit, which then outputs a corresponding analog bias signal to the probability bit calculation array, causing the probability bit calculation array to generate an updated state. The processor simultaneously sends a sampling control signal to the output sampling circuit, the output sampling circuit samples the updated state, and returns the sampling result to the processor; The processor updates the state of the current probability bit unit in the storage module according to the sampling result, and after reaching the preset termination condition, restores the layout boundary information according to the updated state of the probability bit unit, performs layout verification, and outputs the final layout result when the verification passes, and re-initializes the parameters and continues to perform iterative updates when the verification fails.

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