A method and circuit arrangement for voltage protection

Abstract

This invention discloses a method and circuit arrangement for voltage protection. In some embodiments, a controllable switch includes a control terminal, a first channel terminal, and a second channel terminal, and is arranged to switch between an off state and an on state. In the on state, the controllable switch allows current to flow between the first channel terminal and the second channel terminal. An overvoltage protection circuit is configured to determine a voltage difference between a first voltage at the first channel terminal and a second voltage at the second channel terminal. The overvoltage protection circuit also, in response to determining that the voltage difference is greater than or equal to a switching threshold, sets a control signal to a protection value to operate the controllable switch in the off state.

Description

Technical Field

[0001] This application relates to the switching of semiconductor switches (i.e., solid-state switches). Specifically, it prevents semiconductor switches from switching in response to voltage differences across semiconductor switch terminals. Background Technology

[0002] Solid-state switches can be used with components such as precision measuring devices and high-voltage automated testing equipment. Solid-state switches are designed to block large voltages in their off state, but these voltages can damage them if the switch is operated in its on state. For example, if a solid-state switch is blocking a large voltage difference in its off state, switching it from the off state to the on state could damage it. Summary of the Invention

[0003] This invention provides a solid-state switch with voltage-dependent switching. This solid-state switch is suitable for precision measuring equipment and high-voltage automatic testing equipment.

[0004] According to a first aspect, a solid-state switching device is provided, comprising:

[0005] A controllable switch includes a control terminal, a first channel terminal, and a second channel terminal, and is arranged to switch between an off state and an on state, wherein in the on state, the switch allows current to flow between the first channel terminal and the second channel terminal; and

[0006] The overvoltage protection circuit is configured as follows:

[0007] Determine the voltage difference between the first voltage at the first channel terminal and the second voltage at the second channel terminal; and

[0008] In response to determining that the voltage difference is greater than or equal to the switching threshold, the control signal is set to a protection value to operate the controllable switch in the off state.

[0009] The switching threshold can be equal to (or equal to 90% of) the rated breakdown voltage of the controllable switch. The switching threshold can also differ from the threshold voltage Vt (often also referred to as V) of the FETs of the controllable switch (e.g., the first FET and optionally a second FET). th or V GS(th) The switching threshold can be greater than the threshold voltage of the FET of the controllable switch. The switching threshold can be greater than the turn-off voltage of the controllable switch (at least twice as much). The word "switching" in the feature "switching threshold" is just a label, so the feature "switching threshold" can be referred to as "threshold" or "first threshold".

[0010] Optionally, the solid-state switching device is configured to use the control signal when the voltage difference is greater than or equal to a switching threshold: to prevent the controllable switch from the off state to the on state; and / or to control the controllable switch from the on state to the off state.

[0011] Optionally, the overvoltage protection circuit is configured to receive a command signal for controlling the state of the controllable switch to an off state or an on state. Optionally, the overvoltage protection circuit is configured to, in response to determining that the voltage difference is less than the switch threshold, set the control signal to a pass value, such that when the control signal is the pass value, the command signal controls the state of the controllable switch.

[0012] Optionally, the overvoltage protection circuit includes a first buffer, comprising an input terminal and an output terminal, wherein the input terminal is electrically coupled to the first channel terminal. Optionally, the overvoltage protection circuit includes a second buffer, comprising an input terminal and an output terminal, wherein the input terminal is electrically coupled to a second channel terminal.

[0013] Optionally, the first buffer is a unity-gain buffer (UGB), a voltage follower, a cascaded complementary source follower, or a dual-transistor buffer. Optionally, the second buffer is a unity-gain buffer (UGB), a voltage follower, a cascaded complementary source follower, or a dual-transistor buffer.

[0014] The controllable switch can be GaN FET, SiC FET, JFET, FET, MOSFET, DMOS, or lateral double-diffused MOSFET (LDMOS).

[0015] Optionally, the overvoltage protection circuit is arranged to generate a differential signal based on the outputs of the first buffer and the second buffer. Optionally, the voltage difference is compared with the switching threshold by comparing the differential signal with a comparison threshold. Optionally, the comparison threshold and the switching threshold have a predetermined relationship.

[0016] Optionally, the differential signal is a current signal.

[0017] Optionally, the differential signal is proportional to the voltage difference between the first channel terminal and the second channel terminal.

[0018] Optionally, the overvoltage protection circuit further includes a resistor assembly. Optionally, the output terminal of the first buffer is coupled to a first terminal of the resistor assembly. Optionally, the output terminal of the second buffer is coupled to a second terminal of the resistor assembly.

[0019] Optionally, the resistive element is a resistor. Optionally, the output voltage of the first buffer is proportional to the input voltage of the first buffer. Optionally, the output voltage of the second buffer is proportional to the input voltage of the second buffer.

[0020] Optionally, the overvoltage protection circuit includes a first current mirror arrangement configured to generate a differential signal based on the current between the output of the first buffer and the output of the second buffer.

[0021] Optionally, the first current mirror arrangement is configured to have a gain less than or equal to unity gain.

[0022] Optionally, the first current mirror arrangement includes a first current mirror assembly and a second current mirror assembly. Optionally, the first current mirror assembly is located between the output of the first buffer and the resistor assembly. Optionally, the second current mirror assembly is arranged to generate a differential signal based on the current flowing through the first current mirror assembly.

[0023] Optionally, the second current mirror is arranged to have a gain less than unity gain.

[0024] Optionally, the solid-state switching device is a bidirectional solid-state switch. Optionally, the first current mirror arrangement is configured to generate a differential signal if the voltage at the first channel terminal is greater than the voltage at the second channel terminal. Optionally, the overvoltage protection circuit further includes a second current mirror arrangement configured to generate a differential signal if the voltage at the second channel terminal is greater than the voltage at the first channel terminal.

[0025] Optionally, the second current mirror arrangement includes a third current mirror assembly and a fourth current mirror assembly. Optionally, the third current mirror assembly is located between the output terminal of the second buffer and the resistor assembly.

[0026] Optionally, the fourth current mirror assembly is arranged to generate the differential signal based on the current flowing through the third current mirror assembly.

[0027] Optionally, the differential signal is a voltage signal.

[0028] Optionally, the overvoltage protection circuit further includes a first level shifter circuit, arranged to reduce the dynamic range of the first voltage at the first channel terminal to a first voltage range to generate a first voltage output. Optionally, the overvoltage protection circuit further includes a second level shifter circuit, arranged to reduce the dynamic range of the second voltage at the second channel terminal within the first voltage range to generate a second voltage output. Optionally, the overvoltage protection circuit is arranged to generate a differential signal based on the first voltage output and the second voltage output.

[0029] Optionally, the controllable switch includes a first field-effect transistor (FET). Optionally, the control terminal includes the gate terminal of the first FET. Optionally, the first channel terminal includes the drain terminal of the first FET.

[0030] Optionally, the controllable switch further includes a second FET. Optionally, the source terminal of the first FET is coupled to the source terminal of the second FET. Optionally, the control terminal of the controllable switch further includes the gate terminal of the second FET. Optionally, the second channel terminal includes the drain terminal of the second FET.

[0031] According to a second aspect, an overvoltage protection circuit is provided, configured to be coupled to a control terminal of a controllable switch, a first channel terminal of the controllable switch, and a second channel terminal of the controllable switch, wherein the overvoltage protection circuit is configured to:

[0032] Determine the voltage difference between the first channel terminal and the second channel terminal; and

[0033] In response to determining that the voltage difference is greater than or equal to a switching threshold, a control signal is generated to set the controllable switch to operate in the off state.

[0034] The optional features of the first aspect can be applied to the second aspect.

[0035] According to a third aspect, a method is provided for operating a controllable switch for overvoltage protection, the controllable switch including a control terminal, a first channel terminal, and a second channel terminal, and arranged to switch between an off state and an on state, wherein in the on state, the switch allows current to flow between the first channel terminal and the second channel terminal, the method comprising:

[0036] Determine the voltage difference between the first voltage at the first channel terminal and the second voltage at the second channel terminal;

[0037] Determine that the voltage difference is greater than or equal to the switching threshold; and

[0038] In response to determining that the voltage difference is greater than or equal to the switching threshold, the controllable switch is operated in the off state.

[0039] Optionally, when the voltage difference is greater than or equal to the switching threshold, the controllable switch is prevented from switching from the off state to the on state. Optionally, when the voltage difference is greater than or equal to the switching threshold, the controllable switch is controlled to switch from the on state to the off state.

[0040] Optionally, the third aspect of the method receives a command signal for controlling the state of the controllable switch to an off state or an on state. Optionally, when the voltage difference is less than the switching threshold, the state of the controllable switch is controlled to an off state or an on state according to the command signal.

[0041] The optional features of the first aspect can be applied to the third aspect. Attached Figure Description

[0042] Figure 1a The design of the NLDMOS switch is shown.

[0043] Figure 1b A bidirectional NLDMOS switch is shown, comprising a first NLDMOS and a second NLDMOS connected in series.

[0044] Figure 1c The design of the GaN switch is shown.

[0045] Figure 2 A schematic block diagram of a solid-state switch, including a controllable switch and overvoltage protection circuitry, is shown.

[0046] Figure 3 A schematic block diagram of a first unidirectional overvoltage protection circuit with optional functions is shown.

[0047] Figure 4 A schematic block diagram of a first bidirectional overvoltage protection circuit with optional features is shown.

[0048] Figure 5a A schematic block diagram of an overvoltage protection circuit with optional features is shown.

[0049] Figure 5b Displaying optional features Figure 5a Example of a schematic block diagram for an overvoltage protection circuit.

[0050] Figure 6 This explains the process of protecting a controllable switch from high voltage.

[0051] Figure 7 A schematic block diagram of a circuit is shown that compares a differential signal with a comparison threshold and generates a control signal. Detailed Implementation

[0052] When configured as a switch, a controllable switch (such as a field-effect transistor (FET)) can be damaged by large channel voltages. For example, many FET devices are characterized by their “blocking voltage” or “drain-source breakdown voltage,” which is the absolute maximum rated voltage that the FET can handle between its channel terminals (e.g., the drain and source terminals) before entering the breakdown region and permanently failing. If a large voltage difference exists between the FET device's channel terminals, the FET device may be damaged when switching from the off state to the on state. In some cases, due to voltage transients, the voltage between the FET device's channel terminals may even exceed the rated breakdown voltage for short periods. This itself may not damage the FET device, but switching the FET device to the on state during these voltage transients (e.g., above the rated breakdown voltage) can damage it. These voltage transients may be more likely to occur when FET devices are used with precision measuring devices and high-voltage automated test equipment. Furthermore, when switching to the on state, the large voltage difference between the channel terminals of the controllable switch will result in a large current flow, forcing the controllable switch to dissipate power (through resistive heating), which can potentially cause damage. Furthermore, some controllable switches may have limited safe operating areas (e.g., DMOS switches). Therefore, when the controllable switch is in the ON state, the large voltage difference between its channel terminals may cause degradation over time, thus shortening the lifespan of the controllable switch. In such cases, additional circuitry can be used to prevent damage to the FET device.

[0053] Many types of controllable switches, such as various types of FETs (e.g., GaN-FET, SiC-FET, JFET, silicon metal oxide FET (MOSFET or MOS), diffused MOS (DMOS), lateral DMOS (LDMOS), vertical DMOS (VDMOS), etc.), can benefit from additional circuitry. For example, the controllable switch described below can be an LDMOS device configured to function as a switch. Furthermore, an LDMOS device can be a laterally doubly diffused MOS device. A DMOS device may imply a high-voltage device. For example, a voltage greater than 5V or greater than / equal to 10V can be considered high voltage.

[0054] As a brief, non-limiting overview of embodiments of the present invention, a novel solid-state switching device suitable for / used with high-voltage precision instruments is provided. The new solid-state switching device can block high voltage when off and will not be damaged if a control signal is generated to turn the solid-state switch on. The novel solid-state switching device may include a controllable switch and an overvoltage protection circuit configured to operate the controllable switch in the off state in response to comparing a voltage difference with a switching threshold.

[0055] Figure 1a , 1bExamples of controllable switches 10, 18, and 10a are shown in 1c and 1c, respectively.

[0056] Figure 1a The n-type LDMOS 10 (i.e., NLDMOS 10) and its parasitic diodes D1a and D1b are shown. The parasitic diodes D1a and D1b of the NLDMOS 10 are generated by the manufacturing process and exist in some types of DMOS switches. The parasitic diode D1a of the NLDMOS 10 (between the substrate and the isolation layer, such as the N-type buried layer (NBL)) can also exist in MOSFET switches.

[0057] The NLDMOS 10 includes a gate terminal 11, a drain terminal 12, and a source terminal 14. D1a is formed between the substrate and the isolation layer, as shown below. Figure 1a The NBL is coupled to an NBL terminal accessible to the circuit designer. The NBL terminal can typically be shorted to the drain terminal 12 for normal operation, which reduces noise from the substrate. This can be achieved by externally coupling the NBL terminal to the drain terminal 12, or by internally connecting the NBL to the drain. D1b is formed between the source and drain of the NLDMOS 10. Parasitic diodes D1a and D1b are formed between the P-type and N-type materials of the NLDMOS 10.

[0058] The same can be described for P-type LDMOS (PLDMOS) (or other P-type MOS switches).

[0059] LDMOS devices are suitable for high-voltage applications and can have source and channel regions formed using a double-diffusion process. As a result of the manufacturing process, the NLDMOS 10 is a unidirectional solid-state switch, and parasitic diodes D1a and D1b are formed between the high-voltage P-type and N-type materials. For example, when the gate terminal 11 of the (unidirectional) NLDMOS switch 10 receives a "turn-off" signal, current may still flow from the source terminal 14 to the drain terminal 12 through the (forward-biased) parasitic diode D1b.

[0060] Figure 1bA bidirectional NLDMOS switch 18 is shown, comprising a first NLDMOS 10 and a second NLDMOS 20 connected in series. The second NLDMOS 20 includes a gate terminal 21, a drain terminal 22, and a source terminal 24. The second NLDMOS 20 may be identical to the first NLDMOS 10. The source terminal 14 of the first NLDMOS 10 is coupled to the source terminal 24 of the second NLDMOS 20. The bidirectional NLDMOS switch 18 is arranged to prevent current from flowing in both directions in its off state: from the drain terminal 22 of the second NLDMOS 20 to the drain terminal 12 of the first NLDMOS 10; and from the drain terminal 12 of the first NLDMOS 10 to the drain terminal 22 of the second NLDMOS 20. If the gate-source voltage (Vgs) (between the gate terminals 11, 21 and the source terminals 14, 24 of the first LDMOS 10 and the second LDMOS 20) is less than the threshold voltage Vt, for example, 0V, then the first LDMOS 10 and the second LDMOS 20 can be switched to the off state. For example, the first LDMOS 10 and the second LDMOS 20 can be switched to the off state by coupling the gate terminals 11, 21 to the source terminals 14, 24, or by coupling both the gate terminals 11, 21 and the source terminals 14, 24 to the substrate (i.e., 0V).

[0061] If the voltage at the drain terminal 22 of the second NLDMOS 20 is greater than the voltage at the drain terminal 12 of the first NLDMOS 10, then when both the first and second NLDMOS 10 and 20 are in their on-state, the first and second NLDMOS 10 and 20 allow current to flow from the drain terminal 22 of the second NLDMOS 20 to the drain terminal 12 of the first NLDMOS 12. When both the first and second NLDMOS 10 and 20 are in their off-state, the second NLDMOS 20 prevents current from flowing from the drain terminal 22 of the second NLDMOS 20 to the source terminal 24 because the second NLDMOS 20 does not form a channel, and the parasitic diode D2b of the second NLDMOS 20 is reverse biased.

[0062] Figure 1c The n-type GaN 10a and its parasitic diode D1a are shown. The parasitic diode D1a of GaN 10a is generated by the manufacturing process and may exist in some types of GaN switches. The parasitic diode D1a of GaN 10a (between the substrate and the isolation layer, such as an N-type buried layer (NBL)) may also exist in other FET switches.

[0063] The GaN 10a includes a gate terminal 11a, a drain terminal 12a, and a source terminal 14a. D1a is formed between the substrate and the isolation layer, such as... Figure 1cThe NBL is coupled to an NBL terminal accessible to the circuit designer. The NBL terminal can be shorted to either the drain terminal 12a or the source terminal 14a for normal operation, which reduces noise from the substrate. This can be achieved by externally coupling the NBL terminal to the drain terminal 12a or the source terminal 14a, or by internally connecting the NBL to the drain or source. A parasitic diode D1a is formed between the P-type and N-type materials of the GaN 10a.

[0064] Figure 1c A capacitor with a parasitic drain substrate is shown. Parasitic source-drain capacitors ( Parasitic gate-source capacitors ( ) and parasitic gate-drain capacitors ( When GaN 10a is switched to the off state and the voltage at drain 12a is greater than the voltage at source 14a, Figure 1c The parasitic element shown is the main parasitic element.

[0065] P-type GaN (or other P-type FET switches) can be described similarly.

[0066] GaN devices are suitable for high-voltage applications. As a result of the manufacturing process, GaN 10a is a solid-state switch, and the parasitic diode D1a is formed between the high-voltage P-type and N-type materials.

[0067] although Figure 1a , 1b Controllable switches 10, 18, and 10a in 1c are shown as having an NBL terminal, but the NBL terminal is optional. For example, an isolating controllable switch may not include an NBL terminal.

[0068] Figure 2 Solid-state switching device 23 is shown, including overvoltage protection circuit 24 and controllable switch 25 (e.g., Figure 1a NLDMOS 10 Figure 1b 18. Bidirectional NLDMOS switch Figure 1c (GaN 10a). The controllable switch 25 includes control terminals 26 (e.g., 11, 21, 11a), first channel terminals 28 (e.g., 12, 12a), and second channel terminals 30 (e.g., 14, 22, 14a). The controllable switch 25 is arranged to switch between an off state and an on state based on a control signal 32 and / or a command signal 33. The output of an overvoltage protection circuit 24 is coupled to the control terminal 26 of the controllable switch 25. The on state of the controllable switch 23 allows current to flow between the first channel terminal 28 and the second channel terminal 30.

[0069] The overvoltage protection circuit 24 is configured to determine the voltage difference between a first voltage at the first channel terminal 28 and a second voltage at the second channel terminal 30. The voltage difference is compared to a switching threshold, and the overvoltage protection circuit 24 may only allow the controllable switch 25 to switch between its on and off states in response to the comparison.

[0070] In one example, overvoltage protection circuit 24 can generate an output signal 34 that operates controllable switch 25 in the open state. Controllable switch 25 can operate in response to comparing a voltage difference with a switching threshold.

[0071] The overvoltage protection circuit 24 is configured to set the control signal 32 to a protection value or a pass value. The overvoltage protection circuit can also be configured to receive a command signal 33 to control the state of the controllable switch 25 to an off state or an on state.

[0072] In response to determining that the voltage difference between the first channel terminal 28 and the second channel terminal 30 is less than a switching threshold, the overvoltage protection circuit 24 can set the control signal 32 to a pass value. When the control signal 32 is a pass value, the command signal 33 is configured to control the state of the controllable switch 25. For example, if the command signal 33 indicates that the controllable switch 25 is in the off state, the output signal 34 of the overvoltage protection circuit 24 can operate the controllable switch 25 to the off state. In another example, if the command signal 33 indicates that the controllable switch 25 is in the on state, the output signal 34 from the overvoltage protection circuit 24 can operate the controllable switch 25 to the on state. Therefore, the command signal 33 can be used to determine whether the output signal 34 from the overvoltage protection circuit 24 is generated and / or applied to the control terminal 26 of the controllable switch 25.

[0073] In response to determining that the voltage difference between the first channel terminal 28 and the second channel terminal 30 is greater than or equal to a switching threshold, the overvoltage protection circuit 24 can set the control signal 32 to a protection value. When the control signal 32 is set to the protection value, the overvoltage protection circuit 24 can be configured to prevent the controllable switch 25 from switching from the off state to the on state. When the control signal 32 is set to the protection value, the overvoltage protection circuit 24 can be configured to control the controllable switch 25 from the on state to the off state.

[0074] If the controllable switch 25 is in the off state, using control signal 32, the overvoltage protection circuit 24 can be configured to prevent the controllable switch 25 from switching from the off state to the on state in response to determining that the voltage difference is greater than or equal to the switching threshold. If the controllable switch 25 is in the on state, using control signal 32, the overvoltage protection circuit 24 can be configured to control the controllable switch 25 from the on state to the off state in response to determining that the voltage difference is greater than or equal to the switching threshold. The overvoltage protection circuit 24 is configured to generate an output signal 34 to operate the controllable switch 25 in the off state in response to determining that the voltage difference is greater than or equal to the switching threshold.

[0075] In other words, in one example, the overvoltage protection circuit 24 can be configured to receive a command signal 33 and, in response to determining that the voltage difference is less than a switching threshold, transmit the command signal 33 to the control terminal 26 of the controllable switch 25. Therefore, in this example, the command signal 33 can be an output signal 34. Furthermore, the overvoltage protection circuit 24 can prevent the transmission of the command signal 33 to the controllable switch 25 in response to determining that the voltage difference is greater than or equal to the switching threshold (to ensure that the controllable switch 25 is in its off state).

[0076] The switching threshold can be equal to (or substantially equal to 90%) the rated breakdown voltage of the controllable switch 25. The switching threshold can be based on the safe operating area (SOA) of the controllable switch. The characteristics of each controllable switch can be characterized by a datasheet including an SOA diagram. The switching threshold can also be based on the power dissipation rating of the controllable switch or the thermal system including the controllable switch. Depending on the package and thermal system including the controllable switch, a switching threshold based on the power dissipation rating can be used to limit / prevent excessive power.

[0077] Figure 3 The overvoltage protection circuit 24a is shown. The overvoltage protection circuit 24a also includes a first buffer 72, a second buffer 74, and a resistive element 76, such as a resistor.

[0078] The first buffer 72 includes an input terminal and an output terminal. The input terminal of the first buffer 72 is electrically coupled to a first channel terminal 28. The first buffer 72 is configured to detect a first voltage at the first channel terminal 28 and apply a first buffered voltage to a first terminal of the resistive element 76. The first buffered voltage may be proportional to the first voltage. The second buffer 74 includes an input terminal and an output terminal. The input terminal of the second buffer 74 is electrically coupled to a second channel terminal 30. The second buffer 74 may be configured to detect a second voltage at the second channel terminal 30 and apply a second buffered voltage to a second terminal of the resistive element 76. The second buffered voltage may be proportional to the second voltage.

[0079] In another example, the overvoltage protection circuit 24a can be configured to detect a first voltage at the first channel terminal 28 relative to a voltage reference, detect a second voltage at the second channel terminal 30 relative to a voltage reference, and generate a differential signal based on the first and second voltages.

[0080] Each of the first and second buffers 72 and 74 may be at least one of a unity-gain buffer (UGB), a voltage follower, a cascaded complementary source follower, and / or a dual-transistor buffer. Preferably, the output of each of the first buffer 72 and the second buffer 74 acts as a current source and / or a current sink.

[0081] In one example, the first buffer voltage is equal to the first voltage, and the second buffer voltage is equal to the second voltage. Therefore, the voltage across the resistive element 76 is equal to the voltage across the controllable switch 25. Thus, the overvoltage protection circuit 24a can be arranged to generate a differential signal based on the output of the first buffer 72 and the output of the second buffer 74. The differential signal can be a current signal flowing through the resistive element 76 and between the first buffer 72 and the second buffer 74. In one example, the output voltage of the second buffer 74 is greater than the output voltage of the first buffer 72, such that normal current is supplied by the second buffer 74, and the first buffer 72 absorbs current. Therefore, the current signal can be equal to the voltage difference divided by the resistance of the resistive element 76. Figure 3 In the example, the differential signal is detected by current mirror 78 (although other detection methods can also be used).

[0082] The voltage difference between the first and second channel terminals 28 and 30 can be indirectly compared to the switching threshold, for example, by comparing the differential signal ( or ) and comparison threshold (e.g. The comparison threshold can be related to the switch threshold by a predetermined relationship.

[0083] The overvoltage protection circuit 24 may also include a first current mirror arrangement 78.

[0084] The first current mirror arrangement 78 is configured to generate a current signal based on the current between the output of the first buffer 72 and the output of the second buffer 74. The first current mirror arrangement 78 is configured to generate a differential current signal based on the current flowing through the resistive element 76. ).

[0085] The first current mirror arrangement 78 can be arranged to have a gain equal to unity gain. A first current mirror can be provided such that the current differential signal ( The current differential signal is essentially equal to the current flowing through the resistive element 76. Therefore, the current differential signal ( The gain can be proportional to the voltage difference across the controllable switch 25. Alternatively, the first current mirror arrangement 78 can be arranged to have a gain less than unity gain.

[0086] like Figure 3 As shown, the first current mirror arrangement 78 includes a first current mirror assembly 78a and a second current mirror assembly 78b. The first current mirror assembly 78a is located between the output of the second buffer 74 and the resistor assembly 76. The second current mirror assembly 78b is arranged to generate a current signal based on the current flowing through the first current mirror assembly 78a. Alternatively, the first current mirror arrangement 78 may include any current mirror.

[0087] Figure 3 An example subcircuit 50 is shown, which receives a differential signal (( The sub-circuit 50 receives a control signal 32. As shown, the sub-circuit 50 also receives a command signal 33. The sub-circuit 50 can be arranged to generate an output signal 34 based on the control signal 32 and the command signal 33. However, it should be understood that the sub-circuit 50 is one of many alternatives that will be apparent to those skilled in the art.

[0088] Optional, expressed as current ( The differential signal can be converted to a voltage (e.g., by an optional converter 79, such as a resistor or resistive element) via an optional converter 79. (to make comparisons)

[0089] In one example, the differential signal can be provided to comparator 52 and compared with a comparison threshold ( The output of comparator 52 can be input to logic circuit 54 to allow or block the sending of command signal 33 to controllable switch 25. In one example, logic circuit 54 may include logic inverter 56 and AND gate 58 to generate output signal 34.

[0090] When a differential signal ( ) less than the comparison threshold ( When the instruction signal 33 is also "logic 0", the output of comparator 52 (e.g., control signal 32) is "logic 0" (e.g., pass value), and the output of logic inverter 56 is "logic 1". Therefore, due to the action of AND gate 58, if instruction signal 33 is also "logic 0", then output signal 34 is "logic 0", and if instruction signal 33 is also "logic 1", then output signal 34 is "logic 1". Conversely, when the differential signal (… ) greater than the comparison threshold ( When the instruction signal 33 is "logic 1" (e.g., control signal 32), the output of comparator 52 is "logic 1" (e.g., protection value), and the output of the logic inverter is "logic 0". Therefore, due to the AND gate 58, if the instruction signal 33 is "logic 1" or "logic 0", the output signal 34 will be "logic 0".

[0091] Alternatively, the differential signal can be provided to a processor, which can generate (or not generate) control signal 32 and / or output signal 34 based on the differential signal.

[0092] In one example, resistive element 76 is a resistor. In alternative examples, it can be a depletion-type FET (such as a JFET) or any resistive element. The value of resistive element 76 can be predetermined to produce a current proportional to the switching threshold.

[0093] In one example, the switching threshold could be 90V, the voltage difference could be 80V, and the resistor element 76 could be 10K ohms, therefore the differential signal ( The current can be 8mA (assuming unity-gain current mirror 78). The comparison threshold can be 9mA, and therefore has a predetermined relationship with the [90V] switching threshold (i.e., the relationship is proportional and based on the value of the resistor element 76, and optionally based on the gain of the current mirror 78).

[0094] Figure 3 The overvoltage protection circuit 24a is an example of a unidirectional overvoltage protection circuit. If the voltage at the second channel terminal 30 is greater than the voltage at the first channel terminal 28, the circuit may only generate a current differential signal. Alternatively, if the overvoltage protection circuit 24a is arranged to determine whether the voltage at the first channel terminal 28 is greater than that at the second channel terminal 30 and whether it exceeds the switching threshold, then the first current mirror arrangement 78 may be located between the output of the first buffer 72 and the resistive element 76.

[0095] Figure 4 The overvoltage protection circuit 24b is shown. Figure 4 The overvoltage protection circuit 24b, in addition to certain optional features, also displays Figure 3 All features of the overvoltage protection circuit 24a. The same reference numerals are used to indicate the same... Figure 3 Related identical / corresponding features will not be described in detail below. Overvoltage protection circuit 24b is... Figure 3 An alternative circuit to the overvoltage protection circuit 24a shown. A first buffer 72 is configured to be coupled to a first channel terminal 28 and receive the corresponding voltage. A second buffer 74 is configured to be coupled to a second channel terminal 30 and receive the corresponding voltage.

[0096] Solid-state switching device 23 may be a bidirectional solid-state switch. The bidirectional solid-state switch may include a bidirectional overvoltage protection circuit 24b. The first current mirror arrangement 78 is configured to generate a current signal if the voltage at the second channel terminal 30 is greater than the voltage at the first channel terminal 28. The bidirectional overvoltage protection circuit 24b also includes a second current mirror arrangement 88, configured to generate a current signal if the voltage at the first channel terminal 28 is greater than the voltage at the second channel terminal 30 of the controllable switch 25. The first and second diodes 82 and 84 are shown to prevent current signals (). (Generated via one of the current mirror arrangements 78 and 88) flows into the other of the current mirror arrangements 88 and 78, but instead flows to the current-to-voltage converter 79. For example Figure 4 As shown, the output of the current-to-voltage converter 79 is electrically coupled to the input of an optional level shifter 92 to generate a differential signal over a voltage range (e.g., 0 to 5V). The differential signal can be compared with a threshold ( (Compare)

[0097] The second current mirror arrangement 88 may be substantially similar to or different from the first current mirror arrangement 78. In one example, the second current mirror arrangement 88 may include a third current mirror assembly 88a and a fourth current mirror assembly 88b, wherein the third current mirror assembly 88a is located between the output of the first buffer 72 and the resistor assembly 76. The fourth current mirror assembly 88b is arranged to generate a current signal based on the current flowing through the third current mirror assembly 88a. ).

[0098] Figure 5a The overvoltage protection circuit 24c is shown. Figure 5a The overvoltage protection circuit 24c shows Figure 3 Some features of the overvoltage protection circuit 24a, and some optional features. The same reference numerals are used to denote... Figure 3 Related identical / corresponding features will not be described in detail below. Overvoltage protection circuit 24c is... Figure 3 , 4 The replacement circuits for the overvoltage protection circuits 24a and 24b shown are shown.

[0099] Figure 5a An overvoltage protection circuit 24c is shown, which is arranged to generate a control signal 32 configured to stop applying a command signal 33 in response to determining that the voltage difference between the first and second channel terminals 28, 30 is greater than or equal to a switching threshold. .

[0100] The overvoltage protection circuit 24c includes a first buffer 72, a second buffer 74, and a difference and threshold circuit 100. The difference and threshold circuit 100 is arranged to determine the difference between inputs 102 and 104, and then compare this difference with a difference threshold voltage to generate a control signal 32 (i.e., a binary output suitable for input to logic circuit 54). The control signal 32 can be used to block the command signal 33 in response to, for example, determining via logic circuit 54 that the voltage difference between the first and second channel terminals 28 and 30 is greater than or equal to a switching threshold. Optionally, as... Figure 5a As shown, the overvoltage protection circuit 24c also includes first and second level shifter circuits 92b, 92c for reducing the voltage generated by buffers 72, 74 to a low voltage range (i.e., 0 to 5V). Advantageously, this allows the components of the differential and threshold circuit 100 to use low-voltage (5V) components.

[0101] The first level shifter circuit 92b can be arranged to reduce the dynamic range of the first voltage at the first channel terminal to a first voltage range to generate a first voltage output 102. The second level shifter circuit 92c is arranged to reduce the dynamic range of the second voltage at the second channel terminal within the first voltage range to generate a second voltage output 104.

[0102] In another example, without the first and second level shifter circuits 92b and 92c, the inputs 102 and 104 of the differential and threshold circuit 100 can be substantially equal to the first voltage at the first channel terminal 28 and the second voltage at the second channel terminal 30, respectively.

[0103] Figure 5b Showing Figure 5a Example of an overvoltage protection circuit 24c. Figure 5b The overvoltage protection circuit 24c shows Figure 5a All features of the overvoltage protection circuit 24c, and some optional features. The same reference numerals are used to denote... Figure 5a Related identical / corresponding features will not be described in detail below.

[0104] Figure 5b The overvoltage protection circuit 24c shows the first and second level shifter circuits 92b and 92c implemented as voltage divider circuits. Figure 5b An example of the differential and threshold circuit 100 is also shown. Figure 5b The differential and threshold circuit 100 shown is unidirectional, and therefore it is configured to determine a voltage difference when a second voltage at the second channel terminal 30 is less than a first voltage at the first channel terminal 28. The scaling (also referred to as the size) of the transistors in the differential and threshold circuit 100 can be adjusted to appropriately set the comparison threshold. ).exist Figure 5b In the example, determine the comparison threshold ( This allows logic circuit 54 to be configured to prevent instruction signal 33 from being triggered when the voltage difference between the first and second channel terminals 28 and 30 exceeds a switching threshold.

[0105] exist Figure 5b In the example, the differential and threshold circuit 100 may include a first transistor 111, a second transistor 113, a third transistor 119, a current mirror transistor 115, and current source transistors 117, 117a, and 117b. The first current source transistor 117a is sized compared to the second current source transistor 117a, therefore the gate of the third transistor 119 will be "high" until the voltage difference between the voltage at the gate of the first transistor 111 and the current at the gate of the second transistor 113 is less than the comparison threshold. ).

[0106] Reference Figure 2 , 4 5a, 5b, solid-state switching device 23 can be based on such as Figure 6 The method shown is used to set the value of control signal 32. The value of control signal 32 (i.e., protection value, pass value) determines the output signal 34 of overvoltage protection circuit 24, which is applied to the control terminal 26 of controllable switch 25. Control signal 32 is suitable for operating controllable switch 25.

[0107] like Figure 6 As shown, the method of operating the controllable switch 25 may include the following steps:

[0108] S1: Determine the voltage difference between the first voltage of the first channel terminal 28 of the controllable switch 25 and the second voltage of the second channel terminal 30 of the controllable switch 25.

[0109] S2: Determine that the voltage difference is greater than or equal to the switching threshold.

[0110] S3: In response to determining that the voltage difference is greater than or equal to a switching threshold, operate the controllable switch in the off state. Control signal 32 can be set to a protection value to operate the controllable switch in the off state in response to determining that the voltage difference is greater than or equal to the switching threshold. Specifically, control signal 32 can be used to: prevent the controllable switch from the off state to the on state when the voltage difference is greater than or equal to the switching threshold; and / or control the controllable switch from the on state to the off state 25.

[0111] The method may also include one or more optional steps:

[0112] S4: Receive command signal 33, used to control the state of controllable switch 25 to the off state or the on state.

[0113] S5: Determine if the voltage difference is less than the switching threshold.

[0114] S6: In response to determining that the voltage difference is less than the switching threshold, the state of the controllable switch is controlled by a command signal. The control signal 32 can be set to a pass value, such that when the control signal 32 is at the pass value, the command signal 33 controls the state of the controllable switch 25.

[0115] Operating the controllable switch 25 in the off state includes: preventing the controllable switch 25 from switching to the on state if the controllable switch 25 is already in the off state; and / or controlling the controllable switch 25 to switch to the off state if the controllable switch is in the on state.

[0116] Figure 7 Provided reference Figure 3 Alternative sub-circuit 50a to the sub-circuit 50 shown and described. Alternative sub-circuit 50a receives the differential signal as current ( ), and generate an output signal 34. Alternate sub-circuit 50a is arranged to convert the differential signal ( ) and comparison threshold ( The comparison is performed to generate a control signal 32. The alternative sub-circuit 50a includes a current comparator node 120, a level shifter 122, a current mirror 124, and an inverter 126.

[0117] General

[0118] Figures 2 to 5b Each block in section 7 is shown and defined solely for illustrative purposes and is well understood; the algorithm or function represented by each block can be implemented in many other ways, provided the described functionality exists. For example, Figures 2 to 5b Blocks of any of the 7 can be combined and implemented as part of a circuit layout on a single integrated circuit, processor, or computer, or implemented by multiple circuit layouts, integrated circuits, processors, and / or computers.

[0119] exist Figure 4 In one example, the controllable switch 25 is shown as distinct from the overvoltage protection circuit 24. In another example, the overvoltage protection circuit 24 may include the controllable switch 25.

[0120] In one example, the controllable switch 25 may include a FET. The first channel terminal 28 may include the drain terminal of the FET. The switched capacitor of the controllable switch 25 may include the parasitic gate-source capacitor (Cgs) of the FET.

[0121] In one example, the controllable switch 25 is packaged together with the overvoltage protection circuit 24. In another example, the overvoltage protection circuit 24 may be provided separately / independently from the controllable switch 25, allowing the overvoltage protection circuit 24 to be provided to a number of different controllable switches. Therefore, the overvoltage protection circuit 24 is configured to be coupled (or coupleable) to: control terminals (e.g., 11, 21, 11a, 26) of the controllable switches (e.g., 10, 18, 10a, 25); first channel terminals (e.g., 12, 12a, 28) of the controllable switches (e.g., 10, 18, 10a, 25); and second channel terminals (e.g., 14, 22, 14a, 30) of the controllable switches (e.g., 10, 18, 10a, 25). The overvoltage protection circuit (e.g., 24, 24a, 24b, 24c) is also configured to generate a control signal 32 based on the received voltage difference between the first channel terminal and the second channel terminal of the controllable switch.

[0122] Each current mirror component (e.g., 78a, 78b, 88a, 88b) can be any suitable component, such as one or more transistors, such as FETs, MOSFETs, etc.

[0123] As described above, the overvoltage protection circuit 24 is configured to set the control signal 32 to a protection value in response to determining that the voltage difference is greater than or equal to a switching threshold, so as to operate the controllable switch 25 in the off state. In one example, this can be achieved by... or Compare with the threshold respectively The control signal 32 is set by comparing the voltage difference to determine whether it is greater than or equal to the switching threshold.

[0124] Unless the context explicitly requires otherwise, the words “comprising,” “including,” “containing,” and “comprising” should be interpreted as inclusive rather than exclusive or exhaustive throughout the specification and claims; that is, in the sense of “including but not limited to.”

[0125] The terms “coupled” or “connected” as commonly used herein refer to two or more elements that can be directly connected or connected through one or more intermediate elements. Furthermore, the terms “this article,” “above,” “below,” and similar terms as used in this application should refer to the entire application, and not any specific part of it. Where the context permits, singular or plural terms used in detailed descriptions may also include either the plural or singular, respectively. When referring to a list of two or more items, the word “or” is intended to encompass all of the following interpretations: any item in the list, all items in the list, and any combination of items in the list.

[0126] It should be understood that one or more features from one or more of the above embodiments may be combined with one or more features from one or more other of the above embodiments to form further embodiments within the scope of the appended claims.

[0127] Numbering Clauses

[0128] As a non-limiting example, some aspects of this disclosure are set forth in the following numbered clauses.

[0129] Clause 1. A solid-state switching device, comprising:

[0130] A controllable switch includes a control terminal, a first channel terminal, and a second channel terminal, and is arranged to switch between an off state and an on state, wherein in the on state, the switch allows current to flow between the first channel terminal and the second channel terminal; and

[0131] The overvoltage protection circuit is configured as follows:

[0132] Determine the voltage difference between the first voltage at the first channel terminal and the second voltage at the second channel terminal; and

[0133] In response to determining that the voltage difference is greater than or equal to the switching threshold, the control signal is set to a protection value to operate the controllable switch in the off state.

[0134] Clause 2. The solid-state switching device according to Clause 1, wherein the solid-state switching device is configured to use the control signal when the voltage difference is greater than or equal to a switching threshold:

[0135] Prevent the controllable switch from its off state to its on state; and / or

[0136] Control the controllable switch to switch from the on state to the off state.

[0137] Clause 3. A solid-state switching device according to any one of Clauses 1 or 2, wherein the overvoltage protection circuit is configured as follows:

[0138] Receives a command signal for controlling the state of the controllable switch to an off state or an on state; and

[0139] In response to determining that the voltage difference is less than the switching threshold, the control signal is set to a pass value, such that when the control signal is the pass value, the command signal controls the state of the controllable switch.

[0140] Clause 4. A solid-state switching device according to any of the preceding clauses, wherein the overvoltage protection circuit includes:

[0141] A first buffer includes an input terminal and an output terminal, wherein the input terminal is electrically coupled to the first channel terminal; and

[0142] The second buffer includes an input terminal and an output terminal, wherein the input terminal is electrically coupled to the second channel terminal.

[0143] Clause 5. A solid-state switching device according to Clause 4, wherein the overvoltage protection circuit is arranged to generate a differential signal based on the output of the first buffer and the output of the second buffer, wherein the voltage difference is compared with the switching threshold by comparing the differential signal with a comparison threshold, wherein the comparison threshold and the switching threshold have a predetermined relationship.

[0144] Clause 6. The solid-state switching device according to Clause 5, wherein the differential signal is a current signal.

[0145] Clause 7. A solid-state switching device according to any one of Clauses 5 or 6, wherein the differential signal is proportional to the voltage difference between the first channel terminal and the second channel terminal.

[0146] Clause 8. A solid-state switching device according to any one of Clauses 5 to 7, wherein the overvoltage protection circuit further comprises a resistor assembly, wherein the output of a first buffer is coupled to a first terminal of a resistor element, and wherein the output of a second buffer is coupled to a second terminal of the resistor assembly.

[0147] Clause 9. A solid-state switching device according to Clause 8, wherein the resistive element is a resistor, wherein the output voltage of the first buffer is proportional to the input voltage of the first buffer, and wherein the output voltage of the second buffer is proportional to the input voltage of the second buffer.

[0148] Clause 10. A solid-state switching device according to any one of Clauses 5 to 9, wherein the overvoltage protection circuit comprises:

[0149] The first current mirror arrangement is configured as follows:

[0150] A differential signal is generated based on the current between the outputs of the first buffer and the second buffer.

[0151] Clause 11. The solid-state switching device according to Clause 10, wherein the first current mirror arrangement is arranged to have a gain less than or equal to unity gain.

[0152] Clause 12. A solid-state switching device according to any one of Clauses 10 or 11, wherein the first current mirror arrangement includes a first current mirror assembly and a second current mirror assembly, wherein the first current mirror assembly is located between the output of the first buffer and the resistor assembly, wherein the second current mirror assembly is arranged to generate a differential signal based on the current flowing through the first current mirror assembly.

[0153] Clause 13. A solid-state switching device according to any one of Clauses 10 to 12, wherein the solid-state switching device is a bidirectional solid-state switch, wherein the first current mirror arrangement is configured to generate the differential signal if the voltage at the first channel terminal is greater than the voltage at the second channel terminal, and wherein...

[0154] The second current mirror arrangement is configured to generate the differential signal if the voltage at the second channel terminal is greater than the voltage at the first channel terminal.

[0155] Clause 14. The solid-state switching device according to Clause 13, wherein the second current mirror arrangement includes a third current mirror assembly and a fourth current mirror assembly, wherein the third current mirror assembly is located between the output of the second buffer and the resistor assembly.

[0156] Clause 15. The solid-state switching device according to Clause 14, wherein the fourth current mirror assembly is arranged to generate the differential signal based on the current flowing through the third current mirror assembly.

[0157] Clause 16. A solid-state switching device according to any one of Clauses 1 to 15, wherein the differential signal is a voltage signal.

[0158] Clause 17. An overvoltage protection circuit configured to be coupled to a control terminal of a controllable switch, a first channel terminal of the controllable switch, and a second channel terminal of the controllable switch, wherein the overvoltage protection circuit is configured to:

[0159] Determine the voltage difference between the first channel terminal and the second channel terminal; and

[0160] In response to determining that the voltage difference is greater than or equal to a switching threshold, a control signal is generated to set the controllable switch to operate in the off state.

[0161] Clause 18. A method of operating a controllable switch for overvoltage protection, the controllable switch including a control terminal, a first channel terminal, and a second channel terminal, and arranged to switch between an off state and an on state, wherein in the on state, the switch allows current to flow between the first channel terminal and the second channel terminal, the method comprising:

[0162] Determine the voltage difference between the first voltage at the first channel terminal and the second voltage at the second channel terminal;

[0163] Determine that the voltage difference is greater than or equal to the switching threshold; and

[0164] In response to determining that the voltage difference is greater than or equal to the switching threshold, the controllable switch is operated in the off state.

[0165] Clause 19. The method according to Clause 14 further includes, when the voltage difference is greater than or equal to the switching threshold:

[0166] Prevent the controllable switch from its off state to its on state; and / or

[0167] Control the controllable switch to switch from the ON state to the OFF state.

[0168] Clause 20. The method according to any one of Clauses 18 or 19 further includes:

[0169] Receives a command signal for controlling the state of the controllable switch to either the off or on state; and

[0170] When the voltage difference is less than the switching threshold, the state of the controllable switch is controlled to be either off or on according to the instruction signal.

Claims

1. A solid-state switching device, comprising: A controllable switch includes a control terminal, a first channel terminal, and a second channel terminal. The control terminal is operable to control the switching of the controllable switch between an off state and an on state, wherein in the on state, the switch allows current to flow between the first channel terminal and the second channel terminal. and The overvoltage protection circuit is configured as follows: Determine the voltage difference between the first voltage at the first channel terminal and the second voltage at the second channel terminal; and In response to determining that the voltage difference is greater than or equal to the switching threshold, the control signal is set to a protection value to operate the controllable switch in the off state.

2. The solid-state switching device of claim 1, wherein the solid-state switching device is configured to use the control signal when the voltage difference is greater than or equal to a switching threshold: Prevent the controllable switch from its off state to its on state; and / or, Control the controllable switch to switch from the on state to the off state.

3. The solid-state switching device according to claim 1, wherein the overvoltage protection circuit is configured as follows: Receives a command signal for controlling the state of the controllable switch to an off state or an on state; and In response to determining that the voltage difference is less than the switching threshold, the control signal is set to a pass value, such that when the control signal is the pass value, the command signal controls the state of the controllable switch.

4. The solid-state switching device according to claim 1, wherein the overvoltage protection circuit comprises: A first buffer includes an input terminal and an output terminal, wherein the input terminal is electrically coupled to the first channel terminal; and The second buffer includes an input terminal and an output terminal, wherein the input terminal of the second buffer is electrically coupled to the second channel terminal.

5. The solid-state switching device of claim 4, wherein the overvoltage protection circuit is arranged to generate a differential signal based on the output of the first buffer and the output of the second buffer, wherein the voltage difference is compared with the switching threshold by comparing the differential signal with a comparison threshold, wherein the comparison threshold and the switching threshold have a predetermined relationship.

6. The solid-state switching device according to claim 5, wherein the differential signal is a current signal.

7. The solid-state switching device according to claim 5, wherein the differential signal is proportional to the voltage difference between the first channel terminal and the second channel terminal.

8. The solid-state switching device of claim 5, wherein the overvoltage protection circuit further comprises a resistor assembly, wherein the output terminal of the first buffer is coupled to a first terminal of the resistor assembly, and wherein the output terminal of the second buffer is coupled to a second terminal of the resistor assembly.

9. The solid-state switching device of claim 8, wherein the resistive element is a resistor, wherein the output voltage of the first buffer is proportional to the input voltage of the first buffer, and wherein the output voltage of the second buffer is proportional to the input voltage of the second buffer.

10. The solid-state switching device according to claim 5, wherein the overvoltage protection circuit comprises: A first current mirror arrangement is configured to generate a differential signal based on the current between the output of the first buffer and the output of the second buffer.

11. The solid-state switching device of claim 10, wherein the first current mirror arrangement is arranged to have a gain less than or equal to unity gain.

12. The solid-state switching device of claim 10, wherein the first current mirror arrangement includes a first current mirror assembly and a second current mirror assembly, wherein the first current mirror assembly is located between the output of the first buffer and the resistor assembly, wherein the second current mirror assembly is arranged to generate the differential signal based on the current flowing through the first current mirror assembly.

13. The solid-state switching device of claim 10, wherein the solid-state switching device is implemented as a bidirectional solid-state switch, wherein the first current mirror arrangement is configured to generate the differential signal when the voltage at the first channel terminal is greater than the voltage at the second channel terminal, and wherein the overvoltage protection circuit further comprises: The second current mirror arrangement is configured to generate the differential signal when the voltage at the second channel terminal is greater than the voltage at the first channel terminal.

14. The solid-state switching device of claim 13, wherein the second current mirror arrangement includes a third current mirror assembly and a fourth current mirror assembly, wherein the third current mirror assembly is located between the output of the second buffer and the resistor assembly.

15. The solid-state switching device of claim 14, wherein the fourth current mirror assembly is arranged to generate the differential signal based on the current flowing through the third current mirror assembly.

16. The solid-state switching device according to claim 1, wherein the differential signal is a voltage signal.

17. An overvoltage protection circuit configured to be coupled to a control terminal of a controllable switch, a first channel terminal of the controllable switch, and a second channel terminal of the controllable switch, the control terminal being operable to control the switching of the controllable switch between an off state and an on state, wherein the overvoltage protection circuit is configured to: Determine the voltage difference between the first channel terminal and the second channel terminal; and In response to determining that the voltage difference is greater than or equal to a switching threshold, a control signal is generated to set the controllable switch to operate in the off state.

18. A method of operating a controllable switch for overvoltage protection, the controllable switch including a control terminal, a first channel terminal, and a second channel terminal, the control terminal being operable to control switching of the controllable switch between an off state and an on state, wherein in the on state, the switch allows current to flow between the first channel terminal and the second channel terminal, the method comprising: Determine the voltage difference between the first voltage at the first channel terminal and the second voltage at the second channel terminal; Determine that the voltage difference is greater than or equal to the switching threshold; and In response to determining that the voltage difference is greater than or equal to the switching threshold, the controllable switch is operated in the off state.

19. The method of claim 18, further comprising: when the voltage difference is greater than or equal to the switching threshold: Prevent the controllable switch from its off state to its on state; and / or Control the controllable switch to switch from the ON state to the OFF state.

20. The method of claim 18, further comprising: Receives a command signal for controlling the state of the controllable switch to either the off or on state; and When the voltage difference is less than the switching threshold, the state of the controllable switch is controlled to be either off or on according to the instruction signal.

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