A silicon carbide lateral super junction like finfet and a preparation method thereof

Abstract

This invention relates to a silicon carbide lateral superjunction-like FIN FET with a band field and its fabrication method. The device comprises, from bottom to top, a substrate, a P-type epitaxial layer, and an N-type epitaxial layer. The P-type and N-type epitaxial layers are patterned and etched to form a FIN structure. A P-type well region is formed by doping on one side of the N-type epitaxial layer. N+ doped regions are formed in the middle of the P-type well region and on the side of the N-type epitaxial layer away from the P-type well region. An undoped N-type epitaxial layer serves as a drift region. The device of this invention forms a vertically charged, charge-balanced, superjunction-like drift region with the underlying P-type epitaxial layer through a thin and highly doped N-type drift region. This allows the drift region to be completely depleted under reverse bias conditions, thereby achieving a superjunction-like effect of electric field homogenization and voltage withstand capability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a silicon carbide lateral superjunction-type FINFET and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), as a core material of third-generation semiconductors, has completely broken through the performance limits of silicon-based materials in high-voltage, high-temperature, and high-power electronic scenarios due to its superior properties such as wide bandgap, high thermal conductivity, high critical breakdown electric field, and high electron saturation drift velocity. This has made it the preferred substrate material for high-end fields such as new energy vehicle electronic control, photovoltaic inverters, and aerospace power systems. Compared to silicon-based devices, silicon carbide lateral metal-oxide-semiconductor transistors (MOSFETs) can achieve lower conduction losses and higher switching efficiency, possessing irreplaceable value in the miniaturization and lightweighting of high-power-density devices.

[0003] However, the commercial application of silicon carbide lateral MOSFET devices still faces multiple technical bottlenecks, with the core constraint stemming from the mismatch between traditional structural design and the intrinsic properties of the material. The operating principle of traditional lateral MOSFETs relies on the drift region bearing high voltage stress. However, to meet the demands of high-voltage operation, the drift region requires a low doping concentration design, leading to a significant increase in on-resistance and thus limiting device performance. To overcome the performance limitations of the drift region, lateral superjunction structures have become an important optimization direction for silicon carbide MOSFETs. This structure achieves complete charge balance through alternating P / N pillars, effectively homogenizing the electric field distribution and allowing the drift region to maintain high voltage withstand capability even in a highly doped state, thereby significantly reducing on-resistance. However, in actual fabrication, the process of lateral SiC superjunction structures is complex, making large-scale mass production difficult.

[0004] Furthermore, interface channel defects are another key factor limiting the performance of lateral silicon carbide MOSFETs. The SiC / SiO2 interface contains numerous dangling bonds, interface states, and trapped charges. These defects scatter charge carriers within the channel, resulting in an inversion channel electron mobility far lower than theoretical values. In lateral MOSFETs, the channel size is even smaller, making the impact of interface defects on carrier transport more significant. This directly leads to increased on-resistance and decreased switching efficiency, making it difficult to meet the low-loss requirements of high-performance devices. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a silicon carbide lateral superjunction-like FINFET and its fabrication method.

[0006] The main technical problems solved by this invention include: how to improve the electric field control capability and voltage withstand performance of the drift region in a lateral MOSFET device, and how to achieve higher current drive capability in the channel structure of a lateral MOSFET device with a smaller area.

[0007] Terminology Explanation: FINFET: refers to FinFET field-effect transistor.

[0008] FIN structure: refers to a fin-like structure.

[0009] MOCVD (Metal-Organic Chemical Vapor Deposition) refers to the metal-organic chemical vapor deposition method.

[0010] LPCVD refers to low-pressure chemical vapor deposition.

[0011] PECVD method: refers to plasma-enhanced chemical vapor deposition.

[0012] ALD method: refers to atomic layer deposition.

[0013] The technical solution of the present invention is as follows: This invention provides a silicon carbide lateral superjunction-like FIN FET, including a substrate, a FIN structure disposed on the substrate, the FIN structure including a P-type epitaxial layer and an N-type epitaxial layer from bottom to top; a P-type well region is formed by doping on one side of the N-type epitaxial layer, an N+ doped region is disposed in the middle of the P-type well region and on the side of the N-type epitaxial layer away from the P-type well region, a P+ doped region is disposed on the side of the P-type well region away from the N-type epitaxial layer, and the undoped N-type epitaxial layer serves as a drift region; Interlayer dielectric layer one is provided on the top surface and two sides of the drift region corresponding to the FIN structure, and interlayer dielectric layer one extends above the substrate; a three-sided surrounding gate dielectric is provided on one side above interlayer dielectric layer one and around the P-type well region corresponding to the FIN structure, and a gate metal is provided above the gate dielectric; interlayer dielectric layer two is provided above interlayer dielectric layer one and the gate metal; a source contact layer is provided around the P+ doped region corresponding to the FIN structure and its adjacent N+ doped region, and a source metal is provided above the source contact layer; a drain contact layer is provided around the other N+ doped region corresponding to the FIN structure, and a drain metal is provided above the drain contact layer.

[0014] In this invention, the portion of the gate metal located above the P-type well region serves as the gate, and the portion located above the interlayer dielectric layer serves as the field plate, used to control the electric field distribution in the drift region. The drift region exhibits superjunction-like characteristics, where the N-type epitaxial layer is thin and has a high doping concentration, forming a vertical charge balance structure with the underlying P-type epitaxial layer. This allows the drift region to achieve complete depletion under reverse bias conditions, realizing a superjunction-like electric field control capability.

[0015] According to a preferred embodiment of the present invention, the substrate is made of semi-insulating silicon carbide.

[0016] According to a preferred embodiment of the present invention, the material of the P-type epitaxial layer is silicon carbide, and the doping ions are aluminum ions or boron ions, with a doping concentration of 1×10⁻⁶. 15 ~1×10 17 cm -3 The thickness is 1~2μm.

[0017] According to a preferred embodiment of the present invention, the material of the N-type epitaxial layer is silicon carbide, and the doping ions are nitrogen ions or phosphorus ions, with a doping concentration of 1×10⁻⁶. 15 ~5×10 16 cm -3 The thickness is 1~2μm.

[0018] According to a preferred embodiment of the present invention, the doping ions in the P-type well region are aluminum ions, and the doping concentration is 1×10⁻⁶. 17 ~1×10 18 cm -3 The depth is 1~2μm.

[0019] According to a preferred embodiment of the present invention, the dopant ion in the N+ doped region is a nitrogen ion, and the doping concentration is greater than 1 × 10⁻⁶. 18 cm -3 The depth is 0.2~0.5μm.

[0020] According to a preferred embodiment of the present invention, the dopant ion in the P+ doped region is aluminum ion, and the doping concentration is greater than 1×10⁻⁶. 18 cm -3 The depth is 1~2μm.

[0021] According to a preferred embodiment of the present invention, both the first interlayer dielectric layer and the second interlayer dielectric layer are made of silicon dioxide and have a thickness of 0.5~1μm.

[0022] According to a preferred embodiment of the present invention, the material of the gate dielectric is one or more of silicon dioxide, silicon oxynitride, or hafnium dioxide, and the thickness is 20~100nm; the material of the gate metal is titanium nitride or polycrystalline silicon, and the thickness is 0.2~1μm.

[0023] According to a preferred embodiment of the present invention, the source contact layer and the drain contact layer are both made of nickel silicide and have a thickness of 20~100nm.

[0024] According to a preferred embodiment of the present invention, both the source metal and the drain metal are stacked structures composed of a thin metal barrier layer and a metal layer; the material of the thin metal barrier layer is one of titanium, titanium nitride, or tantalum, and the thickness is 50~150nm; the material of the metal layer is one of aluminum, aluminum-copper alloy, or copper, and the thickness is 1~3μm.

[0025] The present invention also provides a method for fabricating the above-mentioned silicon carbide lateral superjunction-like FINFET.

[0026] A method for fabricating a silicon carbide lateral superjunction-like FINFET with a band field plate includes the following steps: S1. Provide a substrate, and sequentially grow a P-type epitaxial layer and an N-type epitaxial layer on the substrate surface; S2. A first hard mask layer is fabricated above the N-type epitaxial layer. A P-type well region window is etched out using a mask, and then a P-type well region is fabricated within the window. S3. Remove the first hard mask layer, fabricate a second hard mask layer above the N-type epitaxial layer, use a mask to etch out the N+ doped region window, and then fabricate the N+ doped region within the window. S4. Remove the second hard mask layer, fabricate a third hard mask layer above the N-type epitaxial layer, use a mask to etch out the P+ doped region window, and then fabricate the P+ doped region within the window. S5. Remove the third hard mask layer, fabricate a carbon-based cover plate on top of the N-type epitaxial layer, anneal in an inert gas atmosphere to activate the implanted ions, and remove the carbon-based cover plate after annealing. S6. Pattern the N-type epitaxial layer and the P-type epitaxial layer to form a FIN structure; S7. A three-sided surrounding interlayer dielectric layer is formed on the top surface and two sides of the drift region corresponding to the FIN structure. S8. A gate dielectric is formed on one side of the interlayer dielectric layer and around the P-type well region corresponding to the FIN structure; a gate metal is formed above the gate dielectric. S9. An interlayer dielectric layer 2 is formed above the first interlayer dielectric layer and the gate metal; S10. A source contact layer is formed above the P+ doped region and its adjacent N+ doped region, and a drain contact layer is formed above another N+ doped region; a source metal is formed above the source contact layer, and a drain metal is formed above the drain contact layer.

[0027] According to a preferred embodiment of the present invention, in step S1, both the P-type epitaxial layer and the N-type epitaxial layer are grown by MOCVD.

[0028] According to a preferred embodiment of the present invention, in step S2, the material of the first hard mask layer is one of silicon dioxide, silicon nitride, or silicon oxynitride, and the first hard mask layer is formed by LPCVD, PECVD, or ALD. Preferably, the material of the first hard mask layer is silicon dioxide, and the first hard mask layer is formed by LPCVD.

[0029] According to a preferred embodiment of the present invention, in step S2, the P-type trap region is formed by ion implantation.

[0030] According to a preferred embodiment of the present invention, in step S3, the material of the second hard mask layer is one of silicon dioxide, silicon nitride, or silicon oxynitride, and the second hard mask layer is formed by LPCVD, PECVD, or ALD. Preferably, the material of the second hard mask layer is silicon dioxide, and the second hard mask layer is formed by LPCVD.

[0031] According to a preferred embodiment of the present invention, in step S3, the N+ doped region is formed by ion implantation.

[0032] According to a preferred embodiment of the present invention, in step S4, the material of the third hard mask layer is one of silicon dioxide, silicon nitride, or silicon oxynitride, and the third hard mask layer is formed by LPCVD, PECVD, or ALD. Preferably, the material of the third hard mask layer is silicon dioxide, and the third hard mask layer is formed by LPCVD.

[0033] According to a preferred embodiment of the present invention, in step S4, the P+ doped region is formed by ion implantation.

[0034] According to a preferred embodiment of the present invention, in step S5, the carbon-based cover plate is formed by photoresist thermal carbonization or PECVD.

[0035] According to a preferred embodiment of the present invention, in step S6, the FIN structure is formed by a dry etching process.

[0036] According to a preferred embodiment of the present invention, in step S7, the interlayer dielectric layer is formed by PECVD or LPCVD.

[0037] According to a preferred embodiment of the present invention, in step S8, the gate dielectric is formed by thermal oxidation, PECVD deposition of silicon oxynitride, or ALD deposition.

[0038] According to a preferred embodiment of the present invention, in step S8, the gate metal is formed by magnetron sputtering or LPCVD.

[0039] According to a preferred embodiment of the present invention, in step S9, the second interlayer dielectric layer is formed by PECVD or LPCVD.

[0040] According to a preferred embodiment of the present invention, in step S10, the source contact layer and the drain contact layer are formed sequentially by magnetron sputtering and annealing.

[0041] According to a preferred embodiment of the present invention, in step S10, both the source metal and the drain metal are formed by magnetron sputtering.

[0042] The technical features and beneficial effects of this invention are as follows: 1. The device of the present invention forms a vertically charged-balanced superjunction-like drift region by a thin and highly doped N-type drift region and its underlying P-type epitaxial layer, which enables the drift region to completely deplete free carriers under reverse bias conditions, thereby achieving electric field homogenization and voltage withstand improvement effects similar to a superjunction. While maintaining high voltage withstand capability, it effectively reduces the drift region resistance and achieves better conduction performance.

[0043] 2. The device of the present invention adopts a surround-type FIN three-dimensional channel structure, which significantly enhances the gate's control capability over the channel, reduces the channel resistance, and improves the switching characteristics of the device; this structure can achieve higher current drive capability in a smaller area, which is beneficial to improving the area efficiency of the device.

[0044] 3. In the device of the present invention, the superjunction-like drift region and the extended field plate structure work together to make the electric field distribution in the drift region more uniform, alleviate the electric field concentration effect, and improve the reliability and breakdown voltage of the device.

[0045] 4. The overall process flow of the device of the present invention is simple and highly controllable, avoiding complex processes such as deep trench filling in traditional superjunction structures, thus saving costs. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the overall structure of the silicon carbide lateral superjunction-type FINFET of the present invention; Figure 2 This is a cross-sectional schematic diagram of the silicon carbide lateral superjunction-like FINFET of the present invention; Figure 3 This is a schematic diagram of the device structure after step S1 in the fabrication method of the silicon carbide lateral superjunction-like FINFET of the present invention. Figure 4 This is a schematic diagram of the device structure after step S2 in the fabrication method of the silicon carbide lateral superjunction-like FINFET of the present invention. Figure 5 This is a schematic diagram of the device structure after step S3 in the fabrication method of the silicon carbide lateral superjunction band field plate FINFET of the present invention. Figure 6 This is a schematic diagram of the device structure after step S4 in the fabrication method of the silicon carbide lateral superjunction band field plate FINFET of the present invention. Figure 7 This is a schematic diagram of the device structure after step S6 in the fabrication method of the silicon carbide lateral superjunction band field plate FINFET of the present invention. Figure 8 This is a schematic diagram of the device structure after step S7 in the fabrication method of the silicon carbide lateral superjunction-like FINFET of the present invention. Figure 9This is a schematic diagram of the device structure after step S8 in the fabrication method of the silicon carbide lateral superjunction band field plate FINFET of the present invention. Figure 10 This is a schematic diagram of the device structure after step S9 in the fabrication method of the silicon carbide lateral superjunction band field plate FINFET of the present invention. Figure 11 This is a simulation structure diagram of the lateral superjunction MOSFET of Experimental Example 1 of the present invention; Figure 12 This is a simulation diagram of the conventional lateral MOSFET in Experiment Example 1 of the present invention; Figure 13 This is the breakdown curve of the lateral superjunction MOSFET in Experiment Example 1 of the present invention; Figure 14 Example 1 of this invention is a conventional lateral MOSFET (N-type epitaxial layer doping concentration 4×10⁻⁶). 16 cm -3 The breakdown curve of ) Figure 15 Example 1 of this invention is a conventional lateral MOSFET (N-type epitaxial layer doping concentration 2×10⁻⁶). 16 cm -3 The breakdown curve of ) Figure 16 This is the electric field distribution diagram of the lateral superjunction MOSFET during breakdown in Experiment Example 1 of the present invention; Figure 17 Example 1 of this invention is a conventional lateral MOSFET (N-type epitaxial layer doping concentration 4×10⁻⁶). 16 cm -3 Electric field distribution diagram during breakdown; Figure 18 Example 1 of this invention is a conventional lateral MOSFET (N-type epitaxial layer doping concentration 2×10⁻⁶). 16 cm -3 Electric field distribution diagram during breakdown; Figure 19 The resistance curve of the lateral superjunction MOSFET in Experiment Example 1 of this invention; Figure 20 Example 1 of this invention is a conventional lateral MOSFET (N-type epitaxial layer doping concentration 4×10⁻⁶). 16 cm -3 The resistance curve of ) Figure 21 Example 1 of this invention is a conventional lateral MOSFET (N-type epitaxial layer doping concentration 2×10⁻⁶). 16 cm -3 The resistance curve of ) Wherein: 1. Substrate; 2. P-type epitaxial layer; 3. N-type epitaxial layer; 4. P-type well region; 5. N+ doped region; 6. P+ doped region; 7. Interlayer dielectric layer one; 8. Gate dielectric; 9. Gate metal; 10. Interlayer dielectric layer two; 11. Source contact layer; 12. Source metal; 13. Drain contact layer; 14. Drain metal. Detailed Implementation

[0047] The present invention will be further described below with reference to embodiments, but is not limited thereto. The described embodiments are some embodiments of the present invention. Based on these embodiments, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. Unless otherwise specified in the embodiments of the present invention, all techniques existing in the art can be used. Example

[0049] like Figures 1-2 As shown, this embodiment provides a silicon carbide lateral superjunction-like FIN FET, including a substrate 1, a FIN structure disposed on the substrate 1, and the FIN structure including a P-type epitaxial layer 2 and an N-type epitaxial layer 3 from bottom to top; a P-type well region 4 is formed by doping on one side of the N-type epitaxial layer 3, and N+ doped regions 5 are disposed in the middle of the P-type well region 4 and on the side of the N-type epitaxial layer 3 away from the P-type well region 4, and a P+ doped region 6 is disposed on the side of the P-type well region 4 away from the N-type epitaxial layer 3, and the undoped N-type epitaxial layer 3 serves as a drift region; Interlayer dielectric layer 7 is provided on the top surface and two sides of the drift region corresponding to the FIN structure, and the interlayer dielectric layer 7 extends above the substrate 1; a three-sided surrounding gate dielectric layer 8 is provided on one side above the interlayer dielectric layer 7 and around the P-type well region 4 corresponding to the FIN structure; a gate metal 9 is provided above the gate dielectric layer 8; an interlayer dielectric layer 10 is provided above the interlayer dielectric layer 7 and the gate metal 9; a source contact layer 11 is provided around the P+ doped region 6 corresponding to the FIN structure and its adjacent N+ doped region 5; a source metal 12 is provided above the source contact layer 11; a drain contact layer 13 is provided around the other N+ doped region 5 corresponding to the FIN structure; a drain metal 14 is provided above the drain contact layer 13.

[0050] The gate metal 9 is located above the channel region (P-type well region 4) and serves as the gate, while the portion above the interlayer dielectric layer 7 serves as the field plate, used to control the electric field distribution in the drift region. The drift region exhibits superjunction-like characteristics, where the N-type epitaxial layer 3 is thin and has a high doping concentration, forming a vertical charge balance structure with the underlying P-type epitaxial layer 2. This allows the drift region to achieve complete depletion under reverse bias conditions, realizing a superjunction-like electric field control capability.

[0051] In this embodiment, the substrate 1 is made of semi-insulating silicon carbide.

[0052] In this embodiment, the material of the P-type epitaxial layer 2 is silicon carbide, the doping ion is aluminum ion, and the doping concentration is 1×10⁻⁶. 15 cm -3 The thickness is 2μm.

[0053] In this embodiment, the N-type epitaxial layer 3 is made of silicon carbide, and the doping ions are nitrogen ions with a doping concentration of 2 × 10⁻⁶. 15 cm -3 The thickness is 1μm.

[0054] In this embodiment, the doped ion in P-type well region 4 is aluminum ion, and the doping concentration is 1×10⁻⁶. 17 cm -3 The depth is 2μm.

[0055] In this embodiment, the dopant ion in N+ doped region 5 is nitrogen ion, and the doping concentration is greater than 7 × 10⁻⁶. 18 cm -3 The depth is 0.4μm.

[0056] In this embodiment, the dopant ion in P+ doped region 6 is aluminum ion, and the doping concentration is 2×10⁶. 18 cm -3 The depth is 2μm.

[0057] In this embodiment, both interlayer dielectric layer 7 and interlayer dielectric layer 10 are made of silicon dioxide and have a thickness of 0.5 μm.

[0058] In this embodiment, the gate dielectric 8 is made of silicon dioxide with a thickness of 100 nm; the gate metal 9 is made of titanium nitride with a thickness of 0.2 μm.

[0059] In this embodiment, both the source contact layer 11 and the drain contact layer 13 are nickel silicide with a thickness of 20 nm.

[0060] In this embodiment, both the source metal 12 and the drain metal 14 are stacked structures composed of a thin metal barrier layer and a metal layer; the material of the thin metal barrier layer is titanium and the thickness is 150nm; the material of the metal layer is aluminum and the thickness is 1μm.

[0061] The above-mentioned method for fabricating silicon carbide lateral superjunction-type FINFETs, such as... Figures 3-10 As shown, the steps are as follows: S1. Provide a substrate 1, and grow a P-type epitaxial layer 2 and an N-type epitaxial layer 3 sequentially on the surface of the substrate 1 by MOCVD.

[0062] S2. A first hard mask layer is fabricated on top of the N-type epitaxial layer 3 using LPCVD. A P-type well region 4 window is etched using a mask, and then the P-type well region 4 is fabricated within the window by ion implantation.

[0063] S3. Remove the first hard mask layer, and fabricate a second hard mask layer on top of the N-type epitaxial layer 3 using LPCVD. Use a mask to etch out the N+ doped region 5 window, and then fabricate the N+ doped region 5 within the window by ion implantation.

[0064] S4. Remove the second hard mask layer, and fabricate the third hard mask layer above the N-type epitaxial layer 3 using LPCVD. Use a mask to etch out the P+ doped region 6 window, and then fabricate the P+ doped region 6 within the window by ion implantation.

[0065] S5. Remove the third hard mask layer and fabricate a carbon-based cover plate on top of the N-type epitaxial layer 3 using photoresist thermal carbonization. Anneal the carbon-based cover plate in an inert gas atmosphere to activate the implanted ions. After annealing, remove the carbon-based cover plate.

[0066] S6. The N-type epitaxial layer 3 and the P-type epitaxial layer 2 are patterned and etched using a dry etching process to form a FIN structure.

[0067] S7. A three-sided surrounding interlayer dielectric layer 7 is formed on the top surface and two sides of the drift region corresponding to the FIN structure using the PECVD method.

[0068] S8. Silicon dioxide is grown on one side of the interlayer dielectric layer 7 and around the P-type well region 4 corresponding to the FIN structure by thermal oxidation to form the gate dielectric 8; titanium nitride is deposited on the gate dielectric 8 by magnetron sputtering to form the gate metal 9.

[0069] S9. An interlayer dielectric layer 10 is formed over the interlayer dielectric layer 7 and the gate metal 9 by PECVD, so that it completely covers the gate metal 9.

[0070] S10. The source region above the P+ doped region 6 and its adjacent N+ doped region 5, and the drain region above another N+ doped region 5, are formed by magnetron sputtering of metallic nickel and annealing to form source contact layer 11 and drain contact layer 13. Unreacted metallic nickel is removed using a piranha solution composed of 98% concentrated sulfuric acid and 30% hydrogen peroxide (volume ratio 3:1). A thin metal barrier layer and a metal layer above it are deposited on the source contact layer 11 and drain contact layer 13 by magnetron sputtering to form source metal 12 and drain metal 14. The device fabrication is complete. Example

[0071] A silicon carbide lateral superjunction-like FINFET, as in Example 1, differs in that: In this embodiment, the doping ions of the P-type epitaxial layer 2 are boron ions, and the doping concentration is 2 × 10⁻⁶. 16 cm -3 The thickness is 1μm.

[0072] In this embodiment, the doping ion of the N-type epitaxial layer 3 is phosphorus ion, and the doping concentration is 1×10⁻⁶. 16 cm -3 The thickness is 2μm.

[0073] In this embodiment, the doping concentration of P-type well region 4 is 1×10⁻⁶. 18 cm -3 The depth is 1μm.

[0074] In this embodiment, the doping concentration of N+ doped region 5 is 1×10⁻⁶. 19 cm -3 The depth is 0.5μm.

[0075] In this embodiment, the dopant ion in P+ doped region 6 is aluminum ion, and the doping concentration is 5 × 10⁶. 18 cm -3 The depth is 1.5μm.

[0076] In this embodiment, the thickness of interlayer dielectric layer 7 and interlayer dielectric layer 10 is 0.8 μm.

[0077] In this embodiment, the gate dielectric 8 is made of hafnium dioxide with a thickness of 30 nm; the gate metal 9 is made of polycrystalline silicon with a thickness of 0.8 μm.

[0078] In this embodiment, both the source contact layer 11 and the drain contact layer 13 are nickel silicide with a thickness of 100 nm.

[0079] In this embodiment, both the source metal 12 and the drain metal 14 are stacked structures composed of a thin metal barrier layer and a metal layer; the material of the thin metal barrier layer is titanium nitride with a thickness of 100 nm; the material of the metal layer is copper with a thickness of 2 μm.

[0080] The method for fabricating the silicon carbide lateral superjunction-like FINFET described above differs from that in Example 1 in that: In step S2, the material of the first hard mask layer is silicon nitride, which is formed by PECVD.

[0081] In step S3, the material of the second hard mask layer is silicon nitride, which is formed by PECVD.

[0082] In step S4, the material of the third hard mask layer is silicon nitride, which is formed by PECVD.

[0083] In step S5, a carbon-based cover plate is formed by depositing a carbon film using the PECVD method.

[0084] In step S7, the interlayer dielectric layer 7 is formed by LPCVD.

[0085] In step S8, the gate dielectric 8 is formed by depositing silicon oxynitride using the PECVD method.

[0086] In step S8, the gate metal 9 is formed by depositing polysilicon using the LPCVD method.

[0087] In step S9, the interlayer dielectric layer 10 is formed by LPCVD.

[0088] In step S10, unreacted metallic nickel is removed using a wet etching solution containing a mixture of 38% hydrochloric acid and 30% hydrogen peroxide in a volume ratio of 3:1.

[0089] Other conditions and steps are the same as in Example 1.

[0090] Experimental Example 1 A two-dimensional device model was created using Sentaurus TCAD. Figure 11 This is a simulation diagram of a lateral superjunction MOSFET. The substrate 1 is made of fully insulating silicon dioxide (since only the breakdown voltage and resistance of the device are being studied, a fully insulating silicon dioxide substrate is used instead of a semi-insulating silicon carbide substrate). The thickness of the p-type epitaxial layer 2 is 2 μm, and the doping concentration is 4 × 10⁻⁶. 16 cm -3 The thickness of the N-type epitaxial layer 3 (drift region) is 2 μm, and the doping concentration is 4 × 10⁻⁶. 16 cm -3 . Figure 12 This is a simulation diagram of a conventional lateral MOSFET, and... Figure 11 The difference between the lateral superjunction MOSFET and the other type is that the P-type epitaxial layer 2 is not provided, and the doping concentration of the N-type epitaxial layer 3 (drift region) is 4×10⁻⁶. 16 cm -3 and 2×10 16 cm -3 .

[0091] The breakdown voltage test condition is Vgs=0V, and the Vds voltage is continuously increased until the device breaks down. The results are as follows. Figures 13-18 As shown.

[0092] Depend on Figures 13-15 It was found that when the N-type epitaxial layer doping concentration is consistent, the breakdown voltage of a conventional lateral MOSFET is only 310V, while the breakdown voltage of a lateral superjunction MOSFET can reach 953V. For a conventional lateral MOSFET, only by reducing the N-type epitaxial layer doping concentration to 2×10⁻⁶ can the breakdown voltage be significantly reduced. 16 cm -3This is necessary to achieve a breakdown voltage of 855V, which will lead to an increase in on-resistance.

[0093] Depend on Figures 16-18 The results show that the electric field at the top of the N-type epitaxial layer of the lateral superjunction MOSFET during breakdown is smooth and does not change much, and the equipotential lines are relatively uniformly distributed. This indicates that the superjunction structure makes the electric field intensity uniformly distributed, which improves the voltage withstand level of the device.

[0094] The on-resistance test conditions are: Vgs = 12V, Vds is scanned from 0V to 5V, and the resistance is calculated based on the voltage near Vds = 2V. The results are as follows. Figures 19-21 As shown.

[0095] Depend on Figures 19-21 It was found that at a withstand voltage of around 900V, the conventional lateral MOSFET (N-type epitaxial layer doping concentration 2×10⁻⁶) 16 cm -3 The on-resistance of the MOSFET is nearly 1.6 times higher than that of the lateral superjunction MOSFET. The lateral superjunction MOSFET can achieve higher breakdown voltage and lower on-resistance, breaking through the constraint relationship between breakdown voltage and on-resistance in traditional device structures, and fully demonstrating the performance advantages of the lateral superjunction MOSFET.

[0096] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A silicon carbide lateral superjunction-like FINFET, characterized in that, The system includes a substrate, on which a FIN structure is disposed. The FIN structure includes, from bottom to top, a P-type epitaxial layer and an N-type epitaxial layer. A P-type well region is formed by doping on one side of the N-type epitaxial layer. N+ doped regions are disposed in the middle of the P-type well region and on the side of the N-type epitaxial layer away from the P-type well region. A P+ doped region is disposed on the side of the P-type well region away from the N-type epitaxial layer. The undoped N-type epitaxial layer serves as a drift region. Interlayer dielectric layer one is provided on the top surface and two sides of the drift region corresponding to the FIN structure, and interlayer dielectric layer one extends above the substrate; a three-sided surrounding gate dielectric is provided on one side above interlayer dielectric layer one and around the P-type well region corresponding to the FIN structure, and a gate metal is provided above the gate dielectric; interlayer dielectric layer two is provided above interlayer dielectric layer one and the gate metal; a source contact layer is provided around the P+ doped region corresponding to the FIN structure and its adjacent N+ doped region, and a source metal is provided above the source contact layer; a drain contact layer is provided around the other N+ doped region corresponding to the FIN structure, and a drain metal is provided above the drain contact layer.

2. The silicon carbide lateral superjunction-like FINFET according to claim 1, characterized in that, The substrate is made of semi-insulating silicon carbide.

3. The silicon carbide lateral superjunction-like FINFET according to claim 1, characterized in that, Includes one or more of the following conditions: a. The material of the P-type epitaxial layer is silicon carbide, and the doping ions are aluminum ions or boron ions, with a doping concentration of 1×10⁻⁶. 15 ~1×10 17 cm -3 The thickness is 1~2μm; b. The material of the N-type epitaxial layer is silicon carbide, and the doping ions are nitrogen ions or phosphorus ions, with a doping concentration of 1×10⁻⁶. 15 ~5×10 16 cm -3 The thickness is 1~2μm.

4. The silicon carbide lateral superjunction-like FINFET according to claim 1, characterized in that, Includes one or more of the following conditions: I. The doping ions in the P-type well region are aluminum ions, with a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 The depth is 1~2μm; II. The dopant ions in the N+ doped region are nitrogen ions, and the doping concentration is greater than 1 × 10⁻⁶. 18 cm -3 The depth is 0.2~0.5μm; III. The dopant ion in the P+ doped region is aluminum ion, and the doping concentration is greater than 1 × 10⁻⁶. 18 cm -3 The depth is 1~2μm.

5. The silicon carbide lateral superjunction-like FINFET according to claim 1, characterized in that, Both the first interlayer dielectric layer and the second interlayer dielectric layer are made of silicon dioxide, and both have a thickness of 0.5~1μm.

6. The silicon carbide lateral superjunction-like FINFET according to claim 1, characterized in that, The gate dielectric material is one or more of silicon dioxide, silicon oxynitride, or hafnium dioxide, with a thickness of 20~100nm; the gate metal material is titanium nitride or polycrystalline silicon, with a thickness of 0.2~1μm.

7. The silicon carbide lateral superjunction-like FINFET according to claim 1, characterized in that, Both the source and drain contact layers are made of nickel silicide and have a thickness of 20-100 nm.

8. The silicon carbide lateral superjunction-like FINFET according to claim 1, characterized in that, Both the source metal and the drain metal are stacked structures consisting of a thin metal barrier layer and a metal layer; the material of the thin metal barrier layer is one of titanium, titanium nitride or tantalum, and the thickness is 50~150nm; the material of the metal layer is one of aluminum, aluminum-copper alloy or copper, and the thickness is 1~3μm.

9. The method for fabricating a silicon carbide lateral superjunction-like FINFET according to claim 1, characterized in that, The steps include the following: S1. Provide a substrate, and sequentially grow a P-type epitaxial layer and an N-type epitaxial layer on the substrate surface; S2. A first hard mask layer is fabricated above the N-type epitaxial layer. A P-type well region window is etched out using a mask, and then a P-type well region is fabricated within the window. S3. Remove the first hard mask layer, fabricate a second hard mask layer above the N-type epitaxial layer, use a mask to etch out the N+ doped region window, and then fabricate the N+ doped region within the window. S4. Remove the second hard mask layer, fabricate a third hard mask layer above the N-type epitaxial layer, use a mask to etch out the P+ doped region window, and then fabricate the P+ doped region within the window. S5. Remove the third hard mask layer and fabricate a carbon-based cover plate on top of the N-type epitaxial layer; perform annealing in an inert gas atmosphere to activate the implanted ions, and remove the carbon-based cover plate after annealing. S6. Pattern the N-type epitaxial layer and the P-type epitaxial layer to form a FIN structure; S7. A three-sided surrounding interlayer dielectric layer is formed on the top surface and two sides of the drift region corresponding to the FIN structure. S8. A gate dielectric is formed on one side of the interlayer dielectric layer and around the P-type well region corresponding to the FIN structure; a gate metal is formed above the gate dielectric. S9. An interlayer dielectric layer 2 is formed above the first interlayer dielectric layer and the gate metal; S10. A source contact layer is formed above the P+ doped region and its adjacent N+ doped region, and a drain contact layer is formed above another N+ doped region. Source metal is formed above the source contact layer, and drain metal is formed above the drain contact layer.

10. The method for fabricating a silicon carbide lateral superjunction-like FINFET according to claim 9, characterized in that, Includes one or more of the following conditions: i. In step S1, both the P-type epitaxial layer and the N-type epitaxial layer are grown by MOCVD. ii. In step S2, the material of the first hard mask layer is one of silicon dioxide, silicon nitride, or silicon oxynitride, and the first hard mask layer is formed by LPCVD, PECVD, or ALD. iii. In step S2, the P-type trap region is formed by ion implantation; iv. In step S3, the material of the second hard mask layer is one of silicon dioxide, silicon nitride, or silicon oxynitride, and the second hard mask layer is formed by LPCVD, PECVD, or ALD. v. In step S3, the N+ doped region is formed by ion implantation; vi. In step S4, the material of the third hard mask layer is one of silicon dioxide, silicon nitride, or silicon oxynitride, and the third hard mask layer is formed by LPCVD, PECVD, or ALD. vii. In step S4, the P+ doped region is formed by ion implantation; viii. In step S5, the carbon-based cover plate is formed by photoresist thermal carbonization or PECVD. ix. In step S6, the FIN structure is formed by a dry etching process; x. In step S7, the interlayer dielectric layer is formed by PECVD or LPCVD. xi. In step S8, the gate dielectric is formed by thermal oxidation, PECVD deposition of silicon oxynitride, or ALD. xii. In step S8, the gate metal is formed by magnetron sputtering or LPCVD. xiii. In step S9, the second interlayer dielectric layer is formed by PECVD or LPCVD. xiv. In step S10, the source contact layer and the drain contact layer are formed sequentially by magnetron sputtering and annealing; xv. In step S10, both the source metal and the drain metal are formed by magnetron sputtering.

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