Semiconductor structure and method for forming a semiconductor structure
By designing an all-ring gate transistor structure, the integration challenges in the fabrication of multi-gate devices were solved, gate control was optimized and short-channel effects were reduced, thereby improving the performance of the semiconductor structure.
CN122248788APending Publication Date: 2026-06-19TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2026-02-12
- Publication Date
- 2026-06-19
AI Technical Summary
Technical Problem
The fabrication of multi-gate devices presents integration challenges, particularly in reducing short-channel effects and improving gate control, which are difficult to effectively address with existing technologies.
Method used
Employing a full-ring gate transistor structure, multiple nanostructures, isolation structures, and gate structures are formed on the substrate. By combining gate portions of different lengths and gate spacer layers, the gate structure design is optimized to reduce the risk of holes or gaps and improve performance.
Benefits of technology
It improves gate control capability, reduces short-channel effect, and enhances the overall performance of semiconductor structure.
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Smart Images
Figure CN122248788A_ABST
Abstract
A semiconductor and a method for forming the same are provided. The semiconductor structure includes: a plurality of nanostructures formed over a substrate; and an isolation structure formed over the substrate. The semiconductor structure includes: a gate structure formed on the nanostructures, the gate structure including a gate dielectric layer and a metal layer located above the gate dielectric layer. The semiconductor structure includes: a first gate spacer layer formed on the sidewalls of the gate structure, and the dielectric constant of the gate dielectric layer being greater than the dielectric constant of the first gate spacer layer. The gate structure includes a first portion located on the isolation structure and a second portion located below the topmost nanostructure, the first portion having a first gate length and the second portion having a second gate length, the first gate length being greater than the second gate length.
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