Light emitting diode and method of manufacturing the same

Abstract

This disclosure provides a light-emitting diode and its fabrication method, belonging to the field of optoelectronic manufacturing technology. The fabrication method includes: providing an epitaxial wafer and a driving substrate, the epitaxial wafer comprising a substrate, a buffer layer, and an epitaxial layer stacked sequentially; bonding the side of the epitaxial layer away from the substrate to the driving substrate, and removing the substrate; wet etching the buffer layer to roughen the surface of the buffer layer away from the driving substrate; and etching using the buffer layer as a mask to form a roughened surface on the surface of the epitaxial layer away from the driving substrate. Embodiments of this disclosure can form a roughened surface on the epitaxial layer without damaging the epitaxial layer due to wet etching, thereby improving light emission performance.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode and its fabrication method. Background Technology

[0002] Augmented reality (AR) glasses and other near-eye display devices place stringent demands on display panels: they must possess extremely high brightness, extremely small pixel size, ultra-high pixel density, and extremely low power consumption. Micro light-emitting diodes (Micro LEDs), with their self-emissive properties and advantages such as high brightness, high efficiency, and long lifespan, are considered the ideal light source for realizing next-generation AR displays.

[0003] When fabricating display panels using related technologies, an epitaxial layer is typically grown on a substrate first, and then the side of the epitaxial layer away from the substrate is bonded to a driving substrate. After the original substrate is removed, the epitaxial layer is etched to form multiple spaced micron-sized light-emitting units.

[0004] To improve light emission, wet etching is often used to roughen the surface of the epitaxial layer after substrate removal. However, the micron-sized light-emitting units are extremely small, and high-concentration etching solutions can easily damage the epitaxial layer structure. This problem has a particularly significant impact on AR displays, which have extremely high image quality requirements. Summary of the Invention

[0005] This disclosure provides a light-emitting diode and its fabrication method, which can form a roughened surface on the epitaxial layer without damaging the epitaxial layer due to wet etching, thereby improving the light emission effect. The technical solution is as follows: On one hand, this disclosure provides a method for fabricating a light-emitting diode, the method comprising: providing an epitaxial wafer, the epitaxial wafer comprising a substrate, a buffer layer and an epitaxial layer stacked sequentially; removing the substrate and wet etching the buffer layer to roughen the surface of the buffer layer away from the epitaxial layer; and etching using the buffer layer as a mask to form a roughened surface on the surface of the epitaxial layer near the buffer layer.

[0006] In one implementation of this disclosure, wet treatment of the buffer layer includes: etching the buffer layer with KOH solution, controlling the reaction temperature to be 60°C to 80°C, controlling the etching time to be 5 min to 10 min, and the concentration of the KOH solution to be 2.38% to 3%.

[0007] In another implementation of this disclosure, the buffer layer includes at least one of a GaN layer, an AlN layer, and an InN layer.

[0008] In another implementation of this disclosure, etching using the buffer layer as a mask includes: completely etching away the buffer layer until the remaining thickness of the epitaxial layer is 1.2 μm to 1.4 μm.

[0009] In another implementation of this disclosure, the substrate comprises a silicon-based substrate, and removing the substrate comprises etching the silicon-based substrate with a silicon etching solution, the silicon etching solution comprising a mixed solution of nitric acid, hydrofluoric acid and acetic acid.

[0010] In another implementation of this disclosure, the substrate includes a sapphire substrate, and the epitaxial wafer further includes an epitaxial sacrificial layer, wherein the epitaxial sacrificial layer, the buffer layer, and the epitaxial layer are sequentially stacked on the substrate; removing the substrate includes: laser decomposition of the epitaxial sacrificial layer, thereby peeling the substrate off from the buffer layer.

[0011] This disclosure provides a light-emitting diode (LED) fabricated using the fabrication method described above.

[0012] In another implementation of this disclosure, the light-emitting diode includes an epitaxial layer, one surface of which is roughened, and the thickness of the epitaxial layer is 1.2 μm to 1.4 μm.

[0013] In another implementation of this disclosure, the epitaxial wafer includes a substrate, a buffer layer, and an epitaxial layer stacked sequentially; the substrate includes a silicon-based substrate; or, the substrate includes a sapphire substrate, and the epitaxial wafer further includes an epitaxial sacrificial layer, wherein the epitaxial sacrificial layer, the buffer layer, and the epitaxial layer are stacked sequentially on the substrate.

[0014] In another implementation of this disclosure, the light-emitting diode further includes a driving substrate, wherein the surface of the epitaxial layer away from the roughened surface is bonded to the driving substrate.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: This embodiment of the disclosure solves the structural damage problem caused by wet etching of epitaxial layers in related technologies by reconstructing the roughening process path, and realizes controllable preparation of a high-uniformity roughened surface, which can improve the light extraction efficiency and image quality of AR displays.

[0016] In related technologies, the epitaxial layer surface is directly wet-etched after substrate removal. However, due to the tiny size of the micron-sized light-emitting units, high-concentration etching solutions easily penetrate, leading to damage to the units. In the embodiments of this disclosure, the buffer layer grown on the substrate itself contains numerous dislocations, grain boundaries, and point defects, resulting in poor crystal quality and weak corrosion resistance. Wet etching preferentially etches the buffer layer rather than the epitaxial layer, avoiding damage to the epitaxial layer and fundamentally solving the problem of easily damaged micron-sized light-emitting units.

[0017] The high defect density of the buffer layer results in uneven corrosion rates across its surface (with faster corrosion at dislocations), naturally forming a rough substrate after wet etching. Subsequent dry etching using this buffer layer as a mask leads to differentiated etching rates in different regions due to variations in buffer layer thickness. Thicker areas etch slowly, retaining more material, while thinner areas etch quickly, exposing more of the epitaxial layer. This masking effect further amplifies surface undulations, ultimately forming a highly uniform roughened surface on the epitaxial layer. Compared to the single control mode of directly etching the epitaxial layer in related technologies, the embodiments of this disclosure achieve precise control of the roughened morphology.

[0018] Furthermore, the uniform roughened surface increases the light scattering path, reduces total internal reflection loss, and improves light extraction efficiency. Meanwhile, the step-by-step processing of the buffer layer and epitaxial layer avoids structural damage and enhances the consistency of the electrical performance of the light-emitting units, making it particularly suitable for AR near-eye display scenarios with stringent requirements for pixel uniformity. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure; Figure 2 This is a state diagram of a method for manufacturing a display panel according to an embodiment of this disclosure; Figure 3 This is a schematic diagram of an epitaxial wafer provided in an embodiment of this disclosure; Figure 4 This is a state diagram of a method for manufacturing a display panel according to an embodiment of this disclosure; Figure 5 This is a state diagram of a method for manufacturing a display panel according to an embodiment of this disclosure; Figure 6 This is a schematic diagram of a display panel provided in an embodiment of this disclosure.

[0021] The markings in the diagram are explained as follows: 10. Light-emitting unit; 11. Substrate; 12. Buffer layer; 13. Epitaxial layer; 130. Roughened surface; 14. Epitaxial sacrificial layer; 20. Driving substrate; 30. Passivation layer; 40. Transparent conductive layer; 50. Connect the electrodes; 60. Light-collecting structure; 70. Bonded metal layer; 71. Bonded metal block. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0023] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0024] Figure 1 This is a flowchart illustrating a method for fabricating a light-emitting diode according to an embodiment of this disclosure. Figure 1 As shown, the preparation method includes: Step S11: Provide an epitaxial wafer.

[0025] The epitaxial wafer comprises a substrate, a buffer layer, and an epitaxial layer stacked sequentially.

[0026] For example, the epitaxial layer may include a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially.

[0027] The first semiconductor layer has a first conductivity type, the second semiconductor layer has a second conductivity type different from the first conductivity type, and the multiple quantum well layer is used to generate light through electron-hole recombination.

[0028] In this process, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0029] As an example, the first semiconductor layer is an n-type layer and the second semiconductor layer is a p-type layer.

[0030] Optionally, the first semiconductor layer is an n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 1 μm.

[0031] Optionally, the multiple quantum well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multiple quantum well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0032] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0033] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0034] Optionally, the second semiconductor layer is a p-type GaN layer. The thickness of the p-type GaN layer can be from 0.1 μm to 1 μm.

[0035] Optionally, a contact layer is also grown on the surface of the second semiconductor layer.

[0036] For example, the contact layer may be at least one of a metal layer and a transparent conductive layer.

[0037] For example, the contact layer can be an ITO layer or an IZO layer.

[0038] Step S12: Remove the substrate and wet-etch the buffer layer to roughen the surface of the buffer layer away from the substrate.

[0039] Step S13: Etch using the buffer layer as a mask to create a roughened surface on the epitaxial layer near the buffer layer.

[0040] This embodiment of the invention solves the structural damage problem caused by wet etching of the epitaxial layer in related technologies by reconstructing the roughening process path, realizes controllable preparation of a high-uniformity roughened surface, and improves the light extraction efficiency and image quality of AR displays.

[0041] In related technologies, the epitaxial layer surface is directly wet-etched after substrate removal. However, due to the tiny size of the micron-sized light-emitting units, high-concentration etching solutions easily penetrate, leading to damage to the units. In the embodiments of this disclosure, the buffer layer grown on the substrate itself contains numerous dislocations, grain boundaries, and point defects, resulting in poor crystal quality and weak corrosion resistance. Wet etching preferentially etches the buffer layer rather than the epitaxial layer, avoiding damage to the epitaxial layer and fundamentally solving the problem of easily damaged micron-sized light-emitting units.

[0042] The high defect density of the buffer layer results in uneven corrosion rates across its surface (with faster corrosion at dislocations), naturally forming a rough substrate after wet etching. Subsequent dry etching using this buffer layer as a mask leads to differentiated etching rates in different regions due to variations in buffer layer thickness. Thicker areas etch slowly, retaining more material, while thinner areas etch quickly, exposing more of the epitaxial layer. This masking effect further amplifies surface undulations, ultimately forming a highly uniform roughened surface on the epitaxial layer. Compared to the single control mode of directly etching the epitaxial layer in related technologies, the embodiments of this disclosure achieve precise control of the roughened morphology.

[0043] Furthermore, the uniform roughened surface increases the light scattering path, reduces total internal reflection loss, and improves light extraction efficiency. Meanwhile, the step-by-step processing of the buffer layer and epitaxial layer avoids structural damage and enhances the consistency of the electrical performance of the light-emitting units, making it particularly suitable for AR near-eye display scenarios with stringent requirements for pixel uniformity.

[0044] Taking a display panel as an example, the process of fabricating light-emitting diodes on the driving substrate of the display panel is as follows: Figure 2 This is a state diagram of a method for manufacturing a display panel according to an embodiment of this disclosure. Figure 2 As shown, the substrate removal process in step S12 may include the following steps: The first step is to form a bonding metal layer 70 on the surface of the epitaxial layer 13 away from the substrate 11 and the surface of the driving substrate 20.

[0045] A composite bonding metal layer 70, consisting of titanium, platinum, aluminum, and tin, is deposited sequentially on the surface of the epitaxial layer 13, the substrate 11, and the driving substrate 20 via magnetron sputtering. The thickness is controlled to be 10 nm to 20 nm to ensure a flat and dense interface, providing uniform active sites for bonding.

[0046] The second step is to bond the bonding metal layer 70 of the epitaxial layer 13 to the bonding metal layer 70 of the driving substrate 20.

[0047] Applying a temperature of 150°C to 200°C and a pressure of 0.5MPa to 1MPa in a vacuum environment causes the two metal layers to undergo thermo-press bonding, forming a robust interface with atomic-level interconnection, thus ensuring the reliability of the mechanical and electrical connection between the epitaxial layer 13 and the driving substrate 20.

[0048] In this embodiment of the disclosure, the substrate may include at least one of a silicon-based substrate and a sapphire substrate. The methods of removing the substrate differ when the substrate is either a silicon-based substrate or a sapphire substrate.

[0049] In one implementation, the substrate includes a silicon-based substrate, and the removal of the substrate in step S12 includes: etching the silicon-based substrate with a silicon etching solution.

[0050] The silicon etching solution includes a mixed solution of nitric acid, hydrofluoric acid, and acetic acid.

[0051] Specifically, this may include: preparing a mixed solution of nitric acid, hydrofluoric acid, and acetic acid in a volume ratio of 3:1:6, immersing the epitaxial wafer in a constant temperature bath at 25°C to 35°C, selectively etching the Si-Si bonds using HF, gradually dissolving the silicon substrate until it is completely removed, and monitoring the solution concentration and etching depth throughout the process.

[0052] The chemical etching is highly selective, reacting only on silicon substrates to avoid damaging the buffer layer 12 and epitaxial layer 13; the etching rate is controllable, making it suitable for rapid stripping of large-area silicon epitaxial wafers.

[0053] In another implementation, Figure 3 This is a schematic diagram of an epitaxial wafer provided in an embodiment of this disclosure. For example... Figure 3 As shown, the substrate includes a sapphire substrate, and the epitaxial wafer also includes an epitaxial sacrificial layer 14. The epitaxial sacrificial layer 14, the buffer layer 12 and the epitaxial layer 13 are sequentially stacked on the substrate 11.

[0054] For example, when preparing such an epitaxial wafer, a thin buffer layer 12 can be formed on a sapphire substrate first, then an epitaxial sacrificial layer 14 can be formed on the thin buffer layer 12, and then the buffer layer 12 and the epitaxial layer 13 can be grown sequentially on the epitaxial sacrificial layer 14.

[0055] Step S12, removing the substrate, includes: laser decomposition of the epitaxial sacrificial layer 14, causing the substrate 11 to peel off from the buffer layer 12.

[0056] Specifically, this can include: using a 355nm pulsed laser to focus the epitaxial sacrificial layer 14 (such as a GaN sacrificial layer), and decomposing it into gaseous products such as N2 through photothermal effect, thereby destroying the interfacial bonding force between the sacrificial layer and the buffer layer 12, and allowing the sapphire substrate to peel off naturally without mechanical stress.

[0057] Laser non-contact decomposition avoids the risk of breakage caused by the hard and brittle nature of sapphire, precisely controls the peeling interface, and preserves the integrity of the epitaxial layer 13 crystal to the maximum extent. It is suitable for the gentle removal of high-hardness sapphire substrates.

[0058] Figure 4 This is a state diagram of a method for manufacturing a display panel according to an embodiment of this disclosure. Figure 4 As shown, step S12 may include: using KOH solution to etch the buffer layer 12, controlling the reaction temperature to be 60℃ to 80℃, and controlling the etching time to be 5min to 10min.

[0059] For example, the concentration of the KOH solution is 2.38% to 3%.

[0060] The buffer layer 12 includes at least one of GaN, AlN and InN layers.

[0061] Specifically, this may include: preparing a KOH solution with a mass fraction of 2.38% to 3%, placing it in a constant temperature water bath at 60°C to 80°C and stirring it evenly; immersing the epitaxial wafer (with the buffer layer 12 facing out) after removing the substrate into the solution, maintaining uniform ion diffusion by magnetic stirring, monitoring the thickness change of the buffer layer 12 in real time, etching for 5 to 10 minutes, removing it, rinsing it with deionized water and drying it with nitrogen.

[0062] For the buffer layer 12 consisting of GaN, AlN, and InN layers, since InN is most easily corroded by KOH and AlN has slightly stronger corrosion resistance, its concentration can be finely adjusted according to the actual composition. For example, when InN is the main component, the lower limit of the mass fraction can be used, and when AlN is the main component, the upper limit of the mass fraction can be used to ensure that the corrosion rate is controllable.

[0063] Because the buffer layer 12 contains a large number of dislocations and grain boundary defects, KOH has a high corrosion rate on it and easily corrodes the buffer layer 12 to form a rough substrate, thus avoiding the epitaxial layer 13 from being eroded by high-concentration alkaline solution and solving the problem of direct corrosion of the epitaxial layer 13 damaging the light-emitting unit 10 in related technologies.

[0064] The combination of a temperature of 60°C to 80°C and a short time (5 min to 10 min) utilizes the accelerated corrosion characteristics at dislocation sites to form initial roughness, while preventing over-etching that could lead to the penetration of the buffer layer 12. During subsequent dry etching, the thickness difference of the buffer layer 12 works in conjunction with surface undulations to ultimately construct a highly uniform roughened surface 130 on the surface of the epitaxial layer 13, thereby improving the light extraction efficiency.

[0065] like Figure 4 As shown, step S13 may include: completely etching away the buffer layer 12 until the remaining thickness of the epitaxial layer 13 is 1.2 μm to 1.4 μm.

[0066] Specifically, this may include: dry etching using inductively coupled plasma (ICP) with a Cl2 / BCl3 / Ar mixed gas (flow ratio 3:2:1) as the etchant, and setting the RF power to 300W to 500W and the chamber pressure to 5mTorr to 10mTorr. The epitaxial wafer after wet etching is placed in the etching chamber, using a buffer layer 12 as a mask (whose surface has already exhibited initial roughness and thickness differences due to wet etching). During etching, the buffer layer 12 is preferentially removed, while a portion of the epitaxial layer 13 is simultaneously etched. The etching endpoint is monitored using in-situ optical emission spectroscopy. Etching stops when the signal from the buffer layer 12 disappears and the thickness of the epitaxial layer 13 decreases to 1.2μm to 1.4μm, ensuring precise and controllable etching depth.

[0067] After wet etching, the surface of the buffer layer 12 is uneven and the thickness is uneven (the dislocation region is thinner). During dry etching, the thin area is etched quickly and the thick area is etched slowly. This mask difference amplifies the surface undulations, and finally forms a highly uniform roughened surface 130 on the surface of the epitaxial layer 13, which can improve the light scattering efficiency.

[0068] Precisely controlling the remaining thickness of the epitaxial layer 13 (1.2 μm to 1.4 μm) to the optimal operating range of the light-emitting unit 10 avoids insufficient roughening due to excessively shallow etching, while also preventing damage to active regions such as quantum wells due to excessively deep etching, resulting in significantly enhanced electrical performance consistency. Furthermore, the buffer layer 12, which serves as a temporary mask, is completely removed after fulfilling its function, avoiding residual contamination.

[0069] Figure 5 This is a state diagram of a method for manufacturing a display panel according to an embodiment of this disclosure. Figure 5 As shown, the following steps may be included after step S13: The first step is to etch through the epitaxial layer 13 to form multiple spaced-apart light-emitting units 10.

[0070] Specifically, this includes: using ICP dry etching (Cl2 / Ar mixed gas), with a photoresist pattern as a mask, etching through the epitaxial layer 13 to the surface of the driving substrate 20 at preset intervals (such as 5μm to 10μm) to form independent micron-level light-emitting units 10.

[0071] The second step is to form a passivation layer 30 covering each light-emitting unit 10 on the surface of the driving substrate 20.

[0072] like Figure 5 As shown, the passivation layer 30 has through holes that expose each light-emitting unit 10.

[0073] For example, the passivation layer 30 may include at least one of a silicon oxide layer, a titanium oxide layer, and an epoxy resin layer.

[0074] For example, the passivation layer 30 may be a distributed Bragg reflector (DBR) layer.

[0075] The DBR layer may include multiple alternating layers of first material and multiple layers of second material, with different refractive indices for the first and second material layers.

[0076] For example, one of the first material layer and the second material layer is a TiO2 layer, and the other of the first material layer and the second material layer is a SiO2 layer.

[0077] Among them, the reflection band of the DBR has wavelength selectivity, which can accurately reflect light while allowing other stray wavelengths to pass through, thus enhancing the directional output of effective light.

[0078] Specifically, this includes: depositing a 1μm to 2.5μm thick SiO2 layer or SiN layer on the surface of the driving substrate 20 via PECVD. x The light-emitting unit 10 is covered by a passivation layer; then, after the through-hole pattern is defined by photolithography, each light-emitting unit 10 is exposed by BOE wet etching. The passivation layer 30 serves both as insulation protection and surface planarization to prevent leakage.

[0079] The third step is to form a transparent conductive layer 40 on the surface of the passivation layer 30 away from the driving substrate 20. The transparent conductive layer 40 is connected to each light-emitting unit 10 through a through hole.

[0080] Specifically, this includes: magnetron sputtering an ITO layer or an IZO layer with a thickness ≥2000 angstroms on the surface of the passivation layer 30, which makes 130-ohm contact with the roughened surface 10 of the light-emitting unit 10 through vias in the passivation layer 30. A transparent conductive layer 40 continuously covers the area of ​​the light-emitting unit 10, providing a common conductive substrate for subsequent connection of the electrode 50 and the light-harvesting structure 60.

[0081] As an example, the thickness of the transparent conductive layer 40 can be greater than or equal to 2000 angstroms. This thickness range ensures good conductivity for effective transmission of electrical signals while also providing high transparency to reduce obstruction of the light emitted by the light-emitting unit 10.

[0082] The fourth step is to form a connection electrode 50 on the surface of the transparent conductive layer 40 away from the driving substrate 20.

[0083] like Figure 5 As shown, the connecting electrode 50 is located in the gap between adjacent light-emitting units 10.

[0084] Specifically, this includes: fabricating a metal conductive mesh (connecting electrode 50) on the transparent conductive layer 40, designed as a high annular barrier structure, and embedding it into the gaps between the light-emitting units 10. The metal conductive mesh is connected to the electrodes of the driving substrate 20, which not only realizes the electrical connection between the light-emitting units 10, but also reduces lateral light escape by utilizing the highly reflective metal barrier, thereby improving light utilization.

[0085] Fifth step: a light-collecting structure 60 is formed on the surface of the transparent conductive layer 40 away from the driving substrate 20.

[0086] like Figure 5 As shown, the light-collecting structure 60 corresponds to at least one light-emitting unit 10, and the orthographic projection of the light-emitting unit 10 on the surface of the driving substrate 20 is located within the orthographic projection of the corresponding light-collecting structure 60 on the surface of the driving substrate 20.

[0087] Specifically, this involves spin-coating PDMS / PMMA or depositing SiO2 on the surface of the transparent conductive layer 40, and then photolithographically etching to form a microlens array / prism structure (light-collecting structure 60), ensuring that the orthogonal projection of each light-emitting unit 10 is covered by the corresponding light-collecting structure 60. This light-collecting structure 60 breaks total internal reflection through refraction / scattering, thereby improving light extraction efficiency.

[0088] This disclosure provides a light-emitting diode (LED) fabricated using the fabrication method described above.

[0089] Optionally, the light-emitting diode includes an epitaxial layer, one surface of which is roughened, and the thickness of the epitaxial layer is 1.2 μm to 1.4 μm.

[0090] Optionally, the epitaxial wafer provided in the fabrication method includes a substrate, a buffer layer and an epitaxial layer stacked sequentially; the substrate includes a silicon-based substrate.

[0091] Such a substrate removal process may include: etching the silicon-based substrate with a silicon etching solution.

[0092] The silicon etching solution includes a mixed solution of nitric acid, hydrofluoric acid, and acetic acid.

[0093] Specifically, this may include: preparing a mixed solution of nitric acid, hydrofluoric acid, and acetic acid in a volume ratio of 3:1:6, immersing the epitaxial wafer in a constant temperature bath at 25°C to 35°C, selectively etching the Si-Si bonds using HF, gradually dissolving the silicon substrate until it is completely removed, and monitoring the solution concentration and etching depth throughout the process.

[0094] The chemical etching is highly selective, reacting only on silicon substrates to avoid damaging the buffer layer 12 and epitaxial layer 13; the etching rate is controllable, making it suitable for rapid stripping of large-area silicon epitaxial wafers.

[0095] Optionally, the substrate provided in the preparation method includes a sapphire substrate, and the epitaxial wafer also includes an epitaxial sacrificial layer, wherein the epitaxial sacrificial layer, the buffer layer and the epitaxial layer are sequentially stacked on the substrate.

[0096] This substrate removal process includes: laser decomposition of the epitaxial sacrificial layer 14, causing the substrate 11 to peel off from the buffer layer 12.

[0097] Specifically, this can include: using a 355nm pulsed laser to focus the epitaxial sacrificial layer 14 (such as a GaN sacrificial layer), and decomposing it into gaseous products such as N2 through photothermal effect, thereby destroying the interfacial bonding force between the sacrificial layer and the buffer layer 12, and allowing the sapphire substrate to peel off naturally without mechanical stress.

[0098] Laser non-contact decomposition avoids the risk of breakage caused by the hard and brittle nature of sapphire, precisely controls the peeling interface, and preserves the integrity of the epitaxial layer 13 crystal to the maximum extent. It is suitable for the gentle removal of high-hardness sapphire substrates.

[0099] Optionally, the light-emitting diode also includes a driving substrate, on which the surface of the epitaxial layer away from the roughened surface is bonded. The epitaxial layer on the driving substrate can be etched to form multiple independent light-emitting units to form a display panel.

[0100] This disclosure provides a display panel that is fabricated using the fabrication method described above.

[0101] Figure 6 This is a schematic diagram of a display panel provided in an embodiment of this disclosure. For example... Figure 6 As shown, the display panel includes a driving substrate 20 and a plurality of light-emitting units 10 spaced apart on the driving substrate 20. Each light-emitting unit 10 is electrically connected to the driving substrate 20, and the surface of the light-emitting unit 10 away from the driving substrate 20 is a roughened surface 130.

[0102] Optionally, such as Figure 6 As shown, the display panel also includes a passivation layer 30 and a transparent conductive layer 40. The passivation layer 30 is on the surface of the driving substrate 20 and covers each light-emitting unit 10. The passivation layer 30 has through holes that expose each light-emitting unit 10. The transparent conductive layer 40 is located on the surface of the passivation layer 30 away from the driving substrate 20, and the transparent conductive layer 40 is connected to each light-emitting unit 10 through the through holes.

[0103] For example, the passivation layer 30 may include at least one of a silicon oxide layer, a titanium oxide layer, and an epoxy resin layer.

[0104] For example, the passivation layer 30 may be a distributed Bragg reflector (DBR) layer.

[0105] For example, the transparent conductive layer 40 is an ITO layer or an IZO layer.

[0106] As an example, the thickness of the transparent conductive layer 40 can be greater than or equal to 2000 angstroms. This thickness range ensures good conductivity for effective transmission of electrical signals while also providing high transparency to reduce obstruction of the light emitted by the light-emitting unit 10.

[0107] Optionally, such as Figure 6 As shown, the display panel also includes a connecting electrode 50, which is located on the surface of the transparent conductive layer 40 and in the gap between each light-emitting unit 10.

[0108] The connecting electrode 50 can establish an additional electrical connection channel in the gap between the light-emitting units 10, which facilitates the effective connection of multiple light-emitting units 10 or light-emitting units 10 in different regions, expands the flexibility of circuit connection, helps to realize complex display driving circuit layout, and meets diverse display needs.

[0109] Meanwhile, by rationally distributing electrical signals through the connecting electrode 50, each light-emitting unit 10 can obtain a more balanced driving current, reducing brightness differences caused by uneven current distribution, thereby improving the display uniformity of the entire display panel.

[0110] Furthermore, by utilizing the gaps between the light-emitting units 10 to set the connecting electrodes 50, the main display space of the display panel is not occupied additionally, thus avoiding the compression of the display area caused by adding connecting structures. This helps to achieve miniaturization and high pixel density design of the display panel and improves space utilization efficiency.

[0111] Optionally, such as Figure 6 As shown, the display panel also includes a plurality of bonding metal blocks 71 corresponding one-to-one with the light-emitting units 10. The bonding metal blocks 71 are located on the driving substrate 20, and each light-emitting unit 10 is located on the corresponding bonding metal block 71.

[0112] like Figure 5 As shown, the orthographic projection of the light-emitting unit 10 on the surface of the driving substrate 20 is located within the orthographic projection of the corresponding bonding metal block 71 on the surface of the driving substrate 20.

[0113] In the above implementation, the orthographic projection of the light-emitting unit 10 is located within the bonding metal block 71, ensuring precise alignment during bonding and preventing misalignment. The bonding metal block 71 provides a large contact area, enhancing the mechanical fixing strength between the light-emitting unit 10 and the driving substrate 20, preventing loosening or detachment after long-term use. Furthermore, the bonding metal block 71 directly supports the light-emitting unit 10, effectively reducing contact resistance, improving driving current transmission efficiency, reducing signal attenuation and heat generation, and ensuring stable driving and efficient light emission of the light-emitting unit 10.

[0114] Optionally, the driving substrate 20 may be a complementary metal-oxide-semiconductor (CMOS) integrated circuit board.

[0115] like Figure 6 As shown, an electrode block corresponding to each light-emitting unit 10 is provided on the driving substrate 20. Each light-emitting unit 10 has a bonding metal block 71 on the side near the driving substrate 20. The bonding metal block 71 of each light-emitting diode is electrically connected to the corresponding electrode block, so as to realize the purpose of the driving substrate 20 controlling the operation of each light-emitting diode.

[0116] For example, the bonding metal block 71 may include at least one of AuBe layer, Au layer, Ti layer, Ni layer and Pt layer.

[0117] Optionally, such as Figure 6As shown, the display panel also includes a light-collecting structure 60, which is located on the surface of the transparent conductive layer 40 away from the driving substrate 20.

[0118] Among them, the light-collecting structure 60 corresponds one-to-one with the light-emitting unit 10, and the orthographic projection of the light-emitting unit 10 on the surface of the driving substrate 20 is located within the orthographic projection of the corresponding light-collecting cone on the surface of the driving substrate 20; the surface of the end of the light-collecting structure 60 away from the driving substrate 20 is an arc surface.

[0119] In this embodiment, the top surface of the light-collecting structure 60 is designed as an arc surface. As a basic optical element, the arc surface has the characteristic of converging light. The arc surface can apply an initial deflection to the emitted light of the light-emitting unit 10, so that the originally dispersed light is concentrated in a more favorable direction.

[0120] Alternatively, the light-collecting structure 60 can be made of PDMS, PMMA, or silicon dioxide.

[0121] Polydimethylsiloxane (PDMS) is a flexible and bendable material; its light transmittance exceeds 90%, which reduces total reflection and makes it suitable for flexible Micro LED panels.

[0122] Among them, polymethyl methacrylate (PMMA) has a light transmittance of over 92%, good optical uniformity, moderate mechanical strength, good weather resistance, and is easy to mold, making it suitable for preparing light-collecting structures for large-area planar displays 60.

[0123] Among them, silicon dioxide has a light transmittance of over 95% and excellent thermal stability, and can be precisely processed into microstructures through etching, making it suitable for high-temperature processes and high-precision display requirements.

[0124] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. The data therein represents only illustrative examples. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method of fabricating a light emitting diode, characterized by, The preparation method includes: An epitaxial wafer is provided, the epitaxial wafer comprising a substrate (11), a buffer layer (12) and an epitaxial layer (13) stacked sequentially. Remove the substrate (11) and wet etch the buffer layer (12) to roughen the surface of the buffer layer (12) away from the epitaxial layer (13); Using the buffer layer (12) as a mask, etching is performed to form a roughened surface (130) on the surface of the epitaxial layer (13) near the buffer layer (12).

2. The preparation method according to claim 1, characterized in that, The wet treatment of the buffer layer (12) includes: The buffer layer (12) was etched with KOH solution, with the reaction temperature controlled at 60°C to 80°C and the etching time controlled at 5 min to 10 min. The concentration of the KOH solution was 2.38% to 3%.

3. The preparation method according to claim 2, characterized in that, The buffer layer (12) includes at least one of GaN, AlN and InN layers.

4. The preparation method according to claim 1, characterized in that, Etching using the buffer layer (12) as a mask includes: The buffer layer (12) is completely etched away until the remaining thickness of the epitaxial layer (13) is 1.2 μm to 1.4 μm.

5. The preparation method according to any one of claims 1 to 4, characterized in that, The substrate (11) includes a silicon-based substrate, and removing the substrate (11) includes: The silicon substrate is etched using a silicon etching solution, which includes a mixture of nitric acid, hydrofluoric acid, and acetic acid.

6. The preparation method according to any one of claims 1 to 4, characterized in that, The substrate (11) includes a sapphire substrate, and the epitaxial wafer further includes an epitaxial sacrificial layer (14). The epitaxial sacrificial layer (14), the buffer layer (12) and the epitaxial layer (13) are sequentially stacked on the substrate (11). Removing the substrate (11) includes: Laser decomposes the epitaxial sacrificial layer (14), causing the substrate (11) to peel off from the buffer layer (12).

7. A light-emitting diode, characterized in that, The light-emitting diode is fabricated using the fabrication method described in any one of claims 1 to 6.

8. The light-emitting diode according to claim 7, characterized in that, The light-emitting diode includes an epitaxial layer (13), one surface of which is a roughened surface (130), and the thickness of the epitaxial layer (13) is 1.2 μm to 1.4 μm.

9. The light-emitting diode according to claim 7 or 8, characterized in that, The epitaxial wafer comprises a substrate (11), a buffer layer (12), and an epitaxial layer (13) stacked sequentially. The substrate (11) comprises a silicon-based substrate; or, The substrate (11) includes a sapphire substrate, and the epitaxial wafer also includes an epitaxial sacrificial layer (14). The epitaxial sacrificial layer (14), the buffer layer (12) and the epitaxial layer (13) are sequentially stacked on the substrate (11).

10. The light-emitting diode according to claim 8, characterized in that, The light-emitting diode also includes a driving substrate (20), and the surface of the epitaxial layer away from the roughened surface (130) is bonded to the driving substrate (20).

Images