A pick-up path planning method for a die bonder in a die picking process and a die bonder in a die picking process

Abstract

This application discloses a die-attaching path planning method and a die-attaching machine for a die-attaching process, relating to the field of die-attaching path planning. The method includes acquiring parameter information of the chip and solder joints, including chip spacing, solder joint spacing, number of chip rows, and number of solder joint rows; determining the number of skip rows based on the ratio of chip spacing to solder joint spacing and the relationship between the number of chip rows and the number of solder joint rows; determining the number of die-attaching passes in a single operation based on the number of skip rows and the number of chip rows; dividing the substrate into a Turbo mode region and a Boost mode region according to the number of solder joint rows and the number of die-attaching passes in a single operation; employing proximity-based die-attaching and S-shaped die-attaching methods in the Turbo mode region; and employing a sequential die-attaching method in the Boost mode region. By optimizing the wafer's movement path relative to the probe, low displacement, high precision, and high efficiency chip die-attaching operations are achieved.

Description

Technical Field

[0001] This application relates to the field of crystal path planning technology, and in particular to a crystal path planning method and a crystal bonding machine for a crystal-piercing process. Background Technology

[0002] In the mass production of semiconductor products such as Mini / MicroLED, the chip picking process is a core packaging step. Its core process involves using flip-chip technology, eliminating the need for wafer stacking, and directly moving the wafer under a pick-and-place tool. The tool then picks up the chip and precisely attaches it to the substrate solder joint. The rationality of the chip picking path directly determines the wafer displacement, chip picking accuracy, and operational efficiency, and is key to solving the industry's pain points of high mass production costs and low efficiency.

[0003] The existing die-attaching path planning of die-attaching machines has the following defects: 1. Large wafer displacement: Traditional die-attaching paths do not take into account the "wafer-needle relative movement" characteristics of flip-chip technology, and do not consider the pitch matching and column adaptation relationship between the chip and the solder joint. This results in the wafer frequently moving a large distance along the X / Y axis, which not only increases positioning time but also easily leads to accumulated errors; 2. Insufficient die-attaching accuracy: Some path planning uses a Z-type die-attaching method, which is prone to reverse error when the motor moves in the opposite direction. Moreover, the vibration generated during the large wafer displacement will further reduce the positioning accuracy of the die-attaching needle, making it difficult to meet the requirements. 3. Low operational efficiency: The high precision requirement of MicroLED chips within ±10μm is not distinguished between high-efficiency chip picking areas and special areas. All solder joints adopt the same chip picking logic, which cannot maximize the efficiency advantage of chip picking nearby, resulting in the overall die bonding efficiency of the equipment being far below the design limit; 4. Poor adaptability: The existing algorithm does not cover various combination scenarios of chip and solder joint pitch and number of columns, and does not adapt to the characteristics of the chip bonding process "supporting full-size chips from 10μm to 800μm". For chips and substrates of different specifications, parameters need to be manually adjusted, resulting in insufficient compatibility and increased mass production debugging costs. Summary of the Invention

[0004] To address the aforementioned challenges, this application provides a method for planning the wafer pick-up path in a wafer bonding machine using a wafer-piercing process, as well as the wafer bonding machine itself. Through a combination strategy of "multi-scenario adaptive region division + nearby wafer pick-up + S-shaped bonding," the method achieves coordinated optimization of wafer displacement, wafer picking accuracy, and operational efficiency.

[0005] To achieve the above objectives, this application provides a method for planning the crystal picking path of a die bonder in a crystal-piercing process, comprising the following steps: S1: Obtain parameter information of the chip and solder joint, including chip spacing, solder joint spacing, number of chip columns and number of solder joint columns; S2: Determine the number of skip columns based on the ratio of chip pitch to solder joint pitch and the relationship between the number of chip columns and the number of solder joint columns; S3: Determine the number of die bonding passes per pass based on the number of skip columns and the number of chip columns; S4: Based on the number of solder joint rows and the number of die bonding passes per pass, the substrate is divided into Turbo mode region and Boost mode region; S5: In the Turbo mode region, the nearest crystal picking and S-shaped crystal bonding method are used; in the Boost mode region, the sequential crystal picking method is used.

[0006] Preferably, the specific method for determining the number of skip columns in step S2 is as follows: If the chip spacing is greater than the solder joint spacing, the skip column number is expressed as: ; in, For chip spacing, Spacing between solder joints; If the chip pitch is less than or equal to the solder joint pitch, the skip column number is expressed as: .

[0007] Preferably, when the chip pitch is less than or equal to the solder joint pitch, the method for determining the number of skip columns in step S2 further includes: Based on the relationship between the number of chip columns and the number of solder joint columns, it is divided into two sub-scenarios: the number of chip columns is less than the number of solder joint columns and the number of chip columns is greater than or equal to the number of solder joint columns. In both sub-scenarios, the die bonding scenario is divided into three cases based on the ratio of chip pitch to solder joint pitch: no skipping columns, skipping 1 column, and skipping 2 columns, corresponding to the number of skipping columns K=0, K=1, and K=2, respectively.

[0008] Preferably, the number of crystals solidified in a single step S3 is expressed as follows: ; in, Number of chip columns This represents the number of skip columns.

[0009] Preferably, the number q of Turbo mode regions in step S4 is represented as: ; The number of columns in the Boost mode region is represented as follows: ; in, This represents the column number of the solder joints; ⌊ ⌋ indicates rounding down to the nearest integer. This indicates the remainder.

[0010] Preferably, the nearest die picking in the Turbo mode area in step S5 includes: performing die bonding operations for one row of chips corresponding to multiple rows of solder joints by skipping columns.

[0011] Preferably, the S-type die bonding method in the Turbo mode region of step S5 includes: During the current row of die bonding process, the crystal ring remains fixed, and the die bonding of the solder joint in that row is completed by needle punching; When a new line is started, the crystal ring moves 0.5 times the solder joint spacing in the X-axis direction and moves the solder joint spacing in the Y-axis direction to align the last chip of the current line with the last solder joint of the next line. The needle penetration process completes the crystal fixation from the end of the next row towards the beginning, forming an S-shaped crystal fixation path.

[0012] Preferably, it also includes a region switching step: After completing the die bonding operation for a Turbo mode region, the control ring moves to the initial position of the next Turbo mode region, aligns the currently unused chip row with the first solder joint position of that region, and continues to perform the die bonding operation.

[0013] Preferably, it also includes a switching step when changing the substrate or wafer: When replacing a substrate or wafer, first process any chips or solder joints that were not completed in the previous round, and then execute a new round of path planning.

[0014] A die bonding machine for a crystal-piercing process includes a processor and a memory. The memory stores a computer program, and when the processor executes the computer program, it implements a die-picking path planning method for such a die bonding machine.

[0015] Therefore, the crystal picking path planning method and crystal bonding machine for the crystal-piercing process described above in this application have the following beneficial effects: 1. Minimize wafer displacement in this application: Combining the characteristics of the chip-piercing process where "the wafer moves to below the needle", by accurately matching the pitch and number of columns of the chip and solder joint, the efficient Turbo mode area is divided, and the wafer is picked up from the nearest location to reduce the invalid displacement of the wafer X / Y axis, which is more than 30% lower than the displacement of traditional algorithms. 2. The precision of die bonding in this application is significantly improved: the Turbo mode area adopts an S-shaped die bonding method to avoid reverse error caused by the reverse movement of the motor. Combined with the low displacement design to reduce wafer vibration, the die bonding positioning accuracy can reach within ±10μm, which meets the high precision packaging requirements of MicroLED chips and improves the yield to over 99.9999%. 3. This application significantly improves operational efficiency: it maximizes the proportion of the Turbo mode area (up to 100% Turbo mode), and the combination of nearby crystal picking and synchronous line switching improves efficiency by more than 40% compared to the traditional sequential crystal picking method. The overall UPH of the equipment can approach the design limit of 720K. 4. This application has strong adaptability: it covers a variety of combination scenarios of CP and JP, CColumn and JColumn, supports full-size chips from 10μm to 800μm, does not require manual parameter adjustment, and can adapt to the packaging requirements of various Mini / MicroLED products such as backlight and direct display. 5. This application has significant cost advantages: the low displacement design reduces equipment energy consumption and wear, and is compatible with the characteristics of the crystal spike process, which is "small in size and does not require wafer arrangement". Under the same production capacity, the equipment investment, power consumption and gas consumption are only less than 30% of the traditional solution. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the crystal picking path planning method for a crystal bonding machine using a crystal-piercing process according to this application. Figure 2 This is a schematic diagram of the chip and solder joint layout (skip 1 column) in this application; Figure 3 This is a schematic diagram of the region division in the embodiments of this application; Figure 4 This is a schematic diagram of the Turbo mode die-bonding ring movement in an embodiment of this application; Figure 5 This is a schematic diagram of area switching in an embodiment of this application. Detailed Implementation

[0017] The following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0018] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning as understood by a person of ordinary skill in the art to which this application pertains.

[0019] The terms "comprising" or "including," as used in this application, mean that the element preceding the term encompasses the element listed after the term, and do not exclude the possibility of encompassing other elements as well. The terms "inner," "outer," "upper," and "lower," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In this application, unless otherwise expressly specified and limited, the term "attached," etc., should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two elements or the interaction relationship between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0020] Example 1: A method for planning the crystal picking path in a crystal bonding machine for a crystal-piercing process, such as... Figure 1 As shown, it includes the following steps: S1: Obtain parameter information of the chip and solder joint, including solder joint spacing (JP), chip spacing (CP), number of chip columns (CColumn), and number of solder joint columns (JColumn). S2: Determine the number of skip columns based on the ratio of chip pitch to solder joint pitch and the relationship between the number of chip columns and the number of solder joint columns; Based on the relationship between CP and JP, and CColumn and JColumn, the process is divided into two core scenarios. In each scenario, Turbo mode / Boost mode regions are adaptively divided. All regions follow the die-piercing process logic of "wafer moving below the needle," as detailed below: Scenario 1: Chip pitch > solder joint pitch (i.e., CP > JP); Calculate the number of skip columns Based on the number of chip columns (CColumn) and the number of skip columns Calculate the number of die-bonded cells that can be covered in a single operation. Turbo mode region number Boost mode region column count .

[0021] Scenario 2: Chip pitch ≤ solder joint pitch (i.e., CP ≤ JP); Further subdivided by the size relationship between CColumn and JColumn and the Pitch ratio, including chip column count < solder joint count and chip column count. There are two sub-scenarios for the number of solder joint columns. Under each sub-scenarios, there are three cases based on the pitch ratio: no column skipping, skipping 1 column, and skipping 2 columns. The corresponding parameters are calculated and the regions are divided accordingly.

[0022] S3: Determine the number of die bonding passes per pass based on the number of skip columns and the number of chip columns; The number of crystals solidified in a single operation is expressed as: ; in, Number of chip columns This represents the number of skip columns.

[0023] S4: Based on the number of solder joint rows and the number of die bonding passes per pass, the substrate is divided into Turbo mode region and Boost mode region; The number q of Turbo mode regions is represented as: ; The number of columns in the Boost mode region is represented as follows: ; in, This represents the column number of the solder joints; ⌊ ⌋ indicates rounding down to the nearest integer. This indicates the remainder.

[0024] S5: In the Turbo mode region, the nearest crystal picking and S-shaped crystal bonding method are used; in the Boost mode region, the sequential crystal picking method is used.

[0025] Prioritize executing the "nearest die pick + S-shaped die bonding" in the Turbo mode area, moving the wafer within a small range under the probe to complete the die bonding, reducing invalid displacement and avoiding reverse errors; after the Turbo mode area is completed, execute the "sequential die pick" in the Boost mode area to ensure full coverage of the remaining solder joints.

[0026] Turbo mode region's nearest die pick-up includes: achieving die bonding operations for one row of chips corresponding to multiple rows of solder joints through a skip-column method.

[0027] The S-type die bonding methods in the Turbo mode region include: During the current row of die bonding process, the crystal ring remains fixed, and the die bonding of the solder joint in that row is completed by needle punching; When a new line is started, the crystal ring moves 0.5 times the solder joint spacing in the X-axis direction and moves the solder joint spacing in the Y-axis direction to align the last chip of the current line with the last solder joint of the next line. The needle penetration process completes the crystal fixation from the end of the next row towards the beginning, forming an S-shaped crystal fixation path.

[0028] Region switching steps: After completing the die bonding operation for a Turbo mode region, the control ring moves to the initial position of the next Turbo mode region, aligns the currently unused chip row with the first solder joint position of that region, and continues to perform the die bonding operation.

[0029] It also includes the switching steps when changing substrates or wafers: When replacing a substrate or wafer, first process any chips or solder joints that were not completed in the previous round, and then execute a new round of path planning.

[0030] Example 2: A die bonding machine for a crystal-piercing process includes a processor and a memory. The memory stores a computer program, and when the processor executes the computer program, it implements a die-picking path planning method for such a die bonding machine.

[0031] Example 3: This embodiment details the solution of this application as follows: Input parameters: CP=0.4675mm (chip horizontal pitch), JP=0.935mm (solder joint pitch), CColumn=160 (number of chip columns), CRow=200 (number of chip rows), JColumn=320 (number of solder joint columns), JRow=180 (number of solder joint rows), chip size: short side 0.0762mm, long side 0.1524mm, number of chips 32000, number of solder joints 57600 (meets requirements) , , (Skip 1 column), such as Figure 2 As shown; Parameter calculation: , , , ; Region division: 4 Turbo mode regions of 80 columns each (total 320 solder joints, Turbo mode regions account for 100%, no Boost mode regions), such as Figure 3 As shown; Die bonding: Turbo mode region die bonding process (4 Turbo mode regions of 80 columns each), such as... Figure 4 As shown: Area 1 (columns 1-80 solder joints): 1. Initial alignment: The wafer is moved under the probe, the first chip is aligned with the first solder joint in the first row, and the third chip is aligned with the second solder joint in the first row (skip 1 column); 2. First row die bonding: The die ring remains stationary, and the first row of 80 columns of solder joints is die bonded by needle punching; 3. Row wrapping operation: The crystal ring moves 0.5×JP=0.4675mm on the X-axis and JP=0.935mm on the Y-axis, aligning the 159th chip in the first row with the solder joint in the 80th column of the second row; 4. Second row of die bonding: With the crystal ring fixed in place, the needle is used to bond the crystal from column 80 in the second row to column 1. 5. Repeat the operation: Repeat the above steps to complete the die bonding of 180 rows of solder joints in area 1 (1 row of chips corresponds to 2 rows of solder joints, a total of 90 rows of chips are required). Area 2 (columns 81-160): 1. Region switching: such as Figure 5 As shown, the crystal ring moves to the initial position in region 2, aligning the chip in row 91 with the solder joint in column 81 of row 1; 2. Repeat die bonding: Following the die bonding process in area 1, complete the die bonding of 180 rows of solder joints in area 2; Area 3 (solder joints 161-240): 1. Region Switching: The crystal ring moves to the initial position of region 3, aligning the chip in row 181 with the solder joint in column 161 of row 1; 2. Repeat die bonding: Following the die bonding process in area 1, complete the die bonding of 180 rows of solder joints in area 3; Area 4 (columns 241-320): 1. Region Switching: The crystal ring moves to the initial position of region 4, aligning the chip in row 181 with the solder joint in column 241 of row 1; 2. Repeat die bonding: Following the die bonding process in area 1, complete the die bonding of 180 rows of solder joints in area 4; Displacement statistics: During the entire substrate die bonding process, the total displacement of the crystal ring along the X-axis is 360 line breaks × 0.4675 mm = 168.3 mm, which is much smaller than the displacement of the traditional algorithm (the traditional algorithm uses a sequential die-taking method, and the total displacement of the crystal ring is about 80,317.44 mm, while the displacement of the algorithm in this application is reduced by about 99.8%).

[0032] Results: The total wafer displacement is reduced by more than 99% compared to traditional algorithms, the crystal spike accuracy meets high precision requirements, the UPH reaches 360K, and the yield is 99.999%.

[0033] Therefore, this application adopts the above-mentioned die-picking path planning method and die-picking process die bonder to minimize the displacement of the wafer relative to the needle, reduce positioning errors and vibration effects, and adapt to the core requirement of "direct assembly" in the die-picking process; avoid motor reverse error, improve the positioning accuracy of the needle, and meet the high-precision packaging requirements of MicroLED chips within ±10μm; maximize the proportion of efficient die-picking area, improve the overall die-bonding efficiency, approach the highest UPH of the equipment design, and solve the efficiency pain point of massive chip transfer; adapt to full-size chips from 10μm to 800μm and various pitch and column combination scenarios, enhance the versatility of the algorithm, and reduce mass production debugging costs.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of this application, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of this application.

Claims

1. A method for planning the crystal picking path in a crystal bonding machine for a crystal-piercing process, characterized in that, Includes the following steps: S1: Obtain parameter information of the chip and solder joint, including chip spacing, solder joint spacing, number of chip columns and number of solder joint columns; S2: Determine the number of skip columns based on the ratio of chip pitch to solder joint pitch and the relationship between the number of chip columns and the number of solder joint columns; S3: Determine the number of die bonding passes per pass based on the number of skip columns and the number of chip columns; S4: Based on the number of solder joint rows and the number of die bonding passes per pass, the substrate is divided into Turbo mode region and Boost mode region; S5: In the Turbo mode region, the nearest crystal picking and S-shaped crystal bonding method are used; in the Boost mode region, the sequential crystal picking method is used.

2. The method for planning the crystal picking path of a crystal bonding machine for a crystal-piercing process according to claim 1, characterized in that: The specific method for determining the number of skip columns in step S2 is as follows: If the chip spacing is greater than the solder joint spacing, the skip column number is expressed as: ； in, For chip spacing, Spacing between solder joints; If the chip pitch is less than or equal to the solder joint pitch, the skip column number is expressed as: 。 3. The method for planning the crystal picking path of a crystal bonding machine for a crystal-piercing process according to claim 2, characterized in that: When the chip pitch is less than or equal to the solder joint pitch, the method for determining the number of skip columns in step S2 further includes: Based on the relationship between the number of chip columns and the number of solder joint columns, it is divided into two sub-scenarios: the number of chip columns is less than the number of solder joint columns and the number of chip columns is greater than or equal to the number of solder joint columns. In both sub-scenarios, the die bonding scenario is divided into three cases based on the ratio of chip pitch to solder joint pitch: no skipping columns, skipping 1 column, and skipping 2 columns, corresponding to the number of skipping columns K=0, K=1, and K=2, respectively.

4. The method for planning the crystal picking path of a crystal bonding machine for a crystal-piercing process according to claim 3, characterized in that: The number of crystals solidified in a single step S3 is expressed as follows: ； in, Number of chip columns This represents the number of skip columns.

5. The method for planning the crystal picking path of a crystal bonding machine for a crystal-piercing process according to claim 4, characterized in that: The number q of Turbo mode regions in step S4 is represented as: ； The number of columns in the Boost mode region is represented as follows: ； in, This represents the column number of the solder joints; ⌊ ⌋ indicates rounding down to the nearest integer. This indicates the remainder.

6. The method for planning the crystal picking path of a crystal bonding machine for a crystal-piercing process according to claim 5, characterized in that, Step S5, Turbo mode region local die picking, includes: using a skip column method to achieve die bonding operation for one row of chips corresponding to multiple rows of solder joints.

7. The method for planning the crystal picking path of a crystal bonding machine for a crystal-piercing process according to claim 6, characterized in that: The S-type die bonding method in the Turbo mode region in step S5 includes: During the current row of die bonding process, the crystal ring remains fixed, and the die bonding of the solder joint in that row is completed by needle punching; When a new line is started, the crystal ring moves 0.5 times the solder joint spacing in the X-axis direction and moves the solder joint spacing in the Y-axis direction to align the last chip of the current line with the last solder joint of the next line. The needle penetration process completes the crystal fixation from the end of the next row towards the beginning, forming an S-shaped crystal fixation path.

8. The method for planning the crystal picking path of a crystal bonding machine for a crystal-piercing process according to claim 7, characterized in that, It also includes the region switching step: After completing the die bonding operation for a Turbo mode region, the control ring moves to the initial position of the next Turbo mode region, aligns the currently unused chip row with the first solder joint position of that region, and continues to perform the die bonding operation.

9. The method for planning the crystal picking path of a crystal bonding machine for a crystal-piercing process according to claim 1, characterized in that: It also includes the switching steps when changing substrates or wafers: When replacing a substrate or wafer, first process any chips or solder joints that were not completed in the previous round, and then execute a new round of path planning.

10. A die bonding machine for a crystal-piercing process, characterized in that, It includes a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement a method for planning the crystal picking path of a crystal bonding machine for a crystal-piercing process as described in any one of claims 1-9.

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