Display device and method of manufacturing the same

Abstract

A display device and a method for manufacturing the same are disclosed. The display device includes: a substrate, comprising an active region having multiple pixel regions and a border region surrounding the active region; a mask layer located on the substrate in the border region and having multiple openings; a planarization layer formed on the entire surface of the substrate including the mask layer; an anode of a light-emitting element located on the planarization layer of each of the multiple pixel regions; a low-voltage power line located on the planarization layer of the border region and overlapping with the mask layer; an insulating film located on the planarization layer to expose the anode and the low-voltage power line; a light-emitting unit of the light-emitting element located on the low-voltage power line of the active region and the border region, wherein portions of the light-emitting unit corresponding to the multiple openings of the mask layer are removed; and a cathode of the light-emitting element located on the light-emitting unit of the light-emitting element and electrically connected to the low-voltage power line.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0189528, filed on December 18, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This invention relates to a display device, and more specifically, to a display device capable of achieving a narrow bezel and a method for manufacturing the same. Background Technology

[0003] Image display devices that display various types of information on screens are a core technology of the information and communication age, and are evolving into thinner, lighter, more portable, and higher-performance display devices. Therefore, display devices that can be manufactured with a light and thin structure are attracting attention.

[0004] Specific examples of such display devices include liquid crystal display (LCD) devices, quantum dot display (QD) devices, field-emitting diode (FED) display devices, and organic light-emitting diode (OLED) display devices.

[0005] Organic light-emitting display devices are self-emissive display devices that are advantageous not only in terms of power consumption due to their low-voltage operation, but also in terms of color performance, response speed, viewing angle, and contrast ratio (CR).

[0006] Research is underway to increase the active area and decrease the border area, which is the non-active area, in this type of organic light-emitting display device.

[0007] However, it is difficult to achieve a narrow bezel structure because the process margin of the common light-emitting layer in the bezel area needs to be considered in order to ensure display performance. Summary of the Invention

[0008] Therefore, the present invention aims to provide a display device and a method for manufacturing the same, which substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0009] One object of the present invention is to provide a display device and a method of manufacturing the same, wherein the cathode is in contact with the power line in a process margin area of ​​a common light-emitting layer in a bezel region.

[0010] Another object of the present invention is to provide a display device and a method for manufacturing the same, which achieves a narrow bezel by connecting a cathode and a power line in the process margin area of ​​the common light-emitting layer in the bezel area to eliminate the process margin area of ​​the common light-emitting layer in the bezel area.

[0011] The purpose of this invention is not limited to the above-described purposes, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0012] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art upon review of the following, or may be learned from practice of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures specifically pointed out in the written description, its claims, and the accompanying drawings.

[0013] To achieve these objectives and other advantages, according to the intent of the invention, as realized and broadly described herein, a display device includes: a substrate comprising an active region having a plurality of pixel regions and a border region surrounding the active region; a mask layer located on the substrate in the border region and having a plurality of openings; a planarization layer formed on the entire surface of the substrate including the mask layer; an anode of a light-emitting element located on the planarization layer of each of the plurality of pixel regions; a low-voltage power line located on the planarization layer of the border region and overlapping the mask layer; a dam insulating film located on the planarization layer to expose the anode and the low-voltage power line; a light-emitting unit of the light-emitting element located on the low-voltage power line of the active region and the border region, wherein portions of the light-emitting unit corresponding to the plurality of openings of the mask layer are removed; and a cathode of the light-emitting element located on the light-emitting unit of the light-emitting element and electrically connected to the low-voltage power line.

[0014] In another aspect of the invention, a method of manufacturing a display device includes: forming a thin-film transistor in each pixel region of a substrate, the substrate including an active region having a plurality of pixel regions and a border region surrounding the active region; forming a mask layer having a plurality of openings on the substrate in the border region; forming a planarization layer on the entire surface of the substrate including the thin-film transistor and the mask layer; forming an anode of a light-emitting element on the planarization layer of each pixel region such that the anode is electrically connected to the thin-film transistor; forming a low-voltage power line on the planarization layer of the border region such that the low-voltage power line overlaps with the mask layer; forming a diaphragm insulating film on the planarization layer to expose the anode and the low-voltage power line; forming a light-emitting unit of the light-emitting element on the low-voltage power line of the active region and the border region; removing portions of the light-emitting unit of the light-emitting element corresponding to the plurality of openings of the mask layer by irradiating a laser from a side of the substrate using the mask layer as a mask; and forming a cathode of the light-emitting element on the light-emitting unit of the light-emitting element and the border region such that the cathode is electrically connected to the low-voltage power line.

[0015] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0016] It should be understood that the foregoing general description and the following detailed description of the present invention are exemplary and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0017] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0018] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention;

[0019] Figure 2 This is a circuit diagram illustrating a pixel circuit in a display device according to an embodiment of the present invention;

[0020] Figure 3 This is a cross-sectional view showing the tolerance margin area of ​​the bezel region of a display panel according to an embodiment of the present invention;

[0021] Figure 4 This is a cross-sectional view of a display panel according to another embodiment of the present invention.

[0022] Figures 5 to 7 This is a plan view of the mask layer according to various embodiments of the present invention;

[0023] Figures 8A to 8E This is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention;

[0024] Figure 9 This is an enlarged cross-sectional view of an opening 228b of a mask layer 228 according to an embodiment of the present invention, and the low-voltage power line EVSS, light-emitting unit 320 and cathode 330 formed therefrom.

[0025] Figure 10 This is an enlarged cross-sectional view of an opening 228b of a mask layer 228 according to another embodiment of the present invention, and the low-voltage power line EVSS, light-emitting unit 320 and cathode 330 formed therefrom.

[0026] Figure 11 This is an enlarged cross-sectional view of an opening 228b of a mask layer 228 according to another embodiment of the present invention, and the low-voltage power line EVSS, light-emitting unit 320 and cathode 330 formed therefrom. Detailed Implementation

[0027] Preferred embodiments of the invention will be described in detail below with reference to the accompanying drawings. Throughout the specification, the same reference numerals denote substantially the same components.

[0028] In the following description, detailed descriptions of known techniques associated with this invention will be omitted if they unnecessarily obscure the spirit of the invention. Furthermore, component names used in the following description are chosen for ease of writing and may differ from the names of components in the actual product.

[0029] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to describe various embodiments of the present invention are given by way of example only, and therefore, the present invention is not limited to the illustrations in the drawings. Throughout the specification, similar reference numerals denote substantially similar components.

[0030] In this invention, when the terms "comprising," "including," etc., are used, other elements may be added unless the term "only" is used. The singular form is also intended to include the plural form, unless the context clearly indicates otherwise.

[0031] In the interpretation of the components included in the various embodiments of the present invention, unless otherwise explicitly described, the components are interpreted as including a range of error.

[0032] When describing various embodiments of the present invention, when describing positional relationships, for example, when using terms such as "above," "over," "below," "side," etc. to describe the positional relationship between two parts, one or more other parts may be located between these two parts, unless the terms "directly" or "immediately adjacent" are used.

[0033] When describing various embodiments of the present invention, when describing temporal relationships, for example, when using terms such as "after", "following", "next", "before" to describe temporal sequence relationships, discontinuous cases may also be included, unless "immediately" or "directly" is used.

[0034] In the description of the various embodiments of the present invention, although terms such as "first" and "second" may be used to describe various elements, these terms are used only to distinguish elements that are the same or similar to each other. Therefore, in this specification, unless otherwise mentioned, an element modified by "first" may be the same as an element modified by "second" within the technical scope of the present invention.

[0035] The features in the various embodiments of the present invention can be combined in part or in whole, and can be operated or driven in a technically related manner, and the various embodiments can be implemented independently of each other or can be implemented in combination.

[0036] In the following description, a display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0037] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0038] Figure 2This is a circuit diagram of pixels included in a display device according to an embodiment of the present invention.

[0039] like Figure 1 As shown, a display device according to an embodiment of the present invention includes: a display panel 100, which includes a plurality of pixels P; a controller 200; a gate driving circuit 300, which provides a gate signal to each of the plurality of pixels P; a data driving circuit 450, which provides a data signal to each of the plurality of pixels P; a power supply 500, which provides the power required to drive each of the plurality of pixels P; a level shifter 600, which adjusts the level of the gate signal applied to the gate driving circuit 300; and a sensing unit (not shown), which detects degradation of the plurality of pixels P. Here, the controller 200, the gate driving circuit 300, the data driving circuit 450, and the sensing unit can be collectively referred to as a control unit.

[0040] The display panel 100 may include an active area AA containing pixel P and a border area BZ surrounding the active area AA. The active area AA may have multiple pixel areas. A gate driving circuit 300 and a data driving circuit 450 may be disposed in the border area BZ. The gate driving circuit 300 may be disposed in the active area AA.

[0041] In the display panel 100, multiple gate lines SCL and EML intersect with multiple data lines DL, and pixel P is connected to the gate lines SCL and EML and the data lines DL. Specifically, a pixel P receives gate signals from the gate driving circuit 300 through the gate lines SCL and EML, receives data signals from the data driving circuit 450 through the data lines DL, and receives a high-level driving voltage VDD and a low-level driving voltage VSS from the power supply 500 through the driving voltage line PL.

[0042] Here, the scan signal SC and the light emission control signal EM are provided through gate lines SCL and EML, and the data voltage Vdata is provided through data line DL. Furthermore, according to various embodiments, the gate lines SCL and EML may include multiple scan lines SCL for providing the scan signal SC and a light emission control line EML for providing the light emission control signal EM. Additionally, the multiple pixels P may further include a power supply line VL to receive a reference voltage Vref or an initialization voltage Vini.

[0043] The TFT constituting each pixel P can be implemented as an oxide TFT including an oxide semiconductor layer. Oxide TFTs may be advantageous for large-area display panels 100 when considering electron mobility, process variations, etc. However, the invention is not limited thereto; the semiconductor layer of the TFT can be formed from amorphous silicon, polycrystalline silicon, etc.

[0044] Furthermore, each pixel P includes a light-emitting element (organic light-emitting diode) OLED and pixel circuitry for controlling the operation of the OLED. Here, the OLED may consist of an anode, a cathode, and a light-emitting layer disposed between the anode and the cathode.

[0045] Each pixel P may include a switching transistor ST, a driving transistor DT, a compensation circuit CC, a light-emitting element OLED, and a storage capacitor Cst, such as Figure 2 As shown.

[0046] The light-emitting element OLED can operate to emit light according to the driving current generated by the driving transistor DT.

[0047] The switching transistor ST performs a switching operation, causing the data signal Vdata provided via the data line DL to be stored as a storage voltage in the storage capacitor Cst in response to the scan signal SC or EM provided via the gate line SCL or EML. The storage capacitor can hold the data voltage for one frame.

[0048] The drive transistor DT can operate in response to the data voltage stored in the storage capacitor Cst to allow a constant drive current to flow between the high-level power line EVDD and the low-level power line EVSS.

[0049] The compensation circuit CC is a circuit used to compensate the threshold voltage of the driving transistor DT, and the compensation circuit CC may include one or more thin-film transistors and capacitors. The configuration of the compensation circuit CC may vary depending on the compensation method.

[0050] For example, Figure 2 The pixel P shown is configured as a 2T (transistor) 1C (capacitor) structure including a switching transistor ST, a driving transistor DT, a storage capacitor Cst, and a light-emitting element OLED. However, if a compensation circuit CC is added, the pixel P can be configured as various structures such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, and 8T1C.

[0051] The display panel 100 can be implemented as a non-transparent display panel or a transparent display panel. A transparent display panel can be used in transparent display devices that display images on a screen while the actual background is visible. The display panel 100 can be manufactured as a flexible display panel. A flexible display panel can be implemented as an organic light-emitting display panel using a plastic substrate.

[0052] Each pixel P can be a red, green, or blue pixel for color implementation. Each pixel P can also include white pixels. Each pixel P includes pixel circuitry.

[0053] A touch sensor may be disposed on the display panel 100. Touch input may be sensed using a separate touch sensor or by means of a pixel P. The touch sensor may be implemented as an on-cell or additional touch sensor disposed on the screen of the display panel 100, or as an in-cell touch sensor built into the display panel 100.

[0054] The controller 200 processes externally input image data (RGB) to fit the size and resolution of the display panel 100, and provides the processed image data (DATA) to the data driving circuit 450. The controller 200 uses externally input timing signals (CS, such as a dot clock signal, a data enable signal (DE), a horizontal synchronization signal (Hsync), and a vertical synchronization signal (Vsync)) to generate a gate control signal (GCS) and a data control signal (DCS). By providing the generated gate control signal (GCS) and data control signal (DCS) to the gate driving circuit 300 and the data driving circuit 450, the controller 200 controls the gate driving circuit 300 and the data driving circuit 450.

[0055] Depending on the device to be installed in the display device, the controller 200 can be configured to be combined with various processors, such as microprocessors, mobile processors, and application processors.

[0056] The host system can be any of the following: TV system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, and vehicle system.

[0057] The controller 200 can multiply the input frame rate by i and control the operating timing of the display panel driver at a frame rate of input frame rate × i (i is a positive integer greater than 0) Hz. In the case of NTSC (National Television Standards Committee), the input frame rate can be 60 Hz, while in the case of PAL (Progressive Line Inversion), the input frame rate can be 50 Hz.

[0058] Controller 200 generates signals that allow pixel P to be driven at various refresh rates. That is, controller 200 generates drive-related signals that allow pixel P to be driven in a variable refresh rate (VRR) mode or to switch between a first refresh rate and a second refresh rate. For example, controller 200 can drive pixel P at various refresh rates by simply changing the rate of the clock signal, generating a synchronization signal to create horizontal or vertical blank periods, or driving the gate drive circuit 300 in a mask manner.

[0059] The controller 200 generates a gate control signal GCS for controlling the operating timing of the gate drive circuit 300 and a data control signal DCS for controlling the operating timing of the data drive circuit 450 based on the timing signal CS received from the host system. The controller 200 controls the operating timing of the display panel driver to synchronize the gate drive circuit 300 and the data drive circuit 450.

[0060] The data driving circuit 450 receives image data DATA and a data control signal DCS from the controller 200. In response to the data control signal DCS from the controller 200, the data driving circuit 450 converts the image data DATA into a gamma-compensated voltage to generate a data voltage Vdata, and provides the data voltage Vdata to the data line DL of the display panel 100 synchronously with the scan signal SC. The data driving circuit 450 can be connected to the data line of the display panel 100 via COG (Chip-on-Glass) or TAB (Tape-on-Bond) technology.

[0061] The gate drive circuit 300 operates according to the gate control signal GCS input from the level shifter 600 to generate a gate signal. The gate signal is then sequentially provided to the gate line SCL or EML. The gate drive circuit 300 can be directly formed on the lower substrate of the display panel 100 in a GIP (Gate In-Panel Driver) structure. The gate drive circuit 300 can be formed in the active area AA (where a screen is displayed on the display panel 100) or in a non-active area outside the active area AA. The non-active area may include the bezel area BZ, or may be the same as the bezel area BZ. In the GIP structure, the level shifter 600 can be mounted on a printed circuit board (PCB) together with the controller 200.

[0062] Power supply 500 uses a DC-DC converter to generate the DC power required to drive the pixel array and display panel driver of display panel 100. The DC-DC converter may include a charge pump, rectifier, buck converter, boost converter, etc. Power supply 500 can receive a DC input voltage applied from a host system (not shown) and generate DC voltages such as gate on-state voltage VGL, gate off-state voltage VGH, high-level drive voltage VDD, and low-level drive voltage VSS. Gate on-state voltage VGL and gate off-state voltage VGH are provided to level shifter 600 and gate drive circuit 300. High-level drive voltage VDD and low-level drive voltage VSS are jointly provided to pixel P.

[0063] The level shifter 600 boosts the TTL (transistor-transistor-logic) level voltage of the gate control signal GCS input from the controller 200 to a gate high voltage VGH and a gate low voltage VGL capable of driving the TFTs formed in the display panel 100, and provides the boosted voltage to the gate drive circuit 300. The gate control signal GCS may include a start signal and a clock signal. The plurality of pixels P of the display panel 100 may include at least a first pixel, a second pixel, and a third pixel. The first pixel, the second pixel, and the third pixel may emit light of different colors. For example, the first pixel may be a red pixel, the second pixel may be a green pixel, and the third pixel may be a blue pixel.

[0064] Multiple pixels P can have the same size or different sizes. Considering the lifespan, color balance, etc. of the light-emitting elements OLEDs included in each of the first, second, and third pixels, the first, second, and third pixels can be designed to have different sizes.

[0065] Figure 3 This is a cross-sectional view showing the tolerance margin area of ​​the bezel area in a display panel according to an embodiment of the present invention.

[0066] like Figure 3 As shown, the display panel according to an embodiment of the present invention can be divided into an active area AA and a border area BZ.

[0067] In the active area AA of the display panel 100, multiple gate lines intersect with multiple data lines, and multiple pixels are connected to the gate lines and data lines.

[0068] like Figure 1 and Figure 2 As described, a switching transistor ST, a driving transistor DT, a compensation circuit CC, a light-emitting element OLED, and a storage capacitor Cst are disposed in each pixel.

[0069] For example, a switching transistor ST, a driving transistor DT, a compensation circuit CC, and a storage capacitor Cst are disposed on the substrate 101 of each pixel region. Furthermore, a planarization layer (not shown in the figures) may be disposed on the substrate 101 on which the switching transistor ST, driving transistor DT, compensation circuit CC, and storage capacitor Cst are disposed. The planarization layer may be disposed in the active region AA and the border region BZ.

[0070] A light-emitting element 300 having an anode 310, a light-emitting unit 320 and a cathode 330 laminated in sequence can be disposed on a planarization layer of each pixel area.

[0071] In each pixel region, the anode 310 can be disposed on the planarization layer and electrically connected to the driving transistor through a contact hole formed in the planarization layer. The low-voltage power line EVSS can be disposed on the planarization layer of the border region BZ.

[0072] The dam insulating film 150 may be disposed on a planarization layer on which the anode 310 and the low-voltage power line EVSS are formed. The dam insulating film 150 may define a light-emitting area EA within each pixel area. For example, the light-emitting area EA of each pixel area is exposed by the dam insulating film 150, and the remaining portion is covered by the dam insulating film 150.

[0073] Furthermore, the light-emitting unit 320 is disposed on the anode 310 and the insulating film 150 and is in contact with the anode 310. The light-emitting unit 320 can generate light with a brightness corresponding to the voltage difference between the anode 310 and the cathode 330. For example, the light-emitting unit 320 may include a light-emitting material layer (EML). The light-emitting material layer may include organic light-emitting materials, inorganic light-emitting materials, or mixed light-emitting materials. For example, the display device according to an embodiment of the present invention may be an organic light-emitting display device including organic light-emitting materials. The light-emitting unit 320 may have a multilayer structure. For example, the light-emitting unit 320 may also include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0074] In the configuration of the light-emitting unit 320, the light-emitting material layer EML can be separately disposed for each pixel area, and at least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), or electron injection layer (EIL) can be jointly disposed in the pixel area. The hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) can be referred to as the common light-emitting layer. The common light-emitting layer can extend to the border area.

[0075] The cathode 330 may be disposed on the light-emitting unit 320. The cathode 330 may include a conductive material. The cathode 330 may include a material different from that of the anode 310.

[0076] The cathode 330 may extend into the border region BZ. The cathode 330 may be electrically connected to the low-voltage power line EVSS in the border region BZ. For example, the cathode 330 may be electrically connected to the low-voltage power line EVSS through a contact hole formed in the dam insulating film 150 in the border region BZ.

[0077] An encapsulation structure 400 that inhibits moisture penetration may be further disposed on the light-emitting element 300. The encapsulation structure 400 can prevent external moisture or oxygen from penetrating into the light-emitting unit 320, which is susceptible to external moisture or oxygen. For this purpose, the encapsulation structure 400 may have a multilayer structure. For example, the encapsulation structure 400 may include a first encapsulation layer 410, a second encapsulation layer 420, and a third encapsulation layer 430 laminated sequentially. The second encapsulation layer 420 may include a material different from the first encapsulation layer 410 and the third encapsulation layer 430. The second encapsulation layer 420 may include a material with relatively high fluidity. For example, the first encapsulation layer 410 and the third encapsulation layer 430 may be inorganic encapsulation layers made of inorganic insulating materials, and the second encapsulation layer 420 may be an organic encapsulation layer made of organic insulating materials.

[0078] An open metal mask (OMM) is used to form the light-emitting unit 320 and the cathode 330 in the active area. However, the frame area is designed with consideration of the hardware (H / W) manufacturing tolerance of the OMM, the alignment tolerance of the device, the tolerance of the in / out shadow length (the gap between the substrate and the mask, etc.), and the inkjet tolerance of the second encapsulation layer 420.

[0079] For example, the light-emitting unit 320 may be formed only in the active region AA and may not be formed in the border region BZ. However, if the aforementioned tolerance of the opening metal mask for the light-emitting unit 320 is not considered, the light-emitting unit 320 may not be formed in the border region BZ. Therefore, considering the tolerance of the opening metal mask for the light-emitting unit 320, the light-emitting unit 320 also needs to be formed in the border region BZ adjacent to the active region AA. Therefore, the border region BZ is designed to have a first EL (electroluminescence) tolerance region a where the light-emitting unit 320 is formed and a second EL tolerance region b where the light-emitting unit 320 is not formed. The light-emitting unit 320 may be located on the low-voltage power line EVSS of the active region AA and the border region BZ.

[0080] Additionally, the cathode 330 needs to be electrically connected to the low-voltage power line EVSS in the frame region BZ. If the aforementioned tolerances for the opening metal mask used for the cathode 330 are disregarded, the cathode 330 may not need to be electrically connected to the low-voltage power line EVSS. Therefore, considering the tolerances for the opening metal mask used for the cathode 330, the frame region BZ is designed to have a cathode contact region c (where the cathode 330 and the low-voltage power line EVSS are connected), a first cathode tolerance region d (where the cathode 330 extends further outward than the cathode contact region c), and a second cathode tolerance region e (where the cathode 330 does not extend).

[0081] Furthermore, considering the inkjet tolerance of the second encapsulation layer 420, the border area BZ is designed to have an inkjet tolerance area f.

[0082] As described above, the border area BZ includes a first EL tolerance area a, a second EL tolerance area b, a cathode contact area c, a first cathode tolerance area d, a second cathode tolerance area e, and an inkjet tolerance area f.

[0083] Therefore, the display panel according to the embodiment of the present invention has limitations in reducing the bezel area.

[0084] Figure 4 This is a cross-sectional view of a display panel according to another embodiment of the present invention.

[0085] In a display panel according to another embodiment of the present invention, such as Figure 4 As shown, the substrate 101 of the display panel 100 is divided into an active area AA and a border area BZ. A buffer insulating film 110 can be formed on the substrate 101 of the active area AA and the border area BZ. The buffer insulating film 110 is provided to block moisture and other substances that may penetrate from the outside, and the buffer insulating film 110 can be formed by laminating multiple layers of silicon oxide (SiO2) film and / or silicon nitride (SiNx) film.

[0086] Transistors can be disposed in each pixel region of the active region AA. Transistors can be disposed below the anode 310 of each light-emitting element 300. Figure 4 The transistor shown represents Figure 2 The driving transistor DT is shown. Each driving transistor DT may include an active layer 221, a gate 223, a source 227, and a drain 225.

[0087] The active layer 221 of each driving transistor DT may be disposed on the buffer insulating film 110. The active layer 221 may include a channel region, a source region disposed on one side of the channel region, and a drain region disposed on the other side of the channel region.

[0088] The active layer 221 may include a polycrystalline semiconductor. The source and drain regions are conductive regions in which the polycrystalline semiconductor material is doped with Group 5 or Group 3 impurity ions, such as phosphorus (P) or boron (B), at a predetermined concentration. The channel region is a region in which the polycrystalline semiconductor material retains its intrinsic state and provides a path for the movement of electrons or holes.

[0089] In another embodiment, the active layer 221 may comprise an oxide semiconductor and include an undoped intrinsic channel region and doped power and drain regions. When the active layer 221 is made of an oxide semiconductor material, a light-shielding layer (not shown in the figures) may be further disposed overlapping the active layer 221.

[0090] The gate insulating film 120 may be disposed on the entire surface of the substrate 101 on which the active layer 221 is formed. The gate insulating film 120 may be formed by laminating inorganic layers such as silicon oxide (SiO2) films and / or silicon nitride (SiNx) films in a single structure or a multilayer structure.

[0091] The gate 223 may be disposed on the gate insulating film 120 on the upper side of the active layer 221. The gate 223 may be made of a metallic material. For example, the gate 223 may be a single layer or multiple layers made of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) and their alloys, but the present invention is not limited thereto.

[0092] An interlayer insulating film 130 may be disposed on each gate 223. The interlayer insulating film 130 may be made of silicon oxide (SiO2), silicon nitride (SiNx), or the like.

[0093] The drain 225 and source 227 of the transistor can be disposed on the interlayer insulating film 130 of each pixel region. The drain 225 and source 227 can be electrically connected to the drain region and source region of the active layer 221 through contact holes formed in the interlayer insulating film 130. The drain 225 and source 227 can include conductive materials. For example, the drain 225 and source 227 can include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), or tungsten (W). The drain 225 and source 227 can be insulated from the gate 223. The drain 225 and source 227 can include materials different from those of the gate 223.

[0094] In the border region BZ, the mask layer 228 may be formed on the interlayer insulating film 130 using the same material as the drain 225 and the source 227. However, the invention is not limited thereto. The mask layer 228 may be formed using a different material than the drain 225 and the source 227. The mask layer 228 may be formed using the same material as the gate 223. The mask layer 228 may be disposed in... Figure 3 The first EL tolerance region a of the border region BZ described herein. As an example, the border region BZ may have a first region, a second region and a third region, wherein a mask layer 228, a low-voltage power line EVSS and a light-emitting unit 320 of a light-emitting element 300 are disposed in the first region, a cathode 330 extends in the second region, and the cathode 330 extends sequentially from the active region AA to the outermost side in the third region.

[0095] Figures 5 to 7 This is a plan view of the mask layer 228 according to various embodiments of the present invention.

[0096] The mask layer 228 can be formed into various shapes, such as Figures 5 to 7As shown. The mask layer 228 may have multiple openings 228b in various forms and disposed in the mask body 228a. For example, as Figure 5 As shown, each opening 228b can be formed into a circular shape. (As...) Figure 6 As shown, each opening 228b can be formed into a rectangular shape. Figure 7 As shown, each opening 228b can be formed into a cross shape.

[0097] A planarization film (or planarization layer) 140 may be disposed on the entire surface of the substrate including the driving transistor DT and the mask layer 228 as described above. The planarization film 140 eliminates steps caused by the driving transistor DT and the mask layer 228. For example, the drain 225, source 227, and mask layer 228 of each pixel region may be covered by the planarization film 140. The upper surface of the planarization film 140 facing the substrate 101 may be flat. For example, the upper surface of the planarization film 140 may be parallel to the upper surface of the substrate 101. The planarization film 140 may include an insulating material. The planarization film 140 may include a material with relatively high fluidity. For example, the planarization film 140 may be an organic insulating film made of an organic insulating material.

[0098] A light-emitting element 300 may be disposed on the planarization film 140 of each pixel region. The light-emitting element 300 of each pixel region may emit light representing a specific color. The light-emitting element 300 may include an anode 310, a light-emitting unit 320, and a cathode 330. The light-emitting element 300 of each pixel region may overlap with the light-emitting area EA defined within the corresponding pixel region. For example, the anode 310, light-emitting unit 320, and cathode 330 of each pixel region may be sequentially laminated onto a portion of the planarization film 140 of the corresponding pixel region exposed by the insulating film 150.

[0099] Each anode 310 may be independently disposed on the planarization film 140 of each pixel region. Each anode 310 may be electrically connected to the source 227 of the driving transistor DT through a contact hole formed in the planarization film 140. The anode 310 may comprise a conductive material. The anode 310 may comprise a material with relatively high reflectivity. For example, the anode 310 may comprise a metal such as aluminum (Al) or silver (Ag). The anode 310 may have a multilayer structure. For example, the anode 310 may have a structure in which a reflective electrode made of metal is located between transparent electrodes made of transparent conductive materials such as ITO and IZO.

[0100] The low-voltage power line EVSS can be disposed on the planarization film 140 of the border area BZ. The low-voltage power line EVSS can overlap with the mask layer 228. The low-voltage power line EVSS can be disposed on... Figure 3In the first EL tolerance region a of the border region BZ described in the figure. For example, the low-voltage power line EVSS may be formed of the same material as the anode 310. The low-voltage power line EVSS may be formed of a different material than the anode 310.

[0101] A dam insulating film 150 may be formed on a planarization film 140 on which an anode 310 and a low-voltage power line EVSS are formed. The dam insulating film 150 may be formed on the planarization film 140 to cover the edge of each anode 310. The dam insulating film 150 may define a light-emitting area EA within each pixel region. For example, an anode 310 overlapping with the light-emitting area EA of each pixel region may be exposed by the dam insulating film 150. The light-emitting area EA of each pixel region may be surrounded by the dam insulating film 150. The anode 310 of each pixel region may be insulated from the anode 310 of adjacent pixel regions by the dam insulating film 150. The dam insulating film 150 may be formed on the planarization film 140 to cover the edge of the low-voltage power line EVSS. For example, the low-voltage power line EVSS may be exposed by the dam insulating film 150. The low-voltage power line EVSS may be surrounded by the dam insulating film 150. The dam insulating film 150 may include an insulating material. For example, the dam insulating film 150 may be an organic insulating film made of an organic insulating material. The insulating film 150 may include a material different from that of the planarization film 140.

[0102] The dam insulating film 150 can form a dam DAM at the outermost edge of the border region BZ. The dam DAM can be formed higher than the dam insulating film 150 set in the active region AA and the border region BZ.

[0103] In addition to the active region AA, the light-emitting unit 320 can also be configured to extend to Figure 3 The first EL tolerance region a of the border region BZ described in the figure. The light-emitting unit 320 may be disposed on each anode 310 and the embankment insulating film 150. The light-emitting unit 320 may also be disposed on the low-voltage power line EVSS exposed by the embankment insulating film 150.

[0104] For example, the light-emitting unit 320 may include a light-emitting material layer (EML). The light-emitting material layer may include organic light-emitting materials, inorganic light-emitting materials, or mixed light-emitting materials. For example, the display device according to an embodiment of the present invention may be an organic light-emitting display device including organic light-emitting materials. The light-emitting unit 320 may have a multilayer structure. For example, the light-emitting unit 320 may also include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Therefore, in a display device according to another embodiment of the present invention, the efficiency of the light-emitting unit 320 can be improved.

[0105] The light-emitting material layer (EML) of the light-emitting unit 320 can be independently disposed on the anode 310 of the light-emitting region EA of each pixel region. At least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) of the light-emitting unit 320 can be jointly disposed in all pixel regions. That is, at least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) of the light-emitting unit 320 can be disposed not only in the active region AA but also in... Figure 3 The first EL tolerance region a of the border region BZ described in the figure is commonly disposed on the embankment insulating film 150.

[0106] The light-emitting units 320 on the upper side of the mask layer 228 can be selectively removed. For example, portions of the light-emitting units 320 corresponding to the plurality of openings 228b in the mask layer 228 can be selectively removed.

[0107] In another embodiment, not only can the light-emitting units 320 on the upper side of the mask layer 228 be selectively removed, but the low-voltage power lines EVSS can also be selectively removed. For example, portions of the light-emitting units 320 and the low-voltage power lines EVSS corresponding to the plurality of openings 228b of the mask layer 228 can be selectively removed.

[0108] A cathode 330 may be disposed on the light-emitting unit 320. The cathode 330 may include a conductive material. The cathode 330 may include a material different from that of the anode 310. The transmittance of the cathode 330 may be greater than that of the anode 310. For example, the cathode 330 may be a transparent electrode made of a transparent conductive material such as ITO or IZO. The cathode 330 may have a different work function than that of the anode 310. For example, the work function of the cathode 330 may be less than that of the anode 310.

[0109] The cathode 330 may be electrically connected to the low-voltage power line EVSS in the frame region BZ. For example, the cathode 330 may be electrically connected to the low-voltage power line EVSS in a region where the light-emitting unit 320 is selectively removed.

[0110] An encapsulation structure 400 may be disposed in the active area AA, wherein the light-emitting element 300 is disposed in each pixel area and the border area BZ. The encapsulation structure 400 can prevent damage to the light-emitting element 300 located in each pixel area due to external impact and moisture. For example, the light-emitting element 300 in each pixel area can be completely covered by the encapsulation structure 400. The encapsulation structure 400 may extend to the border area BZ.

[0111] The encapsulation structure 400 may have a multilayer structure. For example, the encapsulation structure 400 may include a first encapsulation layer 410, a second encapsulation layer 420, and a third encapsulation layer 430 laminated sequentially. The first encapsulation layer 410, the second encapsulation layer 420, and the third encapsulation layer 430 may include insulating materials. The second encapsulation layer 420 may include materials with relatively high fluidity. For example, the first encapsulation layer 410 and the third encapsulation layer 430 may be inorganic encapsulation layers made of inorganic insulating materials, and the second encapsulation layer 420 may be an organic encapsulation layer made of organic insulating materials.

[0112] The first encapsulation layer 410 may be positioned close to the cathode 330. For example, the first encapsulation layer 410 may be configured to extend above the cathode 330 and into the weir DAM.

[0113] The second encapsulation layer 420 may be positioned on the first encapsulation layer 410. The second encapsulation layer 420 may be thicker than the first encapsulation layer 410. For example, the second encapsulation layer 420 can remove the steps caused by the light-emitting elements 300 in each pixel area. The upper surface of the second encapsulation layer 420 facing the substrate 101 may be flat. The second encapsulation layer 420 may fill all the way into the interior of the DAM.

[0114] The third encapsulation layer 430 may be located on the second encapsulation layer 420. The upper surface of the second encapsulation layer 420 may be covered by the third encapsulation layer 430. The light-emitting element 300 and the insulating film 150 of each pixel area may be completely covered by the encapsulation structure 400.

[0115] A method for manufacturing a display device according to an embodiment of the present invention configured as described above will now be described.

[0116] Figures 8A to 8E This is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 9 This is an enlarged cross-sectional view of an opening 228b of a mask layer 228 according to an embodiment of the present invention, and the low-voltage power line EVSS and light-emitting unit 320 formed therefrom.

[0117] like Figure 8A As shown, the substrate 101 of the display panel 100 can be divided into an active area AA and a border area BZ. A buffer insulating film 110 can be formed on the substrate 101 of the active area AA and the border area BZ. The buffer insulating film 110 is formed to block moisture and the like from penetrating from the outside, and can be formed by laminating multiple layers of silicon oxide (SiO2) film and / or silicon nitride (SiNx) film.

[0118] Transistor DT can be formed in each pixel region of the active region AA. Figure 8A The transistor shown corresponds to Figure 2 The driving transistor DT is shown. Therefore, not only the driving transistor DT, but also the switching transistor ST, the storage capacitor Cst, and the components constitute... Figure 2 All transistors in the compensation circuit CC shown can be formed in each pixel area. For ease of description, only the driving transistor DT is shown.

[0119] The driving transistor DT may include an active layer 221, a gate 223, a source 227, and a drain 225. The active layer 221 of the driving transistor DT may be disposed on the buffer insulating film 110. The active layer 221 may include a channel region, a source region disposed on one side of the channel region, and a drain region disposed on the other side of the channel region.

[0120] The active layer 221 may include a polycrystalline semiconductor. The source and drain regions are conductive regions, wherein the polycrystalline semiconductor material is doped with Group 5 or Group 3 impurity ions, such as phosphorus (P) or boron (B), at a predetermined concentration. The channel region provides a path for the movement of electrons or holes by maintaining the intrinsic state of the polycrystalline semiconductor material.

[0121] In another embodiment, the active layer 221 may comprise an oxide semiconductor and may include an undoped intrinsic channel region and doped power and drain regions. When the active layer 221 is made of an oxide semiconductor material, a light shielding layer (not shown in the figures) may be further disposed below the active layer 221.

[0122] The gate insulating film 120 can be formed on the entire surface of the substrate 101 on which the active layer 221 is disposed. The gate insulating film 120 can be formed by laminating inorganic layers such as silicon oxide (SiO2) film and / or silicon nitride (SiNx) film in one or more layers.

[0123] The gate 223 may be formed on the gate insulating film 120 on the upper side of the active layer 221. The gate 223 may be made of a metallic material. For example, the gate 223 may be a single layer or multiple layers of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), and their alloys, but the invention is not limited thereto.

[0124] An interlayer insulating film 130 may be formed on each gate 223. The interlayer insulating film 130 may be made of silicon oxide (SiO2), silicon nitride (SiNx), or the like.

[0125] The drain 225 and source 227 of the transistor may be formed on the interlayer insulating film 130 of each pixel region. The drain 225 and source 227 may be electrically connected to the drain region and source region of the active layer 221 through contact holes formed in the interlayer insulating film 130. The drain 225 and source 227 may include conductive materials. For example, the drain 225 and source 227 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), or tungsten (W). The drain 225 and source 227 may be insulated from the gate 223. The drain 225 and source 227 may include materials different from those of the gate 223.

[0126] Meanwhile, in the border region BZ, the mask layer 228 can be formed of the same material as the drain 225 and source 227 on the interlayer insulating film 130. However, the present invention is not limited thereto. The mask layer 228 can be formed of a different material than the drain 225 and source 227. For example, the mask layer 228 can be formed on the gate insulating film 130 of the same material as the gate 223. When the active layer 221 is made of an oxide semiconductor material, the mask layer 228 can be formed of the same material as the light shielding layer (not shown in the figures) disposed below the active layer 221. The mask layer 228 can be disposed of Figure 3 The first EL tolerance region a of the border region BZ described in the text.

[0127] Mask layer 228 can be configured as follows Figures 5 to 7 Various shapes are shown. The mask layer 228 may have multiple openings 228b arranged in various shapes in the mask body 228a. For example, as Figure 5 As shown, each of the plurality of openings 228b can be formed in a circular shape. For example... Figure 6 As shown, each of the plurality of openings 228b can be formed in a rectangular shape. For example... Figure 7 As shown, each of the plurality of openings 228b can be formed in a cross shape. The mask layer 228 can be formed to be thicker than the low-voltage power line EVSS that will be formed subsequently.

[0128] The planarization film 140 may be formed on the entire surface of the substrate including the driving transistor DT and the mask layer 228 disposed as described above. The planarization film 140 can eliminate the steps caused by the driving transistor DT and the mask layer 228. For example, the drain 225 and source 227 of each pixel region and the mask layer 228 may be covered by the planarization film 140. The upper surface of the planarization film 140 facing the substrate 101 may be flat. For example, the upper surface of the planarization film 140 may be parallel to the upper surface of the substrate 101. The planarization film 140 may include an insulating material. The planarization film 140 may include a material with relatively high fluidity. For example, the planarization film 140 may be an organic insulating film made of an organic insulating material.

[0129] The anode 310 of the light-emitting element 300 may be formed on the planarization film 140 of each pixel region. The anode 310 may be formed independently on the planarization film 140 of each pixel region. Each anode 310 may be electrically connected to the source 227 of the driving transistor DT through a contact hole formed in the planarization film 140. The anode 310 may include a conductive material. The anode 310 may include a material with relatively high reflectivity. For example, the anode 310 may include a metal such as aluminum (Al) or silver (Ag). The anode 310 may have a multilayer structure. For example, the anode 310 may have a structure in which a reflective electrode made of metal is located between transparent electrodes made of transparent conductive materials such as ITO and IZO.

[0130] The low-voltage power line EVSS can be formed on the planarization film 140 of the border region BZ. The low-voltage power line EVSS can overlap with the mask layer 228. The low-voltage power line EVSS can be positioned... Figure 3 In the first EL tolerance region a of the border region BZ described herein. For example, the low-voltage power line EVSS may be formed of the same material as the anode 310. However, the invention is not limited thereto, and the low-voltage power line EVSS may be formed of a different material than the anode 310.

[0131] A dam insulating film 150 may be formed on a planarization film 140 on which anodes 310 and low-voltage power lines EVSS are formed. The dam insulating film 150 may be formed on the planarization film 140 to cover the edges of each anode 310. The dam insulating film 150 may define a light-emitting area EA within each pixel region. For example, anodes 310 overlapping with the light-emitting areas EA of each pixel region may be exposed by the dam insulating film 150. The light-emitting areas EA of each pixel region may be surrounded by the dam insulating film 150. The anodes 310 of each pixel region may be insulated from the anodes 310 of adjacent pixel regions by the dam insulating film 150.

[0132] Furthermore, a dam insulating film 150 may be formed on the planarization film 140 to cover the edge of the low-voltage power line EVSS. For example, the low-voltage power line EVSS may be exposed by the dam insulating film 150. The low-voltage power line EVSS may be surrounded by the dam insulating film 150. The dam insulating film 150 may include an insulating material. For example, the dam insulating film 150 may be an organic insulating film made of an organic insulating material. The dam insulating film 150 may include a material different from the planarization film 140.

[0133] When the dam insulation film 150 is formed, a dam DAM can be formed at the outermost edge of the border region BZ. The dam DAM can be formed higher than the dam insulation film 150 provided in the active region AA and the border region BZ.

[0134] like Figure 8BAs shown, the light-emitting unit 320 is formed on the anode 310 and the insulating film 150. The light-emitting unit 320 can be formed to extend not only into the active region AA, but also into... Figure 3 The first EL tolerance region a of the border region BZ described in the figure. The light-emitting unit 320 may be in direct contact with each anode 310. The light-emitting unit 320 may also be formed on the low-voltage power line EVSS exposed by the dike insulating film 150.

[0135] For example, the light-emitting unit 320 may include a light-emitting material layer (EML). The light-emitting material layer may include organic light-emitting materials, inorganic light-emitting materials, or mixed light-emitting materials. For example, the display device according to an embodiment of the present invention may be an organic light-emitting display device including organic light-emitting materials. The light-emitting unit 320 may have a multilayer structure. For example, the light-emitting unit 320 may also include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0136] The light-emitting material layer (EML) of the light-emitting unit 320 can be independently disposed on the anode 310 of the light-emitting region EA of each pixel region. At least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) of the light-emitting unit 320 can be jointly disposed in all pixel regions. That is, at least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) of the light-emitting unit 320 can be disposed not only in the active region AA but also in... Figure 3 The first EL tolerance region a of the border region BZ described in the figure is commonly disposed on the embankment insulating film 150.

[0137] like Figure 8C As shown, on the side of substrate 101, a mask layer 228 is used as a mask to irradiate the low-voltage power line EVSS and the light-emitting unit 320 formed on the low-voltage power line EVSS with laser light, so as to selectively remove at least the light-emitting unit 320 formed on the low-voltage power line EVSS. For example, the light-emitting unit 320 can be selectively removed by Joule heating of the laser. This will refer to Figure 9 To describe in more detail.

[0138] In another embodiment, not only can the light-emitting units 320 on the upper side of the mask layer 228 be selectively removed, but also the low-voltage power lines EVSS can be selectively removed. For example, by controlling the intensity (energy) of the laser and irradiating the area below the mask layer 228, portions of the low-voltage power lines EVSS and light-emitting units 320 corresponding to the plurality of openings 228b of the mask layer 228 can be selectively removed. Figure 8CThe diagram illustrates an embodiment where the low-voltage power lines EVSS and light-emitting units 320 are selectively removed in the regions corresponding to the plurality of openings 228b of the mask layer 228. This will be referred to... Figure 10 To describe in more detail.

[0139] like Figure 8D As shown, a cathode 330 is formed on the light-emitting unit 320 and the insulating film 150. The cathode 330 may include a conductive material. The cathode 330 may include a material different from that of the anode 310. The transmittance of the cathode 330 may be greater than that of the anode 310. The cathode may be a transparent electrode made of a transparent conductive material such as ITO or IZO. The cathode 330 may have a different work function than the anode 310. For example, the work function of the cathode 330 may be less than that of the anode 310.

[0140] Cathode 330 can be electrically connected to the low-voltage power line EVSS in the frame area BZ. This will refer to... Figure 9 and Figure 10 To describe in more detail.

[0141] like Figure 8E As shown, the encapsulation structure 400 is formed on the active area AA, wherein the light-emitting element 300 is disposed in each pixel area and the border area BZ.

[0142] For example, a first encapsulation layer 410 is formed on the outer surface of the cathode 330, the dam insulating film 150 of the border region BZ, and the dam DAM. A second encapsulation layer 420 is formed on the first encapsulation layer 410. The second encapsulation layer 420 may be thicker than the first encapsulation layer 410. For example, the second encapsulation layer 420 can remove the steps caused by the light-emitting elements 300 in each pixel region. The second encapsulation layer 420 may fill all the way to the inside of the dam DAM. Then, a third encapsulation layer 430 is formed on the second encapsulation layer 420. The first encapsulation layer 410, the second encapsulation layer 420, and the third encapsulation layer 430 may include insulating materials. The second encapsulation layer 420 may include materials different from those of the first encapsulation layer 410 and the third encapsulation layer 430. The second encapsulation layer 420 may include materials with relatively high fluidity. For example, the first encapsulation layer 410 and the third encapsulation layer 430 may be inorganic encapsulation layers made of inorganic insulating materials, and the second encapsulation layer 420 may be an organic encapsulation layer made of organic insulating materials.

[0143] Figure 9 This is an enlarged cross-sectional view of an opening 228b in a mask layer 228 according to an embodiment of the present invention, and a low-voltage power line EVSS, a light-emitting unit 320, and a cathode 330 formed based on the opening 228b.

[0144] For example, by controlling the intensity (energy) of the laser and irradiating the area below the mask layer 228, the portions of the light-emitting unit 320 corresponding to the plurality of openings 228b of the mask layer 228 are heated, and the heated portions of the light-emitting unit 320 can be selectively removed.

[0145] When the light-emitting unit 320 is selectively removed in this manner, the cathode 330 can be electrically connected to the upper surface of the low-voltage power line EVSS in the area where the light-emitting unit 320 is selectively removed.

[0146] Figure 10 This is an enlarged cross-sectional view of an opening 228b of a mask layer 228 according to another embodiment of the present invention, and the low-voltage power line EVSS, light-emitting unit 320 and cathode 330 formed therefrom.

[0147] In another embodiment, not only the light-emitting unit 320 located on the upper side of the mask layer 228, but also the low-voltage power line EVSS can be selectively removed. For example, by controlling the intensity (energy) of the laser and irradiating the area below the mask layer 228, portions of the low-voltage power line EVSS and the light-emitting unit 320 corresponding to the plurality of openings 228b of the mask layer 228 can be selectively removed. In this case, the removed portion of the light-emitting unit 320 can be wider than the removed portion of the low-voltage power line EVSS. For example, the width of the removed portion of the light-emitting unit 320 can be greater than the width of the removed portion of the low-voltage power line EVSS. Therefore, the low-voltage power line EVSS and the light-emitting unit 320 can have steps in the region corresponding to the openings 228b of the mask layer 228. The mask layer 228 can be formed to be thicker than the low-voltage power line EVSS.

[0148] like Figure 10 As described, when the light-emitting unit 320 and the low-voltage power line EVSS are selectively removed, the cathode 330 can be electrically connected to the upper and side surfaces of the low-voltage power line EVSS in the region where the light-emitting unit 320 is selectively removed.

[0149] Figure 11 This is an enlarged cross-sectional view of an opening 228b of a mask layer 228 according to another embodiment of the present invention, and a low-voltage power line EVSS, a light-emitting unit 320 and a cathode 330 formed based on the opening 228b.

[0150] Figure 11 An embodiment is shown in which the low-voltage power line EVSS is formed of the same material as the anode 310 and the anode 310 has a multilayer structure.

[0151] For example, the low-voltage power line EVSS and anode 310 may have a structure in which a reflective electrode made of metal is located between transparent electrodes made of transparent conductive materials such as ITO and IZO. For example, the low-voltage power line EVSS and anode 310 may be formed in which a first transparent conductive layer 310a, a metal layer 310b, and a second transparent conductive layer 310c are laminated.

[0152] Using this structure, if the laser output is adjusted to reduce it, the first transparent conductive layer 310a of the low-voltage power lines EVSS corresponding to the plurality of openings in the mask layer 228 is retained, and portions of the metal layer 310b and the second transparent conductive layer 310c corresponding to the plurality of openings in the mask layer 228 can be removed, such as... Figure 11 As shown. Furthermore, portions of the light-emitting unit 320 corresponding to the plurality of openings in the mask layer 228 can be removed.

[0153] At this time, the removed portion of the light-emitting unit 320 may be wider than the removed portion of each of the metal layer 310b of the low-voltage power line EVSS and the second transparent conductive layer 310c of the low-voltage power line EVSS.

[0154] like Figure 11 As described, when the light-emitting unit 320 and the metal layer 310b and the second transparent conductive layer 310c of the low-voltage power line EVSS are removed with different widths, in the region where the light-emitting unit 320 is selectively removed, the cathode 330 can be electrically connected to the upper surface of the second transparent conductive layer 310c of the low-voltage power line EVSS, the side surfaces of the metal layer 310b and the second transparent conductive layer 310c of the low-voltage power line EVSS, and the upper surface of the first transparent conductive layer 310a of the low-voltage power line EVSS.

[0155] As described above, a mask layer 228 with multiple openings and low-voltage power lines EVSS are disposed in the process margin region of the common light-emitting layer in the border region BZ, and laser is irradiated thereusing the mask layer 228 as a mask. Then, due to the Joule heating of the laser, the portions of the light-emitting units 320 corresponding to the openings of the mask layer 228 are selectively removed, or both the light-emitting units 320 and the low-voltage power lines EVSS corresponding to the openings of the mask layer 228 are selectively removed.

[0156] Then, the cathode is electrically connected to the low-voltage power line EVSS. Therefore, since the cathode 330 and the low-voltage power line EVSS are electrically connected within the process margin region of the common light-emitting layer, it is not necessary to... Figure 3 As shown, the first EL tolerance area a and the cathode contact area c are designed separately in the bezel area BZ, thus enabling a narrow bezel for the display device.

[0157] Furthermore, since the bezel area can be reduced, the active area of ​​the display panel can be maximized.

[0158] The display device according to various embodiments of the present invention can be described as follows.

[0159] A display device according to an embodiment of the present invention may include: a substrate including an active region having a plurality of pixel regions and a border region surrounding the active region; a mask layer located on the substrate in the border region and having a plurality of openings; a planarization layer formed on the entire surface of the substrate including the mask layer; an anode of a light-emitting element located on the planarization layer of each of the plurality of pixel regions; a low-voltage power line located on the planarization layer of the border region and overlapping the mask layer; a dam insulating film located on the planarization layer to expose the anode and the low-voltage power line; a light-emitting unit of the light-emitting element located on the low-voltage power line of the active region and the border region, wherein portions of the light-emitting unit corresponding to the plurality of openings of the mask layer are removed; and a cathode of the light-emitting element located on the light-emitting unit of the light-emitting element and electrically connected to the low-voltage power line.

[0160] According to an embodiment of the present invention, portions of the low-voltage power lines corresponding to the plurality of openings in the mask layer may be removed.

[0161] According to an embodiment of the present invention, the removed portion of the light-emitting unit corresponding to the plurality of openings of the mask layer may be wider than the removed portion of the low-voltage power line corresponding to the openings of the mask layer.

[0162] According to an embodiment of the present invention, the frame area may have a first area, a second area and a third area. The first area is provided with the mask layer, the low-voltage power line and the light-emitting unit of the light-emitting element. The cathode extends in the second area and in the third area does not extend sequentially from the active area to the outermost side.

[0163] According to an embodiment of the present invention, a transistor having an active layer, a gate, a source, and a drain may be further disposed below the anode of each light-emitting element, and the mask layer may include the same material as the gate of the transistor or the source and drain.

[0164] According to an embodiment of the present invention, a light shielding layer may be further disposed below the active layer of the transistor, and the mask layer may include the same material as the light shielding layer.

[0165] According to an embodiment of the present invention, the low-voltage power line may include the same material as the anode.

[0166] According to an embodiment of the present invention, the low-voltage power line and the anode may include a structure in which a first transparent conductive layer, a metal layer and a second transparent conductive layer are laminated, a portion of the first transparent conductive layer of the low-voltage power line corresponding to a plurality of openings of the mask layer may be retained, and a portion of the metal layer and the second transparent conductive layer of the low-voltage power line corresponding to a plurality of openings of the mask layer may be selectively removed.

[0167] According to an embodiment of the present invention, the removed portion of the light-emitting unit of the light-emitting element corresponding to the plurality of openings of the mask layer may be wider than the removed portion of each of the metal layer of the low-voltage power line and the second transparent conductive layer corresponding to the openings of the mask layer.

[0168] According to an embodiment of the present invention, an encapsulation structure may be further provided, the encapsulation structure being disposed on the cathode.

[0169] A method for manufacturing a display device according to an embodiment of the present invention may include: forming a thin-film transistor in each pixel region of a substrate, the substrate including an active region having a plurality of pixel regions and a border region surrounding the active region; forming a mask layer having a plurality of openings on the substrate in the border region; forming a planarization layer on the entire surface of the substrate including the thin-film transistor and the mask layer; forming an anode of a light-emitting element on the planarization layer of each pixel region, such that the anode is electrically connected to the thin-film transistor; forming a low-voltage power line on the planarization layer of the border region, such that the low-voltage power line overlaps with the mask layer; forming a diaphragm insulating film on the planarization layer to expose the anode and the low-voltage power line; forming a light-emitting unit of the light-emitting element on the low-voltage power line of the active region and the border region; selectively removing portions of the light-emitting unit of the light-emitting element corresponding to the plurality of openings of the mask layer by irradiating a laser from the side of the substrate using the mask layer as a mask; and forming a cathode of the light-emitting element on the light-emitting unit of the light-emitting element and the border region, such that the cathode is electrically connected to the low-voltage power line.

[0170] The display device and its manufacturing method according to embodiments of the present invention have the following effects.

[0171] A narrow bezel can be achieved by setting a laser mask and voltage supply line (or power line) in the process margin area of ​​the common light-emitting layer in the bezel region, selectively removing the voltage supply line and the common light-emitting layer using a laser stripping method, and then electrically connecting the cathode to the voltage supply line.

[0172] Because the laser is irradiated through a mask layer, damage to transistors and wiring is prevented. Furthermore, because the laser is irradiated through a mask layer, sufficient margin is ensured related to the laser beam size and processing tolerances.

[0173] Because the border area can be reduced, the active area in the display panel can be maximized.

[0174] The effects of the embodiments are not limited to those described above, and many more effects are included in this invention.

[0175] It will be apparent to those skilled in the art that various modifications and variations can be made to this invention without departing from the spirit or scope thereof. Therefore, this invention is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate, the substrate including an active region having multiple pixel regions and a border region surrounding the active region; A mask layer located on a substrate within the frame area and having multiple openings; A planarization layer is formed on the entire surface of a substrate including the mask layer; The anode of the light-emitting element is located on the planarization layer of each of the plurality of pixel regions; A low-voltage power line is located on the planarization layer of the border area and overlaps with the mask layer. A dike insulating film is placed on the planarization layer to expose the anode and the low-voltage power line; The light-emitting unit of the light-emitting element is located on the low-voltage power line of the active area and the frame area, and the portion of the light-emitting unit corresponding to the multiple openings of the mask layer is removed; as well as The cathode of the light-emitting element is located on the light-emitting unit of the light-emitting element and is electrically connected to the low-voltage power supply line.

2. The display device according to claim 1, wherein portions of the low-voltage power lines corresponding to the plurality of openings in the mask layer are removed.

3. The display device according to claim 2, wherein the removed portion of the light-emitting unit corresponding to the plurality of openings of the mask layer is wider than the removed portion of the low-voltage power line corresponding to the openings of the mask layer.

4. The display device according to claim 1, wherein the bezel area has a first area, a second area and a third area, wherein the mask layer, the low-voltage power line and the light-emitting unit of the light-emitting element are disposed in the first area, the cathode extends in the second area, and the cathode does not extend sequentially from the active area to the outermost side in the third area.

5. The display device of claim 1, further comprising a transistor located below the anode of each light-emitting element, the transistor having an active layer, a gate, a source, and a drain. The mask layer comprises the same material as the gate or source and drain of the transistor.

6. The display device according to claim 5, further comprising a light-shielding layer located below the active layer of the transistor. The mask layer comprises the same material as the light shielding layer.

7. The display device of claim 1, wherein the low-voltage power line comprises the same material as the anode.

8. The display device according to claim 7, wherein the low-voltage power line and the anode comprise a structure in which a first transparent conductive layer, a metal layer, and a second transparent conductive layer are laminated. A portion of the first transparent conductive layer of the low-voltage power line corresponding to the plurality of openings of the mask layer is retained, while portions of the metal layer and the second transparent conductive layer of the low-voltage power line corresponding to the plurality of openings of the mask layer are removed.

9. The display device according to claim 8, wherein the removed portion of the light-emitting unit of the light-emitting element corresponding to the plurality of openings of the mask layer is wider than the removed portion of each of the metal layer of the low-voltage power line and the second transparent conductive layer corresponding to the openings of the mask layer.

10. The display device according to claim 1, further comprising an encapsulation structure disposed on the cathode.

11. A method for manufacturing a display device, comprising: A thin-film transistor is formed in each pixel region of a substrate, the substrate including an active region having multiple pixel regions and a border region surrounding the active region; A mask layer with multiple openings is formed on the substrate in the frame area; A planarization layer is formed on the entire surface of a substrate including the thin-film transistor and the mask layer; An anode of a light-emitting element is formed on the planarization layer of each of the plurality of pixel regions, such that the anode is electrically connected to the thin-film transistor; Low-voltage power lines are formed on the planarization layer of the border area, such that the low-voltage power lines overlap with the mask layer; An insulating film is formed on the planarization layer to expose the anode and the low-voltage power line; The light-emitting unit of the light-emitting element is formed on the low-voltage power line of the active region and the frame region; The portion of the light-emitting unit of the light-emitting element corresponding to a plurality of openings in the mask layer is removed by irradiating the side of the substrate with laser light using the mask layer as a mask; as well as The cathode of the light-emitting element is formed on the light-emitting unit and the frame area of ​​the light-emitting element, such that the cathode is electrically connected to the low-voltage power line.

12. The method of claim 11, further comprising: By using the mask layer as a mask to irradiate the side of the substrate with a laser, the portions of the low-voltage power lines corresponding to the multiple openings of the mask layer are removed.

13. The method of claim 12, wherein the removed portion of the light-emitting unit corresponding to the plurality of openings in the mask layer is wider than the removed portion of the low-voltage power line corresponding to the opening in the mask layer.

14. The method of claim 11, wherein the border region has a first region, a second region and a third region, wherein the mask layer, the low-voltage power line and the light-emitting unit of the light-emitting element are disposed in the first region, the cathode extends in the second region, and the cathode does not extend sequentially from the active region to the outermost side in the third region.

15. The method of claim 11, wherein a transistor is further disposed below the anode of each light-emitting element, the transistor having an active layer, a gate, a source, and a drain. The mask layer comprises the same material as the gate or source and drain of the transistor.

16. The method of claim 15, wherein a light-shielding layer is further disposed below the active layer of the transistor. The mask layer comprises the same material as the light shielding layer.

17. The method of claim 11, wherein the low-voltage power line comprises the same material as the anode.

18. The method of claim 7, wherein the low-voltage power line and the anode comprise a structure in which a first transparent conductive layer, a metal layer, and a second transparent conductive layer are laminated. A portion of the first transparent conductive layer of the low-voltage power line corresponding to the plurality of openings of the mask layer is retained, while portions of the metal layer and the second transparent conductive layer of the low-voltage power line corresponding to the plurality of openings of the mask layer are removed.

19. The method of claim 18, wherein the removed portion of the light-emitting unit of the light-emitting element corresponding to the plurality of openings of the mask layer is wider than the removed portion of each of the metal layer of the low-voltage power line and the second transparent conductive layer corresponding to the openings of the mask layer.

20. The method of claim 11, further comprising: An encapsulation structure is formed on the cathode.

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