Electronic device and method of manufacturing the same

Abstract

This disclosure provides an electronic device and a method for manufacturing the same. The electronic device includes an electronic unit and a connecting substrate. The connecting substrate is electrically connected to the electronic unit and includes a first base layer structure and a second base layer structure disposed between the first base layer structure and the electronic unit. The first base layer structure includes a first insulating layer and a first heat dissipation structure disposed within the first insulating layer. The second base layer structure includes a second insulating layer and a second heat dissipation structure disposed within the second insulating layer. The thickness of the first insulating layer is greater than the thickness of the second insulating layer, and the first heat dissipation structure overlaps with the second heat dissipation structure.

Description

Technical Field

[0001] This disclosure relates to an electronic device and a method of manufacturing the same, particularly an electronic device with improved reliability and a method of manufacturing the same. Background Technology

[0002] In current semiconductor packaging technology, mounting electronic units with different functions on the same substrate is one way to improve the performance of electronic devices. As electronic devices continue to be developed towards lighter, thinner, shorter, and smaller sizes, and as users' performance requirements for electronic devices continue to increase, the density of electronic units mounted on these substrates is also increasing. Coreless substrates are a type of substrate commonly used in advanced packaging to meet the needs of more input / output pads (I / O pads) or lighter and thinner designs. However, coreless substrates still face challenges in terms of support, warpage, and / or heat dissipation efficiency. Therefore, those skilled in the art continue to improve coreless substrates to meet current and future requirements. Summary of the Invention

[0003] This disclosure provides an electronic device with improved reliability and a method for manufacturing the same.

[0004] According to embodiments of this disclosure, an electronic device includes at least one electronic unit, a connecting substrate, and a reinforcing member. The connecting substrate is electrically connected to the electronic unit and includes a first base layer structure and a second base layer structure disposed between the first base layer structure and the electronic unit. The reinforcing member surrounds the connecting substrate. The first base layer structure includes a first insulating layer and a first heat dissipation structure disposed in the first insulating layer, and the second base layer structure includes a second insulating layer and a second heat dissipation structure disposed in the second insulating layer. The first heat dissipation structure overlaps with the second heat dissipation structure, and both the first and second heat dissipation structures are in contact with at least a portion of the reinforcing member.

[0005] According to one embodiment of this disclosure, a method of manufacturing an electronic device includes: providing an electronic unit; providing a connection substrate; and providing a reinforcement surrounding the connection substrate. The connection substrate is electrically connected to the electronic unit and includes a first base layer structure and a second base layer structure disposed between the first base layer structure and the electronic unit. The first base layer structure includes a first insulating layer and a first heat dissipation structure formed in the first insulating layer. The second base layer structure includes a second insulating layer and a second heat dissipation structure formed in the second insulating layer. The first heat dissipation structure overlaps with the second heat dissipation structure, and the first heat dissipation structure contacts at least a portion of the reinforcement.

[0006] Based on the above, in the embodiments of this disclosure, the first heat dissipation structure of the connecting substrate is designed to overlap with the second heat dissipation structure, and the first heat dissipation structure and the second heat dissipation structure are in contact with at least a portion of the reinforcement. This can help improve the heat dissipation efficiency and support of the connecting substrate, thereby improving the reliability of the electronic device.

[0007] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] The accompanying drawings are included to further illustrate this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0009] Figure 1 This is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 2 yes Figure 1 A cross-sectional schematic diagram of the connecting substrate in an embodiment of the present disclosure;

[0011] Figure 3 This is an exploded view of the wiring structure, heat dissipation structure and electronic unit according to an embodiment of the present disclosure;

[0012] Figure 4 This is an exploded view of the wiring structure, support layer and electronic unit according to an embodiment of the present disclosure;

[0013] Figure 5A and Figure 5B This is a cross-sectional schematic diagram of a method for manufacturing a bonding substrate according to an embodiment of the present disclosure;

[0014] Figure 6A and Figure 6B as well as Figure 7A and Figure 7B These are different embodiments of this disclosure. Figure 5B A cross-sectional schematic diagram of some steps in the method for forming the redistribution layer; and

[0015] Figure 8 This is a cross-sectional schematic diagram of a connecting substrate according to another embodiment of the present disclosure. Detailed Implementation

[0016] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure show only a portion of the packaging structure, and specific elements in the drawings are not drawn to scale. Furthermore, the number and dimensions of the elements in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. For example, for clarity, the relative dimensions, thicknesses, and positions of various film layers, regions, and / or structures may be reduced or enlarged.

[0017] Certain terms are used throughout this specification and the appended claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, words such as "having" and "comprising" are open-ended terms and should therefore be interpreted as meaning "including but not limited to...".

[0018] In this document, the phrase "one element is disposed on another element" is used to conveniently describe the relative position between the element and the other element, and is not intended to define the process steps or sequence of the element and the other element.

[0019] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting this disclosure. It should be understood that when an element or membrane is referred to as being "on" or "connected" to another element or membrane, the element or membrane may be directly on or directly connected to the other element or membrane, or there may be an inserted element or membrane between them (in a non-direct case). Conversely, when an element or membrane is referred to as being "directly" on or "directly connected" to another element or membrane, there is no inserted element or membrane between them. Furthermore, when an element or membrane is referred to as overlapping another element, the element or membrane at least partially overlaps with the other element or membrane.

[0020] The terms “about,” “approximately,” “substantially,” or “roughly” used in this document generally mean falling within 10% of a given value or range, or within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Furthermore, the phrases “given range is from a first value to a second value” or “given range falls within the range of a first value to a second value” indicate that the given range includes the first value, the second value, and other values ​​in between.

[0021] In some embodiments of this disclosure, terms such as “connection” and “interconnection” are used to refer to two structures in direct contact, or two structures that are not in direct contact but have other structures disposed between them, unless otherwise defined. Terms such as “connection” and “interconnection” can also include situations where both structures are movable or both structures are fixed. Furthermore, the terms “electrical connection” and “coupling” encompass any direct or indirect electrical connection means.

[0022] In the following embodiments, the same or similar elements will be referred to by the same or similar reference numerals, and their descriptions will be omitted. Furthermore, features in different embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it, and simple equivalent changes and modifications made in accordance with this specification or claims are still within the scope of this disclosure. That is, the embodiments described below can be completed by replacing, recombining, or mixing technical features in several different embodiments without departing from the spirit of this disclosure. In addition, the terms "first," "second," etc., mentioned in this specification or claims are only used to name different elements or distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements, nor are they used to limit the manufacturing order or installation order of the elements.

[0023] In this disclosure, the thickness, length, and width can be measured selectively using an optical microscope (OM) and / or a scanning electron microscope (SEM), but are not limited thereto. For example, the thickness, length, and width can be measured using an optical microscope, while the thickness or width can be measured from a cross-sectional image in an electron microscope, but are not limited thereto. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies that there may be an error of approximately 10% between the first and second values.

[0024] The manufacturing process of the electronic device described in this disclosure may, for example, employ a wafer-level package (WLP) process, such as chip-on-wafer-on-substrate (CoWoS) technology, but is not limited thereto. Alternatively, a panel-level package (PLP) process may be used, such as chip-on-panel-on-substrate (CoPoS) technology, but is not limited thereto. In some embodiments, the manufacturing process of the electronic device described in this disclosure may, for example, employ a chiplast process or a chipfirst process. The electronic device described in this disclosure may be a high-speed computing module, a power module, a semiconductor packaging device, an optical communication module, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device, or a splicing device, but is not limited thereto.

[0025] The following examples illustrate exemplary embodiments of this disclosure, and the same element symbols are used in the drawings and description to denote the same or similar parts.

[0026] Figure 1 This is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 2 yes Figure 1 The connecting substrate is shown in a cross-sectional view of an embodiment of the present disclosure. Figure 3 This is an exploded view of the wiring structure, heat dissipation structure, and electronic unit according to an embodiment of the present disclosure. Figure 4 This is an exploded view of the wiring structure, support layer, and electronic unit according to an embodiment of the present disclosure.

[0027] First, please refer to Figure 1 The electronic device 10 includes at least one electronic unit EU1 or EU2 and a connecting substrate 100. The connecting substrate 100 is electrically connected to the electronic unit EU1 or EU2 and includes a first base structure BS1 and a second base structure BS2 disposed between the first base structure BS1 and the electronic unit EU1 or EU2.

[0028] In this embodiment, at least one electronic unit EU1 or EU2 may include multiple electronic units EU1, EU2 and may be disposed on the connection substrate 100. The electronic units EU1, EU2 may include passive components, active components, or combinations thereof, such as capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical systems (MEMS), system-on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), memory, or logic die, but are not limited thereto.

[0029] In some embodiments, the connector substrate 100 may have panel-level dimensions. For example, the area of ​​the connector substrate 100 may include 5 cm x 5 cm, 10 cm x 10 cm, 30 cm x 30 cm, 50 cm x 50 cm, 70 cm x 70 cm, or any suitable size, but is not limited thereto. In some embodiments, when the connector substrate 100 has panel-level dimensions, the connector substrate 100 can be applied to a fan-out panel-level package (FOPLP) process. In this embodiment, the fan-out panel-level package, due to the use of a connector substrate 100 with panel-level dimensions, can significantly increase production capacity compared to wafer-level packaging. Simultaneously, the connector substrate 100 with panel-level dimensions may have a rectangular outline, which can also significantly improve the utilization rate of the connector substrate 100 compared to wafer-level packaging.

[0030] In this embodiment, the first base structure BS1 includes a first insulating layer IL1 and a first heat dissipation structure HD1 disposed in the first insulating layer IL1. The second base structure BS2 includes a second insulating layer IL2 and a second heat dissipation structure HD2 disposed in the second insulating layer IL2. In this embodiment, the thickness t1 of the first insulating layer IL1 is greater than the thickness t2 of the second insulating layer IL2, and the first heat dissipation structure HD1 and the second heat dissipation structure HD2 at least partially overlap. This helps to improve the heat dissipation efficiency and support of the connecting substrate 100 and reduce warping caused by excessive difference in the coefficient of thermal expansion (CTE), thereby improving the reliability of the electronic device 10. In some embodiments, in the Z direction, the first base structure BS1 is farther away from the electronic unit EU1 or electronic unit EU2 than the second base structure BS2. The heat transfer coefficient (in W / mK) of the first heat dissipation structure HD1 of the first base structure BS1 is different from the heat transfer coefficient of the second heat dissipation structure HD2 of the second base structure BS2. In some embodiments, the thermal conductivity of the first heat dissipation structure HD1 is greater than that of the second heat dissipation structure HD2, so that the heat accumulated in the electronic unit can be dissipated through the connecting substrate 100, thereby improving the reliability of the electronic device 10.

[0031] In some embodiments, the first insulating layer IL1 and the second insulating layer IL2 may each comprise a plurality of insulating layers alternately stacked along the Z direction. For example, such as Figure 2As shown, the first insulating layer IL1 may include an insulating layer IL1a and an insulating layer IL1b disposed on the insulating layer IL1a, while the second insulating layer IL2 may include an insulating layer IL2a and an insulating layer IL2b disposed on the insulating layer IL2a. The first insulating layer IL1 and the second insulating layer IL2 may each comprise an organic material or an inorganic material. Organic materials include, but are not limited to, polyimide (PI), poly-p-xylylene (also known as Parylene), benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymers, or other suitable organic materials. Inorganic materials include, but are not limited to, silicon-containing glass, silicon oxide, silicon nitride, silicon oxynitride, or other suitable inorganic materials. In some embodiments, the coefficients of thermal expansion of the first insulating layer IL1 and the second insulating layer IL2 may be different. For example, there is a first difference between the coefficient of thermal expansion of one of the first insulating layers IL1 and the coefficient of thermal expansion of the electronic unit EU1, which can be greater than or equal to 5 and less than or equal to 16. Similarly, there is a second difference between the coefficient of thermal expansion of one of the second insulating layers IL2 and the coefficient of thermal expansion of the electronic unit EU1, which can be greater than or equal to 10 and less than or equal to 45. The ratio R1 (R1 = first difference / second difference) of the first difference to the second difference can be greater than or equal to 0.12 and less than or equal to 5, or greater than or equal to 0.2 and less than or equal to 4. This helps to improve the support of the connecting substrate 100 and reduce warping caused by excessive differences in the coefficients of thermal expansion. The first difference and the second difference can also be greater than or equal to 0.

[0032] In this embodiment, the first base structure BS1 may include a first wiring structure WS1a, and the second base structure BS2 may include a second wiring structure WS2a electrically connecting the first wiring structure WS1a to electronic units EU1 and EU2. In some embodiments, the wiring structures WS1a and WS2a may include a plurality of conductive patterns / conductive layers formed in the first insulating layer IL1 and the second insulating layer IL2 and alternately stacked along the Z direction, as well as conductive vias connecting the conductive patterns / conductive layers. For example, such as Figure 2As shown, wiring structure WS1a may include wiring structure WS1a1 and wiring structure WS1a2 disposed on wiring structure WS1a1, while wiring structure WS2a may include wiring structure WS2a1 and wiring structure WS2a2 disposed on wiring structure WS2a1. Wiring structures WS1a1, WS1a2, WS2a1, and WS2a2 may each include multiple conductive patterns / conductive layers and conductive vias connecting the conductive patterns / conductive layers. The first wiring structure WS1a and the second wiring structure WS2a may each include any suitable conductive material, such as copper, titanium, nickel, combinations or alloys of the above materials, but are not limited thereto. According to some embodiments, the orientation of the multiple conductive vias in the base structure may be the same (e.g., ...). Figure 2 ) or for mirror design (e.g. Figure 5B ).

[0033] Based on the above, the connecting substrate 100 can serve as the core of the electronic device 10 on which electronic units EU1 and EU2 are disposed, and can also serve as a redistribution substrate for connecting electronic units EU1 and EU2.

[0034] The thickness t1 of the first insulating layer IL1 differs from the thickness t2 of the second insulating layer IL2. The thickness t1 of the first insulating layer IL1 can be between 6 micrometers and 15 micrometers, while the thickness t2 of the second insulating layer IL2 can be between 1 micrometer and 5 micrometers. For example, if the thickness t1 of the first insulating layer IL1 is designed to be greater than the thickness t2 of the second insulating layer IL2, for instance, when the ratio R2 (R2 = thickness t1 / thickness t2) of thickness t1 is greater than or equal to 2 and less than or equal to 8, or greater than or equal to 3 and less than or equal to 6, it can help improve the support of the connection substrate 100, which is the core of the electronic device 10, and can help reduce warping caused by excessive differences in the coefficient of thermal expansion (CTE). For example, the thickness relationship between the first insulating layer IL1 and the second insulating layer IL2 can allow the coefficient of thermal expansion to change gradually, thereby mitigating warping caused by excessive differences in the coefficient of thermal expansion.

[0035] Designing the first heat dissipation structure HD1 and the second heat dissipation structure HD2 to overlap each other and be respectively disposed in the first insulating layer IL1 and the second insulating layer IL2 can help improve the heat dissipation efficiency of the connection substrate 100, which is the core of the electronic device 10. In some embodiments, the first heat dissipation structure HD1 and the second heat dissipation structure HD2 can be disposed around the connection substrate 100 to help conduct heat to the outside. In some embodiments, the first insulating layer IL1 may include a first filler, and the second insulating layer IL2 may include a second filler, and the particle size of the first filler is larger than that of the second filler, which can help further improve the support of the connection substrate 100. In other embodiments, the first filler and / or the second filler may include a thermally conductive material with good thermal conductivity to help improve the heat dissipation efficiency of the connection substrate 100. In some embodiments, the thermally conductive material may include materials such as silicon, diamond powder, silicon carbide (SiC), metal, graphene, barium sulfide (BaS), boron nitride (BN), graphite, TiO2, AlN, Al2O3, or ceramic. In some embodiments, the thermal conductivity (in W / mK) of the first filler may be the same as or different from that of the second filler. For example, the first filler may be filled with silicon carbide and the second filler may be filled with diamond powder. The first filler and the second filler may be in contact with each other at least. This design creates an effective heat dissipation path to improve the heat dissipation effect of the electronic device.

[0036] In some embodiments, the first heat dissipation structure HD1 may include at least one heat dissipation layer HDL1 and at least one heat dissipation via HDV1 overlapping the heat dissipation layer HDL1, and the second heat dissipation structure HD2 may include at least one heat dissipation layer HDL2 and at least one heat dissipation via HDV2 overlapping the heat dissipation layer HDL2. The heat dissipation layer HDL1 and the heat dissipation via HDV1 may be integrated into the process of forming the first wiring structure WS1a, while the heat dissipation layer HDL2 and the heat dissipation via HDV2 may be integrated into the process of forming the second wiring structure WS2a. In other words, the first wiring structure WS1a or the second wiring structure WS2a may include a conductive layer disposed at the same level as the heat dissipation layer HDL1 or HDL2 and a conductive via (e.g., a conductive via disposed at the same level as the heat dissipation via HDV1 or HDV2 and in contact with the conductive layer). Figure 1 (As shown).

[0037] In some embodiments, the heat dissipation layer HDL2 of the second heat dissipation structure HD2 can serve as a heat dissipation plane and be disposed in a dummy region of the second insulating layer IL2 below the electronic unit EU1 and the electronic unit EU2 (e.g., in a region where there is no path electrically connecting the electronic unit EU1 and the electronic unit EU2). In some embodiments, please also refer to... Figure 1 and Figure 3The aforementioned dummy region can correspond to the hot spots of electronic units EU1 and EU2, or the dummy region can overlap with the hot spots of electronic units EU1 and EU2, and the ratio R3 of the horizontal area of ​​the heat dissipation layer HDL2 (e.g., the area observed / measured in the top view, such as the sum of area A1 and area A2) to the horizontal area of ​​electronic units EU1 and EU2 can be greater than or equal to 20% and less than or equal to 40%. It is worth noting that when the heat dissipation layer HDL2 is rectangular, areas A1 and A2 can be obtained by multiplying the dimension of the heat dissipation layer HDL2 in the X direction by its dimension in the Y direction, but this is not a limitation.

[0038] In some embodiments, such as Figure 3 As shown, the conductive layers of the heat dissipation layer HDL2 and the wiring structure WS2a can be disposed at the same horizontal level and spaced apart from each other, and the conductive vias of the heat dissipation via HDV2 and the wiring structure WS2a can be disposed at the same horizontal level and spaced apart from each other. In other embodiments, the conductive layers of the heat dissipation layer HDL2 and the wiring structure WS2a can be disposed at different horizontal levels; for example, the conductive layers of the heat dissipation layer HDL2 and the wiring structure WS2a can be disposed at different horizontal levels. Figure 2 In the insulating layers IL2a and IL2b shown, in an embodiment where the heat dissipation layer HDL2 and the wiring structure WS2a overlap in the Z direction, the conductive vias of the wiring structure WS2a can pass through the heat dissipation layer HDL2 to transmit electrical signals to conductive layers at other levels, and the heat dissipation vias HDV2 can also pass through the conductive layers of the wiring structure WS2a to transfer heat to heat dissipation layers at other levels. When the heat dissipation layer HDL2 comprises a conductive material, the conductive vias of the wiring structure WS2a can pass through the heat dissipation layer HDL2 without contacting it (e.g., the heat dissipation layer HDL2 may include openings for the conductive vias to pass through, but is not limited thereto). When the heat dissipation vias HDV2 comprise a conductive material, the heat dissipation vias HDV2 can pass through the conductive layers of the wiring structure WS2a without contacting it (e.g., the conductive layers of the wiring structure WS2a may include openings for the heat dissipation vias HDV2 to pass through, but is not limited thereto).

[0039] In this embodiment, the second base structure BS2 may include a wiring structure WS2b connecting the first heat dissipation structure HD1 and the second heat dissipation structure HD2, so that the heat from the electronic units EU1 and EU2 can not only be transferred to the adjacent second heat dissipation structure HD2, but also further transferred to the lower first heat dissipation structure HD1 through the wiring structure WS2b, thereby improving the heat dissipation efficiency of the electronic device 10. In this embodiment, the first base structure BS1 may include a wiring structure WS1b connecting the first heat dissipation structure HD1, so that the heat can also be further transferred to the heat dissipation structure in the lower component (e.g., the heat dissipation structure in the external component 200) through the wiring structure WS1b, thereby improving the heat dissipation efficiency of the electronic device 10.

[0040] In some embodiments, such as Figure 1 and Figure 4 As shown, the first base structure BS1 or the second base structure BS2 may include a support layer SL disposed in the first insulating layer IL1 or the second insulating layer IL2, which can help adjust the support and coefficient of thermal expansion of the connecting substrate 100. Figure 4 As shown, the support layer SL can be disposed in the second insulating layer IL2 of the second base structure BS2, but is not limited thereto; the support layer SL can also be disposed in the first insulating layer IL1 of the first base structure BS1. In some embodiments, the conductive layer of the support layer SL and the wiring structure WS2a can be disposed at different levels; for example, the conductive layer of the support layer SL and the wiring structure WS2a can be disposed at different levels. Figure 2 In the insulating layers IL2a and IL2b shown. In some embodiments, such as Figure 4 As shown, a support layer SL may be disposed above some wiring layers WS2ao in the wiring structure WS2a. In some embodiments, when the support layer SL comprises a conductive material, the support layer SL may be disposed above the wiring layers WS2ao without contacting them. In other embodiments, when the support layer SL comprises an insulating material, the support layer SL may be disposed on and in contact with the wiring layers WS2ao.

[0041] In other embodiments, the support layer SL may include a heat-dissipating material and act as a heat-dissipating layer in contact with the reinforcement SR1 (mentioned later), thereby improving heat dissipation efficiency. For example, the support layer SL may include metallic materials (e.g., copper, titanium, molybdenum, or aluminum), alloy materials (e.g., Invar, or nickel-steel alloy), ceramic materials (e.g., boron nitride or silicon carbide), carbon materials with a specific thermal orientation or good thermal conductivity (e.g., graphene or carbon nanotubes), or combinations thereof. In some embodiments, when the support layer SL is an alloy material, the thickness of the support layer SL may be between 10 micrometers and 30 micrometers. In embodiments where the support layer SL acts as a heat dissipating layer, a heat dissipation via HDV2 may be thermally coupled to the support layer SL, allowing heat generated by electronic unit EU1 or electronic unit EU2 to be transferred to other locations through the heat dissipation via HDV2 and the support layer SL, thereby improving heat dissipation efficiency. In some embodiments, a thermal interface layer TIM1 may be provided between the support layer SL and the reinforcement SR1 to improve heat transfer efficiency, but this is not a limitation.

[0042] In other embodiments, the support layer SL may be disposed below the wiring layer WS2ao or at the same level as the wiring structure WS2a. In embodiments where the support layer SL and the wiring layer WS2ao overlap in the Z direction (e.g., the support layer SL may be disposed above or below the wiring layer WS2ao), conductive vias of the wiring structure WS2a may pass through the support layer SL to transmit electrical signals to conductive layers at other levels, and heat dissipation vias HDV2 may also pass through the wiring layer WS2ao to transfer heat to heat dissipation layers at other levels. When the support layer SL comprises a conductive material, conductive vias of the wiring structure WS2a may pass through the support layer SL without contacting it (e.g., the support layer SL may include openings for conductive vias to pass through, but is not limited thereto). When the support layer SL comprises a conductive material and is disposed at the same level as the wiring structure WS2a, the support layer SL and the wiring structure WS2a may be spaced apart from each other.

[0043] In some embodiments, the support layer SL disposed in the second insulating layer IL2 and the support layer SL disposed in the first insulating layer IL1 may have different sizes to accommodate different requirements for heat dissipation efficiency and support. For example, the support layer SL disposed in the second insulating layer IL2 may have a larger size than the support layer SL disposed in the first insulating layer IL1 because it is adjacent to the electronic units EU1 and EU2. This can help improve heat dissipation efficiency (when the support layer SL includes a heat dissipation material), or allow the coefficient of thermal expansion (CTE) of the connecting substrate 100 to vary gradually as needed, thereby helping to improve the reliability of the electronic device 10. In some embodiments, the support layer SL may be disposed near the center of the connecting substrate 100 (e.g., at the center in the horizontal direction) to adjust the coefficient of thermal expansion of the connecting substrate 100 or to improve the stability of the connecting substrate 100.

[0044] The first base structure BS1 may include a first heat dissipation structure HD1 and / or a support layer SL, and the second base structure BS2 may include a second heat dissipation structure HD2 and / or a support layer SL. In embodiments where the first base structure BS1 includes the first heat dissipation structure HD1 and the support layer SL, the first heat dissipation structure HD1 and the support layer SL may be respectively disposed in different insulating layers of the first insulating layer IL1, such as insulating layers IL1a and IL1b, but are not limited thereto. In embodiments where the second base structure BS2 includes the second heat dissipation structure HD2 and the support layer SL, the second heat dissipation structure HD2 and the support layer SL may be respectively disposed in different insulating layers of the second insulating layer IL2, such as insulating layers IL2a and IL2b, but are not limited thereto.

[0045] Please continue to refer to Figure 1 In this embodiment, the coefficient of thermal expansion of the connecting substrate 100 can be calculated in the following way. The volume occupied by the first insulating layer IL1 of the first base structure BS1 is V. A1 And has a value of CTE A1 The coefficient of thermal expansion, and the volume occupied by the wiring structures WS1a and WS1b of the first base structure BS1 is V. B1 And has a value of CTE B1 The coefficient of thermal expansion. The volume occupied by the second insulation layer IL2 of the second base structure BS2 is V. A2 And has a value of CTE A2 The coefficient of thermal expansion, and the volume occupied by the wiring structures WS2a and WS2b of the second base structure BS2 is V. B2 And has a value of CTE B2 The coefficient of thermal expansion. The coefficient of thermal expansion of the connecting substrate 100 can be V. A1 *(CTE A1 ) / (VA1 +V B1 +V A2 +V B2 V B1 *(CTE B1 ) / (V A1 +V B1 +V A2 +V B2 V A2 *(CTE A2 ) / (V A1 +V B1 +V A2 +V B2 ) and V B2 *(CTE B2 ) / (V A1 +V B1 +V A2 +V B2 The sum of ).

[0046] In this embodiment, the connecting substrate 100 may include a first adjustment layer ADL1 disposed between the first base structure BS1 and the second base structure BS2 to help adjust the coefficient of thermal expansion of the connecting substrate 100 (for example, the calculation method of the coefficient of thermal expansion described above will include the coefficient of thermal expansion of the first adjustment layer ADL1 and its volume). In some embodiments, the coefficient of thermal expansion of the first adjustment layer ADL1 is less than the coefficients of thermal expansion of the first insulating layer IL1 and the second insulating layer IL2. In some embodiments, the first adjustment layer ADL1 may be, for example, an organic material, a polymer, an epoxy resin, an oxide, silicon dioxide, or silicon nitride, but is not limited thereto. In some embodiments, the thermal conductivity of the first adjustment layer ADL1 may be between the thermal conductivity of the first base structure BS1 and the thermal conductivity of the second base structure BS2.

[0047] In some embodiments, the connecting substrate 100 may include a second adjustment layer ADL2, wherein the second adjustment layer ADL2 is disposed on the side of the first base structure BS1 away from the second base structure BS2. The second adjustment layer ADL2 may be, for example, a polymer or epoxy resin, but is not limited thereto. In some embodiments, the second adjustment layer ADL2 may be, for example, an anti-warping layer to help improve the warping of the connecting substrate 100. The anti-warping layer may be a single-layer or multi-layer structure comprising organic and / or inorganic materials, wherein the inorganic materials may include silicon dioxide (SiO2) or silicon nitride (SiO2). x N y ), silicon oxynitride (SiO) x N y (or other suitable inorganic materials, but this disclosure is not limited thereto.)

[0048] In some embodiments, the connection substrate 100 may include pads CP1, CP2, and CP3. Pad CP1 may be disposed in the second adjustment layer ADL2 to connect wiring structures WS1a and WS1b in the first base structure BS1 to the underlying external component 200. Pad CP2 may be disposed in the first adjustment layer ADL1 to connect wiring structures WS1a and WS1b in the first base structure BS1 to wiring structures WS2a and WS2b in the upper second base structure BS2. Pad CP3 may be disposed between the second base structure BS2 and electronic units EU1 and EU2 to connect electronic units EU1 and EU2 to the lower second base structure BS2. In some embodiments, pads CP1, CP2, and CP3 may each include signal paths (e.g., paths through wiring structures WS1a and WS2a) passing through signal pads therein and heat dissipation paths (e.g., paths through wiring structures WS1b and WS2b) passing through heat dissipation pads therein. Pads CP1, CP2, and CP3 may each comprise a material with good electrical and thermal conductivity. For example, pads CP1, CP2, and CP3 may comprise materials such as copper (Cu), aluminum (Al), nickel (Ni), or molybdenum (Mo).

[0049] In this embodiment, the electronic device 10 further includes an external component 200, a heat sink 300, and a reinforcement SR1. In some embodiments, the external component 200 may be a circuit board (e.g., a printed circuit board), but this disclosure is not limited thereto. In this embodiment, the external component 200 may be disposed below the connecting substrate 100 and connected to the external component 200 by a conductive element CE1 disposed between the connecting substrate 100 and the external component 200. In some embodiments, the conductive element CE1 may include a solder ball. The material of the conductive element CE1 may include tin-silver (SnAg), tin, silver, nickel, gold, copper, conductive adhesive, or suitable conductive materials thereof, but is not limited thereto. In this embodiment, the conductive element CE1 may improve the reliability of the electronic device 10 by ensuring a connection path between the connecting substrate 100 and the external component 200 through a bottom filler UF1 disposed between the external component 200 and the connecting substrate 100 and surrounding the conductive element CE1. In this embodiment, the first wiring structure WS1a and the second wiring structure WS2a can electrically connect the electronic units EU1 and EU2 to the external component 200.

[0050] In this embodiment, the heat sink 300 may be disposed above the electronic units EU1 and EU2 and may include a heat sink substrate 302 and a heat sink structure 304 disposed on the heat sink substrate 302. The heat sink substrate 302 and the heat sink structure 304 may each include any suitable thermally conductive material. In this embodiment, the heat sink structure 304 may be, for example, a heat sink fin with a fin-like structure. In some embodiments, a thermal interface layer TIM1 may be provided between the electronic units EU1 and EU2 and the heat sink 300 to improve heat transfer efficiency, but this is not a limitation. In some embodiments, a thermal interface layer TIM1 may be provided between the reinforcement SR1 and the heat sink 300 to improve heat transfer efficiency, but this is not a limitation. In some embodiments, a thermal interface layer TIM1 may be provided between the reinforcement SR1 and the external component 200 to improve heat transfer efficiency, but this is not a limitation.

[0051] In this embodiment, a stiffener SR1 may be disposed around the connecting substrate 100 and between the heat sink 300 and the external component 200, wherein heat dissipation layers HDL1 and HDL2 may extend laterally and contact the stiffener SR1, thereby allowing heat to be transferred from the stiffener SR1 to the heat sink 300 above. In some embodiments, heat dissipation layers HDL1 and HDL2 may extend laterally and directly contact the stiffener SR1. In other embodiments, a thermal interface layer TIM1 may be provided between the support layer SL and the stiffener SR1 to improve heat transfer efficiency, but is not limited thereto. In other embodiments, the stiffener SR1 may include a thermal interface material thermally coupled to the support layer SL to provide an interface for thermal coupling between the two. In some embodiments, the stiffener SR1 may be a stiffener ring surrounding the connecting substrate 100. The stiffener SR1 may include any suitable thermally conductive material, such as metal, conductive adhesive, or a combination thereof, such as copper, aluminum, thermal interface material, or a combination thereof, to improve the heat dissipation efficiency of the electronic device 10. In this embodiment, along a direction perpendicular to the Z direction (such as the X direction), the heat dissipation layers HDL1, HDL2 and heat dissipation vias HDV1, HDV2 are closer to the reinforcement SR1 than the conductive layers and conductive vias (e.g., the conductive layers and conductive vias included in the first wiring structure WS1a or the second wiring structure WS2a). That is, in the X direction, the heat dissipation layer HDL1 is disposed between the first wiring structure WS1a and the reinforcement SR1 to facilitate the heat dissipation of the electronic device 10.

[0052] The following will be through Figure 1 and cooperate Figure 2 The method of manufacturing an electronic device is described here, but the method of manufacturing the electronic device 10 is not limited thereto, and the same or similar components are represented by the same or similar element symbols, and will not be repeated here. Figure 2 yes Figure 1The connecting substrate is shown in a cross-sectional view of an embodiment of the present disclosure.

[0053] Please refer to Figure 1 A method for manufacturing an electronic device 10 may include the following steps. First, at least one electronic unit EU1 or EU2 is provided. Next, a connecting substrate 100 is provided, wherein the connecting substrate 100 is electrically connected to the electronic unit EU1 or EU2 and includes a first base structure BS1 and a second base structure BS2 disposed between the first base structure BS1 and the electronic unit EU1 or EU2. In this embodiment, the first base structure BS1 includes a first insulating layer IL1 and a first heat dissipation structure HD1 formed in the first insulating layer IL1, and the second base structure BS2 includes a second insulating layer IL2 and a second heat dissipation structure HD2 formed in the second insulating layer IL2. The thickness t1 of the first insulating layer IL1 is greater than the thickness t2 of the second insulating layer IL2, and the first heat dissipation structure HD1 and the second heat dissipation structure HD2 overlap. In some embodiments, the method of manufacturing the electronic device 10 may further include the following steps: providing a heat sink 300 above the electronic units EU1 and EU2; providing an external component 200 below the connecting substrate 100, wherein the external component 200 is electrically connected to the connecting substrate 100; and providing a reinforcement SR1 around the connecting substrate 100, wherein the reinforcement SR1 may be formed between the heat sink 300 and the external component 200, and the heat dissipation layers HDL1 and HDL2 are in contact with the reinforcement SR1.

[0054] In some embodiments, the first insulating layer IL1 or the second insulating layer IL2 may include a first portion formed using a first photolithography process employing a half-tone mask or a gray-tone mask. In some embodiments, the first insulating layer IL1 or the second insulating layer IL2 may include a second portion formed using a second photolithography process different from the first photolithography process. The second photolithography process uses a photomask different from the half-tone mask or the gray-tone mask, wherein the transmittance of light through the photomask is greater than the transmittance of light through the half-tone mask or the gray-tone mask.

[0055] For example, such as Figure 2As shown, the first base layer structure BS1 may include a redistribution layer RDL1a and a redistribution layer RDL1b located on the redistribution layer RDL1a. The insulating layer IL1a may be formed with vias and grooves containing wiring structures WS1a1 and WS1b using a photomask different from a halftone mask or a grayscale mask. The insulating layer IL1b may be formed with vias of different depths using a halftone mask or a grayscale mask. For example, the depth of the via containing wiring structure WS1a2 may be greater than the depth of the via containing heat dissipation via HDV1. That is, the process for forming the redistribution layer RDL1a may differ from the process for forming the redistribution layer RDL1b.

[0056] Similarly, such as Figure 2 As shown, the second base layer structure BS2 may include a redistribution layer RDL2a and a redistribution layer RDL2b located on the redistribution layer RDL2a. The insulating layer IL2a may use a photomask different from a halftone mask or a grayscale mask to form vias and grooves in which wiring structures WS2a1 and WS2b are formed. The insulating layer IL2b may use a halftone mask or a grayscale mask to form vias of different depths. For example, the depth of the via in which wiring structure WS2a2 is formed may be greater than the depth of the via in which heat dissipation via HDV2 is formed. That is, the process for forming the redistribution layer RDL2a may be different from the process for forming the redistribution layer RDL2b.

[0057] Figure 5A and Figure 5B This is a cross-sectional schematic diagram of a method for manufacturing a bonding substrate according to an embodiment of the present disclosure. Figure 6A and Figure 6B as well as Figure 7A and Figure 7B These are different embodiments of this disclosure. Figure 5B A cross-sectional schematic diagram of some steps in the method for forming the redistribution layer.

[0058] The following will be through Figure 5A and Figure 5B To illustrate the manufacturing method of the connecting substrate 100' in another embodiment.

[0059] Please refer to Figure 5AFirst, a carrier substrate CSub1 is provided. In some embodiments, the material of the carrier substrate CSub1 may include glass, quartz, sapphire, ceramic, stainless steel, silicon wafer, other suitable substrate materials, or combinations thereof, but is not limited thereto. Next, a release layer RL1 is provided on the carrier substrate CSub1. In some embodiments, the release layer RL1 may be a temporary bonding layer, which may include a thermally-type or optically-type release material with adhesive properties, so that subsequently formed working units, elements, or films can be temporarily attached to the release layer RL1. In other words, the release layer RL1 can assist in the removal of working units, elements, or films subsequently formed on the carrier substrate CSub1 from the carrier substrate CSub1. When a thermally-type release material is used to form the release layer RL1, the thermally-type release material loses its adhesiveness upon heating, allowing the elements or films formed thereon to be peeled off from the release layer RL1. For example, the release layer RL1 can be a thermal release tape (HRT) or a light-to-heat-conversion (LTHC) release coating. When an optical release material is used to form the release layer RL1, the optical release material loses its adhesiveness when exposed to radiation, such as ultraviolet light (UV light), allowing the elements or films formed thereon to be peeled off from the release layer RL1. Next, a first base structure BS1' is formed on the release layer RL1. In this embodiment, the first base structure BS1' may include an insulating layer IL1 and wiring structures WS1a' and WS1b' formed in the insulating layer IL1.

[0060] Next, a carrier plate CSub2 is provided. In some embodiments, the carrier plate CSub2 may be made of the materials listed above for the carrier plate CSub1, but is not limited thereto. Then, an anti-warping layer WAL1, a release layer RL2, and a protective layer PL1 are sequentially provided on the carrier plate CSub2. The anti-warping layer WAL1 may be a single-layer or multi-layer structure comprising organic and / or inorganic materials, wherein the inorganic materials may include silicon dioxide (SiO2) and silicon nitride (SiO2). x N y ), silicon oxynitride (SiO) x N y Other suitable inorganic materials may be used, but this disclosure is not limited thereto. Release layer RL2 may be made of the materials listed for release layer RL1 above, but is not limited thereto. Protective layer PL1 may include any suitable material. Next, a second base structure BS2' is formed on protective layer PL1.

[0061] In this embodiment, the second base layer structure BS2' may include a redistribution layer RDL2a' and a redistribution layer RDL2b' located on the redistribution layer RDL2a'. The insulating layer IL2a' may use a halftone mask or a grayscale mask to form vias of different depths. For example, the depth of the vias in which wiring structures WS2a1 and WS2b are formed may be greater than the depth of the vias in which functional elements WS2a' are formed. The insulating layer IL2b' may use a halftone mask or a grayscale mask to form vias of different depths. For example, the depth of the vias in which wiring structure WS2a2 is formed may be greater than the depth of the vias in which heat dissipation via HDV2 is formed.

[0062] Then, please refer to Figure 5A and Figure 5B The second base structure BS2' can be bonded to the first base structure BS1' using a hybrid bond method. In this embodiment, the interfaces between the first base structure BS1' and the second base structure BS2' include metal-to-metal bonding between wiring structures WS2a1, WS2b and wiring structure WS1a', and oxide-to-oxide bonding or PI-PI (polyimide-to-polyimide) bonding between insulating layers IL2a' and IL1.

[0063] In some embodiments, the functional element WS2a' may be a protective line formed in the insulating layer IL2a' and connected to the ground level. In this embodiment, the functional element WS2a' may be formed by filling a groove with metal (e.g., copper) to create a protective line connected to the ground level. In other embodiments, the functional element WS2a' may also be formed by filling a groove with a conductive adhesive to create a protective line connected to the ground level. In some embodiments, filler may be added to the conductive adhesive to adjust the coefficient of thermal expansion and / or increase heat dissipation efficiency. The filler size may be between 0.1 micrometers and 100 micrometers. The filler may include thermally conductive materials such as graphene, graphite, TiO2, AlN, Al2O3, or ceramics, or materials with a low coefficient of thermal expansion such as silicon dioxide. In some alternative embodiments, the functional element WS2a' may also be any adhesive material filled in the groove containing filler capable of adjusting the coefficient of thermal expansion and / or increasing heat dissipation efficiency to form a functional element that adjusts the coefficient of thermal expansion and / or increases heat dissipation efficiency. In some other embodiments, the functional element WS2a' may also be a material (e.g., Invar 36) filled in the groove to enhance support and / or increase heat dissipation efficiency, thus forming a functional element that enhances support and / or increases heat dissipation efficiency. In embodiments where the functional element serves a heat dissipation function, it may be connected to a heat dissipation path via other heat dissipation layers in another cross-section.

[0064] Please refer to Figure 5B and Figure 6A The opening OP1 in the redistribution layer RDL2a' can be an opening OP1 in which a functional element WS2a' is formed, while the opening OP2 in the redistribution layer RDL2a' can be an opening OP2 in which a wiring structure WS2a1 is formed. In some embodiments, openings OP1 and OP2 can be formed by using a mask PR1 (e.g., a halftone mask or a grayscale mask) formed on the insulating layer IL2a' as an etching mask and by a corresponding photolithography process. In some embodiments, openings OP1 and OP2 have different shapes and sizes, so the metal (e.g., copper) filled therein can also have different volumes, which can help adjust the coefficient of thermal expansion of the redistribution layer RDL2a'. That is, the functional element WS2a' can be formed in the desired area in the redistribution layer RDL2a' as needed to help adjust the warpage of the redistribution layer RDL2a'. In some embodiments, openings OP1 and OP2 can include sidewalls having an angle α with respect to the normal direction of their bottom surface. The angle α can be in the range of 30° to 85°. In other embodiments, openings of different shapes can be formed in the insulating layer IL2a' using different masks (e.g., Figure 6B (The openings OP1' and OP2' are shown).

[0065] In some embodiments, such as Figure 7A and Figure 7B As shown, different methods (e.g., excimer laser) can be used to form openings OP3 and OP4 in the insulating layer IL2a'. Opening OP3 in the redistribution layer RDL2a' can be an opening OP3 in which the functional element WS2a' is formed, while opening OP4 in the redistribution layer RDL2a' can be an opening OP4 in which the wiring structure WS2a1 is formed. In this embodiment, opening OP3 in which the functional element WS2a' is formed can have a depth d1, a bottom dimension w1, and a top dimension w2. The ratio of the bottom dimension w1 to the depth d1 can be between 0.3 and 1, and the bottom dimension w1 can be greater than or equal to 1 micrometer. In this embodiment, the top dimension w2 of opening OP3 can be greater than the bottom dimension w1 of opening OP3.

[0066] In other embodiments, such as Figure 7B As shown, opening OP3' may include a through hole V1 and a groove T1 communicating with the through hole V1, and opening OP4' may include a through hole V2 and a groove T2 communicating with the through hole V2. That is to say, opening OP3' in which the functional element WS2a' is formed and opening OP4' in which the wiring structure WS2a1 is formed can also be formed using a dual-damascene process.

[0067] Figure 8 This is a cross-sectional schematic diagram of a connecting substrate according to another embodiment of the present disclosure. Figure 8 The connecting substrate 100 shown is Figure 5B The connection substrate 100' shown is similar to the connection substrate 100', except that the first base structure BS1" and the second base structure BS2" of the connection substrate 100" are different from the first base structure BS1' and the second base structure BS2' of the connection substrate 100'. Other identical or similar components are indicated by the same or similar reference numerals, and will not be described again here.

[0068] Please refer to Figure 8The first base layer structure BS1” may include an insulating layer IL1 and wiring structures WS1a” and WS1b” formed in the insulating layer IL1, while the second base layer structure BS2” may include a redistribution layer RDL2a” and a redistribution layer RDL2b located on the redistribution layer RDL2a”. The insulating layer IL2a may use a photomask different from a halftone mask or a grayscale mask to form vias and grooves in the insulating layer IL2a, in which wiring structures WS2a1 and WS2b are formed. The insulating layer IL2b may use a halftone mask or a grayscale mask to form vias of different depths in the insulating layer IL2b. For example, the depth of the via in which wiring structure WS2a2 is formed may be greater than the depth of the via in which heat dissipation via HDV2 is formed. That is, the process for forming the redistribution layer RDL2a” may be different from the process for forming the redistribution layer RDL2b”.

[0069] In this embodiment, the fabrication process of the wiring structures WS1a” and WS1b” formed in the insulating layer IL1 may include laser drilling, while the fabrication process of the wiring structures WS2a1 and WS2b formed in the insulating layer IL2a and / or the wiring structure WS2a2 formed in the insulating layer IL2b, along with the heat dissipation via HDV2 and heat dissipation layer HDL2 in the heat dissipation structure, may include photolithography. That is, the size of the conductive layer or conductive via of the wiring structures WS1a” and WS1b” formed in the insulating layer IL1 may be larger than the size of the conductive layer or conductive via of the wiring structures WS2a1 and WS2b formed in the insulating layer IL2a, or larger than the size of the conductive layer or conductive via of the wiring structure WS2a2 formed in the insulating layer IL2b, and the size of the heat dissipation via HDV2 and heat dissipation layer HDL2 in the heat dissipation structure. The dimensions referred to in this disclosure may include any one of thickness, height, or width.

[0070] In this embodiment, electronic units EU1' and EU2' can be disposed on the connecting substrate 100", wherein electronic unit EU1' is electrically connected to the connecting substrate 100" via end electrode EE1, and electronic unit EU2' is electrically connected to the connecting substrate 100" via end electrode EE2. End electrode EE1 can extend from the bottom side of electronic unit EU1', contacting the pad CP3, and extending along the sidewall of electronic unit EU1' to the top side of electronic unit EU1'. End electrode EE2 can be disposed on the bottom side of electronic unit EU2' and contacting the pad CP3. End electrodes EE1 and EE2 can each comprise any suitable conductive material.

[0071] In this embodiment, the reinforcement SR1 can be a composite structure. The reinforcement SR1 can include a stack of any suitable thermally conductive materials, such as metals, conductive adhesives, or combinations thereof, such as copper, aluminum, thermal interface materials, or combinations thereof, to improve the heat dissipation efficiency of the electronic device 10. The reinforcement SR1 can have a first sub-part SR1-1 and a second sub-part SR1-2, wherein, in the X direction, the second sub-part SR1-2 is disposed between the first sub-part SR1-1 and the first base structure BS1” and the second base structure BS2”, and the toughness of the second sub-part SR1-2 can be between the insulating layer IL1 of the first sub-part SR1-1 and the insulating layer IL2 of the first base structure BS1” and the second base structure BS2”. The toughness referred to in this disclosure can be measured by a universal testing machine using the stress-strain curve of the sample, and the area enclosed under the stress-strain curve is called the toughness of the material.

[0072] In summary, in the embodiments of this disclosure, the first heat dissipation structure of the connecting substrate is designed to overlap with the second heat dissipation structure, and the first heat dissipation structure and the second heat dissipation structure are in contact with at least a portion of the reinforcement. This can help improve the heat dissipation efficiency and support of the connecting substrate, thereby improving the reliability of the electronic device.

[0073] The above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure. Features between embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0074] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that those skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure, and features between the various embodiments can be arbitrarily mixed and substituted to form other new embodiments. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of the specification. Those skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, material composition, apparatus, methods, and steps can be used according to this disclosure as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments. The scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. An electronic device, characterized in that, include: At least one electronic unit; A connecting substrate, electrically connected to the electronic unit, and comprising a first base layer structure and a second base layer structure disposed between the first base layer structure and the electronic unit; and Reinforcing members surround the connecting substrate. The first base structure includes a first insulating layer and a first heat dissipation structure disposed in the first insulating layer, and the second base structure includes a second insulating layer and a second heat dissipation structure disposed in the second insulating layer. The first heat dissipation structure overlaps with the second heat dissipation structure, and the first heat dissipation structure and the second heat dissipation structure are in contact with at least a portion of the reinforcement.

2. The electronic device according to claim 1, characterized in that, The first insulating layer includes a first filler, the second insulating layer includes a second filler, the thickness of the first insulating layer is greater than the thickness of the second insulating layer, and the particle size of the first filler is greater than the particle size of the second filler.

3. The electronic device according to claim 1, characterized in that, The connecting substrate includes a first adjustment layer disposed between the first base structure and the second base structure.

4. The electronic device according to claim 3, characterized in that, The coefficient of thermal expansion of the first adjustment layer is less than that of the first insulating layer and the second insulating layer.

5. The electronic device according to claim 1, characterized in that, The first heat dissipation structure includes at least one first heat dissipation layer and at least one first heat dissipation through hole overlapping the at least one first heat dissipation layer, and the second heat dissipation structure includes at least one second heat dissipation layer and at least one second heat dissipation through hole overlapping the at least one second heat dissipation layer.

6. The electronic device according to claim 5, characterized in that, The first base structure or the second base structure includes a support layer disposed in the first insulating layer or the second insulating layer.

7. The electronic device according to claim 5, characterized in that, Also includes: A heat sink is disposed above the electronic unit; as well as An external component is disposed below the connecting substrate and electrically connected to the connecting substrate.

8. The electronic device according to claim 7, characterized in that, The first base layer structure includes a first wiring structure, and the second base layer structure includes a second wiring structure, wherein the first wiring structure and the second wiring structure electrically connect the electronic unit to the external component. The first wiring structure or the second wiring structure includes a conductive layer disposed at the same level as the at least one first heat dissipation layer or the at least one second heat dissipation layer, and a conductive via disposed at the same level as the at least one first heat dissipation via or the at least one second heat dissipation via, wherein the conductive layer is in contact with the conductive via.

9. The electronic device according to claim 8, characterized in that, The at least one first heat dissipation layer or the at least one second heat dissipation layer is adjacent to the reinforcement relative to the conductive layer, and the at least one first heat dissipation through hole or the at least one second heat dissipation through hole is adjacent to the reinforcement relative to the conductive through hole.

10. The electronic device according to claim 8, characterized in that, The thickness of the conductive layer in the first wiring structure is greater than the thickness of the conductive layer in the second wiring structure.

11. A method for manufacturing an electronic device, characterized in that, include: Provide at least one electronic unit; A connection substrate is provided, wherein the connection substrate is electrically connected to the electronic unit, and includes a first base layer structure and a second base layer structure disposed between the first base layer structure and the electronic unit; and Provide reinforcement components surrounding the connecting substrate. The first base structure includes a first insulating layer and a first heat dissipation structure formed in the first insulating layer, and the second base structure includes a second insulating layer and a second heat dissipation structure formed in the second insulating layer. The first heat dissipation structure overlaps with the second heat dissipation structure, and the first heat dissipation structure and the second heat dissipation structure are in contact with at least a portion of the reinforcement.

12. The method according to claim 11, characterized in that, The first insulating layer includes a first filler, the second insulating layer includes a second filler, the thickness of the first insulating layer is greater than the thickness of the second insulating layer, and the particle size of the first filler is greater than the particle size of the second filler.

13. The method according to claim 11, characterized in that, The first insulating layer or the second insulating layer includes a first portion formed using a first photolithography process employing a halftone mask or a grayscale mask.

14. The method according to claim 13, characterized in that, The first insulating layer or the second insulating layer includes a second portion formed using a second photolithography process different from the first photolithography process. The second photolithography process uses a photomask different from the halftone mask or the grayscale mask, and the transmittance of light through the photomask is greater than the transmittance of light through the halftone mask or the grayscale mask.

15. The method according to claim 11, characterized in that, The connecting substrate includes a first adjustment layer provided between the first base layer structure and the second base layer structure, wherein the coefficient of thermal expansion of the first adjustment layer is less than the coefficients of thermal expansion of the first insulating layer and the second insulating layer.

16. The method according to claim 11, characterized in that, The first heat dissipation structure includes at least one first heat dissipation layer and at least one first heat dissipation through hole overlapping the at least one first heat dissipation layer, and the second heat dissipation structure includes at least one second heat dissipation layer and at least one second heat dissipation through hole overlapping the at least one second heat dissipation layer.

17. The method according to claim 16, characterized in that, Also includes: A heat sink is provided above the electronic unit; as well as An external component is provided beneath the connecting substrate, wherein the external component is electrically connected to the connecting substrate.

18. The method according to claim 17, characterized in that, The first base layer structure includes a first wiring structure, and the second base layer structure includes a second wiring structure, wherein the first wiring structure and the second wiring structure electrically connect the electronic unit to the external component. The first wiring structure or the second wiring structure includes a conductive layer disposed at the same level as the at least one first heat dissipation layer or the at least one second heat dissipation layer, and a conductive via disposed at the same level as the at least one first heat dissipation via or the at least one second heat dissipation via, wherein the conductive layer is in contact with the conductive via.

19. The method according to claim 18, characterized in that, The at least one first heat dissipation layer or the at least one second heat dissipation layer is adjacent to the reinforcement relative to the conductive layer, and the at least one first heat dissipation through hole or the at least one second heat dissipation through hole is adjacent to the reinforcement relative to the conductive through hole.

20. The method according to claim 18, characterized in that, The thickness of the conductive layer in the first wiring structure is greater than the thickness of the conductive layer in the second wiring structure.

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