Wiring substrate

Abstract

The present invention provides a wiring substrate having a novel structure. The wiring substrate (10) is provided with a substrate (20) having a conductor layer (26), and an optical element region (30) and an optical waveguide (40) are provided on the substrate (20). The optical waveguide (40) has a lower cladding (41), a core (42) and an upper cladding (43). An electrical connection material (50) for electrically connecting the conductor layer (26) to the optical element region (30) is present in the optical element region (30). The core (42) of the optical waveguide (40) that is optically coupled to the optical element region (30) is exposed, and multiple optical waveguides (40) are provided.

Description

Technical Field

[0001] This invention relates to wiring substrates. Background Technology

[0002] Patent Document 1 discloses an optical module having an optical waveguide with tilting mirrors formed on a substrate. Additionally, Patent Document 1 also discloses an optical module having a surface-type optical element mounted on the upper surface of the optical waveguide, with a substrate-side pad and a surface-type optical element-side pad connected by solder protrusions.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2003-215371 Summary of the Invention

[0006] The wiring substrate of the present invention, for example, is configured with a substrate having a conductor layer, on which an optical element region and an optical waveguide are configured. The optical waveguide has a lower cladding, a core, and an upper cladding. An electrical connection material for electrically connecting the conductor layer to the optical element region is present in the optical element region. The core of the optical waveguide that is optically coupled to the optical element region is exposed, and multiple optical waveguides are configured. Attached Figure Description

[0007] Figure 1A This is a cross-sectional view of the wiring substrate 10 with the optical waveguide 40 arranged in two directions.

[0008] Figure 1B This is a top view of the wiring substrate 10 with the optical waveguide 40 arranged in two directions.

[0009] Figure 2 This is a top view of the wiring substrate 10A with the optical waveguide 40 arranged in three directions.

[0010] Figure 3 This is a top view of the wiring substrate 10B with the optical waveguide 40 arranged in four directions.

[0011] Figure 4A This is a cross-sectional view of a wiring substrate 10C in which the optical waveguide 40 is configured in two directions and the chip 80 is configured.

[0012] Figure 4B This is a top view of the wiring substrate 10C on which the optical waveguide 40 is configured in two directions and the chip 80 is configured.

[0013] Figure 4C This is a top view of the wiring substrate 10D on which the optical waveguide 40 is arranged in three directions and the chip 80 is arranged.

[0014] Figure 4DThis is a top view of the wiring substrate 10E on which the optical waveguide 40 is arranged in four directions and the chip 80 is arranged.

[0015] Figure 4E This is a top view of the wiring substrate 10F on which the chip 80 is arranged in two directions and two columns, with the optical waveguide 40 configured.

[0016] Figure 4F This is a top view of the wiring substrate 10G on which the optical waveguide 40 is arranged in three directions and two columns to accommodate the chip 80.

[0017] Figure 4G This is a top view of the wiring substrate 10H on which the optical waveguide 40 is arranged in four directions and two columns to accommodate the chip 80.

[0018] Figure 4H This is a top view of the wiring substrate 10I on which the chip 80 is arranged in a two-direction, three-column configuration of the optical waveguide 40.

[0019] Figure 4I This is a top view of the wiring substrate 10G on which the optical waveguide 40 is arranged in three directions and three columns to accommodate the chip 80.

[0020] Figure 4J This is a top view of the wiring substrate 10K on which the optical waveguide 40 is arranged in four directions and three columns to accommodate the chip 80.

[0021] Figure 5A This is a diagram showing the preparation process of substrate 20.

[0022] Figure 5B This is a diagram showing the formation process of the lower cladding layer 41.

[0023] Figure 5C This is a diagram showing the forming process of core 42.

[0024] Figure 5D This is a diagram showing the formation process of the upper cladding layer 43.

[0025] Figure 5E This is a diagram showing the installation process of the optical element 60.

[0026] Figure 6 This is a diagram showing the wiring substrate 10 of the first connection method.

[0027] Figure 7 This is a diagram showing the wiring substrate 10 of the second connection method.

[0028] Figure 8 This is a diagram showing the wiring substrate 10 of the third connection method.

[0029] Figure 9This is a diagram showing the wiring board 10 of the fourth connection method.

[0030] Figure 10 This is a diagram showing an insulating joint.

[0031] Figure 11 This is a cross-sectional view showing a multilayer substrate.

[0032] Figure 12 This is a cross-sectional view showing the structure of the multilayer substrate 20A.

[0033] Figure 13 This is a top view showing the first example of the optical waveguide 40.

[0034] Figure 14 This is a top view showing the optical waveguide 40 of the second example.

[0035] Figure 15 This diagram illustrates the function of various components, including the wiring board 10. Detailed Implementation

[0036] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The following embodiments are shown as preferred examples of wiring substrates. The embodiments are not limited to these examples.

[0037] The wiring substrate 10 is a substrate for inputting and outputting optical and electrical signals. Multiple optical waveguides 40 can be configured on the wiring substrate 10. In the following description, three types of orientations for configuring the optical waveguides 40 will be explained.

[0038] [Two directions]

[0039] Figure 1A This is a cross-sectional view of the wiring substrate 10 in which the optical waveguide 40 is arranged in two directions. Figure 1B This is a top view of the wiring substrate 10 in two directions in the configuration of the optical waveguide 40.

[0040] Figure 1A and Figure 1B The wiring substrate 10 shown is of the first type. The wiring substrate 10 has a substrate 20 including a conductor layer 26. An optical element region 30 and an optical waveguide 40 are disposed on the substrate 20. The optical waveguide 40 has a lower cladding layer 41, a core 42, and an upper cladding layer 43. In addition, multiple waveguides can also be disposed in one direction.

[0041] The optical element region 30 has an electrical connection material 50 that electrically connects the conductor layer 26 to the optical element region 30. The electrical connection material 50 is a metallic body such as solder bumps. The core 42 of the optical waveguide 40, which is optically coupled to the optical element region 30, is exposed. Multiple optical waveguides 40 are arranged. The multiple optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, two optical waveguides 40 are arranged in the left and right directions of the optical element region 30.

[0042] In addition, Figure 1A and Figure 1B In this configuration, two optical waveguides 40 are arranged in a straight line opposite to the optical element region 30, but they can also be arranged at different angles relative to the optical element region 30. That is, as shown... Figure 1B As shown, the two optical waveguides 40 are configured to intersect the outer edge of the optical element region 30 perpendicularly, but they can also be configured to intersect the outer edge of the optical element region 30 at an angle other than perpendicular (acute or obtuse angle). In this case, the left and right optical waveguides 40 can be configured at different angles. Furthermore, the two optical waveguides 40 may not be configured in a straight line relative to the optical element region 30, but rather in an L-shape or a V-shape. Moreover, the optical waveguides 40 may not be configured in a straight line relative to the optical element region 30. Figure 1B Instead of configuring two on the same straight line in the left and right directions, it is in... Figure 1B Two waveguides 40 are configured on the same straight line in the vertical direction. In other words, the optical waveguides 40 can be configured symmetrically about the left and right relative to the optical element region 30, or symmetrically vertically.

[0043] An optical element 60 is disposed in the optical element region 30. The optical element 60 performs optical signal input and output, and converts electrical signals into optical signals. The exposed portion of the core 42 is optically coupled to the terminal 61 of the optical element 60. In the optical element region 30, one optical element 60 can be coupled to multiple optical waveguides 40. In the optical element region 30, multiple structures combining one optical element with one optical waveguide 40 can be arranged in one direction.

[0044] The end of the upper cladding 43 of the optical waveguide 40 is the boundary with the optical element region 30. At one end of the optical waveguide 40 ( Figure 1A The inner end of the optical waveguide 40 can be configured with an optical element region 30. At the other end of the optical waveguide 40 ( Figure 1A The outer end of the device can be configured with an external connection component 70 (e.g., optical fiber, optical element, etc.).

[0045] [Three directions]

[0046] Figure 2 This is a top view of the wiring substrate 10A with the optical waveguide 40 arranged in three directions.

[0047] Figure 2 The wiring substrate 10A shown is the second type.

[0048] Multiple optical waveguides 40 are arranged in different directions around the optical element region 30. Specifically, three optical waveguides 40 are arranged in the left, right, and bottom directions of the optical element region 30. Other structures are similar to... Figure 1A as well as Figure 1B The same applies. Additionally, multiple waveguides can be configured in one direction. The three optical waveguides 40 are configured in a T-shape, but can also be configured in a Y-shape. The three optical waveguides 40 can also be configured entirely vertically along the up-down or left-right direction. Alternatively, the three optical waveguides 40 can be configured entirely at an angle relative to the up-down or left-right direction. Or, a portion of the three optical waveguides 40 can be configured vertically along the up-down or left-right direction, while the remaining portion is at an angle relative to the up-down or left-right direction.

[0049] [Four directions]

[0050] Figure 3 This is a top view of the wiring substrate 10B with the optical waveguide 40 arranged in four directions.

[0051] Figure 3 The wiring substrate 10B shown is the third type.

[0052] Multiple optical waveguides 40 are arranged in different directions around the optical element region 30. Specifically, four optical waveguides 40 are arranged in four directions: left, right, top, and bottom of the optical element region 30. Other structures are similar to... Figure 1A as well as Figure 1B The same applies. Additionally, multiple waveguides can be configured in one direction. Four optical waveguides 40 can be configured in a cross shape, but also in an X shape. All four optical waveguides 40 can be configured vertically or horizontally. All four optical waveguides 40 can also be configured at an angle relative to the vertical or horizontal direction. Alternatively, a portion of the four optical waveguides 40 can be configured vertically or horizontally, while the remaining portion is configured at an angle relative to the vertical or horizontal direction.

[0053] The optical element region 30 represents the area where optical elements 60 can be disposed. The exposed portion of the core 42 of the optical waveguide 40 can serve as the boundary line between the optical element region 30 and other regions. One or more optical elements 60 can be disposed in the optical element region 30, as well as semiconductor or electronic components other than optical elements 60. Furthermore, the optical element region 30 in areas where the optical waveguide 40 is not disposed can be formed in any size. For example, the optical element region 30 in areas where the optical waveguide 40 is not disposed can be determined by making the distance between the boundary line of the exposed portion of the core 42 of the optical waveguide 40 and the optical element 60 equal. For example, the length from the outer edge of the optical element region 30 to the optical element 60 can be set to the length from the inner end of the upper cladding 43 to the optical element 60.

[0054] 〔chip〕

[0055] Figure 4A This is a cross-sectional view of a wiring substrate 10C in which the optical waveguide 40 is configured in two directions and the chip 80 is configured. Figure 4B This is a top view of the wiring substrate 10C on which the optical waveguide 40 is configured in two directions and the chip 80 is configured.

[0056] Figure 4A as well as Figure 4B The wiring substrate 10C shown has a chip 80 electrically connected to the optical element 60. The chip 80 can be a circuit or an information processing circuit, or other chips. The chip 80 is capable of inputting or outputting electrical signals from the optical element 60. The chip 80 is capable of converting analog signals to digital signals or inputting or outputting electrical signals (digital signals) to other components or external terminals via the conductor layer 26 of the substrate 20.

[0057] like Figure 4B As shown, a chip 81, different from chip 80, can be disposed below chip 80. Chip 81 can be a chip with the same function as chip 80, or it can be a chip with a different function than chip 80. Chip 81 can be electrically connected to chip 80 or to optical element 60. In addition, the configuration of chip 81 shown is an example, and chip 81 can also be disposed in a location not shown (e.g., a substrate different from substrate 20).

[0058] The size of chips 80 and 81 is preferably larger than the size of optical element 60. However, the size of chips 80 and 81 can be smaller than the size of optical element 60, or they can be the same size.

[0059] like Figure 4A As shown, the height of chip 80 is preferably higher than the height of optical element 60. However, the height of chip 80 can be lower than the height of optical element 60, or it can be the same height. The same applies to chip 81.

[0060] like Figure 4B As shown, the size of chip 80 is preferably larger than the size of chip 81. However, the size of chip 80 can be smaller than the size of chip 81, or it can be the same size.

[0061] Chip 80 is positioned between two optical elements 60 in a straight line, with the optical elements 60-chip 80-optical element 60 forming a straight line. Chip 81 is not positioned between the two optical elements 60.

[0062] Chip 80 is configured entirely within optical element region 30. A portion of chip 81 is configured within optical element region 30. Alternatively, chip 81 can be configured entirely within optical element region 30 or outside of it.

[0063] Multiple optical elements 60 are arranged in the optical element region 30. Specifically, two optical elements 60 are arranged in the optical element region 30. Multiple optical waveguides 40 are arranged in different directions around the center of the optical element region 30. Specifically, two optical waveguides 40 are arranged in the left and right directions of the optical element region 30. Multiple optical waveguides 40 and multiple optical elements 60 are arranged in the optical element region 30. In addition, the optical waveguides 40 can be used as... Figure 2 As shown, three can be configured in three directions, or as... Figure 3 Four are arranged in four directions as shown. Furthermore, the optical element 60, chip 80, and chip 81 can be installed either after the optical element 60 is installed, or after the chip 80 and chip 81 are installed; the installation order of the optical element 60, chip 80, and chip 81 is not particularly limited. This is also the case in other wiring substrates.

[0064] Figure 4C This is a top view of the wiring substrate 10D on which the optical waveguide 40 is arranged in three directions and the chip 80 is arranged.

[0065] Figure 4C The wiring substrate 10D shown has a chip 80 that is electrically connected to the optical element 60. A chip 81, which is different from the chip 80, can be arranged below the chip 80.

[0066] Figure 4C The chips 80 and 81 of the wiring substrate 10D shown can be with Figure 4B The wiring substrate 10C shown may contain the same chip 80 and 81, or different chips. Chips 80 and 81 are configured to be integrated into the optical element region 30. Chip 81 may be configured to be partially integrated into the optical element region 30 or located outside the region 30. The size, height, and position of chips 80 and 81 may vary. Figure 4BThe wiring substrate 10C shown may be the same or different. In addition, the contents related to the chips 80 and 81 of the wiring substrate 10D are the same as those of the wiring substrates 10E, 10F, 10G, 10H, 10I, 10J and 10K.

[0067] Chip 80 is positioned between the left and right optical elements 60 in a straight line, with the left optical element 60, chip 80, and right optical element 60 forming a straight line. Chip 80 is positioned between the upper optical element 60 and chip 81 in a straight line, with the upper optical element 60, chip 80, and chip 81 forming a straight line. Chip 81 is not positioned between the left and right optical elements 60.

[0068] Multiple optical elements 60 are arranged in the optical element region 30. Specifically, three optical elements 60 are arranged in the optical element region 30. Multiple optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, three optical waveguides 40 are arranged in the left, right, and top directions of the optical element region 30. Multiple optical waveguides 40 and multiple optical elements 60 are arranged in the optical element region 30.

[0069] Figure 4D This is a top view of the wiring substrate 10E on which the optical waveguide 40 is arranged in four directions and the chip 80 is arranged.

[0070] Figure 4D The wiring substrate 10E shown has a chip 80 that is electrically connected to the optical element 60. On the right side below the chip 80, a chip 81, which is different from the chip 80, can be configured.

[0071] Chip 80 is positioned between the left and right optical elements 60 in a straight line, with the left optical element 60, chip 80, and right optical element 60 forming a straight line. Chip 80 is also positioned between the upper and lower optical elements 60 in a straight line, with the upper optical element 60, chip 80, and lower optical element 60 forming a straight line. Chip 81 is not positioned between the left and right optical elements 60. Chip 81 is not positioned between the upper and lower optical elements 60. Chip 81 is positioned where it partially overlaps with chip 80 when viewed vertically in the figure. Therefore, chip 80 and chip 81 can be connected vertically in the figure. Alternatively, chip 81 can be positioned where it does not overlap with chip 80 when viewed vertically in the figure.

[0072] Multiple optical elements 60 are arranged in the optical element region 30. Specifically, four optical elements 60 are arranged in the optical element region 30. Multiple optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, four optical waveguides 40 are arranged in four directions: left, right, top, and bottom of the optical element region 30. Multiple optical waveguides 40 and multiple optical elements 60 are arranged in the optical element region 30.

[0073] Figure 4E This is a top view of the wiring substrate 10F on which the chip 80 is arranged with the optical waveguides 40 in two directions and two columns. In addition, the two columns of optical waveguides 40 can be arranged in parallel or not in parallel (the same applies below).

[0074] Figure 4E The wiring substrate 10F shown has a chip 80 that is electrically connected to the optical element 60. A chip 81, which is different from the chip 80, can be arranged below the chip 80.

[0075] Chip 80 is positioned between the two left-side optical elements 60 and the two right-side optical elements 60 in a straight line. Chip 81 is not positioned between the two left-side optical elements 60 and the two right-side optical elements 60.

[0076] Multiple optical elements 60 are arranged in the optical element region 30. Specifically, four optical elements 60 are arranged in the optical element region 30. Multiple optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, two rows of optical waveguides 40 are arranged on the left and two rows on the right of the optical element region 30, for a total of four. Multiple optical waveguides 40 and multiple optical elements 60 are arranged in the optical element region 30.

[0077] Figure 4F This is a top view of the wiring substrate 10G on which the optical waveguide 40 is arranged in three directions and two columns to accommodate the chip 80.

[0078] Figure 4F The wiring substrate 10G shown has a chip 80 that is electrically connected to the optical element 60. A chip 81, which is different from the chip 80, can be arranged below the chip 80.

[0079] Chip 80 is positioned between the two left-side optical elements 60 and the two right-side optical elements 60 in a straight line. Chip 80 is also positioned between the two upper-side optical elements 60 and chip 81 in a straight line. Chip 81 is not positioned between the two left-side optical elements 60 and the two right-side optical elements 60.

[0080] Multiple optical elements 60 are arranged in the optical element region 30. Specifically, six optical elements 60 are arranged in the optical element region 30. Multiple optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, two rows of optical waveguides 40 are arranged in each of the three directions of the left, right and top of the optical element region 30, for a total of six. Multiple optical waveguides 40 and multiple optical elements 60 are arranged in the optical element region 30.

[0081] Figure 4G This is a top view of the wiring substrate 10H on which the optical waveguide 40 is arranged in four directions and two columns to accommodate the chip 80.

[0082] Figure 4G The wiring substrate 10H shown has a chip 80 that is electrically connected to the optical element 60. On the right side below the chip 80, a chip 81, which is different from the chip 80, can be configured.

[0083] Chip 80 is positioned between the two left-side optical elements 60 and the two right-side optical elements 60 in a straight line. Chip 80 is also positioned between the two upper-side optical elements 60 and the two lower-side optical elements 60 in a straight line. Chip 81 is not positioned between the two left-side optical elements 60 and the two right-side optical elements 60. Chip 81 is not positioned between the two upper-side optical elements 60 and the two lower-side optical elements 60. Chip 81 is positioned where it partially overlaps with chip 80 when viewed vertically in the figure. Therefore, chips 80 and 81 can be connected vertically in the figure. Alternatively, chip 81 can be positioned where it does not overlap with chip 80 when viewed vertically in the figure.

[0084] Multiple optical elements 60 are arranged in the optical element region 30. Specifically, eight optical elements 60 are arranged in the optical element region 30. Multiple optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, two rows of optical waveguides 40 are arranged in each of the four directions of the left, right, top, and bottom of the optical element region 30, for a total of eight. Multiple optical waveguides 40 and multiple optical elements 60 are arranged in the optical element region 30.

[0085] Figure 4H This is a top view of the wiring substrate 10I on which the chip 80 is arranged with the optical waveguides 40 in two directions and three columns. Furthermore, the three columns of optical waveguides 40 can be arranged in parallel or non-parallel configurations (the same applies below).

[0086] Figure 4HThe wiring substrate 10I shown has a chip 80 that is electrically connected to the optical element 60. A chip 81, which is different from the chip 80, can be arranged below the chip 80.

[0087] Chip 80 is positioned between the three optical elements 60 on the left and the three optical elements 60 on the right in a straight line. Chip 81 is not positioned between the three optical elements 60 on the left and the three optical elements 60 on the right.

[0088] Multiple optical elements 60 are arranged in the optical element region 30. Specifically, six optical elements 60 are arranged in the optical element region 30. Multiple optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, three rows of optical waveguides 40 are arranged on each of the left and right sides of the optical element region 30, for a total of six. Multiple optical waveguides 40 and multiple optical elements 60 are arranged in the optical element region 30.

[0089] Figure 4I This is a top view of the wiring substrate 10G on which the optical waveguide 40 is arranged in three directions and three columns to accommodate the chip 80.

[0090] Figure 4I The wiring substrate 10J shown has a chip 80 that is electrically connected to the optical element 60. On the right side below the chip 80, a chip 81, which is different from the chip 80, can be configured.

[0091] Chip 80 is positioned between the three left-side optical elements 60 and the three right-side optical elements 60 in a straight line. Chip 80 is positioned between the three upper-side optical elements 60 and chip 81 in a straight line. Chip 81 is not positioned between the three left-side optical elements 60 and the three right-side optical elements 60.

[0092] Multiple optical elements 60 are arranged in the optical element region 30. Specifically, nine optical elements 60 are arranged in the optical element region 30. Multiple optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, three rows of optical waveguides 40 are arranged in each of the three directions of the left, right and top of the optical element region 30, for a total of nine. Multiple optical waveguides 40 and multiple optical elements 60 are arranged in the optical element region 30.

[0093] Figure 4J This is a top view of the wiring substrate 10K on which the optical waveguide 40 is arranged in four directions and three columns, and the chip 80 is arranged.

[0094] Figure 4JThe wiring substrate 10K shown has a chip 80 that is electrically connected to the optical element 60. A chip 81, which is different from the chip 80, can be arranged below the chip 80.

[0095] Chip 80 is arranged between the three left-side optical elements 60 and the three right-side optical elements 60 in a straight line. Chip 80 is also arranged between the three upper-side optical elements 60 and the three lower-side optical elements 60 in a straight line. Chip 81 is not positioned between the three left-side optical elements 60 and the three right-side optical elements 60. Chip 81 is not positioned between the three upper-side optical elements 60 and the three lower-side optical elements 60. Chip 81 is positioned where it partially overlaps with chip 80 when viewed vertically in the figure. Thus, chips 80 and 81 can be connected vertically in the figure. Alternatively, chip 81 can be positioned where it does not overlap with chip 80 when viewed vertically in the figure.

[0096] Multiple optical elements 60 are arranged in the optical element region 30. Specifically, 12 optical elements 60 are arranged in the optical element region 30. Multiple optical waveguides 40 are arranged in different directions with the optical element region 30 as the center. Specifically, three rows of optical waveguides 40 are arranged in each of the four directions of the left, right, top, and bottom of the optical element region 30, for a total of 12. Multiple optical waveguides 40 and multiple optical elements 60 are arranged in the optical element region 30.

[0097] The number of columns in the optical waveguide 40 is illustrated with an example of 1 to 3, but it can also be 4 or more.

[0098] The number of columns in the optical waveguide 40 can be changed according to the orientation. For example, the optical waveguide 40 can have one column on the top and left sides, and two columns on the bottom and right sides. Alternatively, the optical waveguide 40 can have one column on the top and bottom sides, and two columns on the left and right sides. Furthermore, the optical waveguide 40 can have one column on the top side, two columns on the left side, three columns on the bottom side, and four columns on the right side.

[0099] The wiring substrates 10, etc. (wiring substrate 10, wiring substrate 10A, wiring substrate 10B, wiring substrate 10C, wiring substrate 10D, wiring substrate 10E, wiring substrate 10F, wiring substrate 10G, wiring substrate 10H, wiring substrate 10I, wiring substrate 10J, wiring substrate 10K) described herein can be manufactured through the processes shown below.

[0100] [Preparation process for substrate 20]

[0101] Figure 5AThis diagram illustrates the preparation process of substrate 20. The top view is a top view. The bottom left view is a side view. The bottom right view is a cross-sectional view. This is in... Figures 5B to 5E as well as Figures 6-9 The same applies to China.

[0102] The preparation process of substrate 20 is the process of preparing substrate 20 for wiring substrate 10. Any substrate can be used for substrate 20. Substrate 20 is preferably a substrate with a solder resist layer formed thereon. Substrate 20 is preferably a multilayer substrate or a subtractive substrate. In order to form electrical connection material 50, an opening is formed in substrate 20 for exposing conductor layer 26.

[0103] [Forming process of the lower cladding layer 41]

[0104] Figure 5B This is a diagram showing the formation process of the lower cladding layer 41.

[0105] The lower cladding layer 41 is formed on the substrate 20. The lower cladding layer 41 is formed by spin-coating onto the substrate 20. A resin film can be used for the lower cladding layer 41. The thickness of the lower cladding layer 41 can be any thickness. The thickness of the lower cladding layer 41 is preferably 5 μm to 100 μm, more preferably 10 μm to 50 μm.

[0106] [Core 42 Formation Process]

[0107] Figure 5C This is a diagram showing the forming process of core 42.

[0108] The core 42 is formed on the lower cladding layer 41. The core 42 is spin-coated onto the lower cladding layer 41 and then exposed and developed to achieve a predetermined shape. The core 42 can be a resin film. The exposed portion of the core 42 is rectangular. The core 42 can also be conical (a tapered shape that narrows towards the left in the figure) (refer to the dotted line). The thickness of the core 42 can be any thickness. The thickness of the core 42 is preferably 1 μm to 20 μm, more preferably 3 μm to 10 μm.

[0109] Core 42 can correspond to either a single-mode or a multi-mode system. The width of core 42 (the lateral length of core 42 as viewed in a side view) can be set to any width. The width of core 42 is preferably 1 μm to 40 μm, more preferably 3 μm to 20 μm. The height of core 42 is preferably 1 μm to 40 μm, more preferably 3 μm to 20 μm. The shape of core 42 (the shape of core 42 as viewed in a side view) can be square, rectangular, circular, elliptical, or other shapes.

[0110] The number of cores 42 can be set to any value. The number of cores 42 is preferably between 2 and 64. The number of cores 42 is preferably even. In the illustrated example, the number of cores 42 is shown as 4, but it can also be 3 or less, or even 5 or more. A cladding layer can also be disposed on the side of the cores 42. In this case, the resin used for the cores 42 can be irradiated with radiation to change the refractive index of the resin and form the cladding layer. The cores 42 can be formed by photolithography, photobleaching, and core cutting.

[0111] [Forming process of the upper cladding layer 43]

[0112] Figure 5D This is a diagram showing the formation process of the upper cladding layer 43.

[0113] The upper cladding layer 43 is formed on the core 42. The upper cladding layer 43 is formed by spin-coating onto the substrate 20. A resin film can be used for the upper cladding layer 43. The thickness of the upper cladding layer 43 can be any thickness. The thickness of the upper cladding layer 43 is preferably 5 μm to 100 μm, more preferably 10 μm to 50 μm. The lower cladding layer 41, the core 42, and the upper cladding layer 43 constitute the optical waveguide 40. In this case, an optical waveguide 40 with the core 42 exposed at one end, an optical waveguide 40 with the core 42 exposed at the other end, or an optical waveguide 40 with the core 42 exposed at both ends can be formed.

[0114] [Installation process of optical element 60]

[0115] Figure 5E This is a diagram showing the installation process of the optical element 60.

[0116] The mounting process of the optical element 60 is a process of mounting the optical element 60 on the substrate 20. In the mounting process of the optical element 60, the exposed portion of the core 42 is optically coupled to the terminal 61 of the optical element 60. One end of the optical element 60 ( Figure 5E The lower right surface of the optical element 60 is optically coupled to the core 42. The other end of the optical element 60 (… Figure 5E The lower left surface is electrically connected to the electrical connection material 50.

[0117] The optical element 60 can be mounted after forming an electrical connection material 50 on the substrate 20 where the optical waveguide 40 is disposed. The electrical connection material 50 can also be formed on the substrate 20 where the optical waveguide 40 is disposed. The optical waveguide 40 can also be disposed on the substrate 20 where the electrical connection material 50 is formed. Furthermore, the electrical connection material 50 can be a metallic body, or it can be a solder bump or a conductive pillar. For example, a tin-based solder or a gold-based solder can be used to form a solder bump. For conductive pillars, metals such as nickel or copper can also be formed. The electrical connection material 50 can also be provided in two or more layers as needed; for example, two layers of tin-based solder or gold-based solder can be used on the conductive pillars.

[0118] A translucent resin can also be disposed between the optical element 60 and the optical waveguide 40. A bottom filler can also be disposed between the optical element 60 and the electrical connection material 50. Furthermore, a bottom filler can be disposed at the other end of the optical waveguide 40 ( Figure 5E External connection component 70 is configured on the right end (see reference). Figure 1A Furthermore, the chip 80 can be configured as needed. The wiring substrate 10 and the like can be manufactured through such a process.

[0119] The wiring substrate 10 can employ, for example, the four connection methods shown below. However, the connection methods are not limited to these. These connection methods can be applied not only to the wiring substrate 10, but also to wiring substrates 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 10J, 10K, etc.

[0120] [First Connection Method]

[0121] Figure 6 This is a diagram showing the wiring substrate 10 of the first connection method.

[0122] The wiring substrate 10 of the first connection method connects an optical element 60 to one end of an optical waveguide 40 and an external connection component 70 to the other end of the optical waveguide 40. An optical element region 30 is disposed at one end of the optical waveguide 40, and the external connection component 70 is disposed at the other end. The core 42 at one end of the optical waveguide 40 is exposed, while the core 42 at the other end is not exposed. Alternatively, the optical waveguide can be disposed in place of the external connection component 70. The right end (the other end) of the optical waveguide 40 is coplanar with the right end of the substrate 20.

[0123] [Second Connection Method]

[0124] Figure 7 This is a diagram showing the wiring substrate 10 of the second connection method.

[0125] The wiring substrate 10 of the second connection method connects an optical element 60 to one end of an optical waveguide 40 and an optical waveguide 140 to the other end of the optical waveguide 40. An optical element region 30 is disposed at one end of the optical waveguide 40, and an optical waveguide 140 exposing a core 142 is disposed at the other end. In this case, the terminal 61 of the optical element 60 is optically coupled to the core 42 of the optical waveguide 40 at one end. Furthermore, the core 42 of the optical waveguide 40 at the other end is optically coupled to the core 142 of the optical waveguide 140.

[0126] In the wiring substrate 10 of the second connection method, the core 42 at one end of the optical waveguide 40 on the left side is exposed, and the core 42 at the other end is also exposed. This is also the case in the third and fourth connection methods.

[0127] [Third connection method]

[0128] Figure 8 This is a diagram showing the wiring substrate 10 of the third connection method.

[0129] The wiring substrate 10 of the third connection method connects an optical element 60 to one end of an optical waveguide 40 and an optical element 160 to the other end of the optical waveguide 40. An optical element region 30 is disposed at one end of the optical waveguide 40, and an optical element region 130, different from the optical element region 30, is disposed at the other end. One or more optical elements 160 can be disposed in the other optical element regions 130. In this case, the terminal 61 of the optical element 60 is optically coupled to the core 42 of the optical waveguide at one end. Additionally, the terminals 161 of the other optical elements 160 are optically coupled to the core 42 of the optical waveguide at the other end. The conductor layer of the substrate 20 is electrically connected to the optical element 60 via an electrical connection material 50. The conductor layer of the substrate 20 is electrically connected to the optical element 160 via an electrical connection material 150.

[0130] [Fourth Connection Method]

[0131] Figure 9 This is a diagram showing the wiring substrate 10 with the fourth connection method. Furthermore, Figure 9 The lower right figure is a cross-sectional view of the connection between the optical waveguide 40 and the external connection component 70.

[0132] The fourth connection method of the wiring substrate 10 involves connecting an optical element 60 to one end of an optical waveguide 40 and an external connection component 70 to the other end of the optical waveguide 40. An optical element region 30 is disposed at one end of the optical waveguide 40, and an external connection component 70 (e.g., optical fiber) exposing a core 71 is disposed at the other end. In this case, the terminal 61 of the optical element 60 is optically coupled to the core 42 of the optical waveguide 40. Additionally, the core 42 of the optical waveguide 40 is optically coupled to the core 71 of the external connection component 70. Furthermore, the external connection component 70 can have the same connection method relative to the wiring substrate 10, or it can have a different connection method relative to the wiring substrate 10. For example, multiple connections of the external connection component 70 can be configured with the same connection method, or they can be configured with different connection methods. Furthermore, when multiple optical waveguides are disposed on one side of the wiring substrate 10, the external connection component 70 can have the same connection method relative to multiple optical waveguides, or it can have a different connection method relative to multiple waveguides. That is, the connection method of the external connection component 70 can be freely changed. Furthermore, the connection method of the multiple connecting parts included in the external connecting component 70 can be freely changed.

[0133] Figure 10This diagram illustrates the thermally insulating bonding. The upper view in the diagram is a cross-sectional view of the wiring substrate 10. The lower view in the diagram is a top view of the wiring substrate 10.

[0134] The thermal bonding enables the exposed core 42 of the optical waveguide 40 to be optically coupled to the terminal 61 of the optical element 60.

[0135] Optical signal 90 is output through core 42 of optical waveguide 40 to terminal 61 of optical element 60. Optical element 60 converts optical signal 90 into electrical signal 91. Electrical signal 91 is output through electrical connection material 50 and transmitted to conductor layer 26. Terminal 61 is made of semiconductor or inorganic material. Terminal 61, for example, forms a silicon optical waveguide. Core 42 is made of organic or inorganic material. Core 42, for example, forms an optical waveguide from thermosetting resin or UV-curable resin.

[0136] Figure 11 This is a cross-sectional view illustrating the multilayer substrate.

[0137] Figure 1A The substrate 20 shown can be used Figure 11 The multilayer substrate 20A shown is a core substrate 21, a first insulating layer 22, a second insulating layer 23, a third insulating layer 24, a solder resist layer 25, a conductor layer 26, and through-holes 27. The first insulating layer 22, the second insulating layer 23, and the third insulating layer 24 are multilayers formed on both sides of the core substrate 21. It should be noted that the insulating layers can be two or fewer, or four or more.

[0138] The dimensions of the multilayer substrate 20A can be any size. Preferably, the dimensions of the multilayer substrate 20A are: less than 200 mm in length × less than 200 mm in width, and more preferably: less than 120 mm in length × less than 120 mm in width.

[0139] Multiple optical waveguides 40 and optical elements 60 are disposed on a multilayer substrate 20A. The optical elements 60 and the multilayer substrate 20A are connected by an electrical connection material 50. At one end of the optical waveguide 40 ( Figure 11 The inner end of the optical waveguide 40 can be configured with an optical element region 30. At the other end of the optical waveguide 40 ( Figure 11 The outer end of the device can be configured with external connection components 70 (such as optical fibers, optical elements, etc.) or optical waveguides.

[0140] The manufacturing process of the wiring substrate 10 (multilayer substrate 20A) is as follows. The following description illustrates one example of the manufacturing process of the wiring substrate 10. The manufacturing process of the wiring substrate 10 is not limited to this.

[0141] [The process of forming the core substrate 21]

[0142] The core substrate 21 formation process is the process of forming the core substrate 21 for the multilayer substrate 20A. In the core substrate 21 formation process, through-holes 27 are formed on the core substrate 21, which is a double-sided copper-clad laminate, by irradiation with a drill bit or laser. Conductors are formed on the inner walls of the through-holes 27 by plating, and conductor layers 26 are formed by a semi-additive or capping method. The voids in the through-holes 27 can be filled with resin. The voids in the through-holes 27 can also be filled with conductors. Conductor layers 26 are formed on both sides of the core substrate 21. The unevenness of the conductor layers 26 and the core substrate 21 can be flattened by filling with resin.

[0143] [The process of forming the insulating layer]

[0144] The insulating layer formation process involves forming insulating layers (first insulating layer 22, second insulating layer 23, and third insulating layer) using insulating resin. In this process, a raised / lowered layer is formed on the conductor layer 26 of the core substrate 21 by solution or plating. This raised / lowered layer ensures close adhesion between the conductor layer 26 and the insulating resin. The insulating resin can be a thermosetting resin or a UV-curable resin. The insulating layer is formed by curing the insulating resin. The insulating resin can be prepared by hot-pressing a film or by coating a resin composition. As an example, the insulating layer is formed by laminating an insulating resin such as a film-like epoxy resin and hot-pressing it. Through-holes are formed in the insulating layer, penetrating the insulating layer by irradiation with a laser such as carbon dioxide.

[0145] After forming through-holes, a conductor layer 26 is formed on the insulating layer using a semi-addition method or similar technique. This forms a via conductor within the through-holes of the insulating layer. The insulating layer is roughened using a strong oxidizing agent (chromic acid, permanganate, etc.). This roughening treatment roughens the resin surface to facilitate the fixation of the electroless copper. After roughening, a catalyst is applied to the entire substrate, and an electroless plating film is formed on the insulating layer. The electroless plating film contains copper, nickel, etc. The thickness of the electroless plating film is not particularly limited, but is preferably 0.1 μm to 5 μm. A dry film is formed on the insulating layer with the electroless plating. A circuit pattern of a conductor is formed on the dry film by exposure. The exposed dry film is developed using an alkali or similar agent to partially remove the film. This allows the formation portion and the non-formation portion of the dry film to be formed on the substrate. An electroplated film is formed on the non-formation portion of the dry film. The electroplated film contains copper, nickel, etc. The thickness of the electroplated film is not particularly limited, but is preferably 3 μm to 20 μm. Next, the dry film is peeled off, and a substrate with conductor layer 26 formed is obtained through chemical etching. Then, by forming an insulating layer on the substrate with conductor layer 26, a substrate with multilayered conductor layers can be obtained. The number of insulating layers is not limited; as an example, a three-layer substrate consisting of a first insulating layer 22, a second insulating layer 23, and a third insulating layer 24 can be used. This results in a substrate with multilayered conductor layers. Furthermore, by bonding two such substrates vertically, a multilayered substrate with three insulating layers – a core substrate with two insulating layers – and another with three insulating layers is formed.

[0146] [The process of forming solder resist layer 25]

[0147] The solder resist layer 25 is formed on the third insulating layer 24. In this process, the solder resist layer 25 is formed by coating or spraying a photosensitive epoxy resin. Through exposure and development, an opening is formed in the solder resist layer 25 that exposes a portion of the conductor layer 26.

[0148] [Forming process of electrical connection material 50]

[0149] The process of forming the electrical connection material 50 is a process of forming the electrical connection material 50 on the solder mask layer 25. In the process of forming the electrical connection material 50, the electrical connection material 50 is formed by mounting conductive balls based on solder or the like and by reflow processing. The multilayer substrate 20A is completed through the above processes.

[0150] [Forming process of optical waveguide 40]

[0151] The formation process of the optical waveguide 40 is a process of forming the optical waveguide 40 on the multilayer substrate 20A. In the formation process of the optical waveguide 40, a plurality of optical waveguides 40 are formed on the solder mask layer 25. In addition, optical elements 60 are arranged between the plurality of optical waveguides 40. The wiring substrate 10 is completed through the above processes.

[0152] Figure 12 This is a cross-sectional view showing the structure of the multilayer substrate 20A.

[0153] The multilayer substrate 20A can use a substrate with a fan-out structure. A fan-out structure is a structure in which wiring extends outward relative to the optical element 60 (chip).

[0154] A plurality of circular external terminals 93 are formed on the back side 92 of the optical element. A plurality of circular external terminals 95 are formed on the back side 94 of the underlying solder mask layer 25. The size of the external terminals 95 is larger than that of the external terminals 93. The number of external terminals 95 is less than the number of external terminals 93.

[0155] Figure 13 This is a top view showing the first example of the optical waveguide 40.

[0156] In the first example of the optical waveguide 40, the end E1 of the core 42 is positioned inside the end E2 of the lower cladding 41. The exposed length L1 of the core 42 can be any length. Preferably, the exposed length L1 of the core 42 is 10 mm or less, more preferably 5 mm or less, and even more preferably 3 mm or less. Furthermore, the exposed length L1 of the core 42 is the distance from the end (left end) of the upper cladding 43 of the optical waveguide 40 through the exposed core 42 to the end (left end) of the core 42.

[0157] Figure 14 This is a top view showing the optical waveguide 40 of the second example.

[0158] In the second example of the optical waveguide 40, the end E1 of the core 42 is positioned aligned with the end E2 of the lower cladding 41. The exposed length L2 of the core 42 can be set to any length. The exposed length L2 of the core 42 can be... Figure 13 The exposed length L1 of the core 42 is the same, or it can be longer than the exposed length L1 of the core 42.

[0159] Figure 15 This is a diagram illustrating the function of each component, such as the wiring substrate 10. The wiring substrate 10 preferably includes at least one of the components shown below.

[0160] The wiring substrate 10 and the like have an information processing circuit 100, a circuit 101 (EIC: Electrical IC), an optical element 60, and an optical waveguide 40.

[0161] The information processing circuit 100 performs information processing (calculation). The information processing circuit 100 outputs the calculation results to other information processing circuits and other components via digital signals.

[0162] Circuit 101 converts digital waveform signals into analog signals. Circuit 101 converts analog signals output from optical elements into digital signals.

[0163] Optical element 60 converts optical signals into analog electrical signals. Optical element 60 also converts analog electrical signals into optical signals. Furthermore, optical element 60 may also include the functionality of circuit 101. Optical element 60 including the functionality of circuit 101 can convert optical signals into analog electrical signals and can also convert analog electrical signals into digital signals. Figure 4A and Figure 4B Chips 80 and 81 in the circuit correspond to circuit 101 or information processing circuit 100.

[0164] Optical waveguide 40 transmits optical signals to other optical components. Optical waveguide 40 functions similarly to copper wiring in electrical signals. The optical signal is in analog form.

[0165] The flow on the incident side is as follows.

[0166] A simulated optical signal is input to optical waveguide 40. A simulated optical signal is output from optical waveguide 40.

[0167] A simulated optical signal is input to the optical element 60. The optical element 60 outputs a simulated electrical signal.

[0168] An analog electrical signal is input to circuit 101. Circuit 101 outputs a digital electrical signal.

[0169] A digital electrical signal is input to the information processing circuit 100. The information processing circuit 100 outputs a digital electrical signal.

[0170] The flow on the exit side is as follows.

[0171] A digital electrical signal is input to the information processing circuit 100. The information processing circuit 100 outputs a digital electrical signal.

[0172] Circuit 101 receives digital electrical signals as input. Circuit 101 outputs analog electrical signals.

[0173] An analog electrical signal is input to the optical element 60. The optical element 60 outputs an analog optical signal.

[0174] A simulated optical signal is input to optical waveguide 40. A simulated optical signal is output from optical waveguide 40.

[0175] As explained above, this embodiment has the following effects.

[0176] (1) According to this embodiment, the optical waveguide 40 exposes the core 42, thus reducing the height of the exposed portion of the core 42. Consequently, the electrical connection material 50 can be reduced in height, providing a wiring substrate 10 with excellent electrical connectivity and optical coupling. The closer the optical waveguide 40 is to the optical element 60, the less likely poor connection is to occur. Furthermore, since multiple optical waveguides 40 exist, they can be used for various applications, providing a wiring substrate 10 with high scalability. Moreover, since multiple optical waveguides 40 expose the core 42, a wiring substrate 10 with a novel structure can be provided.

[0177] (2) According to this embodiment, one or more optical elements 60 are arranged in the optical element region 30, so the number of optical elements 60 can be flexibly changed.

[0178] (3) According to this embodiment, multiple optical waveguides 40 are arranged in different directions (refer to...). Figure 1B , Figure 2 , Figure 3 Therefore, compared to arranging the optical waveguide 40 in one direction, the uses of the optical waveguide 40 can be increased.

[0179] (4) According to this embodiment, since the core 42 at the other end is not exposed (see reference) Figure 6 Therefore, it can suppress the loss of optical signals.

[0180] (5) According to this embodiment, since the core 42 at the other end is exposed (see reference) Figure 7 , Figure 8 , Figure 9 Therefore, the height of the exposed portion of core 42 can also be reduced at the other end.

[0181] (6) According to this embodiment, since an external connection component 70 (e.g., optical fiber) is disposed at the other end of the optical waveguide 40 (see reference 70), Figure 6 Therefore, the use of external connection component 70 can be increased to expand the applications of wiring board 10, etc.

[0182] (7) According to this embodiment, since an optical waveguide 40 (refer to) is disposed at the other end of the optical waveguide 40, Figure 7 Therefore, the optical waveguide 40 can be used to increase the applications of the wiring substrate 10, etc.

[0183] (8) According to this embodiment, other optical element regions 30 (see reference) are disposed at the other end of the optical waveguide 40. Figure 8 Therefore, it is possible to utilize other optical element areas 30 to increase the uses of wiring substrate 10, etc.

[0184] (9) According to this embodiment, since an external connection component 70 (e.g., optical fiber) is disposed at the other end of the optical waveguide 40 to expose the core 71 (see reference 40), Figure 9 Therefore, the external connection component 70 that exposes the core 71 can be used to increase the use of the wiring board 10, etc.

[0185] (10) According to this embodiment, since the chip 80 has multiple optical elements 60 connected (see reference) Figure 4A as well as Figure 4B Therefore, multiple optical elements 60 can cooperate.

[0186] (11) According to this embodiment, the end E1 of the core 42 is positioned inside the end E2 of the lower cladding 41 (see reference). Figure 13 Therefore, damage to the core 42 at the end E1 of the core 42 can be avoided.

[0187] (12) According to this embodiment, the end E1 of the core 42 is disposed at a position aligned with the end E2 of the lower cladding 41 (see reference). Figure 14 Therefore, it is possible to lengthen the exposed portion of core 42.

[0188] (13) According to this embodiment, the substrate 20 can be configured as a multilayer substrate 20A (see reference 20A). Figure 11 Therefore, it can improve the performance of wiring substrate 10, etc.

[0189] (14) The above-described technology has been proposed as a prior art, but a wiring substrate that can efficiently transmit optical signals or electrical signals in the bonding of optical elements and optical waveguides and the connection between optical elements and substrates is desirable. In this regard, according to this embodiment, a plurality of optical waveguides 40 exposing the core 42 are arranged on the substrate 20. Therefore, in the bonding of optical elements 60 and optical waveguides 40 and the connection between optical elements 60 and substrate 20, the distance between optical elements 60 and cores 42 and between optical elements 60 and conductor layers 26 of substrate 20 becomes closer, and wiring substrates 10 and the like that can efficiently perform optical bonding of optical signals or electrical connection of electrical signals can be obtained. In addition, even if the optical or electrical signals are of high capacity, these signals can be communicated efficiently. Furthermore, by reducing the height of the electrical connection material 50, the wiring substrate 10 and the like are less prone to breakage, thus improving connection reliability.

[0190] [Transformation Method]

[0191] The present invention is not limited to the above-described embodiments and can be implemented in various modifications.

[0192] (1) When the optical waveguide 40 is configured in two directions, it can also be configured in an L-shape, such as left and top, left and bottom, right and top, right and bottom.

[0193] (2) Examples of optical waveguide 40 being configured in two to four directions are given, but it can also be configured in more than five directions.

[0194] (3) The wiring substrate may also not have chip 80 and chip 81.

[0195] [Exemplary Issues of the Invention]

[0196] As a prior art, the technology in Patent Document 1 has been proposed, but a wiring substrate with a new structure is desired.

[0197] Therefore, the exemplary object of the present invention is to provide a wiring substrate having a novel structure.

[0198] Furthermore, this invention is merely illustrative and not limited thereto. Additionally, this invention can be configured to include disclosures of at least one of the specific matters shown in this invention. Moreover, in each specific matter shown in this invention, elements defining the specific matter can be added to form a lower-level concept, or elements defining the specific matter can be deleted to form a higher-level concept.

[0199] [Exemplary Effects of the Invention]

[0200] According to the present invention, it is possible to provide a wiring substrate with a novel structure.

[0201] Label Explanation

[0202] 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 10J, 10K: Wiring substrate; 20: Substrate; 20A: Multilayer substrate; 21: Core substrate; 22: First insulating layer; 23: Second insulating layer; 24: Third insulating layer; 25: Solder resist layer; 26: Conductor layer; 27: Through-hole; 30, 130: Optical element area; 40, 140: Optical waveguide; 41, 141: Lower cladding; 42, 142: Core; 43, 143: Upper cladding; 50, 150: Electrical connection material; 60, 160: Optical element; 61, 161: Terminal; 70: External connection component; 71: Core; 80, 81: Chip; 90: Optical signal; 91: Electrical signal; 92: Back side of optical element; 93: External terminal; 94: Back side of solder mask layer; 95: External terminal; 100: Information processing circuit; 101: Circuit.

Claims

1. A wiring substrate having a substrate having a conductor layer, An optical element region and an optical waveguide are disposed on the substrate. The optical waveguide has a lower cladding, a core, and an upper cladding. in, An electrical connection material is present in the optical element region to electrically connect the conductor layer to the optical element region. The core of the optical waveguide, which is optically coupled to the optical element region, is exposed, and multiple optical waveguides are configured.

2. The wiring substrate according to claim 1, wherein, One or more optical elements are arranged in the optical element region.

3. The wiring substrate according to claim 1, wherein, Multiple optical waveguides are arranged in different directions with the optical element region as the center.

4. The wiring substrate according to claim 1, wherein, The core at one end of the optical waveguide is exposed, while the core at the other end is not exposed.

5. The wiring substrate according to claim 1, wherein, The core is exposed at one end of the optical waveguide and at the other end.

6. The wiring substrate according to claim 1, wherein, The optical waveguide has the optical element region at one end and an external connection component at the other end.

7. The wiring substrate according to claim 1, wherein, The optical waveguide has the optical element region at one end and an optical waveguide that exposes the core at the other end.

8. The wiring substrate according to claim 1, wherein, The optical waveguide has an optical element region at one end and an optical element region different from the optical element region at the other end.

9. The wiring substrate according to claim 1, wherein, The optical waveguide has the optical element region at one end and an external connection component that exposes the core at the other end.

10. The wiring substrate according to claim 1, wherein, Multiple optical elements are arranged in the optical element region. The wiring substrate has a chip that is electrically connected to the optical element.

11. The wiring substrate according to claim 1, wherein, The end of the core is positioned inside the end of the lower cladding.

12. The wiring substrate according to claim 1, wherein, The end of the core is positioned aligned with the end of the lower cladding.

13. The wiring substrate according to claim 1, wherein, The substrate is a multilayer substrate, which has a core substrate and multilayers formed on both sides of the core substrate.

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