Dual-chip linkage reset method and system, and dual-chip management system

Abstract

The application provides a double-chip linkage reset method, a double-chip linkage reset system and a double-chip management system, and the method comprises the following steps: a first chip sends working data to a second chip through a communication link in a working state; if the first chip does not receive feedback from the second chip within a preset time length, the first chip controls a corresponding reset driving circuit to output a first reset signal to a hardware reset pin of the second chip through a reset control pin of the first chip; when the second chip receives a reset instruction from the outside, the second chip controls a corresponding reset driving circuit to output a second reset signal to a hardware reset pin of the first chip through a reset control pin of the second chip. The reset method uses an existing communication link to complete survival detection, saves an additional special detection pin and simplifies PCB design; meanwhile, the reset operation is performed by using a hardware reset pin, so that reliable restart can be realized when a kernel of the chip is dead.

Description

Technical Field

[0001] This invention relates to the field of chip reset technology, and in particular to a dual-chip linkage reset method, system, and dual-chip management system. Background Technology

[0002] With the development of energy storage and new energy battery technologies, the requirements for battery management systems (BMS) to achieve high reliability, low power consumption, and compact design are increasing. In existing embedded BMS solutions, a dual-chip architecture consisting of a main control chip and a wireless communication chip (such as a Bluetooth chip) is typically adopted. The two chips communicate via a serial port (UART) to collect and report battery data and exchange external commands.

[0003] To ensure the BMS can self-recover under harsh electromagnetic environments or when software malfunctions, establishing a "survival detection-fault reset" mechanism between chips is crucial. However, existing dual-chip reset schemes still have the following drawbacks in practical applications: First, traditional solutions typically require additional dedicated status detection pins to achieve mutual status monitoring between chips. This not only increases the complexity and cost of printed circuit board (PCB) layout and routing, but also goes against the trend of BMS boards becoming increasingly compact.

[0004] Secondly, existing reset control often relies on software-level triggering via ordinary I / O pins. When the chip experiences a severe crash or kernel hang, the software-controlled I / O pins often fail to output normal level signals, causing reset attempts to fail. Furthermore, if the reset signal is not applied to the chip's underlying dedicated hardware reset pin (RESET pin), it is difficult to ensure that the chip can be forcibly restarted under various crash conditions.

[0005] In addition, when the main control chip crashes and is inside a sealed enclosure, existing technologies often lack an effective remote hardware reset method. Maintenance personnel usually need to physically disassemble the device to manually power off and reset it, which greatly reduces the convenience of on-site maintenance.

[0006] Therefore, a new dual-chip linkage reset solution is urgently needed. Summary of the Invention

[0007] The purpose of this invention is to provide a chip-linked reset method, system, and dual-chip management system that can both ensure the reliability of hardware reset and take into account the compact design.

[0008] To achieve the above objectives, the present invention provides a dual-chip linked reset method, applied to a first chip and a second chip connected via a communication link, wherein the reset control pins of the first chip and the second chip are respectively connected to the hardware reset pin of the other chip via a reset drive circuit; the method includes: When the first chip is in operation, it sends working data to the second chip via the communication link. If the first chip does not receive feedback from the second chip within a preset time period, the first chip controls the corresponding reset drive circuit through its own reset control pin to output a first reset signal to the hardware reset pin of the second chip. When the second chip receives a reset command from the outside, it controls the corresponding reset drive circuit through its own reset control pin to output a second reset signal to the hardware reset pin of the first chip.

[0009] Preferably, the second chip only responds to the received external reset command to trigger the operation of outputting the second reset signal to the first chip.

[0010] Preferably, when the first chip enters a sleep state, the first chip stops sending the working data to the second chip and stops timing detection for the preset duration; If the second chip outputs the second reset signal to the hardware reset pin of the first chip while the first chip is in the sleep state, the first chip will exit the sleep state and resume the working state based on the second reset signal.

[0011] Preferably, when the first chip enters the sleep state, the receive pin of the first chip in the communication link is configured to have an interrupt wake-up function.

[0012] Preferably, the reset drive circuit includes a switching transistor; the reset control pin of the first chip or the second chip is electrically connected to the control terminal of the switching transistor through a current-limiting resistor; the first conducting terminal of the switching transistor is grounded; the second conducting terminal of the switching transistor is electrically connected to the hardware reset pin of the second chip or the first chip, and the second conducting terminal is also connected to a voltage source through a pull-up resistor.

[0013] Preferably, the first chip is the main control chip of the battery management system, the second chip is the near-field wireless communication chip of the battery management system, and the communication link is a serial communication link.

[0014] Preferably, when the first chip is in operation, it collects battery data according to a preset cycle and sends the battery data as the working data to the second chip; the preset duration is longer than the preset cycle.

[0015] The present invention also provides a dual-chip management system, which includes a first chip and a second chip connected by a communication link. The reset control pins of the first chip and the second chip are respectively connected to the hardware reset pin of the other chip via a reset drive circuit. The first chip and the second chip are reset based on the dual-chip linkage reset method described above.

[0016] The present invention also provides a dual-chip linkage reset system, which includes: One or more processors; Memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for performing the dual-chip linked reset method as described above.

[0017] The present invention also provides a computer-readable storage medium comprising a computer program that can be executed by a processor to perform the dual-chip linkage reset method as described above.

[0018] Compared with existing technologies, the dual-chip linkage reset method provided by the above-mentioned technical solution of the present invention firstly, by reusing the existing communication link between the two chips for data transmission and reception and timeout feedback detection, there is no need to add an additional dedicated status detection pin, which effectively saves hardware resources and reduces PCB layout costs; secondly, the reset control pins of the two chips are directly connected to the underlying hardware reset pin of the other through the reset drive circuit, breaking through the technical bottleneck of ordinary I / O ports failing when the chip is severely frozen, and ensuring extremely high reliability of hardware-level forced reset; finally, the second chip performs a reset on the first chip based on the received external reset command, realizing remote reset maintenance without disassembly in the frozen state. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the electronic system in an embodiment of the present invention.

[0020] Figure 2 This is a flowchart of the reset method in an embodiment of the present invention. Detailed Implementation

[0021] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0022] This embodiment discloses a dual-chip linked reset method, such as... Figure 1 It is mainly used in electronic systems that include a first chip U1 and a second chip U2, such as an embedded battery management system (BMS).

[0023] The electronic system includes a first chip U1 and a second chip U2 connected via a communication link. Both chip U1 and chip U2 have a reset control pin PC, and each reset control pin PC is connected to the hardware reset pin RS (RESET pin) of the other chip via a reset drive circuit DR. The communication link (RX / TX) is used for data exchange and liveness monitoring between the two chips.

[0024] The reset linkage logic in this embodiment adopts an asymmetric monitoring mechanism, such as Figure 2 The specific process is as follows: S11: When the first chip U1 is in normal working condition, it periodically sends working data to the second chip U2 through the communication link.

[0025] S12: After sending working data, the first chip U1 starts its internal timer. After receiving the working data, the second chip U2 sends a feedback signal back to the first chip U1 via the communication link.

[0026] S13: If the first chip U1 does not receive a feedback signal from the second chip U2 within a preset time period, it is determined that the second chip U2 has crashed or experienced a communication abnormality. At this time, the first chip U1 outputs a control signal L1 through its own reset control pin PC to the corresponding reset drive circuit DR1, which then outputs a first reset signal T1 to the hardware reset pin RS of the second chip U2, forcing the second chip U2 to perform a hardware restart.

[0027] S14: During operation, the second chip U2 keeps listening for external commands. When the second chip U2 receives a reset command from the outside, it outputs a control signal L2 through its own reset control pin PC to the corresponding reset drive circuit DR2, and outputs a second reset signal T2 to the hardware reset pin RS of the first chip U1, thereby realizing the forced reset or wake-up of the first chip U1.

[0028] Therefore, this embodiment completes the liveness detection by reusing the existing communication link, eliminating the need for additional dedicated detection pins and simplifying the PCB design; at the same time, it uses the hardware reset pin RS to perform the reset operation, ensuring that a reliable restart can still be achieved when the chip core hangs.

[0029] In another embodiment, the reset drive circuit DR includes a switching transistor Q (such as an NPN transistor or an N-channel MOSFET). The reset control pin PC of the first chip U1 (or the second chip U2) is electrically connected to the control terminal (base or gate) of the switching transistor Q through a first resistor R1 (or a second resistor R2) used as a current-limiting resistor; the first conducting terminal (emitter or source) of the switching transistor Q is grounded; the second conducting terminal (collector or drain) of the switching transistor Q is electrically connected to the hardware reset pin RS of the other chip, and the second conducting terminal is also connected to an external voltage source (such as 3.3V) through a third resistor 3 (or a fourth resistor R4) used as a pull-up resistor.

[0030] For example, the first resistor R1 or the second resistor R2 can be a 1kΩ resistor, and the third resistor R3 or the fourth resistor R4 can be a 10kΩ pull-up resistor. The switching transistor Q is an NPN transistor.

[0031] In the non-reset state, the reset control pin PC outputs a low level, the switching transistor Q is off, and the hardware reset pin RS is maintained at a high level by a pull-up resistor. When a reset needs to be triggered, the chip toggles the level signal of the reset control pin PC (from low to high), driving the switching transistor Q to turn on, thereby forcibly pulling the level of the hardware reset pin RS of the other chip low.

[0032] To ensure that the chip can recognize the reset signal, the duration (i.e., level transition time) of the first or second reset signal is preset to 300ms.

[0033] This embodiment achieves efficient driving of the hardware reset pin RS by the low-power pin through the Q-switching transistor driving circuit, and the 300ms pulse width ensures the effective execution of the hardware reset action.

[0034] In another embodiment, the first chip U1 is a BMS main control chip, the second chip U2 is a near-field wireless communication chip (such as a Bluetooth BLE chip), and the communication link is a serial port (UART) link.

[0035] Based on this, the first chip U1 collects data such as battery voltage, current, and SOC at a preset period (e.g., 100ms) and sends it to the second chip U2 as working data.

[0036] The preset duration is set to 2000ms, which is significantly longer than the 100ms sampling period, in order to avoid accidental resets due to occasional communication jitter.

[0037] In another embodiment, the sleep and wake-up logic of the first chip U1 is as follows: S21: When the first chip U1 detects no load or meets the preset sleep conditions, it enters sleep mode (such as STOP mode). At this time, the first chip U1 stops sending working data to the second chip U2 and simultaneously stops timeout monitoring.

[0038] S22: Before entering sleep mode, the first chip U1 configures its serial port receive pin (RX) for interrupt wake-up function so that the second chip U2 can wake it up when forwarding normal communication commands.

[0039] S23: The second chip U2 is configured to only trigger the output of a second reset signal to the first chip U1 in response to a received external reset command. That is, the second chip U2 will not automatically trigger a reset due to no data transmission on the serial port link, thereby ensuring that the first chip U1 is not accidentally reset during sleep.

[0040] S24: If the first chip U1 hangs abnormally during sleep, the external terminal (such as a mobile APP) sends a "master control reset command" to the second chip U2 through a wireless link. The second chip U2 drives the generation of the second reset signal T2, which forces the first chip U1 to exit the sleep state and resume the working state.

[0041] This solution addresses the power consumption bottleneck of the BMS in sleep mode, avoids accidental resets, and allows the static power consumption of the BMS to be controlled at an extremely low level.

[0042] The following specific example illustrates the working process of the dual-chip linkage reset method.

[0043] For example, in a certain energy storage lithium battery BMS system, the main control chip (first chip U1) and the Bluetooth chip (second chip U2) are connected via UART. The main control chip sends battery SOC data every 100ms, and the Bluetooth chip sends an ACK frame in response after receiving it.

[0044] The exception handling process is as follows: Bluetooth crash scenario: If the Bluetooth chip crashes due to electrostatic interference and cannot reply with an ACK frame, the main control chip, after waiting for 2000ms without receiving feedback, determines that the Bluetooth has crashed and pulls the reset control pin PC high for 300ms. Through a transistor circuit, the Bluetooth chip's hardware reset pin RS is pulled low for 300ms, forcing the Bluetooth chip to restart and restore communication.

[0045] Controller crash / remote maintenance scenario: If the main control chip crashes or cannot be woken up from sleep mode, the user can click the "Remote Reset" button via the mobile app. The app sends a reset command to the Bluetooth chip, which immediately pulls its reset control pin PC high for 300ms upon receiving the command. The main control chip's hardware reset pin RS is then pulled low, completing the hardware-level reset and restarting battery data acquisition and reporting.

[0046] Therefore, this invention achieves highly reliable, low-power, and non-disassembly-required dual-chip linkage reset of the BMS by using a serial port link for liveness detection, combined with a hardware reset pin RS direct connection architecture driven by the switch transistor Q, and asymmetric reset logic for the sleep state. It has strong practical engineering value.

[0047] In another preferred embodiment of the present invention, a dual-chip management system is also disclosed, which includes a first chip and a second chip connected via a communication link. The reset control pins of the first chip and the second chip are respectively connected to the hardware reset pin of the other via a reset drive circuit. The first chip and the second chip are reset based on the dual-chip linkage reset method in the above embodiment.

[0048] This invention also discloses another dual-chip linked reset system, which includes one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors. The programs include instructions for performing the dual-chip linked reset method as described above. The processors can be general-purpose central processing units (CPUs), microprocessors, application-specific integrated circuits (ASICs), or one or more integrated circuits, used to execute relevant programs to implement the functions required by the modules in the dual-chip linked reset system of this application embodiment, or to execute the dual-chip linked reset method of this application method embodiment.

[0049] This invention also discloses a computer-readable storage medium comprising a computer program executable by a processor to perform the dual-chip linked reset method described above. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center integrating one or more available media. The available medium can be read-only memory (ROM), random access memory (RAM), or magnetic media, such as floppy disks, hard disks, magnetic tapes, magnetic disks, or optical media, such as digital versatile discs (DVDs), or semiconductor media, such as solid-state disks (SSDs).

[0050] This application also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. The processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the aforementioned dual-chip linked reset method.

[0051] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A dual-chip linkage reset method, applied to a first chip and a second chip connected via a communication link, characterized in that, The reset control pins of the first chip and the second chip are respectively connected to the hardware reset pin of the other chip via a reset drive circuit; the method includes: When the first chip is in operation, it sends working data to the second chip via the communication link. If the first chip does not receive feedback from the second chip within a preset time period, the first chip controls the corresponding reset drive circuit through its own reset control pin to output a first reset signal to the hardware reset pin of the second chip. When the second chip receives a reset command from the outside, it controls the corresponding reset drive circuit through its own reset control pin to output a second reset signal to the hardware reset pin of the first chip.

2. The dual-chip linkage reset method according to claim 1, characterized in that, The second chip only responds to the received external reset command to trigger the operation of outputting the second reset signal to the first chip.

3. The dual-chip linkage reset method according to claim 1, characterized in that, When the first chip enters a sleep state, the first chip stops sending the working data to the second chip and stops timing detection for the preset duration; If the second chip outputs the second reset signal to the hardware reset pin of the first chip while the first chip is in the sleep state, the first chip will exit the sleep state and resume the working state based on the second reset signal.

4. The dual-chip linkage reset method according to claim 3, characterized in that, When the first chip enters the sleep state, the receive pin of the first chip in the communication link is configured to have interrupt wake-up function.

5. The dual-chip linkage reset method according to claim 1, characterized in that, The reset drive circuit includes a switching transistor; the reset control pin of the first chip or the second chip is electrically connected to the control terminal of the switching transistor through a current-limiting resistor; the first conducting terminal of the switching transistor is grounded; the second conducting terminal of the switching transistor is electrically connected to the hardware reset pin of the second chip or the first chip, and the second conducting terminal is also connected to a voltage source through a pull-up resistor.

6. The dual-chip linkage reset method according to claim 1, characterized in that, The first chip is the main control chip of the battery management system, the second chip is the near-field wireless communication chip of the battery management system, and the communication link is a serial communication link.

7. The dual-chip linkage reset method according to claim 6, characterized in that, When the first chip is in operation, it collects battery data according to a preset cycle and sends the battery data as working data to the second chip; the preset duration is longer than the preset cycle.

8. A dual-chip management system, characterized in that, The device includes a first chip and a second chip connected via a communication link. The reset control pins of the first chip and the second chip are respectively connected to the hardware reset pin of the other chip via a reset drive circuit. The first chip and the second chip are reset based on the dual-chip linkage reset method according to any one of claims 1 to 7.

9. A dual-chip linkage reset system, characterized in that, include: One or more processors; Memory; And one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for performing the dual-chip linked reset method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Includes a computer program, which can be executed by a processor to perform the dual-chip linkage reset method as described in any one of claims 1 to 7.

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