Power converter with transient response boost mechanism

Abstract

A power converter with transient response enhancement is provided. The power converter includes a first upper bridge switch, a first lower bridge switch, a second upper bridge switch, a second lower bridge switch, and a control circuit. When an output voltage at a first terminal of the second upper bridge switch is lower than a lower threshold voltage, the control circuit turns on the first upper bridge switch and the second lower bridge switch and turns off the first lower bridge switch and the second upper bridge switch. Conversely, when the output voltage is higher than an upper threshold voltage, the control circuit turns on the first lower bridge switch and the second upper bridge switch and turns off the first upper bridge switch and the second lower bridge switch.

Description

Technical Field

[0001] This invention relates to power converters, and more particularly to a power converter with a transient response enhancement mechanism. Background Technology

[0002] Power converters are indispensable for electronic devices. They regulate power and supply the adjusted power to the electronic device. In a power converter, the control circuit must appropriately switch multiple switching components to ensure a rapid instantaneous response of the current flowing through the inductor used for energy storage, thereby enabling the power converter to efficiently provide the appropriate amount of power to the load. However, the instantaneous response of the inductor current in traditional power converters is too slow, causing them to either fail to supply sufficient power to the load with high efficiency or supply excessive power, resulting in unnecessary power consumption. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a power converter with an instantaneous response enhancement mechanism. The power converter of this invention includes a switching circuit and a control circuit. The switching circuit includes multiple switching components. These multiple switching components include a first upper-bridge switch, a first lower-bridge switch, a second upper-bridge switch, and a second lower-bridge switch. A first terminal of the first upper-bridge switch is coupled to an input voltage. A first terminal of the first lower-bridge switch is connected to a second terminal of the first upper-bridge switch. A node between the first terminal of the first lower-bridge switch and the second terminal of the first upper-bridge switch is connected to a first terminal of an inductor. A first terminal of the second lower-bridge switch is connected to a second terminal of the second upper-bridge switch. The second terminal of the second lower-bridge switch is grounded. A node between the first terminal of the second lower-bridge switch and the second terminal of the second upper-bridge switch is connected to a second terminal of the inductor. The control circuit is connected to a control terminal of each of the switching components and a first terminal of the second upper-bridge switch. The control circuit is configured to switch the switching circuit based on the voltage received from the first terminal of the second upper-bridge switch, causing the current in the inductor to be increased or decreased in advance before a predetermined time point.

[0004] As described above, this invention provides a power converter with an instantaneous response enhancement mechanism. Compared to conventional power converters, the multiple upper-bridge switches and multiple lower-bridge switches of this invention can improve the instantaneous response of the inductor current, enabling the inductor current to rise and fall earlier. Therefore, compared to conventional power converters, this invention's power converter can supply the appropriate amount of power to the load with better power efficiency.

[0005] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0006] Figure 1 This is a circuit diagram of a power converter with an instantaneous response boosting mechanism according to the first embodiment of the present invention.

[0007] Figure 2 This is a circuit diagram of a power converter with an instantaneous response boosting mechanism according to a second embodiment of the present invention.

[0008] Figure 3 This is a block diagram of the control circuit of a power converter with an instantaneous response boosting mechanism according to a third embodiment of the present invention.

[0009] Figure 4 This is a circuit diagram of the control circuit of a power converter with an instantaneous response boosting mechanism according to the fourth embodiment of the present invention.

[0010] Figure 5 The waveform diagrams are of the power converters with instantaneous response boosting mechanisms according to the first to fourth embodiments of the present invention.

[0011] Figure 6 The waveform diagrams are of the power converters with instantaneous response boosting mechanisms according to the first to fourth embodiments of the present invention.

[0012] Figure 7 The waveform diagrams are of the power converter with instantaneous response enhancement mechanism in the first to fourth embodiments of the present invention and the conventional power converter. Detailed Implementation

[0013] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" as used herein may, depending on the actual situation, include any or more combinations of the associated listed items.

[0014] Please see Figure 1 and Figure 7 ,in Figure 1This is a circuit diagram of a power converter with an instantaneous response boosting mechanism according to the first embodiment of the present invention. Figure 7 The waveform diagrams are of the power converter with instantaneous response enhancement mechanism in the first to fourth embodiments of the present invention and the conventional power converter.

[0015] For example, the power converter of the present invention may be a buck-boost converter having multiple operating modes, particularly including a pass-through mode. The operations performed by the power converter of the present invention described below are all performed when operating in pass-through mode.

[0016] like Figure 1 As shown, in a first embodiment, the power converter of the present invention includes a switching circuit SW and a control circuit CTR. The switching circuit SW includes a plurality of switching components, which may include a plurality of upper bridge switches, such as a first upper bridge switch HS1 and a second upper bridge switch HS2, and a plurality of lower bridge switches, such as a first lower bridge switch LS1 and a second lower bridge switch LS2.

[0017] The first upper bridge switch HS1, the first lower bridge switch LS1, the second upper bridge switch HS2, and the second lower bridge switch LS2 can be transistors of any type.

[0018] The first terminal of the first upper bridge switch HS1 is coupled to an input voltage VIN. The first terminal of the first lower bridge switch LS1 is connected to the second terminal of the first upper bridge switch HS1. The node between the first terminal of the first lower bridge switch LS1 and the second terminal of the first upper bridge switch HS1 is connected to the first terminal of the inductor L.

[0019] The first terminal of the second lower bridge switch LS2 is connected to the second terminal of the second upper bridge switch HS2. The second terminal of the second lower bridge switch LS2 is grounded. The node between the first terminal of the second lower bridge switch LS2 and the second terminal of the second upper bridge switch HS2 is connected to the second terminal of the inductor L.

[0020] The first terminal of the second upper bridge switch HS2 serves as the output terminal of the power converter of the present invention. The voltage at the first terminal of the second upper bridge switch HS2 serves as the output voltage VOUT of the power converter of the present invention.

[0021] The control circuit CTR is connected to the control terminal of the first upper bridge switch HS1, the control terminal of the first lower bridge switch LS1, the control terminal of the second upper bridge switch HS2, and the first terminal, as well as the control terminal of the second lower bridge switch LS2.

[0022] The control circuit CTR outputs multiple control signals SHS1, SLS1, SHS2, and SLS2 to the control terminals of the first upper bridge switch HS1, the first lower bridge switch LS1, the second upper bridge switch HS2, and the second lower bridge switch LS2, respectively, to control the first upper bridge switch HS1, the first lower bridge switch LS1, the second upper bridge switch HS2, and the second lower bridge switch LS2.

[0023] It is worth noting that the control circuit CTR is connected to the first terminal of the second upper bridge switch HS2. The control circuit CTR switches the switch circuit SW (including the first upper bridge switch HS1, the first lower bridge switch LS1, the second upper bridge switch HS2 and the second lower bridge switch LS2) according to the output voltage VOUT received from the first terminal of the second upper bridge switch HS2, so as to increase or decrease the current of the inductor L in advance before a predetermined time point.

[0024] The control circuit CTR can connect the output voltage VOUT to, for example... Figure 5 The lower threshold voltage Vth1 is compared with an upper threshold voltage Vth2. The upper threshold voltage Vth2 is greater than the lower threshold voltage Vth1. The lower threshold voltage Vth1 can be lower than the input voltage VIN, while the upper threshold voltage Vth2 can be higher than the input voltage VIN.

[0025] For example, when the control circuit CTR determines that the output voltage VOUT at the first terminal of the second upper bridge switch HS2 is lower than a lower threshold voltage Vth1 and lower than an upper threshold voltage Vth2, the control circuit CTR opens the first upper bridge switch HS1 and the second lower bridge switch LS2 and closes the first lower bridge switch LS1 and the second upper bridge switch HS2. At this time, as... Figure 7 The control terminal of the second lower bridge switch LS2 shown receives a high-level control signal SLS2, which causes the second lower bridge switch LS2 to open.

[0026] The result is, such as Figure 7 The area circled by the dashed line A1 shows that, compared to the inductor current IL0 of a conventional power converter, the inductor current IL of the power converter of this invention rises earlier. Therefore, compared to the inductor current IL0 of a conventional power converter, the inductor current IL of the power converter of this invention has a faster instantaneous rise response.

[0027] like Figure 7As shown, compared to the output voltage VOUT0 of a conventional power converter, the output voltage VOUT of the power converter of this invention can rise more quickly. Therefore, when the load connected to the output terminal of the power converter of this invention transitions from a light load to a medium or heavy load and draws more power, it can prevent the output voltage VOUT of the power converter of this invention from dropping to an excessively low value, as is the case with the output voltage VOUT0 of a conventional power converter. Thus, compared to a conventional power converter, the power converter of this invention can provide sufficient power to the load more efficiently.

[0028] When the control circuit CTR determines that the output voltage VOUT of the first terminal of the second upper bridge switch HS2 is higher than the lower limit threshold voltage Vth1 but lower than the upper limit threshold voltage Vth2, the control circuit CTR turns on the first upper bridge switch HS1 and the second upper bridge switch HS2 and turns off the first lower bridge switch LS1 and the second lower bridge switch LS2.

[0029] For example, when the output voltage VOUT at the first terminal of the second upper bridge switch HS2 is higher than a lower threshold voltage Vth1 and higher than an upper threshold voltage Vth2, the control circuit CTR turns on the first lower bridge switch LS1 and the second upper bridge switch HS2 and turns off the first upper bridge switch HS1 and the second lower bridge switch LS2. At this time, as... Figure 7 The control terminal of the first lower bridge switch LS1 shown receives a high-level control signal SLS1, which causes the first lower bridge switch LS1 to open.

[0030] The result is, such as Figure 7 The area circled by the dashed line A2 shows that, compared to the inductor current IL0 of a conventional power converter, the inductor current IL of the power converter of this invention drops earlier. Therefore, compared to the inductor current IL0 of a conventional power converter, the inductor current IL of the power converter of this invention has a faster instantaneous response.

[0031] like Figure 7 As shown, compared to the output voltage VOUT0 of a conventional power converter, the output voltage VOUT of the power converter of this invention can drop more quickly. Therefore, when the load connected to the output terminal of the power converter of this invention transitions from a medium or heavy load to a light load drawing less power, the output voltage VOUT of the power converter of this invention can be prevented from overvoltage as in a conventional power converter. Thus, compared to conventional power converters, the power converter of this invention and its connected load can avoid burnout due to overvoltage or overcurrent.

[0032] Please see Figure 2 This is a circuit diagram of a power converter with an instantaneous response enhancement mechanism according to the second embodiment of the present invention.

[0033] The second embodiment of the present invention is the same as the first embodiment, and will not be repeated here.

[0034] like Figure 2 As shown, in the second embodiment, the power converter of the present invention, in addition to including a first upper bridge switch HS1, a first lower bridge switch LS1, a second upper bridge switch HS2, a second lower bridge switch LS2 and a control circuit CTR, may also include an output capacitor Cout, a current limiting circuit LMT or two of them.

[0035] The current-limiting circuit LMT may include one or more current-limiting components, such as, but not limited to, transistor Mout. The first terminal of transistor Mout is connected to the first terminal of the second upper-bridge switch HS2. The second terminal of transistor Mout is connected to the first terminal of the output capacitor Cout. The second terminal of the output capacitor Cout is grounded.

[0036] If necessary, the power converter of this invention may also include one or more buffers, such as a first upper bridge buffer BFH1, a first lower bridge buffer BFL1, a second upper bridge buffer BFH2, a second lower bridge buffer BFL2, a current limiting buffer BFout, or any combination thereof.

[0037] The input terminal of the first upper bridge buffer BFH1 is connected to the first output terminal of the control circuit CTR. The output terminal of the first upper bridge buffer BFH1 is connected to the control terminal of the first upper bridge switch HS1. The first upper bridge buffer BFH1 can buffer the control signal SHS1 output from the control circuit CTR to the control terminal of the first upper bridge switch HS1.

[0038] The input of the first lower bridge buffer BFL1 is connected to the second output of the control circuit CTR. The output of the first lower bridge buffer BFL1 is connected to the control terminal of the first lower bridge switch LS1. The first lower bridge buffer BFL1 can buffer the control signal SLS1 output from the control circuit CTR to the control terminal of the first lower bridge switch LS1.

[0039] The input terminal of the second upper bridge buffer BFH2 is connected to the third output terminal of the control circuit CTR. The output terminal of the second upper bridge buffer BFH2 is connected to the control terminal of the second upper bridge switch HS2. The second upper bridge buffer BFH2 can buffer the control signal SHS2 output from the control circuit CTR to the control terminal of the second upper bridge switch HS2.

[0040] The input of the second lower bridge buffer BFL2 is connected to the fourth output of the control circuit CTR. The output of the second lower bridge buffer BFL2 is connected to the control terminal of the second lower bridge switch LS2. The second lower bridge buffer BFL2 can buffer the control signal SHS2 output from the control circuit CTR to the control terminal of the second lower bridge switch LS2.

[0041] The input of the current-limiting buffer BFout is connected to the fifth output of the control circuit CTR. The output of the second lower-bridge buffer BFL2 is connected to the output of the transistor Mou. The second lower-bridge buffer BFL2 is configured to buffer the control signal SLM output from the control circuit CTR to the control terminal of the transistor Mou.

[0042] The first terminal of the output capacitor Cout can be used as the output terminal of the power converter.

[0043] A current limiting circuit LMT is connected between the first terminal of the second upper bridge switch HS2 and the first terminal of the output capacitor Cout. The current limiting circuit LMT limits the amount of current flowing from the first terminal of the second upper bridge switch to the output terminal of the power converter, preventing the load from being burned out due to instantaneous excessive output current received by the power converter of the present invention.

[0044] Please see Figure 3 This is a block diagram of the control circuit of a power converter with an instantaneous response boosting mechanism according to the third embodiment of the present invention.

[0045] like Figure 1 or Figure 2 The control circuit CTR shown can be replaced with, for example: Figure 3 The control circuit CTR shown is illustrated. Figure 3 As shown, the control circuit CTR includes a comparator circuit CM and a switch switching circuit SWG.

[0046] The comparator circuit CM includes a lower limit comparator circuit CM1 and an upper limit comparator circuit CM2.

[0047] The lower limit comparator circuit CM1 and the upper limit comparator circuit CM2 can be connected to the first terminal of the second upper bridge switch HS2, the first terminal of the output capacitor Cout, or the second terminal of the transistor Mout, so as to obtain the output voltage VOUT of the power converter of the present invention from the first terminal of the second upper bridge switch HS2, the first terminal of the output capacitor Cout, or the second terminal of the transistor Mout.

[0048] The lower limit comparator circuit CM1 compares the output voltage VOUT with a lower limit threshold voltage Vth1 to set the level of the lower limit comparator signal and outputs this lower limit comparator signal. The upper limit comparator circuit CM2 compares the output voltage VOUT with an upper limit threshold voltage Vth2 to set the level of the lower limit comparator signal and outputs this upper limit comparator signal.

[0049] For example, the switch switching circuit SWG may include a pulse signal generation circuit PUG and a switch control circuit TL, wherein the pulse signal generation circuit PUG may include a lower limit pulse generation circuit PG1 and an upper limit pulse generation circuit PG2.

[0050] The input of the lower limit pulse generation circuit PG1 is connected to the output of the lower limit comparator circuit CM1. The lower limit pulse generation circuit PG1 outputs a lower limit control pulse signal based on the lower limit comparison signal received from the lower limit comparator circuit CM1.

[0051] The input of the upper limit pulse generation circuit PG2 is connected to the output of the upper limit comparator circuit CM2. The upper limit pulse generation circuit PG2 outputs an upper limit control pulse signal based on an upper limit comparison signal received from the upper limit comparator circuit CM2.

[0052] The switch switching circuit SWG is connected to the output terminal of the lower limit comparison circuit CM1, the output terminal of the upper limit comparison circuit CM2, the control terminal of the first upper bridge switch HS1, the control terminal of the first lower bridge switch LS1, the control terminal of the second upper bridge switch HS2, and the control terminal of the second lower bridge switch LS2.

[0053] like Figure 3 The switch switching circuit SWG shown outputs multiple control signals SHS1, SLS1, SHS2, and SLS2 to the following devices based on the lower limit comparison signal and the upper limit comparison signal: Figure 1 or Figure 2 The control terminals of the first upper bridge switch HS1, the first lower bridge switch LS1, the second upper bridge switch HS2, and the second lower bridge switch LS2 are shown.

[0054] Please see Figures 4 to 6 ,in Figure 4 This is a circuit diagram of the control circuit of a power converter with an instantaneous response boosting mechanism according to the fourth embodiment of the present invention. Figure 5 and Figure 6 The waveform diagrams are of the power converters with instantaneous response boosting mechanisms according to the first to fourth embodiments of the present invention.

[0055] like Figure 1 or Figure 2 The control circuit CTR shown can be replaced with, for example: Figure 4 The control circuit CTR is shown. The fourth embodiment of the present invention is the same as the third embodiment, and will not be described again herein.

[0056] The differences between the fourth embodiment and the third embodiment of the present invention are described in detail below.

[0057] The lower limit comparator circuit CM1 includes a comparator, which serves as the lower limit comparator CMP1. For example... Figure 4 As shown, the first input terminal of the lower limit comparator CMP1, for example, the non-inverting input terminal, is coupled to the lower limit threshold voltage Vth1. Figure 4 The second input terminal of the lower limit comparator CMP1 shown is, for example, connected as follows: Figure 1 or Figure 2 The first terminal of the second upper bridge switch HS2 shown is as follows: Figure 1 or Figure 2 The first terminal of the output capacitor Cout shown is or as... Figure 2 The second terminal of the transistor Mout shown.

[0058] The lower limit comparator CMP1 compares the output voltage VOUT obtained from the first terminal of the second upper bridge switch HS2, the first terminal of the output capacitor Cout, or the second terminal of the transistor Mout with the lower limit threshold voltage Vth1 to output a lower limit comparison signal.

[0059] The lower limit pulse generation circuit PG1 includes a lower limit logic circuit LG1, a first lower limit pulse circuit P11, and a second lower limit pulse circuit P12. The lower limit logic circuit LG1 may include one or more logic gates, for example... Figure 4 The diagram shows a first logic gate GA1 (e.g., a NAND gate) and a second logic gate GN1 (e.g., a NOT gate), or it may actually contain only one logic gate (e.g., an AND gate).

[0060] like Figure 4 As shown, the first input of the first logic gate GA1 (e.g., a NAND gate) included in the lower limit logic circuit LG1 is connected to the output of the lower limit comparator CMP1. The second input of the first logic gate GA1 is connected to the output of the second lower limit pulse circuit P12. One input of the second logic gate GN1 (e.g., a NOT gate) is connected to the output of the first logic gate GA1 (e.g., a NAND gate). The output of the second logic gate GN1 (e.g., a NOT gate) is connected to the input of the first lower limit pulse circuit P11.

[0061] The output of the first lower limit pulse circuit P11 is connected to the input of the second lower limit pulse circuit P12 and the first input of the switch control circuit TL.

[0062] The first logic gate GA1 (e.g., a NAND gate) of the lower limit logic circuit LG1 outputs an initial lower limit logic signal based on the level of the lower limit comparison signal received from the output of the lower limit comparator CMP1 and the level of the lower limit control pulse signal received from the output of the second lower limit pulse circuit P12. The second logic gate GN1 (e.g., a NOT gate) included in the lower limit logic circuit LG1 outputs a lower limit logic signal based on the initial lower limit logic signal received from the first logic gate GA1.

[0063] The first lower limit pulse circuit P11 determines whether to generate a pulse in the lower limit control pulse signal based on the level of the lower limit logic signal received from the second logic gate GN1 of the lower limit logic circuit LG1, and outputs this lower limit control pulse signal to the switch control circuit TL.

[0064] like Figure 4The switch control circuit TL shown above uses a lower limit control pulse signal received from the first lower limit pulse circuit P11 to set the output to... Figure 1 or Figure 2 The voltage levels of multiple control signals SHS1, SLS1, SHS2, and SLS2 at the control terminals of the first upper bridge switch HS1, the first lower bridge switch LS1, the second upper bridge switch HS2, and the second lower bridge switch LS2 are shown.

[0065] If necessary, the control circuit CTR may also include a first NOT gate G1 and a second NOT gate G2. For example... Figure 4 As shown, in the control circuit CTR, one input terminal of the first NOT gate G1 is connected to the first output terminal of the switch control circuit TL. Another input terminal of the first NOT gate G1 is connected to the second output terminal of the switch control circuit TL.

[0066] like Figure 1 or Figure 2 The control terminal of the second lower bridge switch LS2 shown can be connected to, for example... Figure 4 The first output terminal of the switch control circuit TL included in the control circuit CTR shown.

[0067] like Figure 1 or Figure 2 The control terminal of the second upper bridge switch HS2 shown can be connected to, for example... Figure 4 The output of the first NOT gate G1 included in the control circuit CTR shown.

[0068] like Figure 1 or Figure 2 The control terminal of the first upper bridge switch HS1 shown can be connected to, for example... Figure 4 The control circuit CTR shown is included in the second output terminal of the switch control circuit TL.

[0069] like Figure 1 or Figure 2 The control terminal of the first lower bridge switch LS1 shown can be connected to, as follows: Figure 4 The output of the second NOT gate G2 included in the control circuit CTR shown.

[0070] like Figure 5 As shown, when the output voltage VOUT of the power converter of the present invention is not lower than the lower limit threshold voltage Vth1, the lower limit comparator CMP1 outputs a lower limit comparison signal SCM1 at a first level, such as a low level. As a result, the first lower limit pulse circuit P11 outputs a lower limit control pulse signal SP11 at a first level, such as a low level.

[0071] It is worth noting that when the output voltage VOUT of the power converter of the present invention is lower than the lower limit threshold voltage Vth1, the lower limit comparator CMP1 outputs a lower limit comparison signal SCM1 at a second level, such as a high level. As a result, the first lower limit pulse circuit P11 outputs a lower limit control pulse signal SP11 with a pulse or a high level.

[0072] The second lower limit pulse circuit P12 is as follows: Figure 5 As shown, based on a lower limit control pulse signal SP11 with a pulse or high level received from the first lower limit pulse circuit P11, a lower limit masking pulse signal SP12 with a first level, such as a low level, is output, or the output lower limit masking pulse signal SP12 is switched from a second level, such as a high level, to a first level, such as a low level. The falling edge SP12 of this lower limit masking pulse signal can be aligned with the falling edge of a pulse of the first lower limit pulse circuit P11.

[0073] The second lower limit pulse circuit P12 sets a lower limit to block the pulse signal, maintaining it at the second level, for example, the lower level time is equal to a default blocking time. Figure 4 The second input of the first logic gate GA1, such as the NAND gate, remains at a low logic level during this default blocking time, so that the lower limit control pulse signal SP11 output by the first lower limit pulse circuit P11 during this default blocking time will not generate a pulse or will remain at a low level.

[0074] Therefore, after the switching control circuit TL switches the switching circuit SW based on the appearance of a pulse or a high-level lower limit control pulse signal SP11, the switching control circuit TL temporarily stops switching the switching circuit SW based on the lower limit control pulse signal SP11 received from the first lower limit pulse circuit P11 for a default blocking time. This ensures the stable operation of the power converter of the present invention.

[0075] It is worth noting that, such as Figure 5 As shown, when the output voltage VOUT of the power converter of the present invention is lower than the lower limit critical voltage Vth1, as... Figure 1 The control terminal of the second lower bridge switch LS2 shown is from, for example Figure 4 The first output terminal of the switch control circuit TL shown receives, as follows: Figure 5 The second level shown is, for example, a control signal SLS2 for the high level. Simultaneously, the control terminal of the second upper bridge switch HS2 receives a signal from the output of the first NOT gate G1, such as... Figure 5 The first level shown is, for example, a low-level control signal SHS2. Simultaneously, the first upper bridge switch HS1 receives a signal from the second output of the switch control circuit TL, such as... Figure 5The second level shown is, for example, a control signal SHS1 for the high level. Simultaneously, the control terminal of the first lower bridge switch LS1 receives a signal from the output of the second NOT gate G2, such as... Figure 5 The first level shown is, for example, a control signal SLS1 at a low level.

[0076] Therefore, when the output voltage VOUT of the power converter of the present invention is lower than the lower limit critical voltage Vth1, the second lower bridge switch LS2 and the first upper bridge switch HS1 are turned on, while the first lower bridge switch LS1 and the second upper bridge switch HS2 are turned off.

[0077] On the other hand, such as Figure 4 As shown, the upper limit comparator circuit CM2 includes a comparator, which serves as an upper limit comparator CMP2. Figure 4 The first input terminal of the upper limit comparator CMP2 shown is, for example, the non-inverting input terminal connected as follows: Figure 1 or Figure 2 The first terminal of the second upper bridge switch HS2 shown is as follows: Figure 1 or Figure 2 The first terminal of the output capacitor Cout shown is or as... Figure 2 The second terminal of the transistor Mout shown. Figure 4 As shown, the second input terminal of the upper limit comparator CMP2, for example the inverting input terminal, is coupled to an upper limit threshold voltage Vth2.

[0078] The upper limit comparison circuit CM2 compares the output voltage VOUT obtained from the first terminal of the second upper bridge switch HS2, the first terminal of the output capacitor Cout, or the second terminal of the transistor Mout with an upper limit threshold voltage Vth2 to output an upper limit comparison signal.

[0079] The upper limit pulse generation circuit PG2 includes an upper limit logic circuit LG2, a first upper limit pulse circuit P21, and a second upper limit pulse circuit P22. The upper limit logic circuit LG2 may include one or more logic gates, for example... Figure 4 The diagram shows a first logic gate GA2 (e.g., a NAND gate) and a second logic gate GN2 (e.g., a NOT gate), or it may actually contain only one logic gate (e.g., an AND gate).

[0080] like Figure 4 As shown, the first input of the first logic gate GA2 (e.g., a NAND gate) in the upper limit logic circuit LG2 is connected to the output of the upper limit comparator CMP2. The second input of the first logic gate GA2 is connected to the output of the second upper limit pulse circuit P22. One input of the second logic gate GN2 (e.g., a NOT gate) is connected to the output of the first logic gate GA2 (e.g., a NAND gate). The output of the second logic gate GN2 (e.g., a NOT gate) is connected to the input of the first upper limit pulse circuit P21.

[0081] The output of the first upper limit pulse circuit P21 is connected to the input of the second upper limit pulse circuit P22 and the first input of the switch control circuit TL.

[0082] The first logic gate GA2 (e.g., a NAND gate) of the upper limit logic circuit LG2 outputs an initial upper limit logic signal based on the level of an upper limit comparison signal received from the output of the upper limit comparator CMP2 and the level of an upper limit control pulse signal received from the output of the second upper limit pulse circuit P22. The second logic gate GN2 (e.g., a NOT gate) included in the upper limit logic circuit LG2 outputs an upper limit logic signal based on the initial upper limit logic signal received from the first logic gate GA2.

[0083] The first upper limit pulse circuit P21 determines whether to generate a pulse from an upper limit control pulse signal based on the level of an upper limit logic signal received from the second logic gate GN2 of the upper limit logic circuit LG2, and outputs this upper limit control pulse signal to the switch control circuit TL.

[0084] like Figure 4 The switch control circuit TL shown above sets the output to the upper limit control pulse signal received from the first upper limit pulse circuit P21, based on an upper limit control pulse signal received from the first upper limit pulse circuit P21. Figure 1 or Figure 2 The voltage levels of multiple control signals SHS1, SLS1, SHS2, and SLS2 at the control terminals of the first upper bridge switch HS1, the first lower bridge switch LS1, the second upper bridge switch HS2, and the second lower bridge switch LS2 are shown.

[0085] like Figure 6 As shown, when the output voltage VOUT of the power converter of the present invention is not higher than an upper limit threshold voltage Vth2, the upper limit comparator CMP2 outputs an upper limit comparison signal SCM2 at a first level, such as a low level. As a result, the first upper limit pulse circuit P21 outputs an upper limit control pulse signal SP21 at a first level, such as a low level.

[0086] It is worth noting that when the output voltage VOUT of the power converter of the present invention is higher than an upper limit threshold voltage Vth2, the upper limit comparator CMP2 outputs an upper limit comparison signal SCM2 at a second level, such as a high level. As a result, the first upper limit pulse circuit P21 outputs an upper limit control pulse signal SP21 with a pulse or a high level.

[0087] The second upper limit pulse circuit P22 is as follows: Figure 5As shown, based on an upper limit control pulse signal SP21 with a pulse or high level received from the first upper limit pulse circuit P21, an upper limit masking pulse signal SP22 with a first level, for example, a low level, is output, or the output upper limit masking pulse signal SP22 is switched from a second level, for example, a high level, to a first level, for example, a low level. The falling edge of this upper limit masking pulse signal SP22 can be aligned with the falling edge of a pulse of the first upper limit pulse circuit P21.

[0088] The second upper limit pulse circuit P22 sets an upper limit to block the pulse signal, maintaining it at the second level, for example, the low level time is equal to a default blocking time. Figure 4 The second input of the first logic gate GA2, such as the NAND gate, remains at a low level during this default blocking time, so that the upper limit control pulse signal SP21 output by the first upper limit pulse circuit P21 during this default blocking time will not generate a pulse or will remain at a low level.

[0089] Therefore, after the switching control circuit TL switches the switching circuit SW based on the appearance of a pulse or a high-level upper limit control pulse signal SP21, the switching control circuit TL stops switching the switching circuit SW based on the upper limit control pulse signal SP21 received from the first upper limit pulse circuit P21 within a default blocking time. This ensures the stable operation of the power converter of the present invention.

[0090] It is worth noting that when the output voltage VOUT of the power converter of the present invention is higher than an upper limit threshold voltage Vth2, the control terminal of the first lower bridge switch LS1 receives a signal from the output terminal of the second NOT gate G2 as follows: Figure 5 The second level shown is, for example, a control signal SLS1 for the high level. Simultaneously, the first upper bridge switch HS1 receives a signal from the second output terminal of the switch control circuit TL, such as... Figure 5 The first level shown is, for example, a low-level control signal SHS1. Simultaneously, the control terminal of the second upper bridge switch HS2 receives a signal from the output of the first NOT gate G1, such as... Figure 5 The second level shown is, for example, a control signal SHS2 for the high level. Simultaneously, the control terminal of the second lower bridge switch LS2 is from, for example... Figure 4 The first output terminal of the switch control circuit TL shown receives, as follows: Figure 5 The first level shown is, for example, a control signal SLS2 at a low level.

[0091] Therefore, when the output voltage VOUT of the power converter of the present invention is higher than an upper limit threshold voltage Vth2, the first lower bridge switch LS1 and the second upper bridge switch HS2 are turned on, while the first upper bridge switch HS1 and the second lower bridge switch LS2 are turned off.

[0092] In summary, this invention provides a power converter with an instantaneous response enhancement mechanism. Compared to conventional power converters, the multiple upper-bridge switches and multiple lower-bridge switches of this invention can improve the instantaneous response of the inductor current, allowing the inductor current to rise and fall earlier. Therefore, compared to conventional power converters, this invention's power converter can supply the appropriate amount of power to the load with better power efficiency.

[0093] The above-disclosed content is only a preferred and feasible embodiment of the present invention and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included in the claims of the present invention.

Claims

1. A power converter with an instantaneous response enhancement mechanism, characterized in that, The power converter with instantaneous response boost mechanism includes: A switching circuit includes multiple switching components, wherein the multiple switching components include: The first bridge switch, the first terminal of the first bridge switch is coupled to the input voltage; A first lower bridge switch, the first end of the first lower bridge switch is connected to the second end of the first upper bridge switch, and the node between the first end of the first lower bridge switch and the second end of the first upper bridge switch is connected to the first end of an inductor. Second bridge switch; and The second lower bridge switch has its first end connected to the second end of the second upper bridge switch. The second end of the second lower bridge switch is grounded. The node between the first end of the second lower bridge switch and the second end of the second upper bridge switch is connected to the second end of the inductor. as well as A control circuit is connected to the control terminal of each of the switching components and the first terminal of the second upper bridge switch. The control circuit is configured to switch the switching circuit according to the voltage received from the first terminal of the second upper bridge switch, so as to increase or decrease the current of the inductor in advance before a predetermined time point.

2. The power converter with instantaneous response enhancement mechanism according to claim 1, characterized in that, When the output voltage at the first terminal of the second upper bridge switch is lower than the lower limit critical voltage, the control circuit increases the current of the inductor.

3. The power converter with instantaneous response enhancement mechanism according to claim 1, characterized in that, When the output voltage at the first terminal of the second upper bridge switch is higher than an upper limit threshold voltage, the control circuit pulls down the current of the inductor.

4. The power converter with instantaneous response enhancement mechanism according to claim 1, characterized in that, When the output voltage of the first terminal of the second upper bridge switch is lower than a lower threshold voltage and lower than an upper threshold voltage, the control circuit turns on the first upper bridge switch and the second lower bridge switch and turns off the first lower bridge switch and the second upper bridge switch.

5. The power converter with instantaneous response enhancement mechanism according to claim 1, characterized in that, When the output voltage of the first terminal of the second upper bridge switch is higher than a lower threshold voltage but lower than an upper threshold voltage, the control circuit turns on the first upper bridge switch and the second upper bridge switch and turns off the first lower bridge switch and the second lower bridge switch.

6. The power converter with instantaneous response enhancement mechanism according to claim 1, characterized in that, When the output voltage of the first terminal of the second upper bridge switch is higher than a lower threshold voltage and higher than an upper threshold voltage, the control circuit turns on the first lower bridge switch and the second upper bridge switch and turns off the first upper bridge switch and the second lower bridge switch.

7. The power converter with instantaneous response enhancement mechanism according to claim 1, characterized in that, The control circuit includes: A lower limit comparison circuit is connected to the first terminal of the second upper bridge switch. The lower limit comparison circuit is configured to compare an output voltage of the first terminal of the second upper bridge switch with a lower limit threshold voltage to output a lower limit comparison signal. An upper limit comparison circuit is connected to the first terminal of the second upper bridge switch. The upper limit comparison circuit is configured to compare the output voltage with an upper limit threshold voltage to output an upper limit comparison signal. as well as A switch switching circuit is connected to the lower limit comparison circuit, the upper limit comparison circuit, and the control terminal of each of the switch components. The switch switching circuit is configured to switch the switch circuit according to the upper limit comparison signal and the lower limit comparison signal.

8. The power converter with instantaneous response enhancement mechanism according to claim 7, characterized in that, The switching circuit includes: A lower limit pulse generation circuit is connected to the lower limit comparison circuit, and the lower limit pulse generation circuit is configured to output a lower limit control pulse signal based on the lower limit comparison signal. An upper limit pulse generation circuit is connected to the upper limit comparison circuit, and the upper limit pulse generation circuit is configured to output an upper limit control pulse signal based on the upper limit comparison signal. as well as A switch control circuit is connected to the upper limit pulse generation circuit and the lower limit pulse generation circuit. The switch control circuit is configured to control the switch circuit according to the upper limit control pulse signal and the lower limit control pulse signal.

9. The power converter with instantaneous response enhancement mechanism according to claim 8, characterized in that, The lower limit pulse generation circuit includes: A lower limit logic circuit is connected to the lower limit comparison circuit. The lower limit logic circuit is configured to output a lower limit logic signal based on the level of the lower limit comparison signal and the level of the lower limit masking pulse signal. A first lower limit pulse circuit is connected to the lower limit logic circuit. The first lower limit pulse circuit is configured to determine whether to generate a pulse in the lower limit control pulse signal based on the level of the lower limit logic signal. as well as The second lower limit pulse circuit is connected to the first lower limit pulse circuit and the lower limit logic circuit. The second lower limit pulse circuit is configured to determine whether the pulse appears in the lower limit control pulse signal in order to set the level of the lower limit control pulse signal and output the lower limit masking pulse signal.

10. The power converter with instantaneous response enhancement mechanism according to claim 8, characterized in that, The upper limit pulse generation circuit includes: An upper limit logic circuit is connected to the upper limit comparison circuit, the upper limit logic circuit being configured to output an upper limit logic signal based on the level of the upper limit comparison signal and the level of an upper limit masking pulse signal. A first upper limit pulse circuit is connected to the upper limit logic circuit. The first upper limit pulse circuit is configured to determine whether to generate a pulse in an upper limit control pulse signal based on the level of the upper limit logic signal. as well as The second upper limit pulse circuit is connected to the first upper limit pulse circuit and the upper limit logic circuit. The second upper limit pulse circuit is configured to determine whether a pulse appears in the upper limit control pulse signal to set the level of the upper limit masking pulse signal and output the upper limit masking pulse signal.

11. The power converter with instantaneous response enhancement mechanism according to claim 1, characterized in that, The power converter with instantaneous response boost mechanism also includes: An output capacitor, the first end of which is connected to the second end of the inductor, and the second end of the output capacitor is grounded.

12. The power converter with instantaneous response enhancement mechanism according to claim 1, characterized in that, The power converter with instantaneous response boost mechanism also includes: A current limiting circuit is connected between the first terminal of the second upper bridge switch and the output terminal of the power converter. The current limiting circuit is configured to limit the current flowing from the first terminal of the second upper bridge switch to the output terminal of the power converter.

13. The power converter with instantaneous response enhancement mechanism according to claim 12, characterized in that, The current limiting circuit includes a transistor, the first end of which is connected to the first end of the second upper bridge switch, the second end of which is connected to the input end of the control circuit, and the control end of which is connected to the output end of the control circuit.

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