A decoding method and system of a polar code SR1 / SPC node

Abstract

The application discloses a decoding method and system of a polar code SR1 / SPC node. The application realizes efficiency improvement and architecture optimization by constructing a unified matrix constraint and a non-recursive flipping set construction algorithm, eliminates recursive branch judgment and pre-storage overhead, and enhances hardware parallelism and throughput performance. A lossless simplification strategy is proposed for the SR1 / SPC node, which reduces the flipping pair search space from the physical length to the condensed vector length, and greatly reduces the computational complexity without losing the error correction performance. Meanwhile, for a specific SR1 / SPC node containing a Rate-0 source node structure, a CMDD and CITS enhanced decoding scheme is proposed, which makes up for the performance gap between the existing two-stage decoding and the maximum likelihood bound in the low-level source node scenario, significantly improves the decoding reliability while maintaining low latency.

Description

Technical Field

[0001] This invention relates to the field of channel coding and decoding technology in communication systems, specifically to a decoding method and system for a polar code SR1 / SPC node. Background Technology

[0002] Polar codes have been theoretically proven to asymptotically achieve channel capacity in binary input memoryless channels through Successive Cancellation (SC) decoding. However, with finite code lengths, the error correction performance of basic SC decoding is significantly inferior to that of Maximum-Likelihood (ML) decoding. To improve error correction performance, enhancement schemes such as Successive Cancellation List (SCL) decoding have been proposed. However, SC-based algorithms inherently possess the characteristic of serial traversal computation, resulting in extremely high decoding latency, making it difficult to meet the low-latency requirements of modern communication systems.

[0003] To overcome the aforementioned high latency technical drawbacks, existing FastSC (FSC) decoding techniques effectively reduce latency by identifying specially structured constituent nodes in the decoding tree and applying on-the-fly decoding strategies to prune the traversal process. The identification techniques for these special nodes have evolved from basic Rate-0, Rate-1, Single Parity Check (SPC), and Repetition (REP) nodes to generalized types of nodes that can unify most high-rate special nodes, such as SR1 / SPC nodes. The binary tree of SR1 / SPC nodes can be decomposed into the leftmost arbitrary source node and the right-hand sequence Rate-1 or SPC nodes along the leftmost path branch. However, existing decoding schemes for SR1 / SPC nodes still have the following technical drawbacks: First, there is a lack of a unified expression for constraint relationships: existing technologies typically treat the internal parity constraints of SR1 / SPC nodes as two different types when processing them. This approach fails to delve into the highly structured features within the nodes, resulting in the inability to perform lossless simplification during decoding. Consequently, existing two-stage (TS) decoding schemes exhibit redundancy in the flip set used in the second stage when decoding certain SR1 / SPC subclass nodes.

[0004] Secondly, the hardware implementation is not user-friendly: existing two-stage decoding schemes rely on pre-storing the flip set. This table lookup or pre-storage mechanism not only consumes a lot of chip hardware storage resources, but also lacks flexibility and is not conducive to the efficient and real-time generation of underlying hardware.

[0005] Finally, limitations in error correction performance: Existing two-stage decoding schemes for SR1 / SPC nodes still fall short of approximating maximum likelihood (ML) performance in certain scenarios.

[0006] Therefore, determining a unified check constraint relationship on the SR1 / SPC nodes, providing a hardware-friendly method for generating flip sets, and improving the decoding performance of the SR1 / SPC nodes are of great significance for their application in fast SC decoding systems for polar codes. Summary of the Invention

[0007] This application provides a decoding method and system for polar code SR1 / SPC nodes, aiming to solve the problems in the prior art where SR1 / SPC node decoding relies on recursive algorithms to construct flip sets, resulting in high hardware implementation complexity and redundant flip set search space, as well as the significant performance loss in decoding under specific low-level source node scenarios.

[0008] To achieve the above objectives, this invention provides a decoding method for polar code SR1 / SPC nodes, comprising the following steps: S1. Obtain the log-likelihood ratio vector of the SR1 / SPC node, and obtain its corresponding hard decision vector based on the log-likelihood ratio vector. S2. Based on the structural parameters of the SR1 / SPC nodes, construct a unified matrix to uniformly represent the constraint relationships of parallel parity check and segmented parity check. S3. Perform the first stage of decoding based on the parallel constraints in the unified matrix to obtain the intermediate codeword estimate that strictly satisfies all parallel parity checks. S4. Perform the second stage of decoding based on the segmentation constraints in the unified matrix, construct the flip set and flip the intermediate codeword estimates to obtain the final decoded output.

[0009] Preferably, S2 specifically includes: Construct a basis matrix. The upper half of the basis matrix is ​​composed of multiple identity matrices, and the lower half is composed of a block matrix formed by repeatedly concatenating block-type binary expanded column vectors. Perform the Kronecker product operation on the basis matrix and the all-1 row vector to generate a unified matrix, so that the legal codeword vector and the source node codeword estimation vector satisfy the constraint relationship of the unified matrix.

[0010] Preferably, S3 specifically includes: Based on the minimum sum criterion, the log-likelihood ratio vector is propagated to the source node of the SR1 / SPC node to obtain the source node estimate; Based on the parallel constraints in the unified matrix, Wagner decoding is performed on multiple independent parallel parity check groups. In each group, the least reliable bit is found and flipped to obtain an intermediate codeword estimate that strictly satisfies all parallel parity checks.

[0011] Preferably, S4 specifically includes: Calculate the global syndrome of the intermediate codeword estimate and extract the last few bits to form the checksum; If the checksum is not all zeros, construct the flipped set using a non-recursive triplet index mapping method; The index pairs that optimize the path metric are selected from the flip set and flipped to obtain the final decoded output.

[0012] Preferably, the method for constructing the flipped set using a non-recursive triple index mapping method includes: The physical index is decomposed into a triple consisting of replica label, block type, and intra-block offset; Based on the index of the first non-zero bit in the checksum, traverse the starting block type and determine the block type that is paired with it by bitwise XOR logic; Based on the deduplication criteria, the offsets within the block and the copy labels are traversed, and the generated triples are mapped back to the physical index and stored in the flipped set.

[0013] Preferably, when the unified matrix contains several duplicate copies, a lossless simplification strategy is adopted, including: During the first stage of decoding, the aggregated index vector is extracted by comparison tree, and the physical index with the smallest absolute value of log-likelihood ratio among all replicas is selected for each index within the reduced space. During the second stage of decoding, agglomeration flip sets are generated only within the reduced space covered by the base matrix, and agglomeration pairs are selected according to the optimal path metric principle, and then mapped back to the physical index for flipping.

[0014] Preferably, an enhanced CMDD decoding scheme is also provided, including: According to the Chase-II algorithm, the μ positions with the lowest reliability are selected from the log-likelihood ratio vector to generate 2. μ One test pattern; For each test pattern, calculate its corresponding syndrome and construct an error vector based on the syndrome; The current test pattern is corrected based on the error vector to generate candidate codewords; Select the codeword with the best path metric from all candidate codewords as the final decoded output.

[0015] Preferably, an enhanced CITS and RCITS decoding scheme is also provided, including: Select the two positions with the lowest reliability from the log-likelihood ratio vector, and denote them as the first position and the second position; By inverting the sign of the hard decision vector and performing a flip operation at the first and second positions, a test vector containing four flip modes is constructed. For each test vector, compute its hard decision adjoint and decompose the hard decision adjoint into offset and type components; If the number of 1s in the offset component is equal to 2, then enumerate all block types according to the type component and generate physical index pairs as candidate flip sets. Otherwise, perform first-stage decoding and second-stage decoding to generate an internal flip pattern, where the second-stage decoding preserves multiple candidate flip paths in the output; All candidate paths generated by the superposition of the initial flip mode and the internal flip mode are aggregated, and the final decoded output is selected based on the path metric.

[0016] The present invention also provides a decoding system for polar code SR1 / SPC nodes, the system being used to implement the above method, comprising: The acquisition module obtains the log-likelihood ratio vector of the SR1 / SPC node and obtains its corresponding hard decision vector based on the log-likelihood ratio vector. The construction module constructs a unified matrix based on the structural parameters of the SR1 / SPC nodes to uniformly represent the constraint relationships between parallel parity check and segmented parity check. The first decoding module performs the first stage of decoding based on the parallel constraints in the unified matrix, and obtains the intermediate codeword estimate that strictly satisfies all parallel parity checks. The second decoding module performs the second stage of decoding based on the segmentation constraints in the unified matrix, constructs the flip set and flips the intermediate codeword estimates to obtain the final decoded output.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention achieves efficiency improvements and architectural optimizations at the technical level. By constructing a unified matrix constraint and introducing a non-recursive flip set construction algorithm, it eliminates the complex recursive branch judgments and cumbersome pre-storage overhead of existing flip set construction schemes, thereby enhancing the parallelism and throughput performance of the hardware implementation. Specifically, it addresses... The proposed lossless simplification strategy for the SR1 / SPC node can reduce the search space of the flip pair from the original physical length to the condensed vector length, significantly reducing the computational complexity without sacrificing any error correction performance, and providing solid algorithmic support for the high reliability and low latency decoding requirements in 5G and future communication standards.

[0018] Furthermore, regarding error correction performance and applicability, this invention proposes enhanced decoding schemes of CMDD and CITS for specific structures with source nodes at Rate-0, effectively bridging the performance gap between existing two-stage decoding and the maximum likelihood (ML) bound in low-level source node scenarios. While maintaining low complexity and low latency decoding, it further improves the decoding reliability of polar code SR1 / SPC nodes. Attached Figure Description

[0019] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating the overall process of decoding a polar code SR1 / SPC node, as provided in this application embodiment; Figure 2 A schematic diagram of the structure of the SR1 / SPC node in a binary tree representation provided in an embodiment of this application; Figure 3 This application provides a unified matrix structure and a triplet-based index mapping diagram, where the SR1 / SPC node parameters are: ; Figure 4 A flowchart of a non-recursive flip set construction method provided in an embodiment of this application; Figure 5 The decoding scheme provided in the embodiments of this application is in the R0-SSPC node (the source node is Rate-0 and SR1 / SPC node parameter settings The performance curve of the block error rate under ().

[0021] Figure 6 The decoding scheme provided in the embodiments of this application is in the R0-SSPC node (the source node is Rate-0 and SR1 / SPC node parameter settings The performance curve of the block error rate under (). Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] Example 1 In polar code decoding trees, to reduce decoding latency, child nodes with specific structures are typically identified for fast decoding. This application's embodiments target a class of high-rate nodes called SR1 / SPC. For example... Figure 2 As shown, one level is (length is) The SR1 / SPC node of ) has its leftmost branch as a level of (length is) The source node of the sequence is , while the right-side child nodes branching from the leftmost path are either rate-1 nodes or single parity check (SPC) nodes. Let the hierarchical set of the right-side SPC child nodes be . The number of SPC child nodes is And let This is the difference between the SR1 / SPC root node level and the source node level.

[0025] Combination Figure 1 The present application provides a method for decoding SR1 / SPC nodes of polar codes, which specifically includes the following steps: S1. Obtain the log-likelihood ratio vector of the SR1 / SPC node, and obtain its corresponding hard decision vector based on the log-likelihood ratio vector.

[0026] First, the input information of the SR1 / SPC node is obtained. The log-likelihood ratio (LLR) vector λ passed from the previous layer of the polar code decoding tree is received, and its corresponding hard decision vector is extracted using the hard decision function. ,Right now , where HD represents the hard decision function.

[0027] S2. Based on the structural parameters of the SR1 / SPC nodes, construct a unified matrix to uniformly represent the constraint relationships of parallel parity check and segmented parity check.

[0028] This step is primarily used to construct a unified matrix constraint. Existing technologies typically treat parallel parity checks (P-PCs) and segmented parity checks (S-PCs) separately. This embodiment establishes a unified matrix constraint system through mathematical derivation.

[0029] First, construct the basis matrix. Its dimensions are The formula is as follows: The upper part is composed of indivual identity matrix It is composed of concatenations, with the lower half consisting of repeated block-type binary expanded column vectors. The block matrix formed in this way It is assembled from these components. Subsequently, a unified matrix is ​​generated using the Kronecker product. : in, It is a row vector consisting entirely of 1s. d This is expressed as the difference between the SR1 / SPC root node level and the source node level. δ This represents the number of right-hand SPC child nodes in the SR1 / SPC binary tree representation.

[0030] Valid codeword vectors x Must meet: Here, The source node codeword estimation vector (if the source node is Rate-0, then it is an all-zero vector). It is a vector of all zeros.

[0031] S3. Perform the first stage of decoding based on the parallel constraints in the unified matrix to obtain intermediate codeword estimates that strictly satisfy all parallel parity checks.

[0032] First stage decoding. Utilizing The former The row represents the parallel constraint. The LLR is propagated to the source node using the Min-Sum criterion to obtain the source node estimate. Afterwards, Wagner decoding is performed on each independent P-PC group. That is, the least reliable bit in each group is found, and if the checksum is not satisfied, the bit is flipped, thus obtaining an intermediate codeword estimate that strictly satisfies all P-PCs. .at this time, It may still violate S-PCs.

[0033] S4. Perform the second stage of decoding based on the segmentation constraints in the unified matrix, construct the flip set and flip the intermediate codeword estimates to obtain the final decoded output.

[0034] Second-stage decoding. Calculating the global syntactic. Since P-PCs have been satisfied, It must have In the form of. After extraction Bit constitutes a checksum Let its integer form be . .like The fact that the set is not all zero indicates that there are unsatisfied S-PCs, and a flip set needs to be constructed. .

[0035] like Figure 3 and Figure 4 As shown, this embodiment abandons the recursive construction of the flipped set in existing decoding techniques and adopts a hardware-friendly triple index mapping method: arbitrary physical indexes are mapped... Decomposed into triples The physical index and the triple satisfy the following conditions: .in For copy tags, For block type, This is an offset within the block. The specific execution logic of the non-recursive constructor is as follows: (1) Positioning The index of the first non-zero bit in the middle is denoted as . w .

[0036] (2) Type of the starting block for outer loop traversal The type of paired blocks can be directly determined using bitwise XOR logic: , where γint represents The decimal representation of , and Indicates the type of block to be flipped and paired.

[0037] (3) Deduplication judgment: Only when The w The inner loop is executed only when the bit is 0 (or 1, which should be kept consistent) to avoid generating duplicate unordered pairs.

[0038] (4) The inner loop iterates through the offsets within the block. and copy tags and .

[0039] (5) Calculate the physical index of the generated triples using the formula. and Store in the flipped set .

[0040] Finally, in The index pairs that optimize the path metric are selected and flipped to obtain the final output. Since the four nested loops are independent of each other and do not require recursive calls, this method is suitable for parallel construction generation of underlying hardware (such as FPGA / ASIC).

[0041] Example 2 This embodiment provides a lossless simplification strategy (for...) ) Due to the unified matrix Include indivual Duplicate copies, when At this time, the search space of the flipped set is redundant. During the first stage of decoding, this embodiment extracts the agglomerative index vector using a comparison tree. For a length of Each index within the reduced space i Find the physical index with the smallest absolute LLR value among all replicas and store it. .

[0042] Subsequently, during the second stage of generating the flipped set, a forced constraint is applied. Only in the basis matrix Generate condensed flip sets within the covered reduced space At this point, the search scale increased from the original... Descending to Finally, the optimal condensation pair is selected using the following formula: in, This represents the optimal agglomeration inversion pair. This indicates the estimated intermediate codeword. This indicates that the SR1 / SPC node receives the LLR vector passed from the layer above the polar code decoding tree.

[0043] Map it back to the physical index and flip it. x 1. This reduces complexity without sacrificing any error correction performance.

[0044] Example 3 This embodiment also provides a CMDD enhanced decoding scheme (for R0-SSPC nodes, i.e., source nodes are Rate-0 and...). (SR1 / SPC node) When the source node level q When the size is small, traditional two-stage decoding lags behind machine learning in performance. The CMDD decoding scheme proposed in this embodiment is as follows: (1) According to the Chase-II algorithm, select the LLR vector with the lowest reliability. μ 2 are generated at each location. μ Test pattern .

[0045] (2) For each test pattern Calculate the syndrome ,in Let T denote the basis matrix, and T denote the transpose. Let [the matrix be denoted as 'T' The former Position ,back Position .like If all zeros are present, then the error vector is... It is a zero vector; if its predecessor Bit If all zeros are present, then the error vector... At index 0 and The value is 1, where the function BinToInt represents converting a binary vector into a decimal integer representation; if Contains a set of non-zero indexes Take the largest index Then construct the error vector For: For ,and The remaining positions are 0.

[0046] (3) Summarize all candidate codewords It also outputs the path with the best metric.

[0047] Example 4 This embodiment also provides an enhanced CITS and RCITS decoding scheme (for R0-SSPC nodes, i.e., source nodes with Rate-0 and...). (SR1 / SPC node) To balance low latency and high performance, the CITS decoding scheme proposed in this application is as follows: (1) Select the two lowest reliability positions in the LLR vector, and then analyze the vector. The sign negation constructs a test vector containing four flip modes. ,remember It is its hard decision vector.

[0048] (2) For each Calculate its hard decision conjunctive formula And record The former The bit is the offset component, then Bit is a type component If the number of 1s in the offset component is equal to 2, then the corresponding offset index is denoted as . Then directly enumerate all block types Generate what satisfies Physical index pairs As a candidate flip set; if the number of 1s in the offset component is not equal to 2, multiple candidate flip paths are output by performing the first stage decoding and the second stage decoding. The second stage decoding does not need to find the optimal flip pair after constructing the flip set.

[0049] (3) Summarize all candidate paths generated by the superposition of the initial flip mode and the internal flip mode, and filter the final output based on the path metric.

[0050] RCITS optimization strategy: Calculate the original adjoint expression If it were before If the number of bits is an even number of 1s, the test vector retains only the "no flip" and "double flip" modes; if the number of bits is an odd number of 1s, only the "single bit flip" mode is retained. This reduces the number of test paths from four to two, further saving hardware resources.

[0051] Example 5 This embodiment quantitatively verifies the technical effectiveness of various decoding schemes proposed in the preceding embodiments under the 5G standard polar code environment. First, regarding the lossless simplification strategy described in Embodiment 2, its impact on the overall decoding complexity of polar codes is evaluated. In this evaluation process, the following is defined: The length of the mother code for the polar code. The coding rate of the polar code. This indicates the total number of SR1 / SPC nodes contained in the full decoding tree under this configuration, while This indicates that the parameter conditions are met. The number of nodes that can apply the lossless simplification strategy described in Example 2. By comparing four different decoding architectures, namely traditional sequential elimination decoding (SC) (whose computational complexity is denoted as...),... C SC), a fast decoding method that only recognizes basic node types (Rate-0, Rate-1, REP, and SPC nodes) FSC1 (whose computational complexity is denoted as SC). C FSC1), and FSC2, a scheme that integrates SR1 / SPC nodes on top of the basic node type but is not simplified (its computational complexity is denoted as FSC1). C FSC2), and Scheme FSC3 after fully applying the lossless simplification strategy of this application (whose computational complexity is denoted as FSC2). C FSC3) yielded the complexity statistics shown in Table 1. All computational complexity is measured in floating-point operations (FLOPs), corresponding to the total number of floating-point additions and comparisons required for each decoding method in the worst-case scenario.

[0052] Table 1 As shown in Table 1, at all tested bitrates (1 / 3, 1 / 2, 2 / 3), the FSC3 scheme, which applied the lossless simplification strategy, achieved varying degrees of complexity reduction compared to FSC2. This is especially true at certain bitrates. In the scenario described in Example 2, the search size for flip pairs was successfully reduced by using the agglomerative index vector mapping, decreasing the computational overhead from 7712 to 5624. This demonstrates that the FSC3 scheme, which employs the simplified construction technique of this application, can reduce computational complexity to a level comparable to or even better than FSC1 while maintaining error correction performance and latency identical to FSC2. Furthermore, due to the introduction of SR1 / SPC nodes, the overall decoding latency of polar codes is lower than that of FSC1.

[0053] Subsequently, this embodiment evaluated only for R0-SSPC nodes (root node level is The source node level is Block Error Rate (BLER) performance under different configurations; see appendix for specific results. Figure 5 and attached Figure 6 By using list size The SCL decoding is used as an approximate reference for the maximum likelihood (ML) bound. Simulation results show that when the source node level... Smaller (as shown in the attached image) Figure 5 , When the time frame is reached, there is a significant performance gap between existing two-stage (TS) decoding schemes and the ML limit. Within this range, the CMDD and CITS schemes proposed in Embodiments 3 and 4 of this application both exhibit excellent performance, with their BLER curves closely approaching the ML limit. Indicates based on μ A test pattern is generated using unreliable information bits, for the root node level of... SR1 / SPC nodes, Provide more Better performance, decoding complexity is The decoding complexity of CITS is... Meanwhile, the simplified RCITS scheme suffers minimal performance loss compared to the complete CITS scheme, thus verifying the efficiency of the optimization strategy described in this application.

[0054] With the source node level As the performance of TS decoding increases, the performance gap between two-stage ML decoding and TS decoding tends to narrow. For example, in Under the configuration (attached) Figure 6 ), TS decoding in The loss is only about 0.05 dB. In this high-level source node scenario, although the CMDD scheme exhibits significant performance degradation in the low signal-to-noise ratio region, the CITS scheme proposed in this application still demonstrates strong robustness, consistently outperforming TS decoding under various signal-to-noise ratios. This further proves the universality and stability of the CITS scheme under different node parameter configurations.

[0055] Example 6 This embodiment also provides a decoding system for polar code SR1 / SPC nodes, including: an acquisition module for acquiring the log-likelihood ratio vector of the SR1 / SPC node and obtaining its corresponding hard decision vector based on the log-likelihood ratio vector; a construction module for constructing a unified matrix for uniformly representing the constraint relationship between parallel parity check and segmented parity check based on the structural parameters of the SR1 / SPC node; a first decoding module for performing a first-stage decoding based on the parallel constraints in the unified matrix to obtain intermediate codeword estimates that strictly satisfy all parallel parity checks; and a second decoding module for performing a second-stage decoding based on the segmented constraints in the unified matrix, constructing a flip set and flipping the intermediate codeword estimates to obtain the final decoded output.

[0056] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A decoding method for polar code SR1 / SPC nodes, characterized in that, include: S1. Obtain the log-likelihood ratio vector of the SR1 / SPC node, and obtain its corresponding hard decision vector based on the log-likelihood ratio vector. S2. Based on the structural parameters of the SR1 / SPC nodes, construct a unified matrix to uniformly represent the constraint relationships of parallel parity check and segmented parity check. S3. Perform the first stage of decoding based on the parallel constraints in the unified matrix to obtain the intermediate codeword estimate that strictly satisfies all parallel parity checks. S4. Perform the second stage of decoding based on the segmentation constraints in the unified matrix, construct the flip set and flip the intermediate codeword estimates to obtain the final decoded output.

2. The decoding method for polar code SR1 / SPC nodes according to claim 1, characterized in that, S2 specifically includes: Construct a basis matrix. The upper half of the basis matrix is ​​composed of multiple identity matrices, and the lower half is composed of a block matrix formed by repeatedly concatenating block-type binary expanded column vectors. Perform the Kronecker product operation on the basis matrix and the all-1 row vector to generate a unified matrix, so that the legal codeword vector and the source node codeword estimation vector satisfy the constraint relationship of the unified matrix.

3. The decoding method for polar code SR1 / SPC nodes according to claim 1, characterized in that, S3 specifically includes: Based on the minimum sum criterion, the log-likelihood ratio vector is propagated to the source node of the SR1 / SPC node to obtain the source node estimate; Based on the parallel constraints in the unified matrix, Wagner decoding is performed on multiple independent parallel parity check groups. In each group, the least reliable bit is found and flipped to obtain an intermediate codeword estimate that strictly satisfies all parallel parity checks.

4. The decoding method for polar code SR1 / SPC nodes according to claim 1, characterized in that, S4 specifically includes: Calculate the global syndrome of the intermediate codeword estimate and extract the last few bits to form the checksum; If the checksum is not all zeros, construct the flipped set using a non-recursive triplet index mapping method; The index pairs that optimize the path metric are selected from the flip set and flipped to obtain the final decoded output.

5. The decoding method for polar code SR1 / SPC nodes according to claim 4, characterized in that, The method for constructing the flipped set using a non-recursive triple index mapping method includes: The physical index is decomposed into a triple consisting of replica label, block type, and intra-block offset; Based on the index of the first non-zero bit in the checksum, traverse the starting block type and determine the block type that is paired with it by bitwise XOR logic; Based on the deduplication criteria, the offsets within the block and the copy labels are traversed, and the generated triples are mapped back to the physical index and stored in the flipped set.

6. The method according to any one of claims 1-4, characterized in that, When the unified matrix contains several duplicate copies, a lossless simplification strategy is adopted, including: During the first stage of decoding, the aggregated index vector is extracted by comparison tree, and the physical index with the smallest absolute value of log-likelihood ratio among all replicas is selected for each index within the reduced space. During the second stage of decoding, agglomeration flip sets are generated only within the reduced space covered by the base matrix, and agglomeration pairs are selected according to the optimal path metric principle, and then mapped back to the physical index for flipping.

7. The method according to any one of claims 1-4, characterized in that, A CMDD enhanced decoding scheme is also provided, including: According to the Chase-II algorithm, the μ positions with the lowest reliability are selected from the log-likelihood ratio vector to generate 2. μ One test pattern; For each test pattern, calculate its corresponding syndrome and construct an error vector based on the syndrome; The current test pattern is corrected based on the error vector to generate candidate codewords; Select the codeword with the best path metric from all candidate codewords as the final decoded output.

8. The method according to any one of claims 1-4, characterized in that, An enhanced CITS and RCITS decoding scheme is also provided, including: Select the two positions with the lowest reliability from the log-likelihood ratio vector, and denote them as the first position and the second position; By inverting the sign of the hard decision vector and performing a flip operation at the first and second positions, a test vector containing four flip modes is constructed. For each test vector, compute its hard decision adjoint and decompose the hard decision adjoint into offset and type components; If the number of 1s in the offset component is equal to 2, then enumerate all block types according to the type component and generate physical index pairs as candidate flip sets. Otherwise, perform first-stage decoding and second-stage decoding to generate an internal flip pattern, where the second-stage decoding preserves multiple candidate flip paths in the output; All candidate paths generated by the superposition of the initial flip mode and the internal flip mode are aggregated, and the final decoded output is selected based on the path metric.

9. A decoding system for a polar code SR1 / SPC node, the system being used to implement the method according to any one of claims 1-8, characterized in that, include: The acquisition module obtains the log-likelihood ratio vector of the SR1 / SPC node and obtains its corresponding hard decision vector based on the log-likelihood ratio vector. The construction module constructs a unified matrix based on the structural parameters of the SR1 / SPC nodes to uniformly represent the constraint relationships between parallel parity check and segmented parity check. The first decoding module performs the first stage of decoding based on the parallel constraints in the unified matrix, and obtains the intermediate codeword estimate that strictly satisfies all parallel parity checks. The second decoding module performs the second stage of decoding based on the segmentation constraints in the unified matrix, constructs the flip set and flips the intermediate codeword estimates to obtain the final decoded output.

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