A method and device for measuring the energy efficiency ratio of an optical computing chip

Abstract

A kind of optical computing chip energy efficiency ratio measurement method and device, the main steps of the method include: determining the kind of active device in optical computing chip;Respectively calculate the power consumption value of high-speed optoelectronic modulator, phase shifter, photodetector;The total power consumption of optical computing chip is obtained by adding these power consumption values;The energy consumption ratio of optical computing chip is calculated by the ratio of the computing power value of optical computing chip and total power consumption value.The method and device form a systematic measurement method for the energy consumption ratio of optical computing chip, solve the problem of current photonic computing chip energy efficiency ratio index measurement method ambiguity, realize the reliable measurement of optical computing chip energy efficiency ratio index, provide an important basis for the design optimization of optical computing chip.

Description

Technical Field

[0001] This invention relates to the field of chip design and testing technology, and in particular to a method and apparatus for testing the energy efficiency ratio of an optical computing chip. Background Technology

[0002] Optical chips are a new type of integrated optical circuit based on photonics technology. They integrate optical functional components such as lasers, modulators, optical waveguides, and detectors onto a single substrate to construct miniaturized photonic systems. These systems enable the generation, modulation, transmission, and processing of optical signals, offering advantages such as high integration, miniaturization, high efficiency, and low power consumption. Optical computing refers to a type of computing system that processes information or performs data operations based on the wave and particle properties of light. Optical computing chips, as a form of optical chip, can directly implement computational tasks at the physical layer and are a type of chip developed to meet the high-performance computing requirements of applications.

[0003] Optical computing chips consist of optical computing networks, primarily including active devices such as on-chip high-speed modulators, phase shifters, and photodetectors, as well as passive devices such as optical waveguides, beam splitters / combiners, etc. High-speed modulators mainly utilize the electro-optic effect of materials to change the refractive index of the optical waveguide under the influence of an applied electric field, thereby converting electrical signals into optical signal parameters such as intensity and phase. Phase shifters utilize the thermo-optic effect or carrier injection to fine-tune the refractive index of the waveguide material, changing the phase of light wave propagation to precisely control the interference state. In optical computing networks, phase shifters are used to adjust the phase difference between the two arms of an interferometer, thereby changing the weights of matrix elements. Photodetectors utilize the photoelectric effect, where photons excite electron-hole pairs in semiconductor materials to generate current signals, achieving the conversion of optical signals into electrical signals.

[0004] Passive devices require no external energy input, relying on physical structure or manipulation of the light propagation path. Optical waveguides utilize the structural difference between a high-refractive-index core and a low-refractive-index cladding to confine light propagation within the waveguide core through total internal reflection. On-chip single-mode waveguides can achieve sub-micron level optical field confinement, connecting lasers, modulators, computing units, and detectors to construct complex optical computing network topologies. Beam splitters / combiners employ Y-shaped waveguides and multimode interference couplers to guide the optical field through waveguide width variations, distributing input signals to multiple computing nodes and aggregating computational results. The complete workflow of an optical computing chip is described as follows: an electrical signal is encoded into an optical signal by a high-speed modulator; a phase shifter adjusts the interference phase according to matrix weights; a waveguide network guides the optical signal to the computing unit; the optical signal undergoes coherent superposition in a multi-stage interferometer to complete the computational processing; and the intensity distribution of the interferometric light is converted into an electrical signal by a photodetector to output the result.

[0005] The energy efficiency ratio (EER) of optical computing chips is a key parameter for evaluating the overall performance and practical value of these chips. It is an important indicator for measuring the relationship between performance and power consumption, and its significance surpasses that of a single computing speed indicator. Furthermore, the EER can drive the optimization of optical chip design in terms of system integration and task adaptability. However, currently, there is no complete method or device for calculating the EER of optical computing chips to evaluate their energy efficiency.

[0006] Current methods for calculating the energy efficiency ratio (EER) of optical computing chips do not consider the power consumption of each active device in the optical computing network. These methods are rather general, resulting in vague boundaries for system energy consumption statistics and a lack of qualitative analysis of the EER. Consequently, they fail to meet the requirement for reliable measurement of the EER of a single optical computing chip. Furthermore, a systematic measurement method for the EER of optical computing chips has not yet been developed. Summary of the Invention

[0007] This disclosure provides a method and apparatus for measuring the energy efficiency ratio of an optical computing chip. It fully considers the power consumption of each active device in the optical computing chip and uses it as a parameter for calculating the energy efficiency ratio. It defines the power consumption boundary of the optical computing chip, realizes qualitative and quantitative analysis of the energy efficiency ratio index, and forms a relatively systematic method and apparatus for measuring the energy efficiency ratio.

[0008] The method for measuring the energy efficiency ratio of an optical computing chip provided in this disclosure mainly includes the following steps: First, connect all the external devices required for the optical computing chip to work properly, so that it can perform matrix operations and application functions. To determine the types of active devices in an optical computing chip, the active devices in an optical computing chip typically consist of three parts: a high-speed optoelectronic modulator, a phase shifter, and a photodetector. The power consumption of the modulation device is calculated based on the power consumption of a single modulation device in the high-speed optoelectronic modulator of the optical computing chip and the number of optoelectronic modulators in the optical computing chip. The power consumption of the phase shifter is calculated based on the power consumption of a single phase shifter in the optical computing chip and the number of phase shifters in the optical computing chip. When the optical computing chip network is large, the number of phase shifters is large, and the number of phase shifters can be calculated by formula based on the number of channels in the chip. The power consumption of the phase-shifting device is calculated based on the power consumption of a single photodetector in the phase shifter of the optical computing chip and the number of photodetectors in the optical computing chip. The total power consumption of the optical computing chip is obtained by adding the power consumption values ​​of the high-speed optoelectronic modulator, phase shifter, and photodetector. The energy efficiency ratio of an optical computing chip is calculated by comparing its computing power with its total power consumption.

[0009] This disclosure also provides a transpose for measuring the energy efficiency ratio of an optical computing chip, including: The on-chip active device power acquisition module is used to acquire the power consumption of the high-speed optoelectronic modulator, phase shifter and photodetector in the optical computing chip, obtain the corresponding power consumption data, and add the power consumption to obtain the total power consumption of the optical computing chip. The optical computing chip computing power statistics module is used to calculate the computing power of the optical computing chip and obtain the chip's computing power parameters. The energy efficiency ratio calculation and analysis module is used to calculate the energy efficiency ratio of the optical computing chip, obtain the chip's energy efficiency ratio, analyze the changes in the chip's energy efficiency ratio parameters over time, and evaluate the chip's overall performance during normal operation.

[0010] Compared with existing technologies, the beneficial effects of this disclosure are: ① By accurately defining the on-chip power consumption boundary of the optical computing chip and designing a systematic measurement method, qualitative and quantitative analysis of the energy efficiency ratio index is realized, solving the problem of fuzzy and diverse measurement methods for the energy efficiency ratio index of current photonic computing chips; ② The accuracy of energy efficiency ratio calculation is significantly improved; ③ Reliable measurement of the energy efficiency ratio index of optical computing chips is realized; ④ An important basis is provided for the design optimization of optical computing chips. Attached Figure Description

[0011] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments of this disclosure taken in conjunction with the accompanying drawings, in which the same reference numerals generally represent the same components.

[0012] Figure 1 This is a flowchart of the method for measuring the energy efficiency ratio of the optical computing chip in the embodiment; Figure 2 This is a schematic diagram of the basic structural components of the optical computing chip in the embodiment; Figure 3 This is a schematic diagram of singular value decomposition of the cascaded optical computing chip computing network in the embodiment; Figure 4 The diagram shows the triangular decomposition interference architecture and the rectangular decomposition interference network architecture of the optical computing chip in the embodiment. Figure 5 This is a schematic diagram of a device for measuring the energy efficiency ratio of an optical computing chip in one of the embodiments. Detailed Implementation

[0013] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0014] This disclosure provides a method for measuring the energy efficiency ratio of an optical computing chip. In one exemplary embodiment, the specific process is as follows: Figure 1 As shown, it includes the following steps: Step 1: Complete the connection of the external devices required for the optical computing chip to work.

[0015] Specifically, the optical computing chip needs to be connected to a tunable laser source to provide a stable laser signal; a multi-channel voltage / current source needs to be connected to provide a stable voltage / current signal to control the matrix weights in the matrix operations of the optical computing chip; an erbium-doped fiber amplifier and a polarization controller need to be connected to control the optical signal power and polarization mode; a photodetector needs to be connected to convert the optical signal into an electrical signal; and a sampling oscilloscope needs to be connected to acquire the electrical signal and receive the data.

[0016] Step 2: Calculate the power consumption of the high-speed modulator The power consumption of a high-speed modulator is related to the number of modulators used in the optical computing chip and the power of each modulator. Different operating points need to be selected based on the differences in the input signal. Different operating points correspond to different operating voltages, which in turn correspond to different power consumptions. The power consumption of the current modulator can be calculated by selecting the appropriate operating point. The total power consumption of the high-speed modulator can be expressed by Expression 1: (Expression 1) for N×N In an optical computing chip network, each channel typically corresponds to a high-speed modulator. Therefore, the power consumption of the high-speed modulator section can be expressed by expression two: (Expression 2) in, N This indicates the number of channels in the optical computing chip. This represents the electrical power required for a single high-speed modulator to operate.

[0017] Step 3: Calculate the power consumption of the phase shifter The power consumption of phase shifters in optical computing chips depends on the number of phase shifters used and their corresponding electrical power. Commonly used cascaded computing networks for optical computing chips typically employ singular value decomposition to decompose the transmission matrix into a product of a unitary matrix and a diagonal matrix, as illustrated in the diagram below. Figure 3 As shown, the Mach-Zehnder interferometer network architecture is constructed by decomposing it using either a triangle or a rectangle to obtain the corresponding unitary matrix. Schematic diagrams of the triangle-decomposed and rectangle-decomposed interferometer network architectures are shown below. Figure 4 As shown. The total number of phase shifters in the corresponding optical computing chip can be expressed by expression three: (Expression 3) The total power consumption required by the phase shifter in the corresponding optical computing chip is expressed by expression four as follows: (Expression 4) in, This indicates the electrical power corresponding to the operation of a single phase shifter.

[0018] Step 4: Calculate the power consumption of the photodetector The power consumption of photodetectors in optical computing chips depends on the number of photodetectors used and their corresponding electrical power. A certain bias voltage needs to be applied to the photodetector to generate an electro-optic response, thus converting the optical signal into an electrical signal. The power consumption of photodetectors in optical computing chips can be expressed by Expression Five: (Expression 5) in, This represents the electrical power required for a single photodetector to operate.

[0019] In summary, the total power consumption of the on-chip portion of the optical computing chip can be represented by expression six: (Expression 6) Step 5: Calculate the computing power of the optical computing chip The computing power of an optical computing chip is related to its modulation rate and computing scale, which can be specifically expressed by Expression Seven: C =f× N 2 ×2 (Expression 7) in, C The value represents the computing power of the optical computing chip, f represents the modulation rate of the chip's high-speed modulator, and the number 2 indicates that multiplication and addition are performed once in matrix operations.

[0020] Step 6: Calculate the energy efficiency of the optical computing chip. The energy efficiency ratio of an optical computing chip is expressed as the ratio of the chip's computing power to its total power consumption, as shown in Expression Seven: (Expression 8) in, C This indicates the computing power value of the optical computing chip. This refers to the total power consumption of the chip's on-chip portion.

[0021] The above method enables effective calculation of the energy efficiency ratio of optical computing chips. In fact, this method is not only applicable to optical computing chips, but can also be used to calculate the energy efficiency ratio of other photonic chips. By calculating the power consumption of each active device on the chip and summing them, the total on-chip power consumption is obtained. Combining this with the chip's computing power, dividing the chip's computing power by the total on-chip power consumption yields the chip's energy efficiency ratio. The calculation of the energy efficiency ratio not only reflects the overall performance of the chip but also plays a crucial role in assisting in the design optimization of photonic chips.

[0022] Based on the above-described method for measuring the energy efficiency ratio of optical computing chips, this embodiment provides a device for measuring the energy efficiency ratio of optical computing chips, the specific structure of which is as follows: Figure 5 As shown, it includes: an on-chip active device power consumption acquisition module S501, an optical computing chip computing power statistics module S502, and an energy efficiency ratio calculation and analysis module S503.

[0023] The S501 active device power consumption acquisition module is used to collect power consumption data of active devices such as high-speed modulators, phase shifters and photodetectors in optical computing chips. The optical computing chip computing power statistics module S502 is used to collect computing power data corresponding to the normal operation of the optical computing chip. The energy efficiency ratio calculation and analysis module S503 is used to calculate the energy efficiency ratio of the optical computing chip based on the power consumption data obtained from the on-chip active device power consumption acquisition module and the computing power data obtained from the optical computing chip computing power statistics module. By collecting power consumption and computing power data multiple times, multiple energy efficiency ratio results are obtained and averaged to obtain an objective result of the optical computing chip's energy efficiency ratio, truly reflecting the performance of the optical computing chip.

[0024] The above technical solutions are merely exemplary embodiments of the present invention. For those skilled in the art, based on the application methods and principles disclosed in the present invention, it is easy to make various types of improvements or modifications, and not limited to the methods described in the specific embodiments of the present invention. Therefore, the methods described above are merely preferred and not restrictive.

Claims

1. A method for measuring the energy efficiency ratio of an optical computing chip, characterized in that, Includes the following steps: S1 connects to the external devices required for the optical computing chip to work normally, enabling it to perform matrix operations and application functions. S2, determine the types of active devices in the optical computing chip, including: high-speed optoelectronic modulators, phase shifters and photodetectors; S3. Calculate the total power consumption of the high-speed optoelectronic modulator based on the number of high-speed optoelectronic modulators used in the optical computing chip and the power of each modulator. S4. Calculate the total power consumption of the phase shifters based on the number of phase shifters used in the optical computing chip and their corresponding electrical power. S5. Calculate the power consumption value of the photodetector based on the power consumption and number of individual photodetectors in the phase shifter of the optical computing chip. S6, add the power consumption values ​​of the high-speed optoelectronic modulator, phase shifter and photodetector to obtain the total power consumption of the optical computing chip; S7 calculates the energy efficiency ratio of the optical computing chip by combining its computing power and total power consumption.

2. The method according to claim 1, characterized in that, Step S1 specifically includes: A tunable laser source is connected to the optical computing chip to provide a stable laser signal; a multi-channel voltage / current source is connected to provide a stable voltage / current signal to control the matrix weights in the matrix operations of the optical computing chip; an erbium-doped fiber amplifier and a polarization controller are connected to control the optical signal power and polarization mode; a photodetector is connected to convert the optical signal into an electrical signal; and a sampling oscilloscope is connected to acquire and receive the electrical signal.

3. The method according to claim 1 or 2, characterized in that, In step S3, for N×N In an optical computing chip network, each channel typically corresponds to a high-speed modulator. The total power consumption of the high-speed modulator is calculated using the following formula: Where N represents the number of channels in the optical computing chip, This represents the electrical power required for a single high-speed modulator to operate.

4. The method according to claim 3, characterized in that, Step S4 specifically includes: The total number of phase shifters in an optical computing chip is calculated using the chip's channel count N: The total power consumption required by the phase shifter in the corresponding optical computing chip is: in, This indicates the electrical power corresponding to the operation of a single phase shifter.

5. The method according to claim 4, characterized in that, In step S5, the power consumption of the photodetector in the optical computing chip is calculated using the following formula: in, This represents the electrical power required for a single photodetector to operate.

6. The method according to claim 5, characterized in that, In step S6, the total power consumption is: 。 7. The method according to claim 5, characterized in that, In step S6 The computing power of an optical computing chip is calculated using the following formula: C =f× N 2 ×2 in, C This represents the computing power of the optical computing chip; f represents the modulation rate of the chip's high-speed modulator; the number 2 is used to indicate that multiplication and addition are performed once in matrix operations. The energy efficiency ratio of the optical computing chip is: in, C This indicates the computing power value of the optical computing chip. This refers to the total power consumption of the chip's on-chip portion.

8. A device for measuring the energy efficiency ratio of an optical computing chip using the method described in any one of claims 1-7, characterized in that, include: The on-chip active device power acquisition module is used to acquire the power consumption of the high-speed optoelectronic modulator, phase shifter and photodetector in the optical computing chip, obtain the corresponding power consumption data, and add the power consumption to obtain the total power consumption of the optical computing chip. The optical computing chip computing power statistics module is used to calculate the computing power of the optical computing chip and obtain the chip's computing power parameters. The energy efficiency ratio calculation and analysis module is used to calculate the energy efficiency ratio of the optical computing chip and obtain the chip's energy efficiency ratio.

9. The apparatus according to claim 8, characterized in that, The energy efficiency ratio calculation and analysis module is also used to: obtain multiple energy efficiency ratio index results by collecting power consumption data and computing power data multiple times and averaging them, analyze the changes in chip energy efficiency ratio parameters with running time, and evaluate the comprehensive performance of the chip during normal operation.

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