Semiconductor structure and method of manufacturing the same, electronic device
By removing part of the semiconductor layer to form capacitor trenches during DRAM manufacturing before forming the active structure, the problem of limited capacitor trench width is solved, and a capacitor structure with larger capacitance and higher reliability is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2026-05-25
- Publication Date
- 2026-06-23
Smart Images
Figure CN122269692A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method, and an electronic device. Background Technology
[0002] With technological advancements, semiconductor devices are continuously evolving towards miniaturization and higher integration. Dynamic Random Access Memory (DRAM), as an important semiconductor device, can be used to store data or programs for data processing in electronic devices. However, many problems still exist in the actual manufacturing process of DRAM that urgently need improvement. Summary of the Invention
[0003] This disclosure provides a method for manufacturing a semiconductor structure, including: An initial structure is provided, comprising: a substrate; a stacked structure on the substrate, the stacked structure including a first semiconductor layer and a first isolation layer alternately stacked along a first direction; isolation trenches arranged in an array within the stacked structure along a second direction and a third direction; a second isolation layer filling the isolation trenches; and a first opening located within the stacked structure and between adjacent isolation trenches along a third direction; the first direction is perpendicular to the surface of the substrate, and the second direction intersects the third direction and is parallel to the surface of the substrate. A portion of the first semiconductor layer is removed from the first opening to form capacitor trenches on both sides of the first opening along the second direction; A first sacrificial structure is filled into the capacitor groove and the first opening; The second isolation layer is removed to open the isolation trench, and the first semiconductor layer is etched from the isolation trench to form multiple active structures spaced apart along the third direction; A third isolation layer is formed to at least fill the isolation trench; Remove the first sacrificial structure to open the first opening and capacitor slot; A capacitor structure is formed, which includes a first electrode layer that covers the inner wall of the capacitor tank and is electrically connected to the active structure.
[0004] In some embodiments, an initial structure is provided, including: A substrate is provided, and an initial stacked structure is formed on the substrate, the initial stacked structure comprising a first semiconductor layer and a second semiconductor layer alternately stacked along a first direction; Multiple isolation grooves are formed within the initial stacked structure, and a second isolation layer is formed within the isolation grooves; Multiple first openings are formed within the initial stacked structure, and a second semiconductor layer is removed from at least the first openings to form a first gap between adjacent first semiconductor layers; A first isolation layer is formed within the first gap, and a second sacrificial structure is formed within the first opening; Remove the second sacrificial structure to reopen the first opening.
[0005] In some embodiments, forming a first insulating layer within the first gap includes: A first dielectric layer and a first fill layer are formed, wherein the first dielectric layer at least covers the surface of the first semiconductor layer exposed by the first gap, and the first fill layer at least covers the first dielectric layer and fills the first gap; A second isolation layer is formed within the isolation trench, including: A second dielectric layer and a second filling layer are formed. The second dielectric layer covers the inner wall of the isolation trench, and the second filling layer covers the second dielectric layer and fills the isolation trench.
[0006] In some embodiments, after forming the capacitor trench and before forming the first sacrificial structure, a portion of the first dielectric layer and a portion of the second dielectric layer are exposed on the inner wall of the capacitor trench. The method further includes: In the same step, a portion of the first dielectric layer and a portion of the second dielectric layer exposed by the capacitor trench are removed to enlarge the dimensions of the capacitor trench in the first direction and the third direction, and to expose a portion of the first filler layer and a portion of the second filler layer.
[0007] In some embodiments, etching a first semiconductor layer from an isolation trench to form an active structure spaced apart along a third direction includes: A portion of the first semiconductor layer is removed from the isolation trench to reduce the size of the first semiconductor layer in the third direction and to form a plurality of second gaps around the isolation trench. The first semiconductor layer is divided into a plurality of active structures spaced apart in the third direction based on the second gaps, and the third isolation layer also fills the second gaps.
[0008] In some embodiments, after removing the first sacrificial structure to open the first opening and the capacitor slot, and before forming the capacitor structure, the method further includes: The portion of the first filling layer and the portion of the third isolation layer exposed by the capacitor trench are etched to round the inner wall of the capacitor trench and to enlarge the dimensions of the capacitor trench in the first direction and the third direction.
[0009] In some embodiments, forming a capacitor structure includes: A first electrode layer is formed, the first electrode layer having a cup-shaped structure extending along a second direction and with its opening facing the first opening; A capacitor dielectric layer is formed, which at least covers the inner wall of the first electrode layer; A second electrode layer is formed, which covers the capacitor dielectric layer; A capacitor filling layer is formed, which covers the second electrode layer and fills the space enclosed by the second electrode layer.
[0010] In some embodiments, after forming the first electrode layer and before forming the capacitor dielectric layer, the method further includes: A portion of the first isolation layer and a portion of the third isolation layer covering the outer wall of the first electrode layer are removed to form a third gap surrounding a portion of the first electrode layer. The third gap exposes a portion of the outer wall of the first electrode layer, and the capacitor dielectric layer also covers the exposed outer wall of the first electrode layer.
[0011] This disclosure also provides a semiconductor structure, including: A substrate, and a plurality of active structures located on the substrate, the plurality of active structures extending along a second direction and arranged in an array along a first direction and a third direction; the first direction is perpendicular to the surface of the substrate, the second direction intersects the third direction and is parallel to the surface of the substrate; A capacitor structure is located on one side of the active structure along a second direction. The capacitor structure includes a first electrode layer electrically connected to the active structure. The ratio of the dimension of the first electrode layer in the third direction to the dimension of the first electrode layer in the first direction is greater than 1.5.
[0012] In some embodiments, the ratio of the dimension of the first electrode layer in the third direction to the dimension of the active structure in the third direction is greater than 2.
[0013] In some embodiments, the first electrode layer is a cup-shaped structure extending along a second direction and having an opening opposite to the active structure electrically connected to it; the semiconductor structure further includes: The capacitor dielectric layer at least covers the inner wall of the first electrode layer; The second electrode layer covers the capacitor dielectric layer; A capacitor filling layer covers the second electrode layer and fills the space enclosed by the second electrode layer.
[0014] In some embodiments, a portion of the capacitor dielectric layer also surrounds a portion of the first electrode layer and covers a portion of the outer sidewall of the first electrode layer.
[0015] This disclosure also provides an electronic device, including: A processing device, and a storage device electrically connected to the processing device, the storage device comprising a semiconductor structure formed by the manufacturing method of any of the above embodiments, or a semiconductor structure as described in any of the above embodiments.
[0016] In this embodiment of the present disclosure, before etching the first semiconductor layer from the isolation trench to form the active structure, the portion of the first semiconductor layer located between adjacent isolation trenches along the third direction has a dimension in the third direction that is larger than the dimension of the active structure in the third direction. In this embodiment of the present disclosure, by removing a portion of the first semiconductor layer to form a capacitor trench before forming the active structure, compared with the related art scheme of forming a capacitor trench by removing a portion of the active structure after forming the active structure, a capacitor trench with a larger dimension in the third direction can be formed. Thus, a first electrode layer with a larger width in the third direction can be formed, thereby increasing the capacitance of the finally formed capacitor structure and increasing the reliability of the semiconductor structure.
[0017] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and the drawings. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure; Figure 2 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 3 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 4 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 5 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 5 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 4 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 6 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 7 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 7The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 6 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 8 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 9 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 9 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 8 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 10 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 11 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 11 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 10 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 12 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 13 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 13 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 12 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 14 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 15 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 15 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 14 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 16 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 17 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 17 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 16 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 18 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 19 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 19 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 18 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 20 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 21 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 21 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 20 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 22 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 23 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 23 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 22 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 24 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 25 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 25 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 24 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 26 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 27 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 27 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 26 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 28 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 29 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 29 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 28 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 30 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 31A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 31 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 30 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 32 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 33 A schematic diagram of the cross-sections taken from lines C1C2 and D1D2 in the diagram; Figure 33 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 32 A top-view diagram showing the points intercepted by lines A1A2 and B1B2 in the diagram; Figure 34 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 36 and Figure 37 A schematic diagram of the cross-section taken by line C1C2 in the diagram; Figure 35 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 36 and Figure 37 A schematic diagram of the cross-section taken by line D1D2 in the diagram; Figure 36 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 34 and Figure 35 A top-view diagram of the section intercepted by line A1A2; Figure 37 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 34 and Figure 35 A top-view diagram of the section cut by line B1B2; Figure 38 This is a schematic block diagram of the structure of an electronic device provided in some embodiments of this disclosure. Detailed Implementation
[0020] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0021] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0022] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0024] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0026] In semiconductor structures, such as Dynamic Random Access Memory (DRAM), a three-dimensional stacked DRAM architecture is typically employed to further increase memory cell density. In the manufacturing process of three-dimensional DRAM with horizontal memory cells, the semiconductor layer is usually divided into independent active structures. After filling the sides of the active structures with insulating dielectric, a capacitor trench is formed by removing a portion of the active structure, and a capacitor structure is formed within the trench. However, during the formation of the capacitor trench, the width of the trench is limited by the width of the active structure, resulting in a smaller width of the lower electrode of the capacitor structure. This affects the area of the capacitor structure and, consequently, the capacitance.
[0027] Based on this, the technical solutions of the embodiments of this disclosure are proposed. For example... Figure 1 As shown, this disclosure provides a method for manufacturing a semiconductor structure, the method comprising: Step S101: Provide an initial structure, the initial structure including: a substrate, a stacked structure on the substrate, the stacked structure including a first semiconductor layer and a first isolation layer alternately stacked along a first direction; isolation trenches arranged in an array within the stacked structure along a second direction and a third direction; a second isolation layer filling the isolation trenches; a first opening located within the stacked structure and located between adjacent isolation trenches along a third direction; the first direction is perpendicular to the surface of the substrate, the second direction intersects the third direction and is parallel to the surface of the substrate; Step S102: Remove a portion of the first semiconductor layer from the first opening to form capacitor trenches on both sides of the first opening along the second direction; Step S103: Fill the capacitor groove and the first opening with a first sacrificial structure; Step S104: Remove the second isolation layer to open the isolation trench, and etch the first semiconductor layer from the isolation trench to form a plurality of active structures spaced apart along the third direction; Step S105: Form a third isolation layer to at least fill the isolation trench; Step S106: Remove the first sacrificial structure to open the first opening and capacitor slot; Step S107: Form a capacitor structure, the capacitor structure including a first electrode layer, the first electrode layer covering the inner wall of the capacitor tank and electrically connected to the active structure.
[0028] In this embodiment of the present disclosure, before etching the first semiconductor layer from the isolation trench to form the active structure, the portion of the first semiconductor layer located between adjacent isolation trenches along the third direction has a dimension in the third direction that is larger than the dimension of the active structure in the third direction. In this embodiment of the present disclosure, by removing a portion of the first semiconductor layer to form a capacitor trench before forming the active structure, compared with the related art scheme of forming a capacitor trench by removing a portion of the active structure after forming the active structure, a capacitor trench with a larger dimension in the third direction can be formed. Thus, a first electrode layer with a larger width in the third direction can be formed, thereby increasing the capacitance of the finally formed capacitor structure and increasing the reliability of the semiconductor structure.
[0029] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.
[0030] First, execute step S101, as follows: Figures 2 to 13 As shown, an initial structure 20 is provided, which includes: a substrate 10, a stacked structure 11 on the substrate 10, the stacked structure 11 including a first semiconductor layer 111 and a first isolation layer 13 alternately stacked along a first direction; isolation trenches T1 arranged in an array within the stacked structure 11 along a second direction and a third direction; a second isolation layer 12 filling the isolation trenches T1; and a first opening K1 located within the stacked structure 11 and located between adjacent isolation trenches T1 along a third direction; the first direction is perpendicular to the surface of the substrate 10, and the second direction intersects the third direction and is parallel to the surface of the substrate 10.
[0031] Specifically, the initial structure 20 provided may include: A substrate 10 is provided, and an initial stacked structure 11' is formed on the substrate 10. The initial stacked structure 11' may include a first semiconductor layer 111 and a second semiconductor layer 112 alternately stacked along a first direction (e.g., ...). Figures 2 to 3 ); Multiple isolation grooves T1 are formed within the initial stacked structure 11', and a second isolation layer 12 is formed within the isolation grooves T1 (e.g., ...). Figures 4 to 7 ); A plurality of first openings K1 are formed within the initial stacked structure 11', and at least the second semiconductor layer 112 is removed from the first openings K1 to form a first gap S1 between adjacent first semiconductor layers 111 (e.g., Figures 8 to 9 ); A first isolation layer 13 is formed within the first gap S1, and a second sacrificial structure 14 is formed within the first opening K1 (e.g., Figures 10 to 11 ); Remove the second sacrificial structure 14 to reopen the first opening K1 (as shown in the image). Figures 12 to 13 ).
[0032] Here and in the following text, the second direction and the third direction can be perpendicular or oblique.
[0033] In some embodiments, the substrate 10 may be made of a semiconductor material, which may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In some embodiments, the substrate 10 may be a silicon substrate, which may be doped or undoped.
[0034] In some embodiments, the material of the first semiconductor layer 111 may include a semiconductor material, such as single-crystal silicon; the material of the second semiconductor layer 112 may be a material with a larger etching selectivity than the first semiconductor layer 111, and the material of the second semiconductor layer 112 may include a semiconductor material, such as silicon germanium.
[0035] In some embodiments, an epitaxial process can be used to form the initial stacked structure 11'. However, it is not limited to this, and other deposition processes can also be used to form the initial stacked structure 11'.
[0036] See you again Figures 4 to 5 In some embodiments, multiple isolation grooves T1 may penetrate the initial stacked structure 11' along a first direction and may extend along a second direction to divide the initial stacked structure 11' into multiple strip structures (not identified) that extend continuously along the second direction and are sequentially connected along a third direction.
[0037] In some embodiments, the spacing between adjacent isolation trenches T1 in the second direction may be smaller than the spacing between adjacent isolation trenches T1 in the third direction. That is, the size of the portion of the first semiconductor layer 111 located between adjacent isolation trenches T1 in the second direction in the second direction may be smaller than the size of the portion of the first semiconductor layer 111 located between adjacent isolation trenches T1 in the third direction in the third direction.
[0038] In some embodiments, the second isolation layer 12 may have a single-layer or multi-layer structure. See again Figures 6 to 7In some specific embodiments, the second isolation layer 12 may have a multi-layer structure; forming the second isolation layer 12 in the isolation groove T1 may include: forming a second dielectric layer 121 and a second filling layer 122, the second dielectric layer 121 covering the inner wall of the isolation groove T1, and the second filling layer 122 covering the second dielectric layer 121 and filling the isolation groove T1.
[0039] In some embodiments, the material of the second dielectric layer 121 may include one or more of nitrides (e.g., silicon nitride), oxynitrides (e.g., silicon oxynitride), and carbides (e.g., silicon carbide), such as silicon nitride; the material of the second filler layer 122 may also include one or more of sacrificial materials, such as alumina, amorphous carbon, and polycrystalline silicon, such as polycrystalline silicon.
[0040] See you again Figures 8 to 9 In some embodiments, the first opening K1 can penetrate the initial stacked structure 11' along the first direction, and the size of the first opening K1 in the third direction can be substantially equal to the spacing between adjacent isolation trenches T1 in the third direction. The sidewall of the first opening K1 in the third direction can expose part of the second dielectric layer 121, and the sidewall of the first opening K1 in the second direction can completely expose the sidewall of the first semiconductor layer 111 facing the first opening K1, which facilitates the subsequent removal of part of the first semiconductor layer 111 from the first opening K1 to form the capacitor trench T2 (see...). Figures 14 to 15 ).
[0041] However, this is not the only one. In some other embodiments of this disclosure, the size of the first opening K1 in the third direction may be greater than or less than the spacing between the adjacent isolation slots T1 in the third direction, so as to increase the applicability of the scenario.
[0042] See also Figures 8 to 9 In some embodiments, in the same step of forming a plurality of first openings K1 in the initial stacked structure 11', a plurality of second openings K2 may also be formed in the initial stacked structure 11'. The second openings K2 may penetrate the initial stacked structure 11' along a first direction and be located between adjacent isolation trenches T1 along a third direction. The first openings K1 and the second openings K2 may be alternately distributed along a second direction to cut off the first semiconductor layer 111 along the second direction, and the second semiconductor layer 112 may be removed from the plurality of first openings K1 and the plurality of second openings K2.
[0043] In some embodiments, the thickness of the first semiconductor layer 111 may be greater than the thickness of the second semiconductor layer 112. See again Figures 8 to 9In some embodiments, after forming the first gap S1 and before forming the first isolation layer 13, the method may further include: thinning the first semiconductor layer 111 from the first gap S1 to reduce the size of the first semiconductor layer 111 in the first direction, and increasing the size of the first gap S1 in the first direction to facilitate the subsequent formation of the first isolation layer 13 within the first gap S1. Furthermore, by first forming a thicker first semiconductor layer 111 and then thinning the first semiconductor layer 111, the quality of the thinned first semiconductor layer 111 can be effectively improved.
[0044] In some embodiments, the first isolation layer 13 may have a single-layer or multi-layer structure. See again Figures 10 to 11 In some embodiments, the first isolation layer 13 may have a multilayer structure; forming the first isolation layer 13 within the first gap S1 may include forming a first dielectric layer 131 and a first filling layer 132, wherein the first dielectric layer 131 at least covers the surface of the first semiconductor layer 111 exposed by the first gap S1, and the first filling layer 132 at least covers the first dielectric layer 131 and fills the first gap S1.
[0045] See also Figures 10 to 11 In some embodiments, the first dielectric layer 131 may also cover the sidewalls of the second isolation layer 12 exposed by the first gap S1, the first opening K1 and the second opening K2, and the sidewalls of the first semiconductor layer 111 exposed by the first opening K1 and the second opening K2. A portion of the first filling layer 132 may also be located within the first opening K1 and the second opening K2, and may not completely fill the first opening K1 and the second opening K2, so as to define a first space T3 extending in the first direction within the first opening K1 and the second opening K2.
[0046] In some embodiments, the method may further include: forming a third filling layer 133, the third filling layer 133 filling the first space T3; wherein the portions of the first dielectric layer 131 and the first filling layer 132 located within the first gap S1 may serve as the first isolation layer 13, and the portions of the first dielectric layer 131, the first filling layer 132 and the third filling layer 133 located within the first opening K1 may serve as the second sacrificial structure 14.
[0047] In some embodiments, the material of the first dielectric layer 131 may include one or more of nitrides (e.g., silicon nitride), oxynitrides (e.g., silicon oxynitride), and carbides (e.g., silicon carbide), such as silicon nitride; the material of the first filling layer 132 may include oxides, such as silicon oxide; the material of the third filling layer 133 may include a sacrificial material, such as alumina, amorphous carbon, and polycrystalline silicon, such as polycrystalline silicon.
[0048] like Figures 12 to 13As shown, the second sacrificial structure 14 located within the first opening K1 is removed to reopen the first opening K1.
[0049] Next, proceed to step S102, as follows: Figures 14 to 15 As shown, a portion of the first semiconductor layer 111 is removed from the first opening K1 to form capacitor trenches T2 on both sides of the first opening K1 along the second direction.
[0050] In some embodiments, the inner wall of the capacitor tank T2 exposes a portion of the first dielectric layer 131 and a portion of the second dielectric layer 121. Specifically, the capacitor tank T2 exposes a portion of the second dielectric layer 121 on its third-direction sidewall and a portion of the first dielectric layer 131 on its surface in the first direction.
[0051] like Figures 16 to 17 As shown, in some embodiments, after forming the capacitor trench T2, the method may further include: removing a portion of the first dielectric layer 131 and a portion of the second dielectric layer 121 exposed by the capacitor trench T2 in the same step, to enlarge the dimensions of the capacitor trench T2 in the first direction and the third direction, and exposing a portion of the first filler layer 132 and a portion of the second filler layer 122, thereby increasing the first electrode layer 181 subsequently formed in the capacitor trench T2 (see...). Figures 30 to 31 The dimensions in the first and third directions increase the final capacitor structure 18 (see...). Figures 34 to 37 This increases the capacitance of the semiconductor structure and improves its reliability.
[0052] In some embodiments, the first opening K1 also exposes a portion of the second dielectric layer 121 on the third-direction sidewall. While removing the portion of the first dielectric layer 131 and the portion of the second dielectric layer 121 exposed by the capacitor trench T2, the portion of the second dielectric layer 121 exposed by the first opening K1 is also removed, thereby increasing the size of the first opening K1 in the third-direction.
[0053] Next, proceed to step S103, as follows: Figures 18 to 19 As shown, a first sacrificial structure 15 is filled in the capacitor groove T2 and the first opening K1.
[0054] In some embodiments, the first sacrificial structure 15 may have a single-layer or multi-layer structure. For example, the first sacrificial structure 15 may include a third dielectric layer (not shown) and a polysilicon layer (not shown). The material of the third dielectric layer may be silicon carbide or silicon oxynitride, which has an etching selectivity ratio with the second dielectric layer 121. The third dielectric layer is used to protect the polysilicon layer when the second isolation layer 12 is removed. The third dielectric layer may cover the inner surface of the capacitor trench T2 and the first opening K1. The polysilicon layer may cover the third dielectric layer and fill the remaining space of the capacitor trench T2 and the first opening K1.
[0055] In some embodiments, after the capacitor trench T2 is formed and before the first sacrificial structure 15 is formed, a portion of the first dielectric layer 131 and a portion of the second dielectric layer 121 exposed by the capacitor trench T2 may be removed.
[0056] Next, proceed to step S104, as follows: Figures 20 to 23 As shown, the second isolation layer 12 is removed to open the isolation trench T1, and the first semiconductor layer 111 is etched from the isolation trench T1 to form a plurality of active structures 16 spaced apart along the third direction.
[0057] See you again Figures 20 to 21 In some embodiments, after removing the second isolation layer 12 to open the isolation trench T1 and before etching the first semiconductor layer 111 from the isolation trench T1, the method may further include: removing a portion of the first dielectric layer 131 exposed by the isolation trench T1 to form a plurality of fourth gaps S4 around the isolation trench T1, the fourth gaps S4 exposing a portion of the first fill layer 132.
[0058] See you again Figures 22 to 23 In some embodiments, etching the first semiconductor layer 111 from the isolation trench T1 to form active structures 16 spaced apart along the third direction may include: removing a portion of the first semiconductor layer 111 from the isolation trench T1 to reduce the size of the first semiconductor layer 111 in the third direction and forming a plurality of second gaps S2 around the isolation trench T1, wherein the first semiconductor layer 111 is divided into a plurality of active structures 16 spaced apart along the third direction based on the second gaps S2.
[0059] In some embodiments, the spacing between adjacent isolation trenches T1 in the second direction is smaller than the spacing between adjacent isolation trenches T1 in the third direction. That is, the size of the portion of the first semiconductor layer 111 located between adjacent isolation trenches T1 in the second direction is smaller than the size of the portion of the first semiconductor layer 111 located between adjacent isolation trenches T1 in the third direction in the third direction. In the step of etching the first semiconductor layer 111 from the isolation trenches T1 to form the active structure 16, the portion of the first semiconductor layer 111 located between adjacent isolation trenches T1 in the second direction can be sufficiently removed while narrowing the first semiconductor layer 111 in the third direction, thereby breaking the first semiconductor layer 111 in the third direction and forming a plurality of active structures 16 that are separated from each other in the third direction.
[0060] In some embodiments, the remaining first semiconductor layer 111 located between the first opening K1 and the second opening K2 along the second direction serves as an active structure 16. A plurality of active structures 16 extend along the second direction and are arranged in an array along the first direction and the third direction.
[0061] In this embodiment of the present disclosure, before etching the first semiconductor layer 111 from the isolation trench T1 to form the active structure 16, the portion of the first semiconductor layer 111 located between adjacent isolation trenches T1 along the third direction has a dimension in the third direction that is larger than the dimension of the active structure 16 in the third direction. In this embodiment of the present disclosure, before forming the active structure 16, a portion of the first semiconductor layer 111 is removed to form a capacitor trench T2. The dimension of the capacitor trench T2 is related to the dimension of the first semiconductor layer 111. Compared with the related art, where a capacitor trench is formed by removing a portion of the active structure after forming the active structure, and the dimension of the capacitor trench is limited by the dimension of the active structure, this embodiment of the present disclosure can form a capacitor trench T2 with a larger dimension in the third direction. Thus, a first electrode layer 181 with a larger width in the third direction can be formed, thereby increasing the capacitance of the finally formed capacitor structure 18 and increasing the reliability of the semiconductor structure.
[0062] Meanwhile, the process of forming the capacitor groove T2 in this embodiment is relatively simple, without the need to further increase the length of the capacitor groove T2, and the resulting capacitor groove T2 has a more regular shape.
[0063] Next, proceed to step S105, as follows: Figures 24 to 25 This forms a third isolation layer 17 to at least fill the isolation groove T1.
[0064] See you again Figures 24 to 25 In some embodiments, the third isolation layer 17 also fills the second gap S2 and the fourth gap S4.
[0065] In some embodiments, the third isolation layer 17 may include a single-layer structure or a multi-layer structure, and the material of the third isolation layer 17 may include oxides or other low dielectric constant materials, such as silicon oxide.
[0066] Next, proceed to step S106, as follows: Figures 26 to 27 As shown, the first sacrificial structure 15 is removed to open the first opening K1 and the capacitor slot T2.
[0067] like Figures 26 to 27 As shown, in some embodiments, after the first sacrificial structure 15 is removed, the first opening K1 exposes a portion of the third isolation layer 17 on the sidewall in the third direction, and exposes a portion of the first filling layer 132 and a portion of the third isolation layer 17 on the sidewall in the second direction; the capacitor groove T2 exposes a portion of the third isolation layer 17 on the sidewall in the third and second directions, and exposes a portion of the first filling layer 132 on the surface in the first direction.
[0068] Next, proceed to step S107, as follows: Figures 30 to 31 as well as Figures 34 to 37As shown, a capacitor structure 18 is formed. The capacitor structure 18 includes a first electrode layer 181, which covers the inner wall of the capacitor groove T2 and is electrically connected to the active structure 16.
[0069] Specifically, forming the capacitor structure 18 may include: A first electrode layer 181 is formed, the first electrode layer 181 having a cup-shaped structure extending along the second direction and with its opening facing the first opening K1 (e.g., Figures 30 to 31 ); A capacitor dielectric layer 182 is formed, which at least covers the inner wall of the first electrode layer 181; a second electrode layer 183 is formed, which covers the capacitor dielectric layer 182; a capacitor filling layer 184 is formed, which covers the second electrode layer 183 and fills the space enclosed by the second electrode layer 183 (e.g., ...). Figures 34 to 37 (As shown).
[0070] like Figures 28 to 29 As shown, in some embodiments, after removing the first sacrificial structure 15 to open the first opening K1 and the capacitor trench T2, and before forming the capacitor structure 18, the method may further include: etching a portion of the first filling layer 132 and a portion of the third isolation layer 17 exposed by the capacitor trench T2 to round the inner wall of the capacitor trench T2 and expand the dimensions of the capacitor trench T2 in the first direction and the third direction. In this way, on the one hand, the dimensions of the first electrode layer 181 in the first direction and the third direction can be further increased, thereby further increasing the capacitance of the finally formed capacitor structure 18 and further increasing the reliability of the semiconductor structure. On the other hand, the capacitor trench T2 has rounded inner corners, which can improve the deposition quality of the first electrode layer 181 when depositing the first electrode layer 181, reduce or avoid the formation of holes in the first electrode layer 181, and after forming the capacitor structure 18, compared with sharp inner corners, rounded inner corners can avoid or alleviate electric field concentration and leakage caused by excessive local electric field strength, thereby reducing or avoiding adverse effects on the reliability and lifespan of the capacitor structure 18.
[0071] In some embodiments, the inner wall of the capacitor trench T2 can be rounded by a wet etching process. While rounding the inner wall of the capacitor trench T2, the portion of the first filling layer 132 exposed by the first opening K1 and the portion of the third isolation layer 17 can be simultaneously etched to round the first opening K1.
[0072] In some embodiments, the ratio of the dimension of the first electrode layer 181 in the third direction to the dimension of the first electrode layer 181 in the first direction is greater than 1.5, such as 1.8, 2, 2.2, 2.5, etc., and the ratio of the dimension of the first electrode layer 181 in the third direction to the dimension of the active structure 16 in the third direction is greater than 2, such as 2.2, 2.5, 3, etc.
[0073] Thus, by pre-forming the capacitor groove T2 before forming the active structure 16, a capacitor groove T2 with a larger size and a first electrode layer 181 in a third direction can be formed, thereby increasing the capacitance of the capacitor structure 18.
[0074] In some embodiments, before forming the first electrode layer 181, a contact portion (not shown) electrically connected to the active structure 16 can be formed by an epitaxial growth process and a metallization process. The first electrode layer 181 can be electrically connected to the active structure 16 through the contact portion. Alternatively, the contact portion can be formed by directly performing a metallization process on the end of the active structure 16 near the capacitor trench T2. The material of the contact portion can be a metal silicide, such as one or more of molybdenum silicide, titanium silicide, cobalt silicide, and nickel silicide, to reduce the contact resistance between the active structure 16, the contact portion, and the first electrode layer 181.
[0075] like Figures 32 to 33 As shown, in some embodiments, after forming the first electrode layer 181 and before forming the capacitor dielectric layer 182, the method may further include: removing a portion of the first isolation layer 13 (e.g., the first filler layer 132) and a portion of the third isolation layer 17 covering the outer sidewall of the first electrode layer 181 to form a third gap S3 surrounding a portion of the first electrode layer 181, the third gap S3 exposing a portion of the outer sidewall of the first electrode layer 181, and the capacitor dielectric layer 182 also covering the exposed outer sidewall of the first electrode layer 181.
[0076] In some embodiments, the third gap S3 may surround the outer wall of the first electrode layer 181 near the end of the first opening K1. The portion of the first electrode layer 181 not surrounded by the third gap S3 is covered by the first filling layer 132 and the third isolation layer 17, which support the first electrode layer 181. A portion of the capacitor dielectric layer 182 and a portion of the second electrode layer 183 are located within the third gap S3 and cover the outer wall of the first electrode layer 181 exposed by the third gap S3.
[0077] Thus, by etching back a portion of the first isolation layer 13 and a portion of the third isolation layer 17, the surface area of the first electrode layer 181 exposed is increased, thereby increasing the surface area of the first electrode layer 181 covered by the capacitor dielectric layer 182 and the second electrode layer 183, which in turn increases the area of the effective electrode layer in the capacitor structure 18 and further improves the capacitance of the capacitor structure 18.
[0078] In some embodiments, in the third direction, adjacent capacitor structures 18 may be separated by a third isolation layer 17. In the first direction, multiple first electrode layers 181 of multiple capacitor structures 18 formed based on a first opening K1 are spaced apart from each other. The capacitor dielectric layer 182, second electrode layer 183 and capacitor filling layer 184 of multiple capacitor structures 18 formed based on a first opening K1 may be connected to each other respectively. The capacitor dielectric layer 182 also covers the inner surface of the third gap S3 and the first opening K1. The capacitor filling layer 184 covers the second electrode layer 183 and fills the remaining space of the first opening K1, capacitor groove T2 and third gap S3 that is not occupied by the first electrode layer 181, capacitor dielectric layer 182 and second electrode layer 183.
[0079] In some embodiments, the material of the first electrode layer 181 includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy, such as titanium nitride (TiN).
[0080] In some embodiments, the material of the capacitor dielectric layer 182 may include a high dielectric constant material, such as, but not limited to, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), Hafnium silicon oxide (HfSi) x O y Hafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y At least one or a combination thereof, such as praseodymium oxide (Pr2O3) and / or praseodymium oxide (Pr2O3).
[0081] In some embodiments, the material of the second electrode layer 183 may include one or more of the following: tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, conductive doped germanium-silicon-carbon, or silicon-germanium.
[0082] In some embodiments, the material of the capacitor filling layer 184 may include one or more of conductive doped germanium silicon carbon or silicon germanium.
[0083] This disclosure also provides a semiconductor structure. For example... Figures 34 to 37 As shown, the semiconductor structure includes: a substrate 10, and a plurality of active structures 16 located on the substrate 10, the plurality of active structures 16 extending along a second direction and arranged in an array along a first direction and a third direction; the first direction is perpendicular to the surface of the substrate 10, the second direction intersects the third direction and is parallel to the surface of the substrate 10; a capacitor structure 18 located on one side of the active structures 16 along the second direction, the capacitor structure 18 including a first electrode layer 181 electrically connected to the active structures 16; wherein, the ratio of the dimension of the first electrode layer 181 in the third direction to the dimension of the first electrode layer 181 in the first direction is greater than 1.5.
[0084] The material of substrate 10 has been described previously and will not be repeated here.
[0085] In some embodiments, the first electrode layer 181 may be a cup-shaped structure extending in a second direction and having an opening opposite to the active structure 16 electrically connected to it.
[0086] In some embodiments, the semiconductor structure may further include: a capacitor dielectric layer 182, which at least covers the inner wall of the first electrode layer 181; a second electrode layer 183, which covers the capacitor dielectric layer 182; and a capacitor filling layer 184, which covers the second electrode layer 183 and fills the space enclosed by the second electrode layer 183.
[0087] In some embodiments, a plurality of first electrode layers 181 and a plurality of capacitor structures 18 may be arranged in an array along a first direction and a third direction. In the first direction, adjacent active structures 16 may be separated by a first isolation layer 13. In the third direction, adjacent active structures 16 and adjacent capacitor structures 18 may be separated by a third isolation layer 17.
[0088] The materials of the first isolation layer 13 and the third isolation layer 17 have been described above and will not be repeated here.
[0089] In some embodiments, the ratio of the dimension of the first electrode layer 181 in the third direction to the dimension of the first electrode layer 181 in the first direction can be in the range of 1.5-3, for example, 1.8, 2, 2.2, 2.5, 2.8, etc. In some embodiments, the ratio of the dimension of the first electrode layer 181 in the third direction to the dimension of the active structure 16 in the third direction can be greater than 2, for example, 2.2, 2.5, 3, etc.
[0090] Thus, the first electrode layer 181 has a larger dimension in the third direction, thereby increasing the capacitance of the capacitor structure 18 and increasing the reliability of the semiconductor structure.
[0091] In some embodiments, a portion of the capacitor dielectric layer 182 also surrounds a portion of the first electrode layer 181 and covers a portion of the outer sidewall of the first electrode layer 181. In some embodiments, a portion of the capacitor dielectric layer 182 and a portion of the second electrode layer 183 may surround the outer sidewall of the end of the first electrode layer 181 opposite to the end of the active structure 16 electrically connected thereto.
[0092] This increases the surface area of the first electrode layer 181 covered by the capacitor dielectric layer 182 and the second electrode layer 183, thereby increasing the area of the effective electrode layer in the capacitor structure 18 and further improving the capacitance of the capacitor structure 18.
[0093] In some embodiments, the capacitor dielectric layer 182, the second electrode layer 183, and the capacitor filling layer 184 of the plurality of capacitor structures 18 arranged along the first direction can be connected to each other respectively, and the capacitor dielectric layer 182 can also cover the first isolation layer 13 and the third isolation layer 17 on the sidewalls facing the capacitor structure.
[0094] The materials of the first electrode layer 181, the capacitor dielectric layer 182, the second electrode layer 183, and the capacitor filling layer 184 are as described above and will not be repeated here.
[0095] This disclosure also provides an electronic device. For example... Figure 38 As shown, the electronic device 30 provided in this embodiment includes: a processing device 31 and a storage device 32 electrically connected to the processing device 31. The storage device 32 includes a semiconductor structure as provided in any of the above embodiments, or a semiconductor structure formed by the manufacturing method provided in any of the above embodiments.
[0096] In some embodiments, the processing device 31 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc.; the storage device 32 may be configured to store data to be processed by the processing device 31 and / or data processed by the processing device 31.
[0097] In some embodiments, the electronic device 30 may include, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.
[0098] The technical features described in the above embodiments can be arbitrarily combined without conflict. Those skilled in the art can change the order of the above-described forming method steps without departing from the protection scope of this disclosure. In the embodiments of this disclosure, some steps can be executed simultaneously or sequentially without conflict.
[0099] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: An initial structure is provided, the initial structure comprising: a substrate; a stacked structure on the substrate, the stacked structure comprising a first semiconductor layer and a first isolation layer alternately stacked along a first direction; isolation trenches arranged in an array within the stacked structure along a second direction and a third direction; a second isolation layer filling the isolation trenches; and a first opening located within the stacked structure and between adjacent isolation trenches along the third direction; the first direction is perpendicular to the surface of the substrate, and the second direction intersects the third direction and is parallel to the surface of the substrate. A portion of the first semiconductor layer is removed from the first opening to form capacitor trenches on both sides of the first opening along the second direction; A first sacrificial structure is filled into the capacitor groove and the first opening; The second isolation layer is removed to open the isolation trench, and the first semiconductor layer is etched from the isolation trench to form a plurality of active structures spaced apart along the third direction; A third isolation layer is formed to at least fill the isolation trench; Remove the first sacrificial structure to open the first opening and the capacitor slot; A capacitor structure is formed, the capacitor structure including a first electrode layer, the first electrode layer covering the inner wall of the capacitor groove and electrically connected to the active structure.
2. The manufacturing method according to claim 1, characterized in that, The provision of the initial structure includes: A substrate is provided, and an initial stacked structure is formed on the substrate, the initial stacked structure comprising a first semiconductor layer and a second semiconductor layer alternately stacked along the first direction; A plurality of isolation grooves are formed within the initial stacked structure, and a second isolation layer is formed within the isolation grooves; A plurality of the first openings are formed within the initial stacked structure, and at least the second semiconductor layer is removed from the first openings to form a first gap between adjacent first semiconductor layers; The first isolation layer is formed within the first gap, and the second sacrificial structure is formed within the first opening; Remove the second sacrificial structure to reopen the first opening.
3. The manufacturing method according to claim 2, characterized in that, Forming the first isolation layer within the first gap includes: A first dielectric layer and a first fill layer are formed, wherein the first dielectric layer at least covers the surface of the first semiconductor layer exposed by the first gap, and the first fill layer at least covers the first dielectric layer and fills the first gap; Forming a second isolation layer within the isolation groove includes: A second dielectric layer and a second filling layer are formed, the second dielectric layer covering the inner wall of the isolation trench, and the second filling layer covering the second dielectric layer and filling the isolation trench.
4. The manufacturing method according to claim 3, characterized in that, After forming the capacitor trench and before forming the first sacrificial structure, the inner wall of the capacitor trench exposes a portion of the first dielectric layer and a portion of the second dielectric layer. The method further includes: In the same step, a portion of the first dielectric layer and a portion of the second dielectric layer exposed by the capacitor trench are removed to enlarge the dimensions of the capacitor trench in the first direction and the third direction, and to expose a portion of the first filler layer and a portion of the second filler layer.
5. The manufacturing method according to claim 1, characterized in that, Etching the first semiconductor layer from the isolation trench to form an active structure spaced apart along the third direction includes: A portion of the first semiconductor layer is removed from the isolation trench to reduce the size of the first semiconductor layer in the third direction and form a plurality of second gaps around the isolation trench. The first semiconductor layer is divided into a plurality of active structures spaced apart along the third direction based on the second gaps, and the third isolation layer also fills the second gaps.
6. The manufacturing method according to claim 4, characterized in that, After removing the first sacrificial structure to open the first opening and the capacitor slot, and before forming the capacitor structure, the method further includes: The portion of the first filling layer and a portion of the third isolation layer exposed by the capacitor trench are etched to round the inner wall of the capacitor trench and increase the size of the capacitor trench in the first direction and the third direction.
7. The manufacturing method according to claim 1, characterized in that, Forming the capacitor structure includes: The first electrode layer is formed, and the first electrode layer has a cup-shaped structure extending along the second direction and with the opening facing the first opening; A capacitor dielectric layer is formed, wherein the capacitor dielectric layer at least covers the inner wall of the first electrode layer; A second electrode layer is formed, which covers the capacitor dielectric layer; A capacitor filling layer is formed, which covers the second electrode layer and fills the space enclosed by the second electrode layer.
8. The manufacturing method according to claim 7, characterized in that, After forming the first electrode layer and before forming the capacitor dielectric layer, the method further includes: A portion of the first insulating layer and a portion of the third insulating layer covering the outer wall of the first electrode layer are removed to form a third gap surrounding a portion of the first electrode layer, the third gap exposing a portion of the outer wall of the first electrode layer, the capacitor dielectric layer also covering the exposed outer wall of the first electrode layer.
9. A semiconductor structure, characterized in that, include: A substrate, and a plurality of active structures located on the substrate, the plurality of active structures extending along a second direction and arranged in an array along a first direction and a third direction; the first direction is perpendicular to the surface of the substrate, the second direction intersects the third direction and is parallel to the surface of the substrate; A capacitor structure is located on one side of the active structure along the second direction, the capacitor structure including a first electrode layer electrically connected to the active structure; wherein the ratio of the dimension of the first electrode layer in the third direction to the dimension of the first electrode layer in the first direction is greater than 1.
5.
10. The semiconductor structure according to claim 9, characterized in that, The ratio of the dimension of the first electrode layer in the third direction to the dimension of the active structure in the third direction is greater than 2.
11. The semiconductor structure according to claim 9, characterized in that, The first electrode layer has a cup-shaped structure that extends along the second direction and has an opening away from the active structure that is electrically connected to it. The semiconductor structure also includes: A capacitor dielectric layer that at least covers the inner wall of the first electrode layer; The second electrode layer covers the capacitor dielectric layer; A capacitor filling layer covers the second electrode layer and fills the space enclosed by the second electrode layer.
12. The semiconductor structure according to claim 11, characterized in that, The capacitor dielectric layer also surrounds a portion of the first electrode layer and covers a portion of the outer sidewall of the first electrode layer.
13. An electronic device, characterized in that, include: A processing device, and a memory device electrically connected to the processing device, the memory device comprising a semiconductor structure formed by the manufacturing method of any one of claims 1-8, or a semiconductor structure as described in any one of claims 9-12.