Method for manufacturing semiconductor device, semiconductor device, and memory device

Abstract

The application discloses a semiconductor device manufacturing method and a semiconductor device and a storage device. The method comprises the following steps: forming a shallow trench isolation structure in a substrate, wherein the shallow trench isolation structure has a protruding part protruding from the surface of the substrate, and a first groove is formed between the protruding parts of adjacent shallow trench isolation structures; forming a floating gate in the first groove, and performing first etching on part of the protruding part of the shallow trench isolation structure, so that a second groove is formed between adjacent floating gates; performing a width-reducing treatment on the floating gate; performing second etching on the residual part of the protruding part of the shallow trench isolation structure, so as to widen the second groove; and forming a control gate, wherein part of the control gate is filled in the second groove. In this way, the gap generated in the filling process of the control gate is reduced, and the yield of the manufactured semiconductor device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to methods for manufacturing semiconductor devices and semiconductor devices and memory devices. Background Technology

[0002] As semiconductor technology advances, devices are becoming smaller and smaller, making them increasingly difficult to manufacture.

[0003] In semiconductor devices based on floating gate structures, the control gate needs to be completely filled in the gaps between the floating gates. However, during the manufacturing process of semiconductor devices, gaps often occur in the filling between the floating gates, leading to device reliability issues. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a method for manufacturing semiconductor devices and semiconductor devices and memory devices that can reduce voids generated during the filling process of control gates and improve the yield of the manufactured semiconductor devices.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a method for manufacturing a semiconductor device, comprising: forming a shallow trench isolation structure in a substrate, wherein the shallow trench isolation structure has a protrusion protruding from the surface of the substrate, and a first trench is formed between the protrusions of adjacent shallow trench isolation structures; forming a floating gate in the first trench, and performing a first etching on a portion of the protrusion of the shallow trench isolation structure, and forming a second trench between adjacent floating gates; performing a widening treatment on the floating gate; performing a second etching on the remaining portion of the protrusion of the shallow trench isolation structure to widen the second trench; and forming a control gate, wherein a portion of the control gate fills the second trench.

[0006] Before forming the control gate, the process includes etching a dielectric layer onto the floating gate.

[0007] Prior to forming the control gate, the process includes growing a dielectric layer on the floating gate.

[0008] The dielectric layer includes a first oxide layer, a first nitride layer, and a second oxide layer. The dielectric layer is grown on the floating gate, including: growing a first oxide layer on the floating gate; growing a first nitride layer on the first oxide layer; and growing a second oxide layer on the first nitride layer.

[0009] In this process, a portion of the dielectric layer is disposed on the sidewall of the floating gate, forming the sidewall of the second trench.

[0010] The process of forming a floating gate in the first trench includes: forming a polysilicon layer in the first trench; etching the polysilicon layer to form a floating gate, wherein the upper surface of the floating gate is higher than or equal to the upper surface of the shallow trench isolation structure.

[0011] The sidewall of the second groove is formed by the opposing sidewalls between adjacent floating grids; each floating grid has a first sidewall and a second sidewall, the first sidewall is connected to the bottom of the second groove, and the second sidewall is connected to the first sidewall; the angle between the first sidewall and the bottom of the second groove is less than or equal to 90 degrees, and the angle between the second sidewall and the bottom of the second groove is greater than 90 degrees.

[0012] The cross-sectional area of ​​the control gate located at the bottom of the second trench is smaller than that of the control gate located at the opening of the second trench.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a semiconductor device, which is manufactured by the manufacturing method provided by the above-mentioned technical solution.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a storage device, which includes a semiconductor device, wherein the semiconductor device is the semiconductor device as described above, or a semiconductor device manufactured by the manufacturing method described above.

[0015] The beneficial effects of this application are as follows: Unlike the prior art, the semiconductor device manufacturing method and semiconductor device and memory device provided in this application, in the process of preparing the semiconductor device, after the floating gate is made and before the control gate is filled, only part of the protrusion of the shallow trench isolation structure is etched to expose part of the floating gate. Then the floating gate is widened to enlarge the entire opening of the second trench. After etching the protrusion of the shallow trench isolation structure, the gap depth of the second trench is reduced and the aspect ratio is reduced, making it easier to fill the control gate. This reduces the gaps generated by the control gate during the filling process and improves the yield of the manufactured semiconductor device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0017] Figure 1 This is a schematic flowchart of an embodiment of the method for manufacturing a semiconductor device provided in this application;

[0018] Figures 2-10 yes Figure 1 A schematic diagram of the process structure corresponding to the semiconductor memory structure fabrication method;

[0019] Figure 11 yes Figure 9 A magnified view of the area corresponding to the second groove C in the middle;

[0020] Figure 12 This is a schematic flowchart of another embodiment of the method for manufacturing a semiconductor device provided in this application;

[0021] Figures 13 to 14 This is a schematic diagram of another process structure corresponding to the semiconductor device fabrication method provided in this application;

[0022] Figure 15 This is a circuit diagram of a semiconductor device. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0024] It is worth noting that the semiconductor interlayer structure described in this application uses the orientation terms "upper," "lower," and "side," which is based on the scenario where the deposition plane of the semiconductor structure is located on a horizontal plane. The corresponding "height" and "depth" are descriptions based on the vertical direction, and the corresponding "width" is a description based on the horizontal direction. When the overall position of the semiconductor structure changes (such as rotation), the corresponding orientation description changes, but if the structural characteristics are the same as those in this application, it should also be included in the scope of protection of this application.

[0025] As semiconductor technology advances, devices are becoming smaller and smaller, making them increasingly difficult to manufacture.

[0026] In semiconductor devices based on floating gate structures, the control gate needs to be completely filled in the gaps between the floating gates. However, during the manufacturing process of semiconductor devices, gaps often occur in the filling between the floating gates, leading to device reliability issues.

[0027] Based on this, this application proposes that during the fabrication of semiconductor devices, after the floating gate is fabricated and before the control gate is filled, only a portion of the protrusions of the shallow trench isolation structure is etched to expose part of the floating gate. Then, the floating gate is widened to enlarge the entire opening of the second trench. After etching the protrusions of the shallow trench isolation structure again, the gap depth and aspect ratio of the second trench are reduced, making it easier to fill the control gate. This reduces the voids generated during the filling process of the control gate and improves the yield of the fabricated semiconductor devices.

[0028] See Figure 1 , Figure 1 This is a schematic flowchart of an embodiment of a method for fabricating a semiconductor device provided in this application. The method includes:

[0029] Step 11: Form a shallow trench isolation structure in the substrate.

[0030] The substrate is typically a semiconductor material, such as silicon, germanium, silicon germanide, or group III-V compound substrates. Understandably, the substrate is usually a flat material, and its area is determined based on the area of ​​the memory array to be fabricated. A memory array fabricated from a single substrate can be diced to form multiple sub-memory arrays, and each sub-memory array can be further processed to form a memory chip.

[0031] An oxide layer 200 and a silicon nitride layer 300 are sequentially formed on the substrate 100, such as Figure 2 As shown.

[0032] The oxide layer 200 is generally an oxide of silicon, such as silicon oxide.

[0033] Forming an oxide layer 200 or a silicon nitride layer 300 on a substrate 100 can generally be achieved using either Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD). Physical Vapor Deposition (PVD) refers to a technique that uses physical methods under vacuum conditions to vaporize a material source (solid or liquid) into gaseous atoms or molecules, or partially ionize them, and then deposits a thin film with specific functions onto the substrate surface through a low-pressure gas (or plasma) process. PVD deposition techniques are mainly divided into three categories: vacuum evaporation deposition, vacuum sputtering deposition, and vacuum ion deposition. Chemical Vapor Deposition (CVD) refers to a method of synthesizing coatings or nanomaterials by reacting chemical gases or vapors on a substrate surface. It is the most widely used technique in the semiconductor industry for depositing a wide range of materials, including a broad range of insulating materials, most metallic materials, and metal alloys.

[0034] Taking CVD as an example, two or more gaseous raw materials are introduced into a reaction chamber, where they react chemically to form a new material, which is then deposited onto the substrate surface. Silicon nitride (Si3N4) deposition is a good example; it is formed by the reaction of silane and nitrogen.

[0035] In one embodiment, the oxide layer has a deposition thickness of 50 Å-200 Å, and the nitride layer has a deposition thickness of 500 Å-2000 Å.

[0036] Using a hard mask layer as a mask, multiple shallow trenches A are fabricated in the substrate 100, and a silicon nitride layer 300 forms a silicon nitride structure 30a, as shown below. Figure 3 As shown.

[0037] Etching is a common process used to create trenches in materials. It is a crucial step in semiconductor manufacturing, microelectronics IC (integrated circuit) manufacturing, and micro / nano manufacturing. Etching first involves photolithography to expose the photoresist, followed by etching to remove the unwanted material. Etching is a process that selectively removes unwanted material from the surface of a silicon wafer using chemical or physical methods. Its fundamental goal is to accurately replicate the mask pattern on the coated silicon wafer.

[0038] Shallow trench isolation structures 400 are formed within multiple shallow trenches A, and then silicon nitride structures 30a are stripped to form the first trench B, as shown below. Figure 4 As shown, the shallow trench isolation structure 400 has a protrusion protruding from the surface of the substrate 100, and a first trench B is formed between the protrusions of adjacent shallow trench isolation structures 400.

[0039] Step 12: Form a floating gate in the first trench and perform a first etching on the protruding part of the shallow trench isolation structure to form a second trench between adjacent floating gates.

[0040] A floating gate 500 is formed in the first trench B, such as Figure 5 As shown.

[0041] In some embodiments, a polysilicon layer may be formed in the first trench B; the polysilicon layer is etched to form a floating gate 500. The upper surface of the floating gate 500 is higher than or equal to the upper surface of the shallow trench isolation structure 400.

[0042] In other embodiments, a floating gate 500 is formed in the first trench B, such as Figure 6 As shown.

[0043] In some embodiments, a polysilicon layer may be formed in the first trench B; the polysilicon layer is etched to form a floating gate 500. The upper surface of the floating gate 500 is higher than the upper surface of the shallow trench isolation structure 400.

[0044] In some embodiments, there are many ways to form a polysilicon layer in the first trench B, such as using a mask to form it using a deposition process, or using a combination of deposition, CMP, and blanket etch processes.

[0045] Polycrystalline silicon is a form of elemental silicon. When molten elemental silicon solidifies under supercooled conditions, silicon atoms arrange themselves into many crystal nuclei in the form of a diamond lattice. If these crystal nuclei grow into grains with different crystal orientations, these grains combine to crystallize into polycrystalline silicon.

[0046] In other embodiments, polysilicon is deposited in the first trench B using a mask; at this time, the upper surface of the polysilicon is not lower than the upper surface of the shallow trench isolation structure 400, but the depth is not limited; then the polysilicon layer is etched to form a floating gate 500; at this time, the upper surface of the polysilicon is higher than or equal to the upper surface of the shallow trench isolation structure 400; this step can be implemented by photolithography.

[0047] like Figure 7 As shown, after the floating gate 500 is formed in the first trench B, a portion of the protruding part of the shallow trench isolation structure 400 is etched first, and a second trench C is formed between adjacent floating gates 500. That is, a portion of the floating gate 500 is exposed.

[0048] Step 13: Reduce the width of the floating gate.

[0049] like Figure 8 As shown, a second groove C is formed between adjacent floating gates 500, that is, after exposing the floating gates 500, the floating gates 500 are widened. Because the floating gates 500 have a three-dimensional structure, the sides of the floating gates 500 can be etched to make the floating gates trapezoidal. That is, after the floating gates 500 are widened, the distance between adjacent floating gates increases. In other words, the opening of the second groove C increases.

[0050] Step 14: Perform a second etching on the remaining portion of the protrusion of the shallow trench isolation structure to widen the second trench.

[0051] like Figure 9 As shown, after widening the floating gate 500, the remaining portion of the protrusion of the shallow trench isolation structure 400 is further etched to widen the second trench C. At the same time, the second trench C is also deepened.

[0052] During the etching process, not only will the second groove C be deepened, but it may also cause some damage to the side of the floating gate 500, thus widening the second groove C and making the gap between the floating gates 500 more open.

[0053] In some embodiments, a second etching is performed on the residual portion of the protrusion of the shallow trench isolation structure so that the upper surface of the etched shallow trench isolation structure 400 is equal to or lower than the upper surface of the oxide layer 200.

[0054] In some embodiments, such as Figure 11As shown, the sidewalls of the second groove C are formed by the opposing sidewalls between adjacent floating grids 500. Each floating grid's sidewall includes a first sidewall 50b and a second sidewall 50a. The first sidewall 50b is connected to the bottom of the second groove C, and the second sidewall 50a is connected to the first sidewall 50b. The angle α between the first sidewall 50b and the bottom of the second groove C is less than or equal to 90 degrees, and the angle β between the second sidewall 50a and the bottom of the second groove C is greater than 90 degrees. That is, the opening of the second groove C gradually increases from the second sidewall 50a.

[0055] Step 15: Form a control gate, wherein a portion of the control gate is filled in the second trench.

[0056] like Figure 10 As shown, a control gate 600 is formed. A portion of the control gate 600 fills the second trench C. At this time, the cross-sectional area of ​​the control gate 600 located at the bottom of the second trench C is smaller than the cross-sectional area of ​​the control gate 600 located at the opening of the second trench C.

[0057] In the process of fabricating semiconductor devices, after the floating gate 500 is fabricated and before the control gate 600 is filled, only a portion of the protrusions of the shallow trench isolation structure 400 is etched to expose part of the floating gate 500. Then, the floating gate 500 is widened to enlarge the entire opening of the second trench C. After etching the protrusions of the shallow trench isolation structure 400 again, the gap depth and aspect ratio of the second trench C are reduced, making it easier to fill the control gate 600. This reduces the gaps generated by the control gate 600 during the filling process and improves the yield of the fabricated semiconductor devices.

[0058] See Figure 12 , Figure 12 This is a schematic flowchart of another embodiment of the semiconductor device fabrication method provided in this application, the method including:

[0059] Step 21: Form a shallow trench isolation structure in the substrate.

[0060] Step 22: Form a floating gate in the first trench and perform a first etching on the protruding part of the shallow trench isolation structure, forming a second trench between adjacent floating gates.

[0061] Step 23: Reduce the width of the floating gate.

[0062] Step 24: Perform a second etching on the remaining portion of the protrusion of the shallow trench isolation structure to widen the second trench.

[0063] The production diagrams for steps 21 to 24 can be referenced. Figures 2 to 9 This will not be elaborated upon here.

[0064] Step 25: Form a dielectric layer on the floating gate.

[0065] like Figure 12 As shown, a dielectric layer 700 is formed on the floating gate 500.

[0066] The dielectric layer 700 is generally an oxide layer, a nitride layer, or a superposition of the two, such as a mixed layer formed by oxides and nitrides, and then the oxide layer and the mixed layer are superimposed.

[0067] In some embodiments, a dielectric layer 700 may be formed on the floating gate 500 by etching. For example, a first oxide layer may be formed on the floating gate 500; a first nitride layer may be formed on the first oxide layer; and a second oxide layer may be formed on the first nitride layer.

[0068] In some embodiments, a dielectric layer 700 may be grown on the floating gate 500. Exemplarily, a first oxide layer is grown on the floating gate 500; a first nitride layer is grown on the first oxide layer; and a second oxide layer is grown on the first nitride layer. That is, the dielectric layer 700 includes a first oxide layer, a first nitride layer, and a second oxide layer. The first oxide layer, the first nitride layer, and the second oxide layer are stacked on the floating gate 500. The first oxide layer is disposed in close contact with the floating gate 500.

[0069] After forming a dielectric layer 700 on the floating gate 500, a portion of the dielectric layer 700 is disposed on the sidewall of the floating gate, forming the sidewall of the second trench C.

[0070] In some embodiments, the sidewalls of the second trench C are formed by dielectric layers 700 on opposite sidewalls between adjacent floating gates 500. The shape of the dielectric layers 700 is almost identical to the sidewalls of the floating gates 500. A portion of the dielectric layers 700 is disposed in contact with the sidewalls of the floating gates 500.

[0071] Step 26: Form a control gate, wherein a portion of the control gate is filled in the second trench.

[0072] like Figure 14 As shown, a control gate 600 is formed. A portion of the control gate 600 fills the second trench C. At this time, the cross-sectional area of ​​the control gate 600 at the bottom of the second trench C is smaller than the cross-sectional area of ​​the control gate 600 at the opening of the second trench C.

[0073] In this embodiment, during the fabrication of the semiconductor device, after the floating gate 500 is fabricated and before the control gate 600 is filled, only a portion of the protrusions of the shallow trench isolation structure 400 is etched to expose part of the floating gate 500. Then, the floating gate 500 is widened to enlarge the entire opening of the second trench C. After etching the protrusions of the shallow trench isolation structure 400 again, the gap depth and aspect ratio of the second trench C are reduced, making it easier to fill the control gate 600. This reduces the gaps generated by the control gate 600 during the filling process and improves the yield of the fabricated semiconductor device.

[0074] Furthermore, with Figure 14 For example, let's explain the structure of a semiconductor device:

[0075] The semiconductor device includes a substrate 100, an oxide layer 200, a shallow trench isolation structure 400, a floating gate 500, a dielectric layer 700, and a control gate 600.

[0076] The oxide layer 200 is disposed on the substrate 100. The floating gate 500 is disposed on the oxide layer 200.

[0077] A dielectric layer 700 is formed on the surface (upper surface and sidewalls) of the floating gate 500. A control gate 600 is formed in the trenches between the floating gates 500 and on the dielectric layer 700.

[0078] The substrate 100 is generally a semiconductor material, such as silicon, germanium, or silicon germanide; the oxide layer 200 is generally an oxide of silicon, such as silicon oxide; in the NOR FLASH-based memory structure, the oxide layer 200 is also called an electron tunneling oxide (ETOX); the floating gate 500 and the control gate 600 are generally polysilicon; the dielectric layer 700 is generally an oxide layer, a nitride layer, or a superposition of the two, such as a mixed layer formed by oxides and nitrides, and then the oxide layer and the mixed layer are stacked.

[0079] In some embodiments, the semiconductor device further includes a drain / source region (not shown). The drain / source region is typically a conductive region formed by particle implantation / doping in the substrate 100 and led out via connecting metal wires. It is understood that the materials described above are merely examples, and similar materials may be used in other embodiments, which will not be described in detail here.

[0080] The control gate 600 in the aforementioned semiconductor device is equivalent to the gate of a conventional transistor, but with the addition of a floating gate 500. The floating gate 500 has no electrical connection to the outside world; it is encased in an oxide layer 200 and a dielectric layer 700 and floats, hence the name "floating gate." The floating gate can capture and store electrons, and because there is no external circuit, the electrons will not be lost even after power is lost. The amount of electrons stored in the floating gate structure can change the on-state voltage of the field-effect transistor, i.e., Vth. Different Vth values ​​can represent different states, thus achieving information storage.

[0081] The following is combined Figure 15 , Figure 15 This is a circuit diagram of a semiconductor memory structure. The aforementioned semiconductor memory device corresponds to... Figure 15 The field-effect transistor 1000 in the middle, the gate of the transistor corresponds to Figure 14The control gate 600 in the transistor is connected to the word line WL (white line). The drain of the transistor corresponds to the drain of the drain-source region (not shown) of the semiconductor memory device and is connected to the bit line BL (bit line). The source of the transistor corresponds to the source of the drain-source region of the semiconductor memory device, and the source and the common source trace SL (not shown) in the semiconductor device form a storage capacitor.

[0082] The aforementioned semiconductor device can be considered a memory cell, each of which includes an access switch (i.e., a transistor) and a storage capacitor. The storage capacitor represents logical "1" and "0" by the amount of charge stored within it, or in other words, by the voltage difference across its terminals. The on and off states of the access switch determine whether reading and rewriting the information stored in the storage capacitor is permitted or prohibited.

[0083] Specifically, the word line WL determines whether the access switch is on or off, and the bit line BL is the only channel for external access to the storage capacitor. When the access switch is on, external access can read or write to the storage capacitor through the bit line BL.

[0084] In one embodiment, the common terminal of the storage capacitor is connected to the common source line (voltage Vref).

[0085] When the information stored in the storage capacitor is "1", the voltage at the other end of the storage capacitor is 2Vref. At this time, the stored charge is:

[0086] Q = +Vref*C.

[0087] When the information stored in the storage capacitor is "0", the voltage at the other end of the storage capacitor is 0. At this time, the stored charge is:

[0088] Q = -Vref*C.

[0089] In other embodiments, in forming Figure 14 After the semiconductor device is assembled, a protective layer and / or an insulating layer can be covered on the semiconductor memory device. Traces can be routed within the protective layer and / or insulating layer.

[0090] Furthermore, this application also provides a storage device, which includes a semiconductor device, which is a semiconductor device as described above, or a semiconductor device manufactured using the manufacturing method described above.

[0091] Alternatively, the storage device can be a storage device containing flash memory, such as NOR flash.

[0092] Specifically, the storage device may further include a main control chip and a storage chip. The storage chip includes a storage array and corresponding configuration circuits and wiring. The storage array is the semiconductor device provided in the above embodiments or a semiconductor device fabricated using the fabrication method provided in any of the above embodiments.

[0093] When the embodiments of this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0094] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A shallow trench isolation structure is formed in a substrate, wherein the shallow trench isolation structure has a protrusion protruding from the surface of the substrate, and a first trench is formed between the protrusions of adjacent shallow trench isolation structures. A floating gate is formed in the first trench, and a first etching is performed on a portion of the protrusion of the shallow trench isolation structure, and a second trench is formed between adjacent floating gates. The floating gate is widened. The remaining portion of the protrusion of the shallow trench isolation structure is etched a second time to widen the second trench; A control gate is formed, wherein a portion of the control gate is filled in the second trench.

2. The method according to claim 1, characterized in that, Before forming the control gate, the following are included: A dielectric layer is etched onto the floating gate.

3. The method according to claim 1, characterized in that, Before forming the control gate, the process includes growing the dielectric layer on the floating gate.

4. The method according to claim 3, characterized in that, The dielectric layer includes: a first oxide layer, a first nitride layer, and a second oxide layer. Growing the dielectric layer on the floating gate includes: The first oxide layer is grown on the floating gate; The first nitride layer is grown on the first oxide layer; The second oxide layer is grown on the first nitrided layer.

5. The method according to claim 3, characterized in that, A portion of the dielectric layer is disposed on the sidewall of the floating gate, forming the sidewall of the second trench.

6. The method according to claim 1, characterized in that, The process of forming a floating grid in the first trench includes: A polycrystalline silicon layer is formed in the first trench; The polysilicon layer is etched to form the floating gate, the upper surface of which is higher than or equal to the upper surface of the shallow trench isolation structure.

7. The method according to claim 1, characterized in that, The sidewall of the second groove is formed by the opposing sidewalls between adjacent floating grids; each floating grid sidewall includes a first sidewall and a second sidewall, the first sidewall is connected to the bottom of the second groove, and the second sidewall is connected to the first sidewall; the angle between the first sidewall and the bottom of the second groove is less than or equal to 90 degrees, and the angle between the second sidewall and the bottom of the second groove is greater than 90 degrees.

8. The method according to claim 1, characterized in that, The cross-sectional area of ​​the control gate located at the bottom of the second trench is smaller than the cross-sectional area of ​​the control gate located at the opening of the second trench.

9. A semiconductor device, characterized in that, The semiconductor device is manufactured using the manufacturing method described in any one of claims 1-8.

10. A storage device, characterized in that, The storage device includes a semiconductor device, which is the semiconductor device as described in claim 9, or a semiconductor device manufactured using the manufacturing method described in any one of claims 1-8.

Images