A spatial electric field modulation drain and a method of manufacturing the same

Abstract

The application discloses a kind of space electric field modulation drain, located in the drain region of three-dimensional surround gate power device;The drain includes annular ohmic contact drain metal, annular schottky contact drain metal, annular P-type oxide;Wherein, in the buffer layer of drain region, there is formed with ladder structure, from the side close to the surrounding columnar gate to the direction away from the surrounding columnar gate, the depth of step in ladder structure decreases in turn;Annular ohmic contact drain metal and annular P-type oxide are arranged on each step of ladder structure, annular P-type oxide is located at the side close to the surrounding columnar gate, and annular ohmic contact drain metal is located at the side away from the surrounding columnar gate;Annular schottky contact drain metal covers the entire drain region.The application creates a brand-new three-dimensional drain design through the depth fusion of material innovation and structural innovation, and fundamentally solves the strong electric field concentration and voltage endurance bottleneck caused by geometric structure in three-dimensional surround gate power device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a spatial electric field modulated drain and its fabrication method, used for drain structures of three-dimensional wide bandgap semiconductor power devices, and particularly a high-voltage drain suitable for three-dimensional all-around gate architecture that can achieve spatial electric field modulation and its fabrication method. Background Technology

[0002] Wide-bandgap semiconductor materials, due to their superior properties such as high breakdown electric field and high electron saturation drift velocity, have become the core for fabricating next-generation high-efficiency, high-power-density power devices. To further improve the power density and gate control capability of these devices, three-dimensional device structures, especially three-dimensional all-around gate structures, have become an important development direction. These structures achieve three-dimensional all-around control of the channel through the gate, effectively overcoming short-channel effects and providing a larger conduction current per unit area.

[0003] However, when applying three-dimensional all-around gate structures to high-voltage applications, a fundamental problem urgently needs to be solved: their three-dimensional geometry (such as cylinders or mesa) generates severe electric field concentration at structural corners such as the top of the cylinder and the edge of the gate in the off-state. This peak electric field intensity is much higher than that of traditional planar devices, becoming a major bottleneck limiting the overall breakdown voltage and long-term reliability of the device. Therefore, effectively modulating and suppressing the concentrated electric field in the three-dimensional structure is key to overcoming its breakdown voltage limitation.

[0004] Traditional drain termination technologies, such as field-plate or junction termination extensions based on planar devices, rely primarily on two-dimensional lateral or surface modulation of the electric field. These methods struggle to effectively penetrate and planarize the complex and intense electric field distribution within three-dimensional structures. This is particularly true for complex three-dimensional power devices with "ring-like stacked structures" (e.g., ring-like stacks consisting of buffer layers, channel layers, barrier layers, electrostatic shielding layers, and surrounding cylindrical gates), where the electric field distribution in the drain region is even more complex. Existing simple ohmic or Schottky contact drains are completely inadequate to address this three-dimensional electric field challenge. Directly applying traditional designs not only fails to alleviate electric field concentration but may also introduce new parasitic parameters, thereby impairing device performance.

[0005] Therefore, there is an urgent need in this field for an innovative drain design that is no longer a simple current-collecting electrode, but should have the ability to actively modulate the electric field distribution in three-dimensional space. This design needs to be compatible with the three-dimensional architecture of the device and be able to build a gradient electric field buffer layer in the drain region from both the material system and physical structure dimensions, thereby fundamentally solving the voltage withstand bottleneck of three-dimensional all-around gate power devices and releasing their potential for high-voltage applications. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a space electric field modulated drain and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a spatial electric field modulation drain, wherein the spatial electric field modulation drain is located in the drain region of a three-dimensional surrounding gate power device; the spatial electric field modulation drain comprises a ring-shaped ohmic contact drain metal, a ring-shaped Schottky contact drain metal, and a ring-shaped P-type oxide; wherein... A stepped structure is formed within the buffer layer of the drain region. The depth of the steps in the stepped structure decreases sequentially from the side closest to the surrounding cylindrical gate to the side away from the surrounding cylindrical gate. Each step of the stepped structure is provided with an annular ohmic contact drain metal and an annular P-type oxide. The annular ohmic contact drain metal and the annular P-type oxide do not contact each other. The annular P-type oxide is located on the side closest to the surrounding cylindrical gate, and the annular ohmic contact drain metal is located on the side away from the surrounding cylindrical gate structure. The annular Schottky contact drain metal covers the entire drain region.

[0007] In one embodiment of the present invention, the three-dimensional all-around gate power device includes a substrate and a first portion of a GaN buffer layer located on the substrate. A ring-shaped stacked structure is formed in the middle region of the first portion of the GaN buffer layer. The peripheral region of the ring-shaped stacked structure includes a second portion of the GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer stacked sequentially from bottom to top. The central region includes a second portion of the GaN buffer layer and a GaN channel layer stacked sequentially from bottom to top. A plurality of first vias penetrate the AlGaN barrier layer in the peripheral region to the upper surface of the first portion of the GaN buffer layer. Each first via is filled with an all-around cylindrical gate, and an electrostatic shielding layer is filled between the inner wall of each first via and the all-around cylindrical gate. Second vias penetrate the GaN channel layer in the central region to the upper surface of the first portion of the GaN buffer layer. The second vias are filled with a conductive dielectric layer, a source electrode is formed on the conductive dielectric layer, and side gates are formed on both sides of the first vias. An electrostatic shielding layer is formed on one side of each side gate. The stepped structure is formed within the first part of the GaN buffer layer, and the depth of the deepest step in the stepped structure does not exceed 75% of the thickness of the first part of the GaN buffer layer.

[0008] In one embodiment of the present invention, the width of each step in the stepped structure is 1μm to 2μm and the depth is 2.5nm to 20nm.

[0009] In one embodiment of the present invention, the thickness of the annular P-type oxide on each step in the stepped structure is 50 nm to 300 nm.

[0010] In one embodiment of the present invention, the spacing between the annular ohmic contact drain metal and the annular P-type oxide on each step of the stepped structure is 0.1 μm-0.5 μm.

[0011] In one embodiment of the present invention, the cyclic P-type oxide includes one of P-NiO, P-Cu2O, and P-Ga2O3.

[0012] In a second aspect, the present invention provides a method for fabricating a space electric field modulated drain, used to fabricate any of the space electric field modulated drains described in the first aspect, the corresponding fabrication method comprising: Fabrication of the intermediate structure of a three-dimensional all-around gate power device, excluding the source and drain; A stepped pattern is defined by photolithography on the surface of the buffer layer in the drain region of the intermediate structure, and the stepped pattern is used to etch a stepped structure in the buffer layer. A ring-shaped P-type oxide is formed on each step of the stepped structure; On each step of the stepped structure, an annular ohmic contact drain metal is formed; wherein the annular ohmic contact drain metal and the annular P-type oxide do not contact each other, the annular P-type oxide is located on the side closer to the surrounding cylindrical gate, and the annular ohmic contact drain metal is located on the side away from the surrounding cylindrical gate. A ring-shaped Schottky contact drain metal is formed covering the entire drain region.

[0013] In one embodiment of the present invention, a stepped pattern is photolithographically defined on the surface of the buffer layer in the drain region of the intermediate structure, and the stepped pattern is used to etch a stepped structure within the buffer layer, including: A stepped pattern is defined by photolithography on the surface of the buffer layer in the drain region of the intermediate structure, and the buffer layer is etched multiple times at different depths using the stepped pattern to form a stepped structure within the buffer layer; the width of each step in the stepped structure is 1μm~2μm and the depth is 2.5nm~20nm, and the depth of the deepest step in the stepped structure does not exceed 75% of the thickness of the buffer layer.

[0014] In one embodiment of the invention, a ring-shaped P-type oxide is formed on each step of the stepped structure, including: At a growth temperature of 200℃ to 400℃, a ring-shaped P-type oxide with a thickness of 50nm to 300nm is formed on each step of the stepped structure by radio frequency magnetron sputtering. The ring-shaped P-type oxide includes one of P-NiO, P-Cu2O, and P-Ga2O3.

[0015] In one embodiment of the present invention, an annular ohmic contact drain metal is formed on each step of the stepped structure, including: A ring-shaped ohmic contact drain metal with a thickness of 50 nm to 300 nm is formed on each step of the stepped structure; the spacing between the ring-shaped ohmic contact drain metal and the ring-shaped P-type oxide on each step of the stepped structure is 0.1 μm to 0.5 μm.

[0016] The beneficial effects of this invention are: The innovation of this invention lies in the deep integration of drain material innovation and structural innovation, creating a completely new drain design specifically for advanced power devices with three-dimensional all-around gate architectures, fundamentally solving the bottlenecks of traditional technologies. Specifically: This invention designs a stepped structure where the step depth exhibits a gradient distribution decreasing from the near-gate side to the far-gate side. By introducing a third-dimensional stepped structure, the electric field modulation is extended from the surface to the bulk, achieving true three-dimensional depletion. This specific design has profound physical implications: it precisely corresponds to the natural distribution of the electric field intensity in the drain region of a three-dimensional all-around gate power device in the off-state, which decays exponentially from the gate edge inwards. By deploying the deepest, most modulating step at the leading edge region where the electric field peak is highest, and extending the progressively decreasing modulation steps to the electric field decay region, this structure achieves precise spatial matching between protection strength and electric field distribution, thereby fundamentally improving the breakdown voltage and breaking through performance bottlenecks.

[0017] This invention integrates a ring-shaped P-type oxide drain metal and a ring-shaped ohmic contact drain metal on each step of a stepped structure. The ring-shaped P-type oxide forms a PN junction with the N-type GaN channel layer. Under reverse bias, the depletion region generated by the ring-shaped P-type oxide can achieve three-dimensional depletion of the longitudinal electric field from the surface to the bulk, with modulation capability far exceeding surface effects. The ring-shaped P-type oxide is precisely placed at the edge of each step closest to the gate to specifically suppress the local electric field peak caused by the superposition of the three-dimensional geometry and the global electric field. At the same time, the ring-shaped ohmic contact drain metal distributed on each step platform together construct a low-resistance longitudinal current collection network. This layout, in conjunction with the stepped structure, naturally widens the lateral cross-sectional area of ​​current transport, significantly reduces on-resistance and current congestion effects, thereby effectively dispersing current density, reducing on-resistance and thermal effects, and improving the stability and reliability of the device. The integration of the "longitudinal depletion" of the P-type region and the "longitudinal current conduction" of the ohmic region in three-dimensional space achieves synergistic optimization and discrete management of the electric field and current path.

[0018] The Schottky metal covering the drain region in this invention is a continuous Schottky layer. This layer transcends the function of a typical electrode and also acts as a global field plate. Its extended portion, through capacitive coupling, further optimizes the electric field distribution between the gate and drain in the lateral direction. More importantly, it synergizes with the PN junction depletion effect of the steps below, forming a composite enhancement mechanism of the junction field plate, thereby achieving three-dimensional modulation of the electric field in both the vertical and lateral dimensions. The stepped structure extending towards the gate allows for finer control of the high electric field region, suppressing peak electric fields at the gate edge, and flexibly adjusting parasitic capacitance to optimize switching speed.

[0019] The core advantage of this invention lies in its inherent ability to optimize the three-dimensional electric field distribution, enabling it to be effectively integrated into the drain of a three-dimensional surround gate device. This solves the unique challenges of electric field concentration and voltage withstand capability of such devices, and has significant application value and technological potential.

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0021] Figure 1 This is a schematic cross-sectional view of the space electric field modulation drain provided in an embodiment of the present invention; Figure 2 This is provided by the embodiments of the present invention. Figure 1 Corresponding top view structural diagram; Figure 3 This is a schematic flowchart of a method for fabricating a space electric field modulated drain according to an embodiment of the present invention; Figures 4(a) to 4(e) This is a schematic diagram of the fabrication process of the space electric field modulation drain provided in the embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0023] The core idea behind this invention is: can a more efficient depletion mechanism replace or enhance the traditional metal-Schottky junction? A toroidal P-type oxide and N-type gallium nitride form a PN junction, and its depletion region under reverse bias can extend from the surface into the semiconductor bulk, achieving vertical bulk depletion. Theoretically, its electric field modulation depth and efficiency will far exceed those of metal-semiconductor contacts limited to the surface. This concept aims to address the shortcomings of existing technologies, such as a single mechanism and weak ability to control the bulk electric field. However, simple planar toroidal P-type oxide designs (e.g., fabricating a single toroidal P-type oxide in the drain region) introduce new and more challenging problems: (1) Current blocking problem: As a wide bandgap semiconductor, the toroidal P-type oxide has a high resistivity. When a whole toroidal P-type oxide covers the current path, it will seriously hinder electron transport, resulting in a sharp increase in on-resistance, which goes against the original intention of reducing on-resistance.

[0024] (2) Electric field modulation mismatch: When the power device is off, the electric field decays exponentially from the gate edge to the drain, with the peak electric field concentrated near the gate. The planar toroidal P-type oxide structure cannot spatially match this non-uniform electric field distribution. Over-modulation of the low electric field region is a waste of resources, while under-modulation of the high electric field region may result in low efficiency.

[0025] (3) Interface and stress issues: The large-area ring-type oxide is in direct contact with the gallium nitride heterojunction, which will introduce significant interface states and lattice mismatch stress, which may degrade the performance of the two-dimensional electron gas channel and bring reliability risks.

[0026] The aforementioned contradictions prompted this invention to undertake fundamental structural innovation, aiming to decouple and synergistically optimize the functions of electric field modulation and current transport in three-dimensional space. The inspiration for the stepped structure stems from this: (1) Decoupling current and modulation: The platform of the step is used to arrange low-resistance ohmic contacts to provide a low-resistance path for the current in the vertical direction; while the sidewall of the step (especially the edge near the gate) becomes the best position for integrating the ring-shaped P-type oxide functional area, so that it can accurately perform longitudinal depletion modulation of the high electric field region without blocking the main current path.

[0027] (2) Achieving spatial matching between electric field strength and modulation capability: The stepped structure, especially the gradient design where the depth decreases from the near-gate side to the far-gate side, is the essence of achieving efficient modulation. It allows the toroidal P-type oxide with the strongest modulation capability (located in the deepest step) to be precisely deployed in the region with the strongest electric field, and then attenuated step by step. This perfectly matches the natural law of electric field distribution and achieves the optimal configuration of protection resources.

[0028] (3) Naturally expands the current path: The stepped structure itself expands the contact area of ​​the drain in the vertical direction, and the distributed ohmic contact points further transform the horizontal current into the vertical current, effectively dispersing the current density and fundamentally alleviating the current congestion.

[0029] Therefore, the introduction of the toroidal P-type oxide and the stepped structure design are indispensable and deeply integrated innovations of this invention. It is through this step-by-step in-depth thinking that this invention breaks through the limitations of a two-dimensional plane, forming the three-dimensional stepped spatial electric field modulation drain design of this invention. Specifically: Firstly, please see Figure 1This invention provides a spatial electric field modulation drain, which is located in the drain region of a three-dimensional surrounding gate power device; the spatial electric field modulation drain includes a ring-shaped ohmic contact drain metal, a ring-shaped Schottky contact drain metal, and a ring-shaped P-type oxide; wherein, A stepped structure is formed within the buffer layer of the drain region. The depth of the steps in the stepped structure decreases sequentially from the side closest to the surrounding cylindrical gate to the side away from the surrounding cylindrical gate. Each step of the stepped structure is provided with an annular ohmic contact drain metal and an annular P-type oxide. The annular ohmic contact drain metal and the annular P-type oxide do not contact each other. The annular P-type oxide is located on the side closest to the surrounding cylindrical gate, and the annular ohmic contact drain metal is located on the side away from the surrounding cylindrical gate structure. The annular Schottky contact drain metal covers the entire drain region.

[0030] Embodiments of the present invention Figure 1 This illustration depicts the application of a space electric field modulated drain in a three-dimensional gate-all-around power device. The device includes a substrate and a first portion of a GaN buffer layer on the substrate. A ring-shaped stacked structure is formed in the middle region of the first portion of the GaN buffer layer. The peripheral region of the ring-shaped stacked structure includes a second portion of the GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer stacked sequentially from bottom to top. The central region includes a second portion of the GaN buffer layer and a GaN channel layer stacked sequentially from bottom to top. A plurality of first vias penetrate the AlGaN barrier layer in the peripheral region to the upper surface of the first portion of the GaN buffer layer. Each first via is filled with a ring-shaped stacked structure. Around the cylindrical gate, an electrostatic shielding layer is filled between the inner wall of each first through-hole and the surrounding cylindrical gate; a second through-hole penetrates the GaN channel layer in the central region to the upper surface of the first part of the GaN buffer layer, and a conductive dielectric layer is filled inside the second through-hole, on which a source electrode is formed; side gates are formed on both sides of the first through-hole, and an electrostatic shielding layer is formed on one side of each side gate; wherein, a stepped structure is formed in the first part of the GaN buffer layer, and the depth of the deepest step in the stepped structure does not exceed 75% of the thickness of the first part of the GaN buffer layer. The design principle is to ensure that the bottom of the step can effectively modulate the high electric field region in the vertical dimension to achieve electric field optimization that matches the three-dimensional structure.

[0031] In this embodiment of the invention, the width of each step in the stepped structure is 1μm~2μm and the depth is 2.5nm~20nm. Too small a total step width will result in insufficient electric field modulation, while too large a width will increase the on-resistance. Therefore, the total step width (i.e., the length of the Schottky extension region) needs to be optimized through simulation based on the target breakdown voltage; for example, a 1200V device requires 8μm~15μm. This stepped structure is the physical basis for achieving spatial matching between electric field strength and modulation capability. Its principle is that when the device is off, the electric field strength decays from the gate edge to the drain. This design ensures that the deepest step, with the strongest modulation capability, handles the strongest peak electric field, while subsequent shallower steps smoothly decay the electric field, achieving spatial matching between modulation capability and electric field strength. This avoids resource waste and optimizes the electric field distribution, which is the physical basis for achieving efficient three-dimensional modulation.

[0032] In this embodiment of the invention, the thickness of the annular P-type oxide on each step of the stepped structure is 50 nm to 300 nm. The doping concentration of the annular P-type oxide must ensure that its depletion region width matches the step depth, thereby ensuring that its depletion region does not punch through under breakdown voltage. The core principle is that the annular P-type oxide forms a PN junction with the underlying N-type GaN. Under reverse bias, the depletion region generated by this PN junction can efficiently modulate the bulk electric field in the vertical dimension, which is far superior to the simple metal-semiconductor surface effect.

[0033] In the stepped structure of this invention, the spacing between the annular ohmic contact drain metal and the annular P-type oxide on each step is 0.1 μm-0.5 μm. This spacing is the minimum spacing between the annular ohmic contact drain metal and the annular P-type oxide to avoid short circuits, while interconnection is achieved through the top Schottky metal.

[0034] The cyclic P-type oxides in the embodiments of the present invention include one of P-NiO, P-Cu2O, and P-Ga2O3.

[0035] In this embodiment of the invention, the Schottky metal extension region near the gate can also be patterned to further optimize the electric field and adjust the parasitic capacitance. Figure 2 The diagram illustrates the top view of the space electric field modulation drain structure. The arrayed pattern is in the form of bars, but it is not limited to bars; it can also be in the form of circles, triangles, etc.

[0036] The drain design in this embodiment of the invention has structural universality. This drain design can be used as a general structure in different devices. Figure 1 It only illustrates its application on the drain of a three-dimensional all-around gate power device.

[0037] In summary, the innovation of the spatial electric field modulation drain proposed in this invention lies in the deep integration of drain material innovation and structural innovation, creating a completely new drain design specifically for advanced power devices with three-dimensional all-around gate architectures, fundamentally solving the bottlenecks of traditional technologies. Specifically: This invention designs a stepped structure where the step depth exhibits a gradient distribution decreasing from the near-gate side to the far-gate side. By introducing a third-dimensional stepped structure, the electric field modulation is extended from the surface to the bulk, achieving true three-dimensional depletion. This specific design has profound physical implications: it precisely corresponds to the natural distribution of the electric field intensity in the drain region of a three-dimensional all-around gate power device in the off-state, which decays exponentially from the gate edge inwards. By deploying the deepest, most modulating step at the leading edge region where the electric field peak is highest, and extending the progressively decreasing modulation steps to the electric field decay region, this structure achieves precise spatial matching between protection strength and electric field distribution, thereby fundamentally improving the breakdown voltage and breaking through performance bottlenecks.

[0038] This invention integrates a ring-shaped P-type oxide drain metal and a ring-shaped ohmic contact drain metal on each step of a stepped structure. The ring-shaped P-type oxide forms a PN junction with the N-type GaN channel layer. Under reverse bias, the depletion region generated by the ring-shaped P-type oxide can achieve three-dimensional depletion of the longitudinal electric field from the surface to the bulk, with modulation capability far exceeding surface effects. The ring-shaped P-type oxide is precisely placed at the edge of each step closest to the gate to specifically suppress the local electric field peak caused by the superposition of the three-dimensional geometry and the global electric field. At the same time, the ring-shaped ohmic contact drain metal distributed on each step platform together construct a low-resistance longitudinal current collection network. This layout, in conjunction with the stepped structure, naturally widens the lateral cross-sectional area of ​​current transport, significantly reduces on-resistance and current congestion effects, thereby effectively dispersing current density, reducing on-resistance and thermal effects, and improving the stability and reliability of the device. The integration of the "longitudinal depletion" of the P-type region and the "longitudinal current conduction" of the ohmic region in three-dimensional space achieves synergistic optimization and discrete management of the electric field and current path.

[0039] The Schottky metal covering the drain region in this invention is a continuous Schottky layer. This layer transcends the function of a typical electrode and also acts as a global field plate. Its extended portion, through capacitive coupling, further optimizes the electric field distribution between the gate and drain in the lateral direction. More importantly, it synergizes with the PN junction depletion effect of the steps below, forming a composite enhancement mechanism of the junction field plate, thereby achieving three-dimensional modulation of the electric field in both the vertical and lateral dimensions. The stepped structure extending towards the gate allows for finer control of the high electric field region, suppressing peak electric fields at the gate edge, and flexibly adjusting parasitic capacitance to optimize switching speed.

[0040] The drain design described in this invention possesses high structural compatibility and application potential, providing an efficient solution, particularly for the severe electric field management challenges in advanced power devices with three-dimensional gate-around architectures. Through its inherent three-dimensional spatial modulation capability, this design can be integrated into critical electric field concentration regions of devices such as three-dimensional cylindrical or gate-around devices, efficiently modulating their complex longitudinal and radial electric field distributions, thereby significantly improving overall breakdown voltage and reliability. Furthermore, its design principles are also applicable to optimizing the termination characteristics of other semiconductor devices. This targeted support for cutting-edge three-dimensional architectures and its broad applicability together expand the technical scope and application market potential of this invention.

[0041] Secondly, please see Figure 3 This invention provides a method for fabricating a space electric field modulated drain, used to fabricate any of the space electric field modulated drains described in the first aspect, the corresponding fabrication method including: S10. Fabricate the intermediate structure of the three-dimensional all-around gate power device, excluding the source and drain.

[0042] The present invention first prepares or provides an intermediate structure for a three-dimensional all-around gate power device, which forms a platform for subsequent drain integration. The structure includes a substrate (such as silicon, silicon carbide, or sapphire) and a first portion of a GaN buffer layer on the substrate. A ring-shaped stacked structure is formed in the middle region of the first portion of the GaN buffer layer. The peripheral region of the ring-shaped stacked structure includes a second portion of the GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer stacked sequentially from bottom to top. The central region includes a second portion of the GaN buffer layer and a GaN channel layer stacked sequentially from bottom to top. Several first vias penetrate the AlGaN barrier layer in the peripheral region to the upper surface of the first portion of the GaN buffer layer. Each first via is filled with a surrounding cylindrical gate, and an electrostatic shielding layer is filled between the inner wall of each first via and the surrounding cylindrical gate. Second vias penetrate the GaN channel layer in the central region to the upper surface of the first portion of the GaN buffer layer. The second vias are filled with a conductive dielectric layer, and a source electrode is formed on the conductive dielectric layer. Side gates are formed on both sides of the first vias, and an electrostatic shielding layer is formed on one side of each side gate. The prototype of the three-dimensional all-around gate power device prepared above is shown in Figure 4(a), which serves as the basis for the subsequent fabrication of a spatial electric field modulated drain in a specific region.

[0043] S20. A stepped pattern is defined by photolithography on the surface of the buffer layer in the drain region of the intermediate structure, and the stepped pattern is used to etch and form a stepped structure in the buffer layer.

[0044] After completing the intermediate structure of the three-dimensional gate-around power device, the crucial step of forming the spatially modulated drain begins. In the first part of the GaN buffer layer in the drain region, a stepped pattern is defined using photolithography. Then, anisotropic dry etching processes such as ICP (Inductively Coupled Plasma) or RIE (Reactive Ion Etching) are used to etch the first part of the GaN buffer layer multiple times at different depths, thus forming a stepped structure with gradient depth, as shown in Figure 4(b). The depth of the steps decreases sequentially from the side closest to the gate-around column towards the side furthest from the gate-around column. In this embodiment of the invention, the width of each step in the stepped structure is 1μm~2μm, and the depth is 2.5nm~20nm. The depth of the deepest step in the stepped structure does not exceed 75% of the thickness of the first part of the GaN buffer layer.

[0045] For example, for the first part of the GaN buffer layer, the initial etching depth in this embodiment can reach 20 nm to form the deepest step. Subsequent etching, by adjusting the time or power, forms shallower steps in 10 nm depth increments. This illustrates a two-stage step etching. The etching gas is typically a Cl2 / BCl3-based mixture.

[0046] S30, a ring-shaped P-type oxide is formed on each step of the stepped structure.

[0047] After forming the stepped mesa, this embodiment of the invention fabricates a ring-shaped P-type oxide on each step near the surrounding cylindrical gate, as shown in Figure 4(c). This step can be achieved by radio frequency magnetron sputtering. First, a ring-shaped P-type oxide film, such as a NiO film, is grown on the entire device surface, with a typical thickness of 50 nm to 300 nm. The growth temperature can be controlled between 200 °C and 400 °C to optimize the film quality. Subsequently, the ring-shaped P-type oxide film is patterned using photolithography and wet (or dry) etching processes to form strip-shaped ring-shaped P-type oxide covering each step near the surrounding cylindrical gate.

[0048] S40. An annular ohmic contact drain metal is formed on each step of the stepped structure; wherein the annular ohmic contact drain metal and the annular P-type oxide do not contact each other, the annular P-type oxide is located on the side closer to the surrounding cylindrical gate, and the annular ohmic contact drain metal is located on the side away from the surrounding cylindrical gate.

[0049] As shown in Figure 4(d), an annular ohmic contact drain metal is formed on each step of the stepped structure. This includes forming an annular ohmic contact drain metal with a thickness of 50 nm to 300 nm on each step of the stepped structure. The annular ohmic contact drain metal and the annular P-type oxide are not in contact. The annular P-type oxide is located on the side closer to the surrounding cylindrical gate, and the annular ohmic contact drain metal is located on the side farther from the surrounding cylindrical gate. The spacing between the annular ohmic contact drain metal and the annular P-type oxide on each step of the stepped structure is 0.1 μm to 0.5 μm. Specifically: This step aims to provide a low-resistance vertical convergence path for current. On the stepped surface where the toroidal P-type oxide has been grown, ohmic contact regions are defined by photolithography. Then, annular ohmic contact drain metal with a thickness of 50nm~300nm is formed using electron beam evaporation or sputtering. For example, standard GaN toroidal ohmic contact drain metal stacks such as Ti / Al / Ni / Au are deposited sequentially, with typical thicknesses of 20 / 160 / 55 / 45nm. The spacing between the toroidal ohmic contact drain metal and the toroidal P-type oxide must be controlled within 0.1μm~0.5μm. Afterwards, rapid thermal annealing is performed in a nitrogen atmosphere at 800℃~900℃ for 30s~60s to form low-resistance ohmic contacts. It is important to emphasize that this process step can simultaneously complete the fabrication of ohmic contacts in the source region, demonstrating the integration and efficiency of the process. These ohmic contact points distributed on each step collectively constitute the low-loss current network of the drain.

[0050] S50 forms a ring-shaped Schottky contact drain metal covering the entire drain region.

[0051] The final step is to achieve global field plate modulation and electrode interconnection. In this embodiment of the invention, photolithography is used to define a region covering the entire drain area (including the ring-shaped P-type oxide and the ring-shaped ohmic contact drain metal). Electron beam evaporation is used to deposit stacks of ring-shaped Schottky contact drain metals such as Ni / Au or Pt / Au, typically 150 nm thick, to cover the entire drain area as shown in Figure 4(e). This ring-shaped Schottky contact drain metal has the following advantages: 1) At the drain, it acts as a continuous Schottky metal layer covering all steps, forming a good connection with the underlying ring-shaped P-type oxide and ring-shaped ohmic contact drain metal, acting as a global field plate and generating a lateral field plate effect; 2) It synergizes with the PN junction depletion effect of the ring-shaped P-type oxide to form a composite enhancement mechanism for the junction field plate; 3) This step can usually also simultaneously complete the metallization of other electrodes in the device. The Schottky metal extension region near the side surrounding the cylindrical gate can also be patterned to further optimize the electric field and adjust parasitic capacitance. Finally, a passivation dielectric layer, such as silicon nitride, is deposited on the device surface to stabilize the surface potential and provide protection. The passivation dielectric layer can be made of materials such as SiO2, SiN, AlN, or Al2O3. Subsequently, electrode contact windows are opened using photolithography and etching, and metal interconnect wiring is performed to complete the device fabrication.

[0052] As for the second aspect of the preparation method embodiment, since it is basically similar to the first aspect of the device structure embodiment, the description is relatively simple. For relevant details, please refer to the description of the first aspect of the device structure embodiment.

[0053] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0054] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0055] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A spatial electric field modulated drain, characterized in that, The spatial electric field modulated drain is located in the drain region of the three-dimensional surrounding gate power device; the spatial electric field modulated drain includes a ring-shaped ohmic contact drain metal, a ring-shaped Schottky contact drain metal, and a ring-shaped P-type oxide; wherein... A stepped structure is formed within the buffer layer of the drain region. The depth of the steps in the stepped structure decreases sequentially from the side closest to the surrounding cylindrical gate to the side away from the surrounding cylindrical gate. Each step of the stepped structure is provided with an annular ohmic contact drain metal and an annular P-type oxide. The annular ohmic contact drain metal and the annular P-type oxide do not contact each other. The annular P-type oxide is located on the side closest to the surrounding cylindrical gate, and the annular ohmic contact drain metal is located on the side away from the surrounding cylindrical gate structure. The annular Schottky contact drain metal covers the entire drain region.

2. The spatial electric field modulation drain according to claim 1, characterized in that, The three-dimensional all-around gate power device includes a substrate and a first portion of a GaN buffer layer on the substrate. A ring-shaped stacked structure is formed in the middle region of the first portion of the GaN buffer layer. The peripheral region of the ring-shaped stacked structure includes a second portion of the GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer stacked sequentially from bottom to top. The central region includes a second portion of the GaN buffer layer and a GaN channel layer stacked sequentially from bottom to top. A plurality of first vias penetrate the AlGaN barrier layer in the peripheral region to the upper surface of the first portion of the GaN buffer layer. Each first via is filled with an all-around cylindrical gate, and an electrostatic shielding layer is filled between the inner wall of each first via and the all-around cylindrical gate. Second vias penetrate the GaN channel layer in the central region to the upper surface of the first portion of the GaN buffer layer. A conductive dielectric layer is filled in the second via, and a source electrode is formed on the conductive dielectric layer. Side gates are formed on both sides of the first vias, and an electrostatic shielding layer is formed on one side of each side gate. The stepped structure is formed within the first part of the GaN buffer layer, and the depth of the deepest step in the stepped structure does not exceed 75% of the thickness of the first part of the GaN buffer layer.

3. The spatial electric field modulation drain according to claim 1, characterized in that, The width of each step in the stepped structure is 1μm~2μm and the depth is 2.5nm~20nm.

4. The spatial electric field modulation drain according to claim 1, characterized in that, The thickness of the ring-shaped P-type oxide on each step in the stepped structure is 50 nm to 300 nm.

5. The spatial electric field modulation drain according to claim 1, characterized in that, In the stepped structure, the spacing between the annular ohmic contact drain metal and the annular P-type oxide on each step is 0.1 μm-0.5 μm.

6. The spatial electric field modulation drain according to claim 1, characterized in that, Cyclic p-type oxides include one of P-NiO, P-Cu2O, and P-Ga2O3.

7. A method for fabricating a space electric field modulated drain, characterized in that, The method for preparing the space electric field modulated drain according to any one of claims 1 to 6 includes: Fabrication of the intermediate structure of a three-dimensional all-around gate power device, excluding the source and drain; A stepped pattern is defined by photolithography on the surface of the buffer layer in the drain region of the intermediate structure, and the stepped pattern is used to etch a stepped structure in the buffer layer. A ring-shaped P-type oxide is formed on each step of the stepped structure; On each step of the stepped structure, an annular ohmic contact drain metal is formed; wherein the annular ohmic contact drain metal and the annular P-type oxide do not contact each other, the annular P-type oxide is located on the side closer to the surrounding cylindrical gate, and the annular ohmic contact drain metal is located on the side away from the surrounding cylindrical gate. A ring-shaped Schottky contact drain metal is formed covering the entire drain region.

8. The method for preparing a space electric field modulated drain according to claim 7, characterized in that, A stepped pattern is photolithographically defined on the surface of the buffer layer in the drain region of the intermediate structure, and the stepped pattern is used to etch a stepped structure within the buffer layer, including: A stepped pattern is defined by photolithography on the surface of the buffer layer in the drain region of the intermediate structure, and the buffer layer is etched multiple times at different depths using the stepped pattern to form a stepped structure within the buffer layer; the width of each step in the stepped structure is 1μm~2μm and the depth is 2.5nm~20nm, and the depth of the deepest step in the stepped structure does not exceed 75% of the thickness of the buffer layer.

9. The method for preparing a space electric field modulated drain according to claim 7, characterized in that, A ring-shaped P-type oxide is formed on each step of the stepped structure, including: At a growth temperature of 200℃ to 400℃, a ring-shaped P-type oxide with a thickness of 50nm to 300nm is formed on each step of the stepped structure by radio frequency magnetron sputtering. The ring-shaped P-type oxide includes one of P-NiO, P-Cu2O, and P-Ga2O3.

10. The method for preparing a space electric field modulated drain according to claim 7, characterized in that, A ring-shaped ohmic contact drain metal is formed on each step of the stepped structure, including: A ring-shaped ohmic contact drain metal with a thickness of 50 nm to 300 nm is formed on each step of the stepped structure; the spacing between the ring-shaped ohmic contact drain metal and the ring-shaped P-type oxide on each step of the stepped structure is 0.1 μm to 0.5 μm.

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