Display device and manufacturing method of display device

Abstract

Disclosed are a display device and a manufacturing method of the display device. The display device includes a plurality of first thin film transistors, a plurality of second thin film transistors, and a plurality of third thin film transistors on a substrate, wherein the first thin film transistor includes a first active layer and a first gate electrode on the first active layer, wherein the second thin film transistor includes a second active layer and a second gate electrode on the second active layer, wherein the third thin film transistor includes a third active layer and a third gate electrode on the third active layer, wherein a distance between the second active layer and the second gate electrode is greater than a distance between the third active layer and the third gate electrode, wherein the first thin film transistor further includes a first auxiliary electrode between the substrate and the first active layer, and wherein the first auxiliary electrode is electrically connected to the first gate electrode.

Description

Technical Field

[0001] This disclosure relates to display devices including thin-film transistors and methods of manufacturing the same. Background Technology

[0002] Transistors are widely used as switching or driving devices in electronic devices. In particular, thin-film transistors can be fabricated on glass or plastic substrates, making them widely used as switching elements in display devices such as liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs).

[0003] Thin-film transistors can be classified according to the material of the active layer into amorphous silicon thin-film transistors that use amorphous silicon as the active layer, polycrystalline silicon thin-film transistors that use polycrystalline silicon as the active layer, and oxide semiconductor thin-film transistors that use oxide semiconductors as the active layer.

[0004] Oxide-semiconductor (OSB) thin-film transistors (TFTs) offer advantages such as high mobility and readily obtainable desired characteristics because resistance variations can be adjusted based on oxygen content. Furthermore, the oxide layer constituting the active layer in OSB TFT manufacturing processes can be formed at relatively low temperatures, resulting in low manufacturing costs. Since OSBs are transparent due to the nature of oxides, OSB TFTs are also advantageous for realizing transparent displays.

[0005] Display devices utilize various thin-film transistors (TFTs) that perform a variety of functions. For example, TFTs used as switching elements in displays require excellent on-off characteristics, while TFTs used as driving elements require excellent grayscale representation characteristics. However, oxide semiconductor TFTs typically have low s-factors, making them difficult to use as driving TFTs for grayscale representation in display devices.

[0006] Furthermore, as display devices become higher resolution and larger size, there is a need to apply high mobility materials to thin-film transistors, and it is necessary to ensure the operational reliability of thin-film transistors using high mobility materials.

[0007] The description provided in the Background section should not be assumed to be prior art simply because it is mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter art, and the description in this section does not limit this disclosure. Summary of the Invention

[0008] The inventors have recognized that display devices require the use of various thin-film transistors that perform a variety of functions. Therefore, an exemplary embodiment of this disclosure will provide a display device including thin-film transistors with excellent switching characteristics and thin-film transistors with large s-factors.

[0009] Furthermore, an exemplary embodiment of this disclosure will provide a display device including a plurality of thin-film transistors configured to have different driving characteristics according to pixels.

[0010] An exemplary embodiment of this disclosure provides a display device that can simultaneously achieve excellent stability and grayscale performance characteristics by making the active layer compositions of the switching transistors and driving transistors different.

[0011] An exemplary embodiment of this disclosure provides a display device designed to achieve high-fidelity grayscale in pixels requiring precise grayscale representation by adjusting the distance between the active layer and the gate electrode differently for each pixel.

[0012] Exemplary embodiments of this disclosure are intended to provide a method of manufacturing a display device as described above.

[0013] To achieve the above-mentioned technical objectives, an exemplary embodiment of this disclosure provides a display device including a plurality of first thin-film transistors, a plurality of second thin-film transistors, and a plurality of third thin-film transistors on a substrate. The first thin-film transistors include a first active layer and a first gate electrode on the first active layer. The second thin-film transistors include a second active layer and a second gate electrode on the second active layer. The third thin-film transistors include a third active layer and a third gate electrode on the third active layer. The distance between the second active layer and the second gate electrode is greater than the distance between the third active layer and the third gate electrode. The first thin-film transistors also include a first auxiliary electrode located between the substrate and the first active layer, and the first auxiliary electrode is electrically connected to the first gate electrode.

[0014] The distance between the first active layer and the first gate electrode can be smaller than the distance between the second active layer and the second gate electrode.

[0015] The second active layer and the third active layer may each include a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0016] The second oxide semiconductor layer can have a higher mobility than the first oxide semiconductor layer.

[0017] The first oxide semiconductor layer can have a 14cm thickness.2 / V·s or less mobility, and the second oxide semiconductor layer can have a mobility of 15cm. 2 / V·s or a greater migration rate.

[0018] The first active layer can be formed of the same material as the first oxide semiconductor layer.

[0019] The display device further includes a gate insulating film between the first active layer and the first gate electrode, between the second active layer and the second gate electrode, and between the third active layer and the third gate electrode, wherein the thickness of the gate insulating film between the first active layer and the first gate electrode is defined as t1, the thickness of the gate insulating film between the second active layer and the second gate electrode is defined as t2, and the thickness of the gate insulating film between the third active layer and the third gate electrode is defined as t3, and satisfying "t2>t1" and "t2>t3".

[0020] The display device further includes a gate insulating film between the first active layer and the first gate electrode, between the second active layer and the second gate electrode, and between the third active layer and the third gate electrode, wherein the thickness of the gate insulating film between the first active layer and the first gate electrode is defined as t1, the thickness of the gate insulating film between the second active layer and the second gate electrode is defined as t2, and the thickness of the gate insulating film between the third active layer and the third gate electrode is defined as t3, and satisfies "t2>t1>t3".

[0021] The display device further includes a buffer layer on the substrate, the buffer layer having a first recess, and the second active layer may be disposed in the first recess.

[0022] The first recess may have a flat surface and an inclined surface, and a portion of the second active layer may be disposed on the flat surface, and another portion of the second active layer may be disposed on the inclined surface.

[0023] The second active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, and at least a portion of the first oxide semiconductor layer may be disposed on the inclined surface.

[0024] The display device also includes an insulating layer between the substrate and the buffer layer, and a second auxiliary electrode and a third auxiliary electrode on the insulating layer, wherein the second auxiliary electrode may overlap with the second active layer, and the third auxiliary electrode may be spaced apart from the second auxiliary electrode and may overlap with the third active layer.

[0025] The second auxiliary electrode may have light-shielding properties and be electrically connected to the second active layer, and the third auxiliary electrode may have light-shielding properties and be electrically connected to the third active layer.

[0026] The insulating layer has a second recess, and the second auxiliary electrode can be disposed in the second recess.

[0027] The second recess has a flat surface and an inclined surface, and a portion of the second auxiliary electrode is disposed on the flat surface, while another portion of the second auxiliary electrode is disposed on the inclined surface.

[0028] The first auxiliary electrode can be disposed between the substrate and the insulating layer.

[0029] The second thin-film transistor can have a larger s-factor than the third thin-film transistor.

[0030] The display device may include a first pixel and a second pixel on a substrate, wherein the first pixel includes one of a plurality of first thin-film transistors, one of a plurality of second thin-film transistors and a first display element connected to the second thin-film transistor, and wherein the second pixel includes another of the plurality of first thin-film transistors, one of a plurality of third thin-film transistors and a second display element connected to the third thin-film transistor.

[0031] The first pixel can emit green light, and the second pixel can emit light of any color other than green.

[0032] The display device further includes a gating driver that provides a scan signal to each of the first pixel and the second pixel, and the gating driver includes a buffer transistor that controls the application of the scan signal and a switching transistor that controls the driving of the buffer transistor, and the switching transistor may include the first thin-film transistor.

[0033] The buffer transistor may include a fourth auxiliary electrode on the substrate, a fourth active layer on the fourth auxiliary electrode, and a fourth gate electrode on the fourth active layer. The fourth active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, and the fourth auxiliary electrode may be electrically connected to the fourth gate electrode.

[0034] Another exemplary embodiment of this disclosure provides a method for manufacturing a display device, the method comprising: forming a first auxiliary electrode on a substrate; forming a buffer layer on the first auxiliary electrode; forming a first active layer, a second active layer, and a third active layer on the buffer layer; forming a gate insulating film on the first active layer, the second active layer, and the third active layer; and forming a first gate electrode, a second gate electrode, and a third gate electrode on the gate insulating film, wherein forming the buffer layer includes forming a first recess; wherein a second active layer is formed to be disposed in the first recess; and wherein the first auxiliary electrode is electrically connected to the first gate electrode.

[0035] The manufacturing method further includes: forming an insulating layer on the substrate before forming the buffer layer, and forming a second auxiliary electrode and a third auxiliary electrode on the insulating layer, wherein forming the insulating layer includes forming a second recess, and the second auxiliary electrode may be formed in the second recess.

[0036] The distance between the second active layer and the second gate electrode can be greater than the distance between the third active layer and the third gate electrode.

[0037] The distance between the second active layer and the second gate electrode can be greater than the distance between the first active layer and the first gate electrode.

[0038] The distance between the second active layer and the second gate electrode can be greater than the distance between the first active layer and the first gate electrode, and the distance between the first active layer and the first gate electrode can be greater than the distance between the third active layer and the third gate electrode.

[0039] The purpose of this disclosure is not limited to the foregoing, and other purposes of this disclosure, which have not yet been described, will become clearer to those skilled in the art from the following detailed description. Attached Figure Description

[0040] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0041] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure.

[0042] Figure 2 yes Figure 1 The circuit diagram of the pixels.

[0043] Figure 3 yes Figure 1 A cross-sectional view of the thin-film transistors included in the pixels.

[0044] Figure 4 yes Figure 3 Enlarged cross-sectional view of the first concave portion.

[0045] Figure 5 This is a cross-sectional view of thin-film transistors included in a pixel of a display device according to another exemplary embodiment of the present disclosure.

[0046] Figure 6 yes Figure 5 Enlarged cross-sectional view of the second concave portion.

[0047] Figure 7 This is a schematic circuit diagram of an exemplary implementation of a shift register included in a gating driver.

[0048] Figure 8 This is a cross-sectional view of a thin-film transistor with a gating driver.

[0049] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F and Figure 9G This is a schematic cross-sectional view illustrating the manufacturing process of a display device according to an exemplary embodiment of the present disclosure.

[0050] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G and Figure 10H This is a schematic cross-sectional view illustrating the manufacturing process of a display device according to another exemplary embodiment of the present disclosure.

[0051] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Implementation

[0052] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. The described progression of processing steps and / or operations is illustrative; however, the order of steps and / or operations is not limited to that described herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following explanation may have been chosen merely for convenience in drafting the specification and may therefore differ from the names used in actual products.

[0053] The advantages and features of this disclosure, as well as the methods for implementing them, will become clearer with reference to the embodiments described in detail below and the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. These embodiments are provided only to ensure that the disclosure is complete and to inform those skilled in the art of the present invention.

[0054] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc., disclosed in the accompanying drawings for explaining the embodiments of this disclosure are merely illustrative, and this disclosure is not limited to the details depicted in the drawings. Throughout the specification, the same components may be represented by the same reference numerals. Furthermore, in describing this disclosure, detailed descriptions of related known technologies will be omitted if they are deemed unnecessarily obscuring the essential points of this disclosure.

[0055] The dimensions of the various components shown in the accompanying drawings, including size and thickness, are shown for ease of description, and this disclosure is not limited to the size and thickness of the components shown. However, it should be noted that the relative dimensions of the components shown in the various accompanying drawings, including relative size, position, and thickness, are part of this disclosure.

[0056] In this specification, when the words “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed by,” or “composed of” are used, other components may be added unless the expression “only” is used. When a component is represented in the singular, the plural is included unless otherwise expressly stated.

[0057] When interpreting a component, it is interpreted as including the tolerance range, even if there is no separate explicit description.

[0058] When describing positional relationships, for example, when the positional relationship between two parts is described as "on," "above," "above," "below," "below," "next to," "under," "near," "close to," "adjacent to," "on the side," "near," etc., one or more other parts may be located between the two parts unless the expressions "exactly" or "directly" are used.

[0059] As illustrated in the accompanying drawings, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” can be used to readily describe the relationship between one element or component and another. In addition to the orientations depicted in the drawings, spatially relative terms should be understood to include different orientations of the elements during use or operation. For example, if an element depicted in the drawings is flipped, an element described as “below” or “under” another element may end up being placed “above” another element. Thus, the exemplary term “below” can encompass both the above and below directions. Similarly, the exemplary terms “above” or “above” can encompass both the above and below directions.

[0060] When describing temporal relationships, such as when describing them as “after,” “following,” “next,” “before,” etc., it can also include discontinuous cases as long as the expressions “immediately” or “directly” are not used.

[0061] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the scope of this disclosure, the "first" component mentioned below can also be the "second" component.

[0062] The word “exemplary” is used to indicate that something is an example or illustration. “Aspect” refers to an exemplary aspect. “Implementation,” “example,” “aspect,” etc., should not be construed as superior to or best of other implementations. Unless otherwise stated, implementation, example, exemplary implementation, aspect, etc., may refer to one or more implementations, one or more examples, one or more exemplary implementations, one or more aspects, etc. Furthermore, the word “may” encompasses all the meanings of the word “able to.”

[0063] The term "at least one" should be understood to include all possible combinations of one or more related items. For example, "at least one of the first, second, and third items" can mean not only the first, second, or third item, but also any combination of items that can be represented by two or more of the first, second, and third items.

[0064] As used herein, the term "device" can refer to a display device that includes a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting elements, etc. Additionally, examples of devices may include laptops, televisions, computer monitors, automotive devices, wearable devices and automotive equipment, as well as assemblies of electronic devices (or equipment) or assemblies (or devices) that include light-emitting elements as complete products or end products, such as mobile electronic devices like smartphones or tablets, but embodiments of this disclosure are not limited thereto.

[0065] Features of each of the various embodiments of this disclosure may be combined in part or in whole, and various technical connections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship.

[0066] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will be further understood that terms, as defined in commonly used dictionaries, shall be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0067] In the specification, when adding reference numerals to elements in each figure, care should be taken to ensure that, whenever possible, the same reference numerals used to denote the element in other figures are used for that element. Furthermore, for ease of description, the scale of the constituent elements shown in the figures may differ from the actual scale. That is, the scale of the constituent elements shown in the figures should not be interpreted as the same as the scale shown in the figures.

[0068] In the following, a display device and a method of manufacturing the same according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When assigning reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible, even if they are shown in different drawings.

[0069] In the exemplary embodiments of this disclosure, the source electrode and the drain electrode are distinguished only for illustrative purposes, and the source electrode and the drain electrode are interchangeable. Specifically, in one exemplary embodiment, the source electrode may be the drain electrode, and in another exemplary embodiment, the drain electrode may be the source electrode.

[0070] Figure 1 This is a schematic diagram of a display device 100 according to an exemplary embodiment of the present disclosure.

[0071] like Figure 1 As shown, a display device 100 according to an exemplary embodiment of the present disclosure includes a display panel 10, a strobe driver 20, a data driver 30, and a controller 40.

[0072] The display panel 10 may include a display area AA and a non-display area NDA. Pixels P1 and P2 are disposed in the display area AA to display images. Driving units, wiring, pads, terminals, etc., may be disposed in the non-display area NDA. Images are not displayed in the non-display area NDA.

[0073] The display panel 10 is equipped with a gate line GL and data lines DL1 and DL2, and pixels P1 and P2 are arranged at the intersection of the gate line GL and the data lines DL1 and DL2. Images are displayed by driving pixels P1 and P2.

[0074] Controller 40 controls strobe driver 20 and data driver 30.

[0075] The controller 40 uses signals supplied from an external system to output a gating control signal GCS for controlling the gating driver 20 and a data control signal DCS for controlling the data driver 30. Furthermore, the controller 40 samples the input image data from the external system, rearranges it, and supplies the rearranged digital image data (RGB) to the data driver 30.

[0076] The controller 40 can be configured to connect to various processors, such as microprocessors, mobile processors, application processors, etc., depending on the device installed therein.

[0077] The controller 40 can be implemented in a separate component from the data driver 30, or integrated with the data driver 30, so that the controller 40 and the data driver 30 can be implemented in a single integrated circuit.

[0078] Controller 40 may be a timing controller used in typical display technologies, or a control device / apparatus capable of performing additional control functions beyond the typical functions of a timing controller. In one or more embodiments, controller 40 may be one or more other control circuits different from the timing controller, or circuits or components within a control device / apparatus. Controller 40 may be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0079] The controller 40 can be mounted on a printed circuit board or flexible printed circuit, and can be electrically connected to the data driver 30 and the strobe driver 20 via the printed circuit board or flexible printed circuit.

[0080] The controller 40 can send signals to and receive signals from the data driver 30 via one or more predetermined interfaces. For example, such interfaces may include a low-voltage differential signaling (LVDS) interface, an embedded point-to-point clock interface (EPI), a serial peripheral interface (SPI), etc. However, this disclosure is not limited thereto.

[0081] The gating control signal GCS includes the gating start pulse GSP, the gating shift clock GSC, the gating output enable signal GOE, the start signal Vst, and the gating clock GCLK. Additionally, the gating control signal GCS may include control signals for controlling the shift register 50.

[0082] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0083] The data driver 30 supplies data voltage to the data lines DL1 and DL2 of the display panel 10. Specifically, the data driver 30 converts the image data RGB input from the controller 40 into analog data voltage and supplies this data voltage to the data lines DL1 and DL2.

[0084] The strobe driver 20 includes a shift register 50, and the shift register 50 may include a plurality of thin-film transistors.

[0085] The shift register 50 uses a start signal and a gating clock sent from the controller 40 to sequentially supply one frame of gating pulses to the gating line GL. Here, one frame refers to a period of time during which one image is output through the display panel 10. The gating pulses have a turn-on voltage that enables the switching elements (thin-film transistors) in pixels P1 and P2 to conduct.

[0086] Additionally, during the remaining time period when no strobe pulse is supplied during a frame, shift register 50 supplies a strobe cutoff signal to the strobe line GL, which can turn off the switching element. In the following text, the strobe pulse and the strobe cutoff signal will be collectively referred to as the scan signal SS or Scan.

[0087] According to an exemplary embodiment of this disclosure, the gate driver 20 may be mounted on the substrate 101. As described above, the structure in which the gate driver 20 is directly mounted on the substrate 101 is called a gate-in-panel (GIP) structure. The gate driver 20 may include a plurality of thin-film transistors.

[0088] The active layer of a thin-film transistor (TFT) can be formed from semiconductor materials, such as oxide semiconductors, amorphous semiconductors, or polycrystalline semiconductors, but is not limited to these.

[0089] Oxide semiconductor materials offer excellent leakage current prevention and relatively low manufacturing costs. Oxide semiconductors can be made from metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals and their oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti). Specifically, oxide semiconductors can include, but are not limited to, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO).

[0090] Polycrystalline semiconductor materials exhibit high mobility due to the fast movement speed of charge carriers such as electrons and holes, resulting in low energy consumption and excellent reliability. Polycrystalline semiconductors can be made of polycrystalline silicon (poly-Si), but are not limited to this.

[0091] Amorphous semiconductor materials can be made of amorphous silicon (a-Si), but are not limited to this.

[0092] Figure 2 yes Figure 1 Circuit diagrams for pixels P1 and P2.

[0093] Figure 1 The circuit diagram is an equivalent circuit diagram of pixels P1 and P2 of a display device 100 including organic light-emitting diodes (OLEDs) as display elements ED1 and ED2. According to an exemplary embodiment of this disclosure, the display device 100 is an organic light-emitting display device including organic light-emitting diodes (OLEDs) as display elements ED1 and ED2.

[0094] Each pixel P1, P2 includes display elements ED1, ED2 and a pixel driving circuit PDC that drives display elements ED1, ED2.

[0095] Figure 2 Each pixel driving circuit PDC includes a switching transistor sTR and a driving transistor dTR.

[0096] The switching transistor sTR is connected to the gating line GL and the data lines DL1 and DL2, and is turned on or off by the scan signal SS supplied via the gating line GL.

[0097] Data lines DL1 and DL2 supply data voltage Vdata to the pixel drive circuit PDC, and the switching transistor sTR controls the application of data voltage Vdata.

[0098] The driving power line PL provides the driving voltage Vdd to the display elements ED1 and ED2, and the driving transistor dTR controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diodes (OLEDs) that serve as display elements ED1 and ED2.

[0099] When the switching transistor sTR is turned on by the scan signal SS applied from the gate driver 20 via the gate line GL, the data voltage Vdata supplied via the data lines DL1 and DL2 is supplied to the gate electrode G2 of the driving transistor dTR connected to the display elements ED1 and ED2. The data voltage Vdata is charged into the storage capacitor Cst formed between the gate electrode G2 and the source electrode S2 of the driving transistor dTR.

[0100] The amount of current supplied to the organic light-emitting diodes (OLEDs) that serve as display elements ED1 and ED2 is controlled by the data voltage Vdata through the driving transistor dTR, and the grayscale of the light output from the display elements ED1 and ED2 can be controlled accordingly.

[0101] Although Figure 2 The illustration shows pixels P1 and P2, each having two thin-film transistors sTR and dTR and one capacitor Cst, but one exemplary embodiment of this disclosure is not limited thereto. Each pixel P1 and P2 may include three or more thin-film transistors and two or more capacitors.

[0102] A display device 100 according to an exemplary embodiment of the present disclosure includes the aforementioned switching transistor sTR and driving transistor dTR. The switching transistor sTR and driving transistor dTR may also be made of thin-film transistors.

[0103] Figure 3 yes Figure 1 Cross-sectional view of the thin-film transistors included in pixels P1 and P2.

[0104] The switching transistor sTR included in a display device 100 according to an exemplary embodiment of the present disclosure may have, for example, a relationship with... Figure 3 The first thin-film transistor TR1 has the same structure. The driving transistor dTR included in a display device 100 according to an exemplary embodiment of this disclosure may have, for example, the same structure as... Figure 3 The second thin-film transistor TR2 or the third thin-film transistor TR3 have the same structure.

[0105] Reference Figures 1 to 3 A display device 100 according to an exemplary embodiment of the present disclosure may include a plurality of first thin-film transistors TR1, a plurality of second thin-film transistors TR2 and a plurality of third thin-film transistors TR3 disposed on a substrate 101.

[0106] The first thin-film transistor TR1 includes a first active layer A1 and a first gate electrode G1 on the first active layer A1. The second thin-film transistor TR includes a second active layer A2 and a second gate electrode G2 on the second active layer A2. The third thin-film transistor TR3 includes a third active layer A3 and a third gate electrode G3 on the third active layer. Here, the distance t2 between the second active layer A2 and the second gate electrode G2 is greater than the distance t3 between the third active layer A3 and the third gate electrode G3.

[0107] The first thin-film transistor TR1 also includes a first auxiliary electrode E1 located between the substrate 101 and the first active layer A1, and the first auxiliary electrode E1 can be electrically connected to the first gate electrode G1.

[0108] According to an exemplary embodiment of this disclosure, a first thin-film transistor TR1 can be used as a switching transistor sTR for a first pixel P1, and a second thin-film transistor TR2 can be used as a driving transistor dTR for the first pixel P1. Furthermore, the first thin-film transistor TR1 can be used as a switching transistor sTR for a second pixel P2, and a third thin-film transistor TR3 can be used as a driving transistor dTR for the second pixel P2.

[0109] In the following text, refer to Figure 3 The structures of the first thin-film transistor TR1, the second thin-film transistor TR2, and the third thin-film transistor TR3 are described in detail.

[0110] Reference Figure 3 The first thin-film transistor TR1, the second thin-film transistor TR2, and the third thin-film transistor TR3 can be disposed on the substrate 101.

[0111] The substrate 101 may be made of glass or plastic. For example, the substrate may include a flexible polymer film. For example, the flexible polymer film may be made of any of the following: polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and this disclosure is not limited thereto.

[0112] The substrate 101 can be made of glass or plastic. A flexible, transparent plastic such as polyimide can be used. When using polyimide as the substrate 101, considering the high-temperature film formation process on the substrate 101, a heat-resistant polyimide capable of withstanding high temperatures can be used.

[0113] The first auxiliary electrode E1 can be disposed on the substrate 101. The first auxiliary electrode E1 can be conductive and light-shielding.

[0114] The first auxiliary electrode E1 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first auxiliary electrode E1 may also have a multilayer structure comprising at least two conductive films with different physical properties.

[0115] The first auxiliary electrode E1 can be configured to overlap with the first active layer A1. The first auxiliary electrode E1 can protect the first active layer A1 by blocking light incident from the outside.

[0116] An insulating layer 110 may be disposed on the first auxiliary electrode E1. The insulating layer 110 may also be disposed on the substrate 101. According to an exemplary embodiment of this disclosure, the first auxiliary electrode E1 may be disposed between the substrate 101 and the insulating layer 110.

[0117] The insulating layer 110 may include at least one of silicon oxide and silicon nitride. The insulating layer 110 has planarization properties and can planarize the upper part of the substrate 101.

[0118] Insulating layer 110 may include, for example, a first insulating layer 111 and a second insulating layer 112 on the first insulating layer 111, such as Figure 3 As shown. The first insulating layer 111 and the second insulating layer 112 may each comprise at least one of silicon oxide and silicon nitride. For example, each of the first insulating layer 111 and the second insulating layer 112 may be formed by a single or multiple inorganic film. For example, the single inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple inorganic film may be formed by alternately stacking at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon oxynitride (SiON) films and one or more amorphous silicon (a-Si), but this disclosure is not limited thereto. Insulating layer 110 may be omitted if necessary.

[0119] The second auxiliary electrode E2 and the third auxiliary electrode E3 can be disposed on the insulating layer 110. The second auxiliary electrode E2 and the third auxiliary electrode E3 are spaced apart from each other.

[0120] The second auxiliary electrode E2 overlaps with the second active layer A2, and the third auxiliary electrode E3 overlaps with the third active layer A3. Both the second auxiliary electrode E2 and the third auxiliary electrode E3 are conductive and can also provide light-shielding properties.

[0121] The second auxiliary electrode E2 can protect the second active layer A2 by blocking light incident from the outside. Additionally, the third auxiliary electrode E3 can protect the third active layer A3 by blocking light incident from the outside.

[0122] The second auxiliary electrode E2 and the third auxiliary electrode E3 may each include at least one of aluminum-based metals such as aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti).

[0123] A buffer layer 120 may be disposed on the second auxiliary electrode E2 and the third auxiliary electrode E3. The buffer layer 120 may include at least one of silicon oxide and silicon nitride. The buffer layer 120 protects the active layers A1, A2, and A3.

[0124] Buffer layer 120 may include, for example, a first buffer layer 121 and a second buffer layer 122 on the first buffer layer 121, such as Figure 3 As shown. The first buffer layer 121 and the second buffer layer 122 may each comprise at least one of silicon oxide and silicon nitride. For example, each of the first buffer layer 121 and the second buffer layer 122 may be formed by a single or multiple inorganic film. For example, the single inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple inorganic film may be formed by alternately stacking at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon oxynitride (SiON) films and one or more amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0125] According to an exemplary embodiment of this disclosure, the buffer layer 120 may have a first recess 125 (see [link]). Figure 4 The first recess 125 can be formed by removing a portion of the buffer layer 120. The first recess 125 can overlap with the second active layer A2.

[0126] The first active layer A1, the second active layer A2, and the third active layer A3 are disposed on the buffer layer 120. The second active layer A2 may be disposed in the first recess 125 of the buffer layer 120 (see...). Figure 4 ).

[0127] According to an exemplary embodiment of this disclosure, the first active layer A1, the second active layer A2, and the third active layer A3 may each comprise an oxide semiconductor material. For example, the first active layer A1, the second active layer A2, and the third active layer A3 may each comprise a semiconductor material selected from IGZO (InGaZnO)-based oxide semiconductor materials, IZO (InZnO)-based oxide semiconductor materials, ITZO (InSnZnO)-based oxide semiconductor materials, FIZO (FeInZnO)-based oxide semiconductor materials, ZnO-based oxide semiconductor materials, SIZO (SiInZnO)-based oxide semiconductor materials, ZnON (Zn-oxide-nitride)-based oxide semiconductor materials, GZO (GaZnO)-based oxide semiconductor materials, IGO (InGaO)-based oxide semiconductor materials, IGZTO (InGaZnSnO)-based oxide semiconductor materials, GO (GaO)-based oxide semiconductor materials, GZTO (GaZnSnO)-based oxide semiconductor materials, and IWZO (InWZnO)-based oxide semiconductor materials.

[0128] The first active layer A1 can be configured to overlap with the first auxiliary electrode E1.

[0129] The first active layer A1 may comprise an oxide semiconductor material with excellent stability and low mobility. For example, the first active layer A1 may have a 14 cm⁻¹ diameter. 2 / V·s or lower migration rate.

[0130] According to an exemplary embodiment of this disclosure, the first active layer A1 may include at least one of IGZO (InGaZnO)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, IGO (InGaO)-based oxide semiconductor material, and GZTO (GaZnSnO)-based oxide semiconductor material. When the oxide semiconductor material constituting the first active layer A1 includes gallium (Ga) and indium (In), the concentration of gallium (Ga) is set to be higher than the concentration of indium (In) in molar quantities [Ga concentration > In concentration].

[0131] Gallium (Ga) is known to form stable oxygen bonds and contribute to film stability. Therefore, a first active layer A1 containing a relatively large amount of gallium (Ga) can exhibit excellent stability. As a result, even if the first thin-film transistor TR1, used as a switching transistor sTR, has a short channel, the first thin-film transistor TR1 can still exhibit stable switching characteristics without causing a shift or reduction in the threshold voltage Vth (Vth roll-off).

[0132] According to an exemplary embodiment of this disclosure, the second active layer A2 and the third active layer A3 may each include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131. The first oxide semiconductor layer 131 may be disposed on the buffer layer 120.

[0133] In the second active layer A2 and the third active layer A3, the second oxide semiconductor layer 132 can have a greater mobility than the first oxide semiconductor layer 131. Specifically, the first oxide semiconductor layer 131 can have excellent stability, and the second oxide semiconductor layer 132 can have excellent current characteristics.

[0134] For example, the first oxide semiconductor layer 131 can have a thickness of 14 cm. 2 / V·s or even lower mobility. Additionally, the second oxide semiconductor layer 132 can have a mobility of 15 cm⁻¹. 2 / V·s or greater mobility. The first oxide semiconductor layer 131 may include a low-mobility oxide semiconductor material, and the second oxide semiconductor layer 132 may include a high-mobility oxide semiconductor material.

[0135] According to an exemplary embodiment of this disclosure, the second thin-film transistor TR2 and the third thin-film transistor TR3 can be used as driving transistors dTR. The driving transistors dTR are used to control the grayscale of display elements ED1 and ED2. To facilitate grayscale control, the driving transistors dTR typically have a larger channel length than the switching transistors sTR. However, if the channel length increases, the threshold voltages of the second thin-film transistors TR2 and TR3 may shift in the positive (+) direction. If the threshold voltage shift becomes large, it becomes difficult to control the thin-film transistors TR2 and TR3, which is therefore undesirable.

[0136] Therefore, according to an exemplary embodiment of this disclosure, the second thin-film transistor TR2 and the third thin-film transistor TR3, which are driving thin-film transistors, are designed to include a second oxide semiconductor layer 132, which comprises a high-mobility oxide semiconductor material. Because the second thin-film transistor TR2 and the third thin-film transistor TR3 include the second oxide semiconductor layer 132, excessive shift of the threshold voltage in the second thin-film transistor TR2 and the third thin-film transistor TR3 is prevented or suppressed.

[0137] Meanwhile, high-mobility oxide semiconductor materials may not have excellent stability. Therefore, according to an exemplary embodiment of this disclosure, a first oxide semiconductor layer 131 with excellent stability is disposed beneath a second oxide semiconductor layer 132 comprising a high-mobility oxide semiconductor material.

[0138] The first oxide semiconductor layer 131 exhibits excellent stability, but in return, it has relatively low mobility. The first oxide semiconductor layer 131 can protect and support the second oxide semiconductor layer 132. Therefore, the first oxide semiconductor layer 131 can also be referred to as a support layer.

[0139] According to an exemplary embodiment of this disclosure, the first oxide semiconductor layer 131 may be disposed on the opposite side of the gate electrodes G2 and G3 relative to the second oxide semiconductor layer 132. (Refer to...) Figure 3 The first oxide semiconductor layer 131 can be disposed between the second oxide semiconductor layer 132 and the substrate 101.

[0140] According to an exemplary embodiment of this disclosure, the first oxide semiconductor layer 131 may include at least one of IGZO (InGaZnO)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, IGO (InGaO)-based oxide semiconductor material, and GZTO (GaZnSnO)-based oxide semiconductor material. When the oxide semiconductor material constituting the first oxide semiconductor layer 131 includes gallium (Ga) and indium (In), the concentration of gallium (Ga) is set to be higher than the concentration of indium (In) in molar terms [Ga concentration > In concentration].

[0141] According to an exemplary embodiment of this disclosure, the first active layer A1 may be formed of the same material as the first oxide semiconductor layer 131. For example, the first active layer A1 may be formed of the same material as the first oxide semiconductor layer 131 using the same process.

[0142] According to an exemplary embodiment of this disclosure, the second oxide semiconductor layer 132 may include IGZO (InGaZnO)-based oxide semiconductor materials, IZO (InZnO)-based oxide semiconductor materials, IGZTO (InGaZnSnO)-based oxide semiconductor materials, ITZO (InSnZnO)-based oxide semiconductor materials, FIZO (FeInZnO)-based oxide semiconductor materials, ZnO-based oxide semiconductor materials, InO-based oxide semiconductor materials, TO (SnO)-based oxide semiconductor materials, SIZO (SiInZnO)-based oxide semiconductor materials, and ZnON (Zn-oxide-saturated oxide)-based oxide semiconductor materials. When the oxide semiconductor material constituting the second oxide semiconductor layer 132 includes indium (In) and gallium (Ga), the concentration of indium (In) is higher than the concentration of gallium (Ga) on an atomic basis [In concentration > Ga concentration].

[0143] The second oxide semiconductor layer 132 has high mobility characteristics and can have a 15cm² length. 2 / V·s or greater mobility. Additionally, the second oxide semiconductor layer 132 can have a mobility of 20 cm⁻¹. 2 / V·s or greater migration rates can achieve 20~50cm 2 The mobility in the range of / V·s can be 20~40cm. 2 The migration rate is in the range of / V·s, or can be 20~30cm. 2 The migration rate within the range of / V·s.

[0144] According to an exemplary embodiment of the present disclosure, the second active layer A2 may be disposed in the first recess 125 formed in the buffer layer 120.

[0145] Figure 4 yes Figure 3 Enlarged cross-sectional view of the first recess 125.

[0146] Reference Figure 3 and Figure 4 The first recess 125 may have a flat surface 125b and an inclined surface 125s. Referring to the figures, the flat surface 125b may be, for example, a plane parallel to the substrate 101. The inclined surface 125s may be, for example, a surface inclined at a predetermined angle relative to the substrate 101.

[0147] According to an exemplary embodiment of this disclosure, a flat surface 125b and an inclined surface 125s may be formed in the buffer layer 120. (Refer to...) Figure 4 The flat surface 125b and the inclined surface 125s can be formed in the second buffer layer 122. Each of the flat surface 125b and the inclined surface 125s can be said to be a surface formed on the buffer layer 120.

[0148] The first recess 125 may be defined by a flat surface 125b and an inclined surface 125s. The first recess 125 may be a region or space surrounded by the flat surface 125b and the inclined surface 125s.

[0149] According to an exemplary embodiment of this disclosure, a portion of the second active layer A2 may be disposed on a flat surface 125b, and another portion of the second active layer A2 may be disposed on an inclined surface 125s.

[0150] Alternatively, a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132, which are included in the second active layer A2, may be provided in the first recess 125. (Refer to...) Figure 3 and Figure 4 A portion of the first oxide semiconductor layer 131 may be disposed on the flat surface 125b. Alternatively, another portion of the first oxide semiconductor layer 131 may be disposed on the inclined surface 125s.

[0151] According to an exemplary embodiment of this disclosure, the second oxide semiconductor layer 132 may be disposed on the flat surface 125b of the first recess 125. Specifically, the second oxide semiconductor layer 132 may be disposed on the first oxide semiconductor layer 131 above the flat surface 125b of the first recess 125. For example, the first oxide semiconductor layer 131 may be disposed on the flat surface 125b and the inclined surface 125s, and the second oxide semiconductor layer 132 may be disposed on the first oxide semiconductor layer 131 located above the flat surface 125b, but not on the first oxide semiconductor layer 131 located above the inclined surface 125s; however, this disclosure is not limited thereto.

[0152] The first oxide semiconductor layer 131 disposed on the flat surface 125b and the inclined surface 125s can efficiently support and protect the second oxide semiconductor layer 132. The first oxide semiconductor layer 131 can support the bottom surface of the second oxide semiconductor layer 132 and protect the side surfaces of the second oxide semiconductor layer 132.

[0153] A gate insulating film 140 is disposed on the first active layer A1, the second active layer A2, and the third active layer A3.

[0154] The gate insulating film 140 protects the active layers A1, A2, and A3 and separates the active layers A1, A2, and A3 from the gate electrodes G1, G2, and G3. According to an exemplary embodiment of this disclosure, the gate insulating film 140 is disposed at least between the first active layer A1 and the first gate electrode G1, between the second active layer A2 and the second gate electrode G2, and between the third active layer A3 and the third gate electrode G3.

[0155] The gate insulating film 140 may have a single-layer or multi-layer structure. The gate insulating film 140 may include at least one of, for example, silicon oxide, silicon nitride, and metal oxide. For example, the gate insulating film 140 may be formed by a single or multiple inorganic film. For instance, the single-layer inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multi-layer inorganic film may be formed by alternately stacking at least one of a silicon oxide (SiOx) film, one or more silicon nitride (SiNx) film, and one or more silicon oxynitride (SiON) film, and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0156] The first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 are disposed on the gate insulating film 140.

[0157] The first gate electrode G1 overlaps with at least a portion of the first active layer A1, the second gate electrode G2 overlaps with at least a portion of the second active layer A2, and the third gate electrode G3 overlaps with at least a portion of the third active layer A3. The regions of the active layers A1, A2, and A3 that overlap with the gate electrodes G1, G2, and G3 can be channel regions.

[0158] Each of the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals based on molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). Each of the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may have a multilayer structure comprising at least two conductive layers with different physical properties.

[0159] According to an exemplary embodiment of this disclosure, when the second active layer A2 is disposed in the first recess 125, the thickness of the gate insulating film 140 can vary depending on its position. As a result, the distance between the active layers A1, A2, A3 and the gate electrodes G1, G2, G3 can vary depending on their position.

[0160] According to an exemplary embodiment of this disclosure, when the thickness of the gate insulating film 140 between the first active layer A1 and the first gate electrode G1 is t1, the thickness of the gate insulating film 140 between the second active layer A2 and the second gate electrode G2 is t2, and the thickness of the gate insulating film 140 between the third active layer A3 and the third gate electrode G3 is t3, the conditions "t2>t1" and "t2>t3" are satisfied. For example, the thickness of the gate insulating film 140 between the first active layer A1 and the first gate electrode G1 is t1, the thickness of the gate insulating film 140 between the second active layer A2 and the second gate electrode G2 is t2, and the thickness of the gate insulating film 140 between the third active layer A3 and the third gate electrode G3 is t3, and "t2>t1>t3", but this disclosure is not limited thereto.

[0161] An interlayer insulating film 150 is disposed on the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3.

[0162] The interlayer insulating film 150 is made of an insulating material. Specifically, the interlayer insulating film 150 may be made of organic materials, inorganic materials, or a laminate of organic and inorganic layers. The interlayer insulating film 150 may include silicon oxide (SiOx) or silicon nitride (SiNx).

[0163] Reference Figure 3The interlayer insulating film 150 may include a first insulating film 151 and a second insulating film 152. The first insulating film 151 and the second insulating film 152 may each include at least one of silicon oxide (SiOx) and silicon nitride (SiNx). For example, each of the first insulating film 151 and the second insulating film 152 may be formed by a single layer or multiple layers of inorganic films. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple-layer inorganic film may be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film, and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0164] The source electrodes S1, S2, S3 and the drain electrodes D1, D2, D3 can be disposed on the interlayer insulating film 150.

[0165] The source electrodes S1, S2, S3 and the drain electrodes D1, D2, D3 may each comprise at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. The source electrodes S1, S2, S3 and the drain electrodes D1, D2, D3 may each be formed as a single layer made of metal or metal alloy, or they may be formed as a multilayer comprising two or more layers.

[0166] The first source electrode S1 and the first drain electrode D1 are spaced apart from each other and are each connected to the first active layer A1. The first source electrode S1 and the first drain electrode D1 can be connected to the first active layer A1 through contact holes formed in the gate insulating film 140 and the interlayer insulating film 150, respectively, but this disclosure is not limited thereto.

[0167] The second source electrode S2 and the second drain electrode D2 are spaced apart from each other and are each connected to the second active layer A2. The second source electrode S2 and the second drain electrode D2 can be connected to the second active layer A2 through contact holes formed in the gate insulating film 140 and the interlayer insulating film 150, respectively, but this disclosure is not limited thereto.

[0168] Alternatively, the second source electrode S2 can also be connected to the second auxiliary electrode E2 through a contact hole. As a result, the second auxiliary electrode E2 can be electrically connected to the second active layer A2. Specifically, the second auxiliary electrode E2 can be electrically connected to the second active layer A2 through the second source electrode S2.

[0169] The third source electrode S3 and the third drain electrode D3 are spaced apart from each other and are each connected to the third active layer A3. The third source electrode S3 and the third drain electrode D3 can be connected to the third active layer A3 through contact holes formed in the gate insulating film 140 and the interlayer insulating film 150, respectively, but this disclosure is not limited thereto.

[0170] Furthermore, the third source electrode S3 can be connected to the third auxiliary electrode E3 through a contact hole. As a result, the third auxiliary electrode E3 can be electrically connected to the third active layer A3. Specifically, the third auxiliary electrode E3 can be electrically connected to the third active layer A3 through the third source electrode S3.

[0171] According to an exemplary embodiment of the present disclosure, the first thin-film transistor TR1 may include a first auxiliary electrode E1, a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

[0172] According to an exemplary embodiment of this disclosure, the first gate electrode G1 can be connected to the first auxiliary electrode E1. Therefore, the same voltage as the first gate electrode G1 can be applied to the first auxiliary electrode E1. The first auxiliary electrode E1 overlaps with the first active layer A1 and can be used as the gate electrode of the first active layer A1. Therefore, according to an exemplary embodiment of this disclosure, the first thin-film transistor TR1 can have a dual-gate structure in which gate electrodes are disposed on the upper and lower sides of the first active layer A1.

[0173] Furthermore, the distance between the first active layer A1 and the first gate electrode G1 can be designed to be smaller than the distance t2 between the second active layer A2 and the second gate electrode G2 of the second thin-film transistor TR2. Therefore, when a voltage is applied to the first gate electrode G1, a relatively strong electric field can be applied to the first active layer A1.

[0174] The first thin-film transistor TR1 with this structure can have excellent switching characteristics. The first thin-film transistor TR1 has a dual-gate structure, thus exhibiting excellent on-off characteristics, and the first active layer A1 includes a stable first oxide semiconductor layer 131 with low mobility, enabling the first thin-film transistor TR1 to have excellent functional stability.

[0175] According to an exemplary embodiment of the present disclosure, the second thin-film transistor TR2 may include a second auxiliary electrode E2, a second active layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

[0176] Since the second auxiliary electrode E2 is connected to the second source electrode S2 and overlaps with the second active layer A2, a capacitance can be formed between the second auxiliary electrode E2 and the second active layer A2 when the second thin-film transistor TR2 is turned on. As a result, when the second thin-film transistor TR2 is turned on, the current I... DS Relative to voltage V GS The increase is small. Therefore, the second thin-film transistor TR2 can have a large s-factor.

[0177] Therefore, the second thin-film transistor TR2 according to an exemplary embodiment of the present disclosure can be used as the driving transistor dTR of the display device 100.

[0178] The third thin-film transistor TR3 may include a third auxiliary electrode E3, a third active layer A3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3.

[0179] Since the third auxiliary electrode E3 is connected to the third source electrode S3 and overlaps with the third active layer A3, a capacitance can be formed between the third auxiliary electrode E3 and the third active layer A3 when the third thin-film transistor TR3 is turned on. As a result, when the third thin-film transistor TR3 is turned on, the current I... DS Relative to voltage V GS The increase is small. Therefore, the third thin-film transistor TR3 can have a large s-factor.

[0180] Therefore, the third thin-film transistor TR3 according to an exemplary embodiment of the present disclosure can be used as the driving transistor dTR of the display device 100.

[0181] The s-factor will be explained in more detail below.

[0182] In order to enable the current-driven display device 100 (e.g., an organic light-emitting display device) to have excellent grayscale performance, it is advantageous to have a large s-factor of the driving transistor dTR of the pixels driving the organic light-emitting display device.

[0183] The s-factor, known as the "subthreshold sway," represents the drain current I of thin-film transistors TR1, TR2, and TR3. DS Relative to gate voltage V GS The grayscale values ​​of pixels P1 and P2 are derived from the inverse of the slope of the curve showing the variation within the threshold voltage Vth. Furthermore, the grayscale values ​​of pixels P1 and P2 can be controlled by the magnitude of the drain-source current, which in turn is controlled by the gate voltage.

[0184] As the s-factor increases, within the threshold voltage Vth range, the drain-source current I... DSThe change in gate voltage decreases or gradually decreases. Therefore, when the s-factor is large, the drain-source current I is controlled by controlling the gate voltage. DS The size becomes easy to adjust.

[0185] Furthermore, the greater the distance between the gate electrodes G1, G2, G3 and the active layers A1, A2, A3, the weaker the electric field applied to the active layers A1, A2, A3, resulting in a weaker drain-source current I. DS Relative to gate voltage V GS The slope decreases, resulting in an increase in the s-factor.

[0186] According to an exemplary embodiment of this disclosure, a second active layer A2 is disposed in a first recess 125 formed in a buffer layer 120. As a result, the distance t2 between the second active layer A2 and the second gate electrode G2 is greater than the distance t3 between the third active layer A3 and the third gate electrode G3 (t2 > t3). Consequently, when the same voltage is applied to the second gate electrode G2 and the third gate electrode G3, the intensity of the electric field applied to the second active layer A2 is less than the intensity of the electric field applied to the third active layer A3. Consequently, the current I of the second thin-film transistor TR2... DS Voltage V relative to the threshold voltage Vth region GS The increase is less than that of the current I of the third thin-film transistor TR3. DS Voltage V relative to the threshold voltage Vth region GS The degree of increase.

[0187] Therefore, the second thin-film transistor TR2 can have a larger s-factor than the third thin-film transistor TR3.

[0188] The second thin-film transistor TR2, which has a larger s-factor than the third thin-film transistor TR3, can be applied to pixels that require more precise grayscale control.

[0189] According to an exemplary embodiment of this disclosure, when white light is implemented in an organic light-emitting display, the brightness of green light accounts for a large portion of the total brightness. For example, a display device 100 according to an exemplary embodiment of this disclosure may include red pixels, green pixels, and blue pixels, and when the display device 100 displays white light, the brightness of green light may account for about 70% of the total brightness, the brightness of red light may account for about 23% to 24% of the total brightness, and the brightness of blue light may account for about 6% to 7% of the total brightness. Therefore, in order to control the brightness and grayscale of the display device 100, it is necessary to precisely control the brightness of green light.

[0190] To precisely control the brightness of green light, according to an exemplary embodiment of this disclosure, the second thin-film transistor TR2 can be used as the driving transistor dTR for green pixels. Since the second thin-film transistor TR2 can have a larger s-factor than the third thin-film transistor TR3, the second thin-film transistor TR2, having a larger s-factor than the third thin-film transistor TR3, can be applied to pixels requiring more precise grayscale control. Therefore, the second thin-film transistor TR2 can be used as the driving transistor dTR for green pixels.

[0191] According to an exemplary embodiment of this disclosure, the first pixel P1 may be a green pixel, and the second pixel P2 may be a non-green pixel. Specifically, the first pixel P1 may emit green light, and the second pixel P2 may emit non-green light. For example, the second pixel P2 may emit red or blue light.

[0192] The first pixel P1 that emits green light may include a first thin-film transistor TR1 and a second thin-film transistor TR2. The second thin-film transistor TR2 may be connected to a first display element ED1. Here, the first display element ED1 may be a green organic light-emitting element.

[0193] The second pixel P2 may include a first thin-film transistor TR1 and a third thin-film transistor TR3. The third thin-film transistor TR3 may be connected to the second display element ED2. Here, the second display element ED2 may be, for example, a red organic light-emitting element or a blue organic light-emitting element.

[0194] According to an exemplary embodiment of this disclosure, the second thin-film transistor TR2 may have an s-factor of, for example, 0.3 or greater. When the second thin-film transistor TR2 has an s-factor of 0.3 or greater, the grayscale of the first pixel P1, which is a green pixel, can be easily controlled. Furthermore, when the s-factor of the second thin-film transistor TR2 becomes excessively large, the power consumption of the display device 100 increases. With this in mind, the second thin-film transistor TR2 according to an exemplary embodiment of this disclosure may have an s-factor in the range of 0.3 to 0.5; for example, the second thin-film transistor TR2 according to an exemplary embodiment of this disclosure may have an s-factor in the range of 0.35 to 0.45, but this disclosure is not limited thereto.

[0195] As described above, in one exemplary embodiment of this disclosure, the configuration of the driving transistor dTR can be designed differently depending on the color of the pixel equipped with the driving transistor dTR, and thus the display characteristics of the display device 100 can be improved.

[0196] Figure 5This is a cross-sectional view of thin-film transistors TR1, TR2, and TR3 included in pixels P1 and P2 of a display device 200 according to another exemplary embodiment of this disclosure. In the following text, to avoid redundancy, descriptions of the already described components are omitted or simplified.

[0197] Reference Figure 5 The insulating layer 110 may have a second recess 115. Additionally, a second auxiliary electrode E2 may be disposed in the second recess 115.

[0198] Figure 6 yes Figure 5 Enlarged cross-sectional view of the second recess 115.

[0199] Reference Figure 6 The second recess 115 may have a flat surface 115b and an inclined surface 115s. A portion of the second auxiliary electrode E2 may be disposed on the flat surface 115b of the second recess 115, and another portion of the second auxiliary electrode E2 may be disposed on the inclined surface 115s of the second recess 115.

[0200] Since a portion of the second auxiliary electrode E2 is disposed on the inclined surface 115s of the second recess 115, the second auxiliary electrode E2 can effectively protect the second active layer A2 from light incident from the side surface direction.

[0201] Furthermore, as the second recess 115 is formed in the insulating layer 110, the distance t2 between the second active layer A2 and the second gate electrode G2 overlapping with the second recess 115 can be increased. As the distance t2 increases, the s-factor of the second thin-film transistor TR2 increases, thus providing more precise grayscale control.

[0202] Figure 7 This is a schematic circuit diagram of an exemplary embodiment of the shift register 50 included in the strobe driver 20.

[0203] A display device 100 according to an exemplary embodiment of the present disclosure may include a gating driver 20, and the gating driver 20 provides a scan signal SS to each of a first pixel P1 and a second pixel P2. The gating driver 20 may include a buffer transistor bTR for controlling the application of the scan signal SS and a switching transistor sTR for controlling the driving of the buffer transistor bTR.

[0204] Specifically, the buffer transistor bTR and the switching transistor sTR can be set in the shift register 50 of the gating driver 20.

[0205] Reference Figure 7The shift register 50 included in the strobe driver 20 may include a pull-up node Q, a pull-down node QB, a node control unit NC, and a buffer unit BF.

[0206] The buffer unit BF is connected to the output terminal Vout and may include a pull-up transistor Tu, a pull-down transistor Td, and a capacitor Cp.

[0207] When the pull-up node Q is charged to the gating high voltage, the pull-up transistor Tu can be turned on to output the gating signal for the gating shift clock (GCLK). For example, the gating signal for the gating shift clock (GCLK) can be the high voltage of the gating shift clock, but is not limited to this.

[0208] When the pull-down node QB is charged to a gating low voltage to output a gating cutoff signal (e.g., a low potential voltage or a low voltage supply with a transistor cutoff voltage level), the pull-down transistor Td can be turned on.

[0209] According to an exemplary embodiment of this disclosure, the pull-up transistor Tu and pull-down transistor Td included in the buffer unit BF are referred to as buffer transistor bTR. Buffer transistor bTR controls the application of scan signal SS to pixels P1 and P2.

[0210] The capacitor Cp is used to maintain the gate high voltage supplied to the gate electrode (or pull-up node Q) of the pull-up transistor Tu for one frame. The capacitor Cp can be placed between the gate electrode and the first electrode of the pull-up transistor Tu. For example, the first electrode of the pull-up transistor Tu can be the source electrode or the drain electrode. For example, the capacitor Cp can be a parasitic capacitance between the gate electrode and the first electrode of the pull-up transistor Tu, but is not limited thereto.

[0211] The node control unit NC controls the charging and discharging of pull-up node Q and pull-down node QB. The node control unit NC may include a pull-up node control unit NC_Q for controlling the charging and discharging of pull-up node Q and a pull-down node control unit NC_QB for controlling the charging and discharging of pull-down node QB. The pull-up node control unit NC_Q may include at least one transistor TQ for controlling the voltage (or charging and discharging voltage) of pull-up node Q. The pull-down node control unit NC_QB may include at least one transistor TQB for controlling the voltage (or charging and discharging voltage) of pull-down node QB.

[0212] The output of the strobe signal or low voltage (or strobe cutoff signal) SS to the output terminal Vout can be stably controlled by the node control unit NC. Specifically, the node control unit NC discharges the pull-down node QB to the strobe low voltage (or low potential voltage) when charging the pull-up node Q to the strobe high voltage, and discharges the pull-up node Q to the strobe low voltage (or low potential voltage) when charging the pull-down node QB to the strobe high voltage.

[0213] Therefore, when the strobe start signal Vst is applied, the pull-up node Q is charged with a strobe high voltage through the operation of multiple transistors TQ and TQB set in the node control unit NC, thereby turning on the pull-up transistor Tu. At the same time, the voltage of the pull-down node QB is discharged to a strobe low voltage, thereby turning off the pull-down transistor Td. This allows the strobe turn-on signal of the strobe shift clock (GCLK) to be output to the output terminal Vout through the turned-on pull-up transistor Tu.

[0214] In addition, when the strobe reset signal Vrst is applied, the voltage of the pull-up node Q is discharged to the strobe low voltage through the operation of multiple transistors TQ and TQB set in the node control unit NC, so that the pull-up transistor Tu is turned off. At the same time, the strobe high voltage is charged at the pull-down node QB, so that the pull-down transistor Td is turned on, and the low potential voltage VSS is output to the output terminal Vout through the turned pull-down transistor Td.

[0215] According to an exemplary embodiment of this disclosure, multiple transistors TQ and TQB disposed in the node control unit NC are referred to as switching transistors. The switching transistor of the gating driver 20 may be referred to as the operation of the control buffer transistor bTR. The switching transistor sTR of the gating driver 20 may include a first thin-film transistor TR1. The switching transistor sTR of the gating driver 20 may have a... Figure 3 and Figure 5 The first thin-film transistor TR1 has the same structure, but this disclosure is not limited thereto.

[0216] Figure 8 This is a cross-sectional view of the thin-film transistors bTR and sTR of the gate driver 20.

[0217] Figure 8 The thin-film transistors bTR and sTR can be set in the shift register 50 of the gating driver 20.

[0218] According to an exemplary embodiment of this disclosure, the switching transistor sTR disposed in the gating driver 20 may have, for example, a relationship with... Figure 8 The first thin-film transistor TR1 has the same structure. According to an exemplary embodiment of this disclosure, the buffer transistor bTR disposed in the gating driver 20 may have, for example, the same structure as... Figure 8 It has the same structure as the fourth thin-film transistor TR4.

[0219] Figure 8 The first thin-film transistor TR1 has the same characteristics as... Figure 3 The first thin-film transistor TR1 has the same structure. To avoid redundancy, a detailed description of the switching transistor sTR of the gating driver 20, which has the same structure as the first thin-film transistor TR1, is omitted.

[0220] Reference Figure 8 The fourth thin-film transistor TR4, which is a buffer transistor bTR, includes a fourth auxiliary electrode E4 on the substrate 101, a fourth active layer A4 on the fourth auxiliary electrode E4, and a fourth gate electrode G4 on the fourth active layer A4.

[0221] The fourth auxiliary electrode E4 is electrically connected to the fourth gate electrode G4. The same voltage as the fourth gate electrode G4 can also be applied to the fourth auxiliary electrode E4. The fourth auxiliary electrode E4 overlaps with the fourth active layer A4 and can be used as the gate electrode of the fourth active layer A4. Therefore, according to an exemplary embodiment of this disclosure, the fourth thin-film transistor TR4 can have a dual-gate structure in which gate electrodes are disposed on the upper and lower sides of the fourth active layer A4.

[0222] According to an exemplary embodiment of this disclosure, a first thin-film transistor TR1 having a dual-gate structure can have excellent on-off characteristics.

[0223] Additionally, the fourth active layer A4 includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131. The first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 have already been described. For example, the first oxide semiconductor layer 131 is disposed on a flat surface of the buffer layer 120, and the second oxide semiconductor layer 132 is disposed on the first oxide semiconductor layer 131 located above the flat surface, but this disclosure is not limited thereto.

[0224] The first oxide semiconductor layer 131 can exhibit excellent stability, and the second oxide semiconductor layer 132 can exhibit excellent current characteristics. Therefore, the fourth active layer A4 can exhibit both excellent current characteristics and excellent stability.

[0225] Therefore, the buffer transistor bTR according to an exemplary embodiment of the present disclosure has excellent switching characteristics and excellent drive stability, and can also have excellent current characteristics.

[0226] In the following text, reference will be made to Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F and Figure 9G A manufacturing method and display device 100 according to an exemplary embodiment of the present disclosure are described.

[0227] Figures 9A to 9G This is a schematic cross-sectional view used to illustrate the manufacturing process of a display device 100 according to an exemplary embodiment of the present disclosure.

[0228] Reference Figure 9A To manufacture the display device 100, a first auxiliary electrode E1 is formed on the substrate 101. Additionally, an insulating layer 110 is formed on the first auxiliary electrode E1. The insulating layer 110 may include a first insulating layer 111 and a second insulating layer 112.

[0229] Reference Figure 9A The second auxiliary electrode E2 and the third auxiliary electrode E3 can be formed on the insulating layer 110.

[0230] Additionally, the buffer layer 120 can be formed on the second auxiliary electrode E2 and the third auxiliary electrode E3. The buffer layer 120 may include a first buffer layer 121 and a second buffer layer 122.

[0231] Reference Figure 9B A portion of the buffer layer 120 may be removed to create a first recess 125. The first recess 125 may be formed in the buffer layer 120. As described above, forming the buffer layer 120 may include forming the first recess 125.

[0232] Reference Figure 9C and Figure 9D A first active layer A1, a second active layer A2, and a third active layer A3 are formed on the buffer layer 120. The second active layer A2 may be formed in the first recess 125.

[0233] Specifically, refer to Figure 9C A first oxide semiconductor layer 131 is formed on the buffer layer 120. The first active layer A1 may be formed by the first oxide semiconductor layer 131 formed at the position overlapping with the first auxiliary electrode E1.

[0234] Reference Figure 9D A second oxide semiconductor layer 132 is formed on the first oxide semiconductor layer 131 overlapping with the second auxiliary electrode E2, and a second oxide semiconductor layer 132 is formed on the first oxide semiconductor layer 131 overlapping with the third auxiliary electrode E3.

[0235] The second active layer A2 can be formed by a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 formed in the region overlapping with the second auxiliary electrode E2.

[0236] The third active layer A3 can be formed by a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 formed in the region overlapping with the third auxiliary electrode E3.

[0237] Reference Figure 9E A gate insulating film 140 is formed on the first active layer A1, the second active layer A2, and the third active layer A3.

[0238] Reference Figure 9F A first gate electrode G1, a second gate electrode G2, and a third gate electrode G3 are formed on the gate insulating film 140.

[0239] Reference Figure 9G An interlayer insulating film 150 is formed on the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3. The interlayer insulating film 150 may include a first insulating film 151 and a second insulating film 152.

[0240] In addition, source electrodes S1, S2, S3 and drain electrodes D1, D2, D3 can be formed on the interlayer insulating film 150.

[0241] A display device 100 according to an exemplary embodiment of the present disclosure can be manufactured by means of the process described above.

[0242] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G and Figure 10H This is a schematic cross-sectional view illustrating the manufacturing process of a display device 200 according to another exemplary embodiment of the present disclosure.

[0243] Reference Figure 10A To manufacture the display device 100, a first auxiliary electrode E1 is formed on the substrate 101. Additionally, an insulating layer 110 is formed on the first auxiliary electrode E1. The insulating layer 110 may include a first insulating layer 111 and a second insulating layer 112.

[0244] Reference Figure 10B A second recess 115 is formed in the insulating layer 110. The second recess 115 can be formed by removing a portion of the insulating layer 110.

[0245] Reference Figure 10C The second auxiliary electrode E2 and the third auxiliary electrode E3 are formed on the insulating layer 110. The second auxiliary electrode E2 may be formed on the second recess 115.

[0246] Reference Figure 10DA buffer layer 120 is formed on the second auxiliary electrode E2 and the third auxiliary electrode E3. The buffer layer 120 may include a first buffer layer 121 and a second buffer layer 122.

[0247] In addition, refer to Figure 10D The first recess 125 may be formed in the buffer layer 120. The first recess 125 may be formed on the second recess 115.

[0248] Reference Figure 10E A first oxide semiconductor layer 131 is formed on the buffer layer 120. The first active layer A1 may be formed by the first oxide semiconductor layer 131 formed at the position overlapping with the first auxiliary electrode E1.

[0249] Reference Figure 10F A second oxide semiconductor layer 132 is formed on the first oxide semiconductor layer 131 overlapping with the second auxiliary electrode E2, and a second oxide semiconductor layer 132 is formed on the first oxide semiconductor layer 131 overlapping with the third auxiliary electrode E3.

[0250] The second active layer A2 can be formed by a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 formed in the region overlapping with the second auxiliary electrode E2.

[0251] The third active layer A3 can be formed by a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 formed in the region overlapping with the third auxiliary electrode E3.

[0252] Reference Figure 10G A gate insulating film 140 is formed on a first active layer A1, a second active layer A2 and a third active layer A3, and a first gate electrode G1, a second gate electrode G2 and a third gate electrode G3 are formed on the gate insulating film 140.

[0253] Reference Figure 10H An interlayer insulating film 150 can be formed on the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3, and source electrodes S1, S2, S3 and drain electrodes D1, D2, D3 can be formed on the interlayer insulating film 150.

[0254] A display device 100 according to an exemplary embodiment of the present disclosure can be manufactured by means of the process described above.

[0255] The present disclosure described above is not limited to the exemplary embodiments and drawings described above. It will be apparent to those skilled in the art that various substitutions, modifications and alterations can be made without departing from the technical details of the present disclosure.

[0256] A display device according to an exemplary embodiment of the present disclosure includes both a thin-film transistor with excellent switching characteristics and a thin-film transistor with a large s-factor, resulting in fast response speed and easy grayscale representation.

[0257] According to an exemplary embodiment of this disclosure, since it includes a plurality of thin-film transistors configured to have different driving characteristics according to pixels, the driving characteristics of pixels can be controlled for each color. Therefore, according to an exemplary embodiment of this disclosure, thin-film transistors can be designed to achieve accurate grayscale representation in pixels requiring accurate grayscale representation, and the structure of thin-film transistors can be designed more simply in pixels that do not require accurate grayscale representation. Furthermore, thin-film transistors with high mobility characteristics can be disposed in pixels requiring high mobility.

[0258] According to an exemplary embodiment of this disclosure, the switching transistor can exhibit excellent stability. Therefore, a short channel can be implemented, and even when implemented using a short channel, threshold voltage shift can be suppressed and a stable threshold voltage can be ensured.

[0259] According to an exemplary embodiment of this disclosure, the switching transistor applied to a display device can have a stable threshold voltage while having a short channel length, the driving transistor can have excellent grayscale performance characteristics by having a large s-factor, and can have excellent mobility by including a high-mobility semiconductor material.

[0260] In addition to the effects mentioned above, other features and advantages of this disclosure are described below, or may be clearly understood by those skilled in the art from such description and explanation.

[0261] Cross-reference to related applications

[0262] This application claims priority and benefit to Korean Patent Application No. 10-2024-0193622, filed on December 23, 2024, the entire contents of which are hereby expressly incorporated herein by reference for all purposes.

Claims

1. A display device, the display device comprising: Multiple first thin-film transistors, multiple second thin-film transistors, and multiple third thin-film transistors on a substrate. The first thin-film transistor includes a first active layer and a first gate electrode on the first active layer. The second thin-film transistor includes a second active layer and a second gate electrode on the second active layer. The third thin-film transistor includes a third active layer and a third gate electrode on the third active layer. The distance between the second active layer and the second gate electrode is greater than the distance between the third active layer and the third gate electrode. The first thin-film transistor further includes a first auxiliary electrode between the substrate and the first active layer, and The first auxiliary electrode is electrically connected to the first gate electrode.

2. The display device according to claim 1, wherein, The distance between the first active layer and the first gate electrode is less than the distance between the second active layer and the second gate electrode.

3. The display device according to claim 1, wherein, Each of the second active layer and the third active layer includes: First oxide semiconductor layer; and A second oxide semiconductor layer is disposed on the first oxide semiconductor layer.

4. The display device according to claim 3, wherein, The second oxide semiconductor layer has a higher mobility than the first oxide semiconductor layer.

5. The display device according to claim 4, in, The mobility of the first oxide semiconductor layer is 14 cm. 2 / V·s or less, and The mobility of the second oxide semiconductor layer is 15 cm⁻¹. 2 / V·s or greater.

6. The display device according to claim 3, wherein, The first active layer is formed of the same material as the first oxide semiconductor layer.

7. The display device according to claim 1, further comprising: A gate insulating film is disposed between the first active layer and the first gate electrode, between the second active layer and the second gate electrode, and between the third active layer and the third gate electrode. The thickness of the gate insulating film between the first active layer and the first gate electrode is defined as t1. The thickness of the gate insulating film between the second active layer and the second gate electrode is defined as t2. The thickness of the gate insulating film between the third active layer and the third gate electrode is defined as t3, and Where t2 > t1 and t2 > t3.

8. The display device according to claim 1, further comprising: A gate insulating film is disposed between the first active layer and the first gate electrode, between the second active layer and the second gate electrode, and between the third active layer and the third gate electrode. The thickness of the gate insulating film between the first active layer and the first gate electrode is defined as t1. The thickness of the gate insulating film between the second active layer and the second gate electrode is defined as t2. The thickness of the gate insulating film between the third active layer and the third gate electrode is defined as t3, and Among them, t2>t1>t3.

9. The display device according to claim 1, further comprising: Buffer layer on the substrate, The buffer layer includes a first recess, and The second active layer is disposed in the first recess.

10. The display device according to claim 9, in, The first recess includes a flat surface and an inclined surface, and A portion of the second active layer is disposed on the flat surface, and another portion of the second active layer is disposed on the inclined surface.

11. The display device according to claim 10, in, The second active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, and At least a portion of the first oxide semiconductor layer is disposed on the inclined surface.

12. The display device according to claim 9, further comprising: An insulating layer between the substrate and the buffer layer; as well as The second auxiliary electrode and the third auxiliary electrode on the insulating layer, Wherein, the second auxiliary electrode overlaps with the second active layer, and The third auxiliary electrode is spaced apart from the second auxiliary electrode and overlaps with the third active layer.

13. The display device according to claim 12, in, The second auxiliary electrode has light-shielding properties and is electrically connected to the second active layer. The third auxiliary electrode is light-shielding and is electrically connected to the third active layer.

14. The display device according to claim 13, in, The insulating layer includes a second recess, and The second auxiliary electrode is disposed in the second recess.

15. The display device according to claim 14, in, The second recess includes a flat surface and an inclined surface, and A portion of the second auxiliary electrode is disposed on the flat surface, and another portion of the second auxiliary electrode is disposed on the inclined surface.

16. The display device according to claim 12, wherein, The first auxiliary electrode is disposed between the substrate and the insulating layer.

17. The display device according to claim 1, wherein, The second thin-film transistor has a larger s-factor than the third thin-film transistor.

18. The display device according to claim 1, further comprising: The first pixel and the second pixel on the substrate, Wherein, the first pixel includes: One of the plurality of first thin-film transistors; One of the plurality of second thin-film transistors; and A first display element, the first display element being connected to the second thin-film transistor, and The second pixel includes: Another of the plurality of first thin-film transistors; One of the plurality of third thin-film transistors; and A second display element is connected to the third thin-film transistor.

19. The display device according to claim 18, in, The first pixel emits green light, and The second pixel emits light of a color other than green.

20. The display device according to claim 19, wherein, The second thin-film transistor has a larger s-factor than the third thin-film transistor.

21. The display device according to claim 18, further comprising: A gating driver, the gating driver being used to provide a scan signal to each of the first pixel and the second pixel. The gating driver includes a buffer transistor for controlling the application of the scan signal and a switching transistor for controlling the operation of the buffer transistor. The switching transistor includes the first thin-film transistor.

22. The display device according to claim 21, in, The buffer transistor includes: The fourth auxiliary electrode on the substrate; The fourth active layer on the fourth auxiliary electrode; and The fourth gate electrode on the fourth active layer, The fourth active layer includes: First oxide semiconductor layer; and A second oxide semiconductor layer on the first oxide semiconductor layer, and The fourth auxiliary electrode is electrically connected to the fourth gate electrode.

23. A method for manufacturing a display device, the method comprising: A first auxiliary electrode is formed on the substrate; A buffer layer is formed on the first auxiliary electrode; A first active layer, a second active layer, and a third active layer are formed on the buffer layer; A gate insulating film is formed on the first active layer, the second active layer and the third active layer; as well as A first gate electrode, a second gate electrode, and a third gate electrode are formed on the gate insulating film. The formation of the buffer layer includes forming a first recess. The second active layer is formed in the first recess, and The first auxiliary electrode is electrically connected to the first gate electrode.

24. The method for manufacturing a display device according to claim 23, further comprising: An insulating layer is formed on the substrate prior to the formation of the buffer layer; as well as A second auxiliary electrode and a third auxiliary electrode are formed on the insulating layer. The step of forming the insulating layer includes forming a second recess, and The second auxiliary electrode is formed in the second recess.

25. The method for manufacturing a display device according to claim 23, wherein, The distance between the second active layer and the second gate electrode is greater than the distance between the third active layer and the third gate electrode.

26. The method for manufacturing a display device according to claim 25, wherein, The distance between the second active layer and the second gate electrode is greater than the distance between the first active layer and the first gate electrode.

27. The method for manufacturing a display device according to claim 23, wherein, The distance between the second active layer and the second gate electrode is greater than the distance between the first active layer and the first gate electrode, and the distance between the first active layer and the first gate electrode is greater than the distance between the third active layer and the third gate electrode.

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