Light emitting diode display device and display panel

Abstract

The present disclosure provides a light emitting diode display device and a display panel included therein. A light emitting diode display device includes a substrate including a pixel including a light emitting area and a non-light emitting area, a first insulating layer disposed on the substrate, a step compensation pattern disposed on the first insulating layer and corresponding to the light emitting area, a second insulating layer covering the step compensation pattern, a first electrode disposed on the second insulating layer and corresponding to the step compensation pattern, and a pixel definition layer disposed on the second insulating layer and disposed in the non-light emitting area, the pixel definition layer covering an edge of the first electrode and having an opening corresponding to a center of the first electrode, wherein the step compensation pattern has the same shape as the opening.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0193961, filed on December 23, 2024 in the Republic of Korea, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device capable of preventing light leakage at the edges and providing a high-quality image. Background Technology

[0004] Recently, there has been an increase in demand for flat panel display devices with small footprints. Among flat panel display devices, the technology of light-emitting display devices is developing rapidly.

[0005] LED display devices can be divided into organic LED display devices and inorganic LED display devices.

[0006] For example, in an organic light-emitting diode (OLED) display device, holes from the anode and electrons from the cathode combine to generate excitons in the organic light-emitting layer, and the excitons transition from an excited state to the ground state. As a result, light is emitted from the OLED. Summary of the Invention

[0007] This disclosure relates to a light-emitting diode display device that substantially eliminates one or more problems associated with the limitations and disadvantages of related conventional technologies.

[0008] The purpose of this disclosure is to provide a light-emitting diode display device with improved luminous efficiency and lifespan.

[0009] The purpose of this disclosure is to provide a light-emitting diode display device that includes a first electrode having improved flatness.

[0010] Additional features and advantages of this disclosure are set forth in the description which follows, and will be apparent from the description, or from practice of the disclosure. The purposes and other advantages of this disclosure are realized and obtained through the features described herein and in the accompanying drawings.

[0011] To achieve these and other advantages of embodiments according to this disclosure, as described herein, one aspect of this disclosure is a light-emitting diode display device comprising: a substrate including pixels, the pixels including light-emitting regions and non-light-emitting regions; a first insulating layer disposed on the substrate; a step compensation pattern disposed on the first insulating layer and corresponding to the light-emitting regions; a second insulating layer covering the step compensation pattern; a first electrode disposed on the second insulating layer and corresponding to the step compensation pattern; and a pixel defining layer disposed on the second insulating layer and disposed in the non-light-emitting regions, the pixel defining layer covering the edge of the first electrode and having an opening corresponding to the center of the first electrode, wherein the step compensation pattern has the same shape as the opening.

[0012] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to further explain the claimed contents of this disclosure. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0014] Figure 1 This is a schematic diagram illustrating an organic light-emitting display device according to the present disclosure.

[0015] Figure 2 This is a schematic circuit diagram of the organic light-emitting display device disclosed herein.

[0016] Figure 3 This is a schematic plan view showing a light-emitting diode display device according to a first embodiment of the present disclosure.

[0017] Figure 4 This is a cross-sectional schematic diagram showing a light-emitting diode display device according to a first embodiment of the present disclosure.

[0018] Figure 5 This is a schematic plan view showing a light-emitting diode display device according to a second embodiment of the present disclosure.

[0019] Figure 6 This is a cross-sectional schematic diagram showing a light-emitting diode display device according to a second embodiment of the present disclosure.

[0020] Figure 7 This is a cross-sectional schematic diagram showing an organic light-emitting diode display device according to a third embodiment of the present disclosure.

[0021] Figure 8This is a schematic plan view showing a light-emitting diode display device according to the fourth embodiment of the present disclosure.

[0022] Figure 9 This is a cross-sectional schematic diagram illustrating a fourth embodiment of the light-emitting diode display device according to the present disclosure. Detailed Implementation

[0023] Reference will now be made in detail to various aspects of this disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted where such obscuration unnecessarily obscures the essential points of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals always denote the same elements. The names of the various elements used in the following explanation are chosen solely for ease of writing and may therefore differ from those used in actual products.

[0024] The advantages and features of this disclosure, as well as methods for implementing them, will become apparent from the aspects described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the aspects disclosed below, but can be implemented in various different forms, and only these aspects allow for the completion of the content disclosed herein. This disclosure is provided to fully inform those skilled in the art of this disclosure of its scope.

[0025] The shapes, dimensions, scales, angles, numbers, etc., disclosed in the accompanying drawings, which are used to explain various aspects of this disclosure, are illustrative, and this disclosure is not limited to what is shown. Throughout the specification, the same reference numerals refer to the same elements. Furthermore, in describing this disclosure, a detailed description of the relevant known art may be omitted if it is determined that such a detailed description unnecessarily obscures the subject matter of this disclosure. When terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. When a component is indicated in the singular, the plural is included unless otherwise stated.

[0026] The expression "at least one of a, b, and c" described throughout this specification may encompass "only a", "only b", "only c", "a and b", "a and c", "b and c", or "all of a, b, and c". The advantages and features of this disclosure, as well as the methods for implementing them, will become apparent from the embodiments described in detail below with reference to the accompanying drawings.

[0027] When interpreting a component, it is interpreted as including a range of errors or tolerances, even though there is no explicit description of such a range of errors or tolerances.

[0028] When describing positional relationships, for example, when the positional relationship between two parts is described as such as "on," "above," "below," and "beside," one or more other parts may be placed between the two parts, unless more restrictive terms such as "only" or "directly" are used.

[0029] When describing temporal relationships, such as when time sequence is described as “after,” “next,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “only,” “immediately,” or “directly” are used.

[0030] For ease of explanation, the area, length, or thickness of each component described in the specification is shown, and this disclosure is not necessarily limited to the area and thickness of the components shown.

[0031] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0032] Features of various aspects of this disclosure may be linked or combined with each other, either partially or in whole, and may interoperate and be technically driven differently from each other, as will be fully understood by those skilled in the art. Various aspects of this disclosure may be performed independently of each other or may be performed together in an interdependent relationship.

[0033] Unless otherwise specified, the transistors constituting the pixel circuits of this disclosure may include at least one of oxide thin-film transistors (oxide TFTs), amorphous silicon TFTs (a-Si TFTs), and low-temperature polycrystalline silicon (LTPS) TFTs.

[0034] Reference will now be made in detail to some examples and preferred embodiments shown in the accompanying drawings.

[0035] Figure 1 This is a schematic diagram illustrating a light-emitting diode display device according to the present disclosure.

[0036] The light-emitting diode display device can be an OLED display device that uses organic light-emitting materials and includes organic light-emitting diodes (OLEDs), or an inorganic light-emitting diode display device that uses inorganic light-emitting materials and includes inorganic light-emitting diodes.

[0037] like Figure 1 As shown, an embodiment of the present disclosure of a light-emitting diode display device includes a timing control unit 120 (e.g., a circuit), a data driving unit 122 (e.g., a circuit), a first gate driving unit 124 and a second gate driving unit 126 (e.g., a circuit), and a display panel 128.

[0038] The timing control unit 120 uses image signals transmitted from an external system such as a graphics card or television system and multiple timing signals, including a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, to generate image data RGB, data control signals, and gate control signals. The timing control unit 120 transmits image data and data control signals to the data driving unit 122, and transmits gate control signals to the first gate driving unit 124 and the second gate driving unit 126.

[0039] Data drive unit 122 generates (using image data and data control signals sent from timing control unit 120) Figure 2 The data signal (data voltage) Vda is sent to the data line DL of the display panel 128.

[0040] The first gate driving unit 124 and the second gate driving unit 126 generate gate control signals transmitted from the timing control unit 120. Figure 2 The gate signals (gate voltages) Vsc and Vse are applied to the gate line GL of the display panel 128.

[0041] The first gate driving unit 124 and the second gate driving unit 126 may have a gate in panel (GIP) type formed in the non-display area NDA of the substrate of the display panel 128 having gate lines GL, data lines DL and pixels P.

[0042] Despite Figure 1 In one embodiment, the first gate driving unit 124 and the second gate driving unit 126 are disposed in two sides of the display panel 128, but in another embodiment, a gate driving unit may be disposed in one side of the display panel 128.

[0043] Display panel 128 includes a display area DA at its center and a non-display area NDA surrounding the display area DA. Display panel 128 uses gate signals Vsc and Vse and data signal Vda to display images. In order to display images, display panel 128 includes multiple pixels P, multiple gate lines GL, and multiple data lines DL in the display area DA.

[0044] Each of the plurality of pixels P is one of the first, second, third, and fourth pixels P1, P2, P3, and P4, and the gate line GL and the data line DL intersect each other to define the first, second, third, and fourth pixels P1, P2, P3, and P4. Each of the first, second, third, and fourth pixels P1, P2, P3, and P4 is connected to the gate line GL and the data line DL. For example, the first, second, third, and fourth pixels P1, P2, P3, and P4 and SP4 can correspond to red, green, blue, and white, respectively.

[0045] Each of the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4 may include, for example, ( Figure 2 (of) switching transistor Tsw, ( Figure 2 The driving transistor Tdr and ( Figure 2 The multiple transistors of the sensing transistor Tse, ( Figure 2 The storage capacitor Cst and ( Figure 2 (The light-emitting diode D.)

[0046] Figure 2 This is a schematic circuit diagram of the organic light-emitting display device disclosed herein.

[0047] exist Figure 2 In the embodiment of the present disclosure, each of the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4 of the display panel 128 of the light-emitting diode display device includes a switching transistor Tsw, a driving transistor Tdr, a sensing transistor Tse, a storage capacitor Cst, and a light-emitting diode D.

[0048] Despite Figure 2 In one embodiment, each of the first, second, third, and fourth pixels P1, P2, P3, and P4 has a 3T1C structure with three transistors and a storage capacitor. However, in another embodiment, each of the first, second, third, and fourth pixels P1, P2, P3, and P4 may have one of a 6T1C structure with six transistors and a storage capacitor, a 7T1C structure with seven transistors and a storage capacitor, or an 8T1C structure with eight transistors and a storage capacitor.

[0049] Despite Figure 2 In one embodiment, the switching transistor Tsw, the driving transistor Tdr, and the sensing transistor Tse can be negative, but in another embodiment, at least one of the switching transistor Tsw, the driving transistor Tdr, and the sensing transistor Tse can be positive.

[0050] The switching transistor Tsw is switched according to the scan signal Vsc to transmit the data signal Vda to the first node N1.

[0051] The gate of the switching transistor Tsw is connected to the gate line GL to receive the scan signal Vsc, the drain of the switching transistor Tsw is connected to the data line DL to receive the data signal Vda, and the source of the switching transistor Tsw is connected to the first node N1.

[0052] The driving transistor Tdr switches according to the voltage of the first node N1 to transmit the high-level signal (high-level voltage) Vdd to the second node N2.

[0053] The gate of the driving transistor Tdr is connected to the first node N1, the drain of the driving transistor Tdr is connected to the high-level power supply line to receive the high-level signal Vdd, and the source of the driving transistor Tdr is connected to the second node N2.

[0054] The sensing transistor Tse switches according to the sensing signal (sensing voltage) Vse to transmit the reference signal (reference voltage) Vre to the second node N2 or to transmit the voltage of the second node N2 to the reference line.

[0055] The gate electrode of the sensing transistor Tse is connected to the gate line GL to receive the sensing signal Vse, the drain electrode of the sensing transistor Tse is connected to the reference line to receive the reference signal Vre or to transmit the voltage of the second node N2 to the reference line, and the source electrode of the sensing transistor Tse is connected to the second node N2.

[0056] The storage capacitor Cst holds the data signal Vda provided to the first node N1 for one frame and stores the threshold voltage Vth of the driving transistor Tdr.

[0057] The first capacitor electrode of the storage capacitor Cst is connected to the first node N1, and the second capacitor electrode of the storage capacitor Cst is connected to the second node N2.

[0058] The light-emitting diode D emits light with a brightness proportional to the current driving the transistor Tdr.

[0059] The anode of LED D is connected to the second node N2, and the cathode of LED D is connected to the low-level power supply line to receive the low-level signal (low-level voltage) Vss.

[0060] The source of the switching transistor Tsw, the gate of the driving transistor Tdr, and the first capacitor electrode of the storage capacitor Cst constitute the first node N1, and the source of the driving transistor Tdr, the source of the sensing transistor Tse, the second capacitor electrode of the storage capacitor Cst, and the anode of the light-emitting diode D constitute the second node N2.

[0061] The light-emitting diode D can display an image with brightness corresponding to the RGB values ​​of the image data, based on the driving of the pixel circuits of the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4.

[0062] Figure 3 This is a schematic plan view showing a light-emitting diode display device according to a first embodiment of the present disclosure.

[0063] Reference Figure 3 According to a first embodiment of the present disclosure, a light-emitting diode display device 100 includes: a first pixel P1; a second pixel P2; a third pixel P3; a first signal line SL1, a second signal line SL2, and a third signal line SL3, the first signal line SL1, the second signal line SL2, and the third signal line SL3 intersecting with the first pixel P1 and the third pixel P3 and extending in one direction; and a fourth signal line SL4, the fourth signal line SL4 intersecting with the second pixel P2 and extending parallel to the first signal line SL1, the second signal line SL2, and the third signal line SL3.

[0064] For example, the first pixel P1 can be a red pixel, the second pixel P2 can be a green pixel, and the third pixel P3 can be a blue pixel. The light-emitting diode display device 100 may also include a fourth pixel as a white pixel.

[0065] The first pixel P1 and the third pixel P3 can have the same shape, and the second pixel P2 can have a different shape than the first pixel P1 and the third pixel P3. However, the shapes of the first pixel P1, the second pixel P2, and the third pixel P3 are not restricted.

[0066] The area of ​​the third pixel P3 can be larger than the area of ​​each of the first pixel P1 and the second pixel P2, and the area of ​​the first pixel P1 can be equal to or smaller than the area of ​​the second pixel P2. However, the areas of the first pixel P1, the second pixel P2, and the third pixel P3 are not limited.

[0067] First pixel P1 and third pixel P3 are arranged alternately along the first direction X. Second pixel P2 is spaced apart from the pixel column including first pixel P1 and third pixel P3 along the second direction Y and is arranged along the first direction X. The second direction Y intersects the first direction X. The second direction Y may be perpendicular to the first direction X.

[0068] ( Figure 2 The first electrode 160a of the light-emitting diode D is arranged in an island shape in each of the first pixel P1, the second pixel P2 and the third pixel P3.

[0069] Each of the first to fourth signal lines SL1, SL2, SL3 and SL4 extends along the second direction Y and is spaced apart from each other in the first direction X. The first signal line SL1 is located between the second signal line SL2 and the third signal line SL3, and the fourth signal line SL4 is located on one side of the second signal line SL2 and on one side of the third signal line SL3.

[0070] The first signal line SL1 can be used to apply ( Figure 2 The high-level signal line Vdd is the high-level signal line, and each of the second signal line SL2 and the third signal line SL3 can be ( Figure 1 The data line DL. The fourth signal line SL4 can be used to apply ( Figure 2 (The reference signal line of the reference signal Vre)

[0071] Figure 4 This is a cross-sectional schematic diagram showing a light-emitting diode display device according to a first embodiment of the present disclosure. Figure 4 It shows along Figure 3 The cross-sectional view taken from line I-I'.

[0072] like Figure 4 As shown, the light-emitting diode display device 100 includes: a substrate 102 including a pixel P; a pixel circuit layer disposed above the substrate 102 and including a first transistor T1 and a second transistor T2; a first insulating layer 150a disposed above the pixel circuit layer; a first signal line SL1, a second signal line SL2, and a third signal line SL3 disposed above the first insulating layer 150a; a second insulating layer 150b covering the first signal line SL1, the second signal line SL2, and the third signal line SL3; and a light-emitting diode D disposed on the second insulating layer 150b. The pixel circuit layer corresponds to the pixel P.

[0073] Multiple pixels P are defined on substrate 102. Pixel P includes a light-emitting region EA and a non-light-emitting region NEA. The non-light-emitting region NEA may surround the light-emitting region EA. Substrate 102 may be a glass substrate or a plastic substrate.

[0074] In embodiments of this disclosure, substrate 102 may have a three-layer structure, including a first polyimide (PI) layer, a second PI layer, and an interlayer inorganic layer located between the first PI layer and the second PI layer.

[0075] A first buffer layer 104 is disposed on the substrate 102. External moisture and / or oxygen can be blocked by the first buffer layer 104.

[0076] A first light-shielding pattern 106 is disposed on the first buffer layer 104. Light from one side of the substrate 102 can be blocked by the first light-shielding pattern 106.

[0077] The first capacitor electrode 108 is disposed on the first buffer layer 104. The first capacitor electrode 108 may be spaced apart from the first light-shielding pattern 106.

[0078] The second buffer layer 110 is disposed above the substrate 102 to cover the first light-shielding pattern 106 and the first capacitor electrode 108. External moisture and / or oxygen can be blocked by the second buffer layer 110.

[0079] A second capacitor electrode 112, corresponding to the first capacitor electrode 108, is disposed on the second buffer layer 110. The second capacitor electrode 112 overlaps with the first capacitor electrode 108. The first capacitor electrode 108, the second buffer layer 110, and the second capacitor electrode 112 constitute a storage capacitor Cst.

[0080] A third buffer layer 114 is disposed above the substrate 102 to cover the second capacitor electrode 112. External moisture and / or oxygen can be blocked by the third buffer layer 114.

[0081] The second light-shielding pattern 116 is disposed on the third buffer layer 114. Light from one side of the substrate 102 can be blocked by the second light-shielding pattern 116.

[0082] A fourth buffer layer 118 is disposed on the substrate 102 to cover the second light-shielding pattern 116. External moisture and / or oxygen can be blocked by the fourth buffer layer 118.

[0083] A first semiconductor layer 130 and a second semiconductor layer 132 spaced apart from the first semiconductor layer 130 are disposed on the fourth buffer layer 118. The first semiconductor layer 130 corresponds to the first light-shielding pattern 106, and the second semiconductor layer 132 corresponds to the second light-shielding pattern 116.

[0084] Each of the first semiconductor layer 130 and the second semiconductor layer 132 may include one of a polycrystalline semiconductor material, an amorphous semiconductor material, and an oxide semiconductor material.

[0085] In embodiments of this disclosure, each of the first semiconductor layer 130 and the second semiconductor layer 132 may include an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (CuO2), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO).

[0086] In embodiments of this disclosure, each of the first semiconductor layer 130 and the second semiconductor layer 132 may include a polycrystalline semiconductor material such as polycrystalline silicon.

[0087] In embodiments of this disclosure, one of the first semiconductor layer 130 and the second semiconductor layer 132 may include an oxide semiconductor material, and the other of the first semiconductor layer 130 and the second semiconductor layer 132 may include a polycrystalline semiconductor material. In this case, the first semiconductor layer 130 and the second semiconductor layer 132 may be disposed at different layers.

[0088] The first semiconductor layer 130 includes a first channel region 130a, a first drain region 130b located on one side of the first channel region 130a, and a first source region 130c located on the other side of the first channel region 130a. Each of the first drain region 130b and the first source region 130c may be doped with impurities.

[0089] The second semiconductor layer 132 includes a second channel region 132a, a second drain region 132b located on one side of the second channel region 132a, and a second source region 132c located on the other side of the second channel region 132a. Each of the second drain region 132b and the second source region 132c may be doped with impurities.

[0090] A gate insulating layer 134 covering the first semiconductor layer 130 and the second semiconductor layer 132 is disposed above the fourth buffer layer 118.

[0091] A first gate electrode 136 corresponding to the first channel region 130a of the first semiconductor layer 130 and a second gate electrode 138 corresponding to the second channel region 132a of the second semiconductor layer 132 are disposed on the gate insulating layer 134.

[0092] A first interlayer insulating layer 140 covering the first gate electrode 136 and the second gate electrode 138 is disposed above the gate insulating layer 134.

[0093] A first source electrode 142a, a first drain electrode 142b, a second source electrode 144a, and a second drain electrode 144b are disposed on the first interlayer insulating layer 140, spaced apart from each other.

[0094] The first source electrode 142a and the first drain electrode 142b are connected to the first source region 130c and the first drain region 130b of the first semiconductor layer 130 through contact holes in the first interlayer insulating layer 140 and the gate insulating layer 134, respectively. Furthermore, the first source electrode 142a is connected to the first capacitor electrode 108 through contact holes in the first interlayer insulating layer 140, the gate insulating layer 134, the fourth buffer layer 118, the third buffer layer 114, and the second buffer layer 110.

[0095] The second source electrode 144a and the second drain electrode 144b are connected to the second source region 132c and the second drain region 132b of the second semiconductor layer 132 through contact holes in the first interlayer insulating layer 140 and the gate insulating layer 134, respectively. Furthermore, the second source electrode 144a is connected to the second capacitor electrode 112 through contact holes in the first interlayer insulating layer 140, the gate insulating layer 134, the fourth buffer layer 118, and the third buffer layer 114.

[0096] The first semiconductor layer 130, the first gate electrode 136, the first source electrode 142a, and the first drain electrode 142b constitute the first transistor T1, and the second semiconductor layer 132, the second gate electrode 138, the second source electrode 144a, and the second drain electrode 144b constitute the second transistor T2. Each of the first transistor T1 and the second transistor T2 can be a thin-film transistor.

[0097] An insulating layer 150 covering the first source electrode 142a, the first drain electrode 142b, the second source electrode 144a, and the second drain electrode 144b is disposed on the first interlayer insulating layer 140. That is, the insulating layer 150 covers the first transistor T1 and the second transistor T2.

[0098] The insulating layer 150 may include a first insulating layer 150a on the first source electrode 142a, the first drain electrode 142b, the second source electrode 144a, and the second drain electrode 144b, and a second insulating layer 150b on the first insulating layer 150a. For example, the first insulating layer 150a and the second insulating layer 150b may be formed of the same material.

[0099] A connection electrode 152 corresponding to the second source electrode 144a is disposed on the first insulating layer 150a. The connection electrode 152 can be connected to the second source electrode 144a through a contact hole formed in the first insulating layer 150a.

[0100] A first signal line SL1, a second signal line SL2, and a third signal line SL3 are disposed on a first insulating layer 150a. Each of the first signal line SL1, the second signal line SL2, and the third signal line SL3 is spaced apart from the connecting electrode 152. In addition, the first signal line SL1, the second signal line SL2, and the third signal line SL3 are spaced apart from each other.

[0101] The second insulating layer 150b covers the connecting electrode 152 and the first signal line SL1, the second signal line SL2, and the third signal line SL3, and the first electrode 160a is disposed on the second insulating layer 150b. The first electrode 160a is connected to the connecting electrode 152 through a contact hole formed in the second insulating layer 150b.

[0102] First electrodes 160a are formed in each pixel region P. The first electrode 160a may be an anode and may include a transparent conductive oxide (TCO) layer and a reflective layer, the transparent conductive oxide layer being formed of a conductive material (e.g., a transparent conductive oxide material) having a relatively high work function.

[0103] The transparent conductive oxide material may include at least one of the following: indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), tin oxide (SnO), zinc oxide (ZnO), indium copper oxide (ICO), and aluminum zinc oxide (Al:ZnO, AZO), and the reflective layer may include at least one of the following: silver (Ag), an alloy of Ag, and one of palladium (Pd), Cu, In, and Nd, as well as an aluminum palladium copper alloy (APC). For example, the first electrode 160a may have a two-layer structure of Ag / ITO or APC / ITO, or a three-layer structure of ITO / Ag / ITO or ITO / APC / ITO.

[0104] A pixel defining layer (e.g., a dam) 154 is formed on the second insulating layer 150b at the boundary of the pixel region. The pixel defining layer 154 covers the edge of the first electrode 160a and has an opening to expose the center of the first electrode 160a.

[0105] Although not shown, spacers can be provided on the pixel delimiting layer 154.

[0106] A light-emitting layer 160b is provided, covering the first electrode 160a and the pixel defining layer 154. The light-emitting layer 160b contacts the first electrode 160a in the opening of the pixel defining layer 154. That is, the light-emitting layer 160b can be formed to contact the upper surface of the first electrode 160a and the side and upper surfaces of the pixel defining layer 154.

[0107] For example, the light-emitting layer 160b may include a light-emitting material layer comprising a host and a dopant. Alternatively, the light-emitting material layer of the light-emitting layer 160b may include an inorganic light-emitting material, such as a quantum dot. The light-emitting layer 160b may also include at least one of a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer to have a multilayer structure.

[0108] The second electrode 160c is formed above the substrate 102 at the location where the light-emitting layer 160b is formed. The second electrode 160c covers the entire surface of the display area. The second electrode 160c can be formed of at least one of ITO, IZO, Al, Ag, Cu, Pb, magnesium (Mg), Mo, Ti, and alloys thereof, and has a single-layer structure or a multi-layer structure. The second electrode 260c can have a thin profile (small thickness) to provide light transmission characteristics (or semi-transmission characteristics).

[0109] The first electrode 160a, the organic light-emitting layer 160b, and the second electrode 160c constitute a light-emitting diode D. The light-emitting diode D can emit red light, green light, and blue light in the red pixel region, the green pixel region, and the blue pixel region, respectively.

[0110] In the light-emitting diode display device 100, light from the light-emitting layer 160b passes through the second electrode 160c to display an image. That is, the light-emitting diode display device 100 of this disclosure is a top-emitting type display device.

[0111] An encapsulation layer (or encapsulation film) 162 is formed on the second electrode 160c to prevent moisture from penetrating into the light-emitting diode D. The encapsulation layer 162 may include, but is not limited to, a first inorganic insulating layer 162a, an organic insulating layer 162b, and a second inorganic insulating layer 162c stacked in sequence.

[0112] A fifth buffer layer 164 is disposed on the encapsulation layer 162 and over the entire substrate 102. External moisture and / or oxygen can be blocked by the fifth buffer layer 164.

[0113] The bridging pattern 166 is disposed on the fifth buffer layer 164. When the fifth buffer layer 164 is omitted, the bridging pattern 166 can be directly disposed on the encapsulation layer 162.

[0114] The second interlayer insulating layer 170 is disposed on the fifth buffer layer 164 and over the entire substrate 102.

[0115] Touch electrodes 172 are disposed on the second interlayer insulating layer 170. The touch electrodes include a first touch electrode 172a and a second touch electrode 172b. The first touch electrodes 172a are spaced apart from each other, and the second touch electrode 172b is disposed between the first touch electrodes 172a. The second touch electrode 172b is connected to the bridging pattern 166 through a contact hole formed in the second interlayer insulating layer 170.

[0116] The first protective layer 174 is disposed on the first touch electrode 172a and the second touch electrode 172b and is disposed over the entire substrate 102.

[0117] A black matrix 175 is disposed on the first protective layer 174. The black matrix 175 is disposed within the boundary of the pixel region P and has an opening corresponding to the light-emitting diode D. That is, the opening of the black matrix 175 can correspond to the opening of the pixel defining layer 154.

[0118] A color filter layer 177 corresponding to the opening of the black matrix 175 is disposed on the first protective layer 174, and a second protective layer 179 is disposed on the black matrix 175 and the color filter layer 177 and is disposed above the entire substrate 102.

[0119] In the first embodiment of the light-emitting diode display device 100 according to the present disclosure, since the first signal line SL1, the second signal line SL2 and the third signal line SL3 are configured to intersect with the pixel P, the limitation on the width of the first signal line SL1, the second signal line SL2 and the third signal line SL3 can be minimized.

[0120] However, since the first signal line SL1, the second signal line SL2, and the third signal line SL3 are disposed below the first electrode 160a of the light-emitting diode D through the second insulating layer 150b, each of the second insulating layer 150b and the first electrode 160a has an uneven (e.g., non-flat) surface caused by the step difference generated by the first signal line SL1, the second signal line SL2, and the third signal line SL3. Therefore, the luminous efficiency and / or lifespan of the light-emitting diode D and the light-emitting diode display device 100 are reduced.

[0121] Figure 5 This is a schematic plan view showing a light-emitting diode display device according to a second embodiment of the present disclosure.

[0122] Reference Figure 5 According to a second embodiment of the present disclosure, a light-emitting diode display device 200 includes: a first pixel P1; a second pixel P2; a third pixel P3; a first signal line SL1, a second signal line SL2, and a third signal line SL3, the first signal line SL1, the second signal line SL2, and the third signal line SL3 intersecting with the first pixel P1 and the third pixel P3 and extending in one direction; and a fourth signal line SL4, the fourth signal line SL4 intersecting with the second pixel P2 and extending parallel to the first signal line SL1, the second signal line SL2, and the third signal line SL3.

[0123] For example, the first pixel P1 can be a red pixel, the second pixel P2 can be a green pixel, and the third pixel P3 can be a blue pixel. The light-emitting diode display device 200 may also include a fourth pixel as a white pixel.

[0124] The first pixel P1 and the third pixel P3 can have the same shape, and the second pixel P2 can have a different shape than the first pixel P1 and the third pixel P3. However, the shapes of the first pixel P1, the second pixel P2, and the third pixel P3 are not restricted.

[0125] The area of ​​the third pixel P3 can be larger than the area of ​​each of the first pixel P1 and the second pixel P2, and the area of ​​the first pixel P1 can be equal to or smaller than the area of ​​the second pixel P2. However, the areas of the first pixel P1, the second pixel P2, and the third pixel P3 are not limited.

[0126] First pixel P1 and third pixel P3 are arranged alternately along the first direction X. Second pixel P2 is spaced apart from the pixel column including first pixel P1 and third pixel P3 along the second direction Y and is arranged along the first direction X. The second direction Y intersects the first direction X. The second direction Y may be perpendicular to the first direction X.

[0127] The first to fourth signal lines SL1, SL2, SL3 and SL4 extend along the second direction Y and are spaced apart from each other in the first direction X. The first signal line SL1 is located between the second signal line SL2 and the third signal line SL3, and the fourth signal line SL4 is located on one side of the second signal line SL2 and on one side of the third signal line SL3.

[0128] The first signal line SL1 can be used to apply ( Figure 2 The high-level signal line Vdd is the high-level signal line, and each of the second signal line SL2 and the third signal line SL3 can be ( Figure 1 The data line DL. The fourth signal line SL4 can be used to apply ( Figure 2 (The reference signal line of the reference signal Vre)

[0129] exist Figure 5 In the first pixel P1, the second pixel P2, and the third pixel P3, a first signal line SL1, a second signal line SL2, and a third signal line SL3 are disposed in each of the first pixel P1 and the third pixel P3, and a fourth signal line SL4 is disposed in the second pixel P2. However, in the LED display device 200 of this disclosure, the arrangement of pixels P1, P2, and P3, as well as signal lines SL1, SL2, SL3, and SL4, is not limited.

[0130] ( Figure 2 The first electrode 260a of the light-emitting diode D is arranged in an island shape in each of the first pixel P1, the second pixel P2 and the third pixel P3.

[0131] Additionally, a step compensation pattern 280 corresponding to the first electrode 260a is provided in each of the first pixel P1, the second pixel P2, and the third pixel P3 and is provided below the first electrode 260a.

[0132] Figure 6 This is a cross-sectional schematic diagram of a light-emitting diode display device according to the second embodiment of this disclosure. Figure 6 It shows along Figure 5 The cross-sectional view taken from line II-II'.

[0133] like Figure 6As shown, the light-emitting diode display device 200 includes: a substrate 202 including a pixel P; a pixel circuit layer disposed above the substrate 202 and including a first transistor T1 and a second transistor T2; a first insulating layer 250a disposed above the pixel circuit layer; a first signal line SL1, a second signal line SL2, and a third signal line SL3 disposed above the first insulating layer 250a; a second insulating layer 250b covering the first signal line SL1, the second signal line SL2, and the third signal line SL3; a step compensation pattern 280 disposed on the second insulating layer 250b; a third insulating layer 250c disposed on the step compensation pattern 280; and a light-emitting diode D disposed on the third insulating layer 250b. The pixel circuit layer corresponds to the pixel P.

[0134] Multiple pixels P are defined on substrate 202. Pixel P includes a light-emitting region EA and a non-light-emitting region NEA. The non-light-emitting region NEA may surround the light-emitting region EA. Substrate 202 may be a glass substrate or a plastic substrate. For example, substrate 202 may be one of a polyimide (PI) substrate, a polyethersulfone (PES) substrate, a polyethylene naphthalate (PEN) substrate, a polyethylene terephthalate (PET) substrate, and a polycarbonate (PC) substrate.

[0135] In embodiments of this disclosure, substrate 202 may have a three-layer structure, including a first polyimide (PI) layer, a second PI layer, and an interlayer inorganic layer located between the first PI layer and the second PI layer.

[0136] A first buffer layer 204 is disposed on the substrate 202. External moisture and / or oxygen can be blocked by the first buffer layer 204. For example, the first buffer layer 204 can be formed of an inorganic insulating material, such as silicon oxide or silicon nitride. The first buffer layer 204 can have a single-layer structure or a multi-layer structure.

[0137] A first light-shielding pattern 206 is disposed on the first buffer layer 204. Light from one side of the substrate 202 can be blocked by the first light-shielding pattern 206.

[0138] The first capacitor electrode 208 is disposed on the first buffer layer 204. The first capacitor electrode 208 may be spaced apart from the first light-shielding pattern 206.

[0139] Each of the first light-shielding pattern 204 and the first capacitor electrode 208 can be formed of the same material. For example, each of the first light-shielding pattern 204 and the first capacitor electrode 208 can be formed of a metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Furthermore, each of the first light-shielding pattern 204 and the first capacitor electrode 208 can have a single-layer structure or a multi-layer structure.

[0140] A second buffer layer 210 is disposed above the substrate 202 to cover the first light-shielding pattern 206 and the first capacitor electrode 208. External moisture and / or oxygen can be blocked by the second buffer layer 210. For example, the second buffer layer 210 can be formed of an inorganic insulating material, such as silicon oxide or silicon nitride. The second buffer layer 210 can have a single-layer structure or a multi-layer structure.

[0141] A second capacitor electrode 212, corresponding to the first capacitor electrode 208, is disposed on the second buffer layer 210. For example, the second capacitor electrode 212 can be formed of a metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Furthermore, the second capacitor electrode 212 can have a single-layer structure or a multi-layer structure.

[0142] The second capacitor electrode 212 overlaps with the first capacitor electrode 208. The first capacitor electrode 208, the second buffer layer 210, and the second capacitor electrode 212 constitute the storage capacitor Cst.

[0143] A third buffer layer 214 is disposed above the substrate 202 to cover the second capacitor electrode 212. External moisture and / or oxygen can be blocked by the third buffer layer 214. For example, the third buffer layer 214 can be formed of an inorganic insulating material, such as silicon oxide or silicon nitride. The third buffer layer 214 can have a single-layer structure or a multi-layer structure.

[0144] The second light-shielding pattern 216 is disposed on the third buffer layer 214. Light from one side of the substrate 202 can be blocked by the second light-shielding pattern 216. For example, the second light-shielding pattern 216 can be formed of a metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Furthermore, the second light-shielding pattern 216 can have a single-layer structure or a multi-layer structure.

[0145] A fourth buffer layer 218 is disposed on the substrate 202 to cover the second light-shielding pattern 216. External moisture and / or oxygen can be blocked by the fourth buffer layer 218. For example, the fourth buffer layer 218 can be formed of an inorganic insulating material, such as silicon oxide or silicon nitride. The fourth buffer layer 218 can have a single-layer structure or a multi-layer structure.

[0146] A first semiconductor layer 230 and a second semiconductor layer 232 spaced apart from the first semiconductor layer 230 are disposed on the fourth buffer layer 218. The first semiconductor layer 230 corresponds to the first light-shielding pattern 206, and the second semiconductor layer 232 corresponds to the second light-shielding pattern 216.

[0147] Each of the first semiconductor layer 230 and the second semiconductor layer 232 may include one of a polycrystalline semiconductor material, an amorphous semiconductor material, and an oxide semiconductor material.

[0148] In embodiments of this disclosure, each of the first semiconductor layer 230 and the second semiconductor layer 232 may include an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (CuO2), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO).

[0149] In embodiments of this disclosure, each of the first semiconductor layer 230 and the second semiconductor layer 232 may include a polycrystalline semiconductor material such as polycrystalline silicon.

[0150] In embodiments of this disclosure, one of the first semiconductor layer 230 and the second semiconductor layer 232 may include an oxide semiconductor material, and the other of the first semiconductor layer 230 and the second semiconductor layer 232 may include a polycrystalline semiconductor material. In this case, the first semiconductor layer 230 and the second semiconductor layer 232 may be disposed at different layers.

[0151] The first semiconductor layer 230 includes a first channel region 230a, a first drain region 230b located on one side of the first channel region 230a, and a first source region 230c located on the other side of the first channel region 230a. Each of the first drain region 230b and the first source region 230c may be doped with impurities.

[0152] The second semiconductor layer 232 includes a second channel region 232a, a second drain region 232b located on one side of the second channel region 232a, and a second source region 232c located on the other side of the second channel region 232a. Each of the second drain region 232b and the second source region 232c may be doped with impurities.

[0153] A gate insulating layer 234 covering the first semiconductor layer 230 and the second semiconductor layer 232 is disposed above the fourth buffer layer 218. For example, the gate insulating layer 234 may be formed of an inorganic insulating material, such as silicon oxide or silicon nitride. The gate insulating layer 234 may have a single-layer structure or a multi-layer structure.

[0154] A first gate electrode 236 corresponding to the first channel region 230a of the first semiconductor layer 230 and a second gate electrode 238 corresponding to the second channel region 232a of the second semiconductor layer 232 are disposed on the gate insulating layer 234. For example, each of the first gate electrode 236 and the second gate electrode 238 may be formed of a metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Furthermore, each of the first gate electrode 236 and the second gate electrode 238 may have a single-layer structure or a multi-layer structure.

[0155] A first interlayer insulating layer 240 covering the first gate electrode 236 and the second gate electrode 238 is disposed above the gate insulating layer 234. External moisture and / or oxygen can be blocked by the first interlayer insulating layer 240. For example, the first interlayer insulating layer 240 can be formed of an inorganic insulating material, such as silicon oxide or silicon nitride. The first interlayer insulating layer 240 can have a single-layer structure or a multi-layer structure.

[0156] A first source electrode 242a, a first drain electrode 242b, a second source electrode 244a, and a second drain electrode 244b are disposed on the first interlayer insulating layer 240, which are spaced apart from each other.

[0157] The first source electrode 242a and the first drain electrode 242b are connected to the first source region 230c and the first drain region 230b of the first semiconductor layer 230 through contact holes in the first interlayer insulating layer 240 and the gate insulating layer 234, respectively. Furthermore, the first source electrode 242a is connected to the first capacitor electrode 208 through contact holes in the first interlayer insulating layer 240, the gate insulating layer 234, the fourth buffer layer 218, the third buffer layer 214, and the second buffer layer 210.

[0158] The second source electrode 244a and the second drain electrode 244b are connected to the second source region 232c and the second drain region 232b of the second semiconductor layer 232 through contact holes in the first interlayer insulating layer 240 and the gate insulating layer 234, respectively. Furthermore, the second source electrode 244a is connected to the second capacitor electrode 212 through contact holes in the first interlayer insulating layer 240, the gate insulating layer 234, the fourth buffer layer 218, and the third buffer layer 214.

[0159] The first source electrode 242a, the first drain electrode 242b, the second source electrode 244a, and the second drain electrode 244b can be disposed on the same layer and formed of the same material. For example, each of the first source electrode 242a, the first drain electrode 242b, the second source electrode 244a, and the second drain electrode 244b can be formed of a metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Furthermore, each of the first source electrode 242a, the first drain electrode 242b, the second source electrode 244a, and the second drain electrode 244b can have a single-layer structure or a multi-layer structure.

[0160] The first semiconductor layer 230, the first gate electrode 236, the first source electrode 242a, and the first drain electrode 242b constitute the first transistor T1, and the second semiconductor layer 232, the second gate electrode 238, the second source electrode 244a, and the second drain electrode 244b constitute the second transistor T2. Each of the first transistor T1 and the second transistor T2 can be a thin-film transistor.

[0161] exist Figure 6 In the first transistor T1, a first gate electrode 236, a first source electrode 242a, and a first drain electrode 242b are disposed above the first semiconductor layer 230, and a second gate electrode 238, a second source electrode 244a, and a second drain electrode 244b are disposed above the second semiconductor layer 232. That is, each of the first transistor T1 and the second transistor T2 has a coplanar structure. Optionally, in each of the first transistor T1 and the second transistor T2, the gate electrode may be disposed below the semiconductor layer, and the source electrode and the drain electrode may be disposed above the semiconductor layer. That is, each of the first transistor T1 and the second transistor T2 may have an inverted interleaved structure.

[0162] An insulating layer 250 covering the first source electrode 242a, the first drain electrode 242b, the second source electrode 244a, and the second drain electrode 244b is disposed on the first interlayer insulating layer 240. That is, the insulating layer 250 covers the first transistor T1 and the second transistor T2.

[0163] The insulating layer 250 may include a first insulating layer 250a on the first source electrode 242a, a second insulating layer 250b on the first insulating layer 250a, and a third insulating layer 250c on the second insulating layer 250b. For example, the first insulating layer 250a and the second insulating layer 250b may be formed of the same material. Each of the first insulating layer 250a, the second insulating layer 250b, and the third insulating layer 250c may be formed of an organic insulating material, such as photopropylene or benzocyclobutene (BCB). The first insulating layer 250a, the second insulating layer 250b, and the third insulating layer 250c may be formed of the same material.

[0164] A first signal line SL1, a second signal line SL2, and a third signal line SL3 are disposed on a first insulating layer 250a. The first signal line SL1, the second signal line SL2, and the third signal line SL3 extend along a second direction Y and are spaced apart from each other in a first direction X. The first signal line SL1 can be used for applying (…). Figure 2 The high-level signal line Vdd is the high-level signal line, and each of the second signal line SL2 and the third signal line SL3 can be ( Figure 1 (The) data cable DL.

[0165] Each of the first signal line SL1, the second signal line SL2, and the third signal line SL3 may be formed of a metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Furthermore, each of the first signal line SL1, the second signal line SL2, and the third signal line SL3 may have a single-layer structure or a multi-layer structure.

[0166] A second insulating layer 250b covering the first signal line SL1, the second signal line SL2 and the third signal line SL3 is disposed on the first insulating layer 250a.

[0167] A connection electrode 252 corresponding to the second source electrode 244a is disposed on the second insulating layer 250b. The connection electrode 252 can be connected to the second source electrode 244a through a contact hole formed in the second insulating layer 250b.

[0168] Additionally, a step compensation pattern 280 is disposed on the second insulating layer 250b. The step compensation pattern 280 corresponds to the first signal line SL1, the second signal line SL2, and the third signal line SL3, and is spaced apart from the connection pattern 252.

[0169] Pixel P includes a light-emitting area and a non-light-emitting area surrounding the light-emitting area. A step compensation pattern 280 is disposed in the light-emitting area and has an island shape. The step compensation pattern 280 has an uneven bottom surface and a flat top surface.

[0170] The first signal line SL1, the second signal line SL2, and the third signal line SL3 are configured to correspond to pixel P, such that the second insulating layer 250b has an uneven surface. That is, the step differences between the first signal line SL1, the second signal line SL2, and the third signal line SL3 are reflected on the second insulating layer 250b, thereby reducing the flatness of the second insulating layer 250b.

[0171] In the LED display device 200 of this disclosure, a step compensation pattern 280 corresponding to the first signal line SL1, the second signal line SL2 and the third signal line SL3 covers the uneven surface of the second insulating layer 250b, thereby compensating for the unevenness of the second insulating layer 250b.

[0172] In embodiments of this disclosure, each of the first signal line SL1, the second signal line SL2, and the third signal line SL3 may have a first thickness, and the step compensation pattern 280 may have a second thickness greater than the first thickness.

[0173] Each of the connecting electrode 252 and the step compensation pattern 280 can be formed of a metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Furthermore, each of the connecting electrode 252 and the step compensation pattern 280 can have a single-layer structure or a multi-layer structure.

[0174] exist Figure 6 In this configuration, the connecting electrode 252 is disposed on the second insulating layer 250b. Alternatively, the connecting electrode 252 may be disposed on the first insulating layer 250a and below the second insulating layer 250b.

[0175] A third insulating layer 250c is disposed on the connecting electrode 252 and the step compensation pattern 280, and a first electrode 260a is disposed on the third insulating layer 250c. The first electrode 260a is connected to the connecting electrode 252 through a contact hole formed in the third insulating layer 250c.

[0176] First electrodes 260a are formed in each pixel region P. The first electrode 260a may be an anode and may include a transparent conductive oxide (TCO) layer and a reflective layer, the transparent conductive oxide layer being formed of a conductive material (e.g., a transparent conductive oxide material) having a relatively high work function.

[0177] The transparent conductive oxide material may include at least one of the following: indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), tin oxide (SnO), zinc oxide (ZnO), indium copper oxide (ICO), and aluminum zinc oxide (Al:ZnO, AZO), and the reflective layer may include at least one of the following: silver (Ag), an alloy of Ag, and one of palladium (Pd), Cu, In, and Nd, as well as an aluminum palladium copper alloy (APC). For example, the first electrode 260a may have a two-layer structure of Ag / ITO or APC / ITO, or a three-layer structure of ITO / Ag / ITO or ITO / APC / ITO.

[0178] A pixel defining layer (e.g., a dam) 254 is formed on the third insulating layer 250c at the boundary of the pixel region. The pixel defining layer 254 is disposed in the non-light-emitting region. The pixel defining layer 254 covers the edge of the first electrode 260a and has an opening to expose the center of the first electrode 260a. For example, the pixel defining layer 254 may be formed of an organic insulating material, such as photopolymer, BCB, or PI.

[0179] The step compensation pattern 280 can have a substantially similar shape. For example, the step compensation pattern 280 can have the same shape as the opening of the pixel defining layer 254. The step compensation pattern 280 can have an area larger than the opening of the pixel defining layer 254 and smaller than the area of ​​the first electrode 260a.

[0180] In the LED display device 200 according to the second embodiment of this disclosure, the step difference between the first signal line SL1, the second signal line SL2, and the third signal line SL3 is compensated by a step compensation pattern 280, such that at least a portion of the first electrode 260a (e.g., the first electrode 260a in the opening of the pixel defining layer 254) has a flat (e.g., level) surface. Therefore, a reduction in the luminous efficiency and / or lifetime of the LED display device 200 can be minimized or prevented.

[0181] Although not shown, space can be provided on the pixel defining layer 254. The spacer can have an area smaller than that of the pixel defining layer 254.

[0182] A light-emitting layer 260b is provided, covering the first electrode 260a and the pixel defining layer 254. The light-emitting layer 260b contacts the first electrode 260a in the opening of the pixel defining layer 254. That is, the light-emitting layer 260b can be formed to contact the upper surface of the first electrode 260a and the side and upper surfaces of the pixel defining layer 254.

[0183] For example, the light-emitting layer 260b may include a light-emitting material layer comprising a host and a dopant. Alternatively, the light-emitting material layer of the light-emitting layer 260b may include an inorganic light-emitting material, such as a quantum dot. The light-emitting layer 260b may also include at least one of a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer to have a multilayer structure.

[0184] The second electrode 260c is formed above the substrate 202 at the location where the light-emitting layer 260b is formed. The second electrode 260c covers the entire surface of the display area. The second electrode 260c can be formed of at least one of ITO, IZO, Al, Ag, Cu, Pb, magnesium (Mg), Mo, Ti, and alloys thereof, and has a single-layer or multi-layer structure. The second electrode 260c can have a thin profile (small thickness) to provide light transmission characteristics (or semi-transmission characteristics).

[0185] The first electrode 260a, the organic light-emitting layer 260b, and the second electrode 260c constitute a light-emitting diode D. The light-emitting diode D can emit red light, green light, and blue light in the red pixel region, the green pixel region, and the blue pixel region, respectively.

[0186] In the LED display device 200, light from the light-emitting layer 260b passes through the second electrode 260c to display an image. That is, the LED display device 200 of this disclosure is a top-emitting type display device.

[0187] In embodiments of this disclosure, the first electrode 260a may be a transparent electrode. That is, the first electrode 260a may have a single-layer structure with a transparent conductive oxide layer.

[0188] In this configuration, the step compensation pattern 280 beneath the first electrode 260a serves as a reflective layer for light passing through the first electrode 260a. Therefore, although the first electrode 260a in the top-emitting diode display device 200 has a single-layer structure with a transparent conductive oxide layer, the efficiency of the diode display device 200 is not reduced.

[0189] Furthermore, since the first electrode 260a has a single-layer structure of a transparent conductive oxide layer, process defects that may occur during the patterning process of the first electrode 260a can be prevented. For example, in a light-emitting diode device 200 including a first electrode 260a with an ITO / Ag / ITO structure or an ITO / APC / ITO structure, a masking process is performed to form the first electrode 260a after sequentially stacking a transparent conductive oxide material layer, a reflective layer, and a transparent conductive oxide material layer. Process defects may exist in etching processes using different materials, which may cause short-circuit problems between the first electrodes 260a in adjacent pixels and / or current leakage problems in adjacent pixels.

[0190] However, in the LED display device 200 of this disclosure, the step compensation pattern 280 serves as a reflective layer, and the first electrode 260a has a single-layer structure of a transparent conductive oxide layer. Therefore, the LED display device 200 of this disclosure can provide improved luminous efficiency and / or lifetime without the aforementioned problems.

[0191] An encapsulation layer (or encapsulation film) 262 is formed on the second electrode 260c to prevent moisture from penetrating into the light-emitting diode D. The encapsulation layer 262 may include, but is not limited to, a first inorganic insulating layer 262a, an organic insulating layer 262b, and a second inorganic insulating layer 262c stacked in sequence.

[0192] For example, each of the first inorganic insulating layer 262a and the second inorganic insulating layer 262c may be formed of an inorganic insulating material, such as silicon oxide or silicon nitride, and the organic insulating layer 262b may be formed of an organic insulating material, such as acryloyl resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0193] A fifth buffer layer 264 is disposed on the encapsulation layer 262 and over the entire substrate 202. External moisture and / or oxygen can be blocked by the fifth buffer layer 264. For example, the fifth buffer layer 264 can be formed of an inorganic insulating material, such as silicon oxide or silicon nitride. The fifth buffer layer 264 can have a single-layer structure or a multi-layer structure.

[0194] The bridging pattern 266 is disposed on the fifth buffer layer 264. When the fifth buffer layer 264 is omitted, the bridging pattern 266 can be directly disposed on the encapsulation layer 262. For example, the bridging pattern 266 can be formed of a metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Furthermore, the bridging pattern 266 can have a single-layer structure or a multi-layer structure.

[0195] The second interlayer insulating layer 270 is disposed on the fifth buffer layer 264 and over the entire substrate 202. For example, the second interlayer insulating layer 270 may be formed of an inorganic insulating material (e.g., silicon oxide or silicon nitride) or an organic insulating material (e.g., photoacryloyl or BCB). The second interlayer insulating layer 270 may have a single-layer structure or a multilayer structure.

[0196] Touch electrodes 272 are disposed on the second interlayer insulating layer 270. The touch electrodes include a first touch electrode 272a and a second touch electrode 272b. The first touch electrodes 272a are spaced apart from each other, and the second touch electrode 272b is disposed between the first touch electrodes 272a. The second touch electrode 272b is connected to the bridging pattern 266 through a contact hole formed in the second interlayer insulating layer 270.

[0197] For example, each of the first touch electrode 272a and the second touch electrode 272b may be formed from one of ITO, IZO, Al, Ag, Cu, Pb, Mg, Mo, Ti, and alloys thereof. Furthermore, each of the first touch electrode 272a and the second touch electrode 272b may have a single-layer structure or a multi-layer structure.

[0198] A first protective layer 274 is disposed on the first touch electrode 272a and the second touch electrode 272b and over the entire substrate 202. The first protective layer 274 may be formed of an inorganic insulating material (e.g., silicon oxide or silicon nitride) or an organic insulating material (e.g., photoacryloyl or BCB). The first protective layer 274 may have a single-layer structure or a multi-layer structure.

[0199] A black matrix 275 is disposed on the first protective layer 274. The black matrix 275 is disposed within the boundary of the pixel region P and has an opening corresponding to the light-emitting diode D. That is, the opening of the black matrix 275 can correspond to the opening of the pixel defining layer 254.

[0200] The opening of the black matrix 275 can have an area larger than that of the opening of the pixel defining layer 254. For example, the pixel defining layer 254 can have a first width, and the black matrix 275 can have a second width smaller than the first width. When the area of ​​the opening of the black matrix 275 is equal to or smaller than the area of ​​the opening of the pixel defining layer 254, the viewing angle of the light-emitting diode display device 200 will decrease.

[0201] A color filter layer 277 corresponding to the opening of the black matrix 275 is disposed on the first protective layer 274. The color filter layer 277 may include a red color filter corresponding to a red pixel, a green color filter corresponding to a green pixel, and a blue color filter corresponding to a blue pixel.

[0202] The color filter layer 277 may include organic materials and color particles (e.g., color pigments or color dyes). For example, the organic materials may be selected from, but are not limited to, polymethyl methacrylate, polycarbonate, polyacrylate, polyurethane, epoxy resin, polyester and polyimide.

[0203] The second protective layer 279 is disposed on the black matrix 275 and the color filter layer 277 and is disposed over the entire substrate 202. For example, the second protective layer 279 may be formed of an inorganic insulating material, such as silicon oxide or silicon nitride. The second protective layer 279 may have a single-layer structure or a multi-layer structure.

[0204] In the LED display device 200 according to the second embodiment of the present disclosure, since the first signal line SL1, the second signal line SL2 and the third signal line SL3 are configured to intersect with the pixel P, the limitation on the width of the first signal line SL1, the second signal line SL2 and the third signal line SL3 can be minimized.

[0205] Furthermore, the LED display device 200 includes a step compensation pattern 280, which covers the first signal line SL1, the second signal line SL2, and the third signal line SL3 and is disposed below the first electrode 260a, thereby improving the flatness of the first electrode 260a. Therefore, the reduction in luminous efficiency and / or lifespan of the LED display device 200 caused by the non-uniformity of the first electrode 260a can be minimized or prevented.

[0206] Figure 7 This is a schematic cross-sectional view showing an organic light-emitting diode display device according to a third embodiment of the present disclosure, and showing along... Figure 5 The cross-sectional view taken from line II-II'.

[0207] For ease of explanation, the arrangement between the substrate 302 and the first insulating layer 350c, the arrangement above the second electrode 360c, and (are not shown) are not shown. Figure 6 (The) connecting electrode 252.

[0208] like Figure 7 As shown, the light-emitting diode display device 300 includes: a substrate 302 including a pixel P; a first insulating layer 350a disposed above the substrate 302; a first signal line SL1, a second signal line SL2, and a third signal line SL3 disposed above the first insulating layer 350a; a second insulating layer 350b covering the first signal line SL1, the second signal line SL2, and the third signal line SL3; a step compensation pattern 380 disposed on the second insulating layer 350b; a third insulating layer 350c disposed on the step compensation pattern 380; and a light-emitting diode D disposed on the third insulating layer 350b and including a second electrode 360c electrically connected to the step compensation pattern 380.

[0209] A first signal line SL1, a second signal line SL2, and a third signal line SL3 are disposed on a first insulating layer 350a. The first signal line SL1, the second signal line SL2, and the third signal line SL3 extend along a second direction Y and are spaced apart from each other. The first signal line SL1 can be used for applying (…). Figure 2 The high-level signal line Vdd is the high-level signal line, and each of the second signal line SL2 and the third signal line SL3 can be ( Figure 1 (The) data cable DL.

[0210] A second insulating layer 350b covering the first signal line SL1, the second signal line SL2 and the third signal line SL3 is disposed on the first insulating layer 350a.

[0211] A step compensation pattern 380 is disposed on the second insulating layer 350b. The step compensation pattern 380 corresponds to and covers the first signal line SL1, the second signal line SL2, and the third signal line SL3, and is consistent with ( Figure 6 The connecting patterns 252 are spaced apart.

[0212] The first signal line SL1, the second signal line SL2, and the third signal line SL3 are configured to correspond to pixel P, such that the second insulating layer 350b has an uneven surface. That is, the step differences between the first signal line SL1, the second signal line SL2, and the third signal line SL3 are reflected on the second insulating layer 350b, thereby reducing the flatness of the second insulating layer 350b.

[0213] In the LED display device 300 of this disclosure, a step compensation pattern 380 corresponding to the first signal line SL1, the second signal line SL2 and the third signal line SL3 covers the uneven surface of the second insulating layer 350b, thereby compensating for the unevenness of the second insulating layer 350b.

[0214] The step compensation pattern 380 includes an extension 382 disposed below the pixel defining layer 354. That is, at least one end of the step compensation pattern 380 extends below the pixel defining layer 354 to form the extension 382. The extension 382 protrudes from the first electrode 360a. Specifically, the extension 382 extends below the first electrode 360a beyond the edge of the first electrode 360a.

[0215] In embodiments of this disclosure, each of the first signal line SL1, the second signal line SL2, and the third signal line SL3 may have a first thickness, and the step compensation pattern 380 may have a second thickness greater than the first thickness.

[0216] The step compensation pattern 380 can be formed of metallic materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Furthermore, the step compensation pattern 380 can have a single-layer or multi-layer structure.

[0217] The third insulating layer 350c is disposed on the step compensation pattern 380, and the first electrode 360a is disposed on the third insulating layer 350c.

[0218] First electrodes 360a are formed in each pixel region P. The first electrode 260a may be an anode and may include a transparent conductive oxide (TCO) layer and a reflective layer, the transparent conductive oxide layer being formed of a conductive material (e.g., a transparent conductive oxide material) having a relatively high work function.

[0219] In embodiments of this disclosure, the first electrode 360a may be a transparent electrode 360a. That is, the first electrode 360a may have a single-layer structure with a transparent conductive oxide layer.

[0220] The step compensation pattern 380 below the first electrode 360a serves as a reflective layer for light passing through the first electrode 360a. Therefore, although the first electrode 360a has a single-layer structure of a transparent conductive oxide layer in the top-emitting diode display device 300, the efficiency of the diode display device 300 is not reduced.

[0221] A pixel defining layer (e.g., a dam) 354 is formed on the third insulating layer 350c at the boundary of the pixel region. The pixel defining layer 354 covers the edge of the first electrode 360a and has an opening to expose the center of the first electrode 360a.

[0222] The step compensation pattern 380 can have a substantially similar shape. For example, the step compensation pattern 380 can have the same shape as the opening of the pixel defining layer 354. The step compensation pattern 380 can have an area larger than the opening of the pixel defining layer 354 and smaller than the area of ​​the first electrode 260a.

[0223] In the LED display device 300 according to the third embodiment of this disclosure, the step difference between the first signal line SL1, the second signal line SL2, and the third signal line SL3 is compensated by a step compensation pattern 380, such that at least a portion of the first electrode 360a (e.g., the first electrode 360a in the opening of the pixel defining layer 354) has a flat (e.g., smooth) surface. Therefore, a reduction in the luminous efficiency and / or lifetime of the LED display device 300 can be minimized or prevented.

[0224] An auxiliary contact hole 356 corresponding to the extension portion 382 of the step compensation layer 380 is formed in the pixel defining layer 354 and the third insulating layer 350c. That is, the extension portion 382 of the step compensation layer 380 is exposed through the auxiliary contact hole 356 in the pixel defining layer 354 and the third insulating layer 350c.

[0225] A light-emitting layer 360b is provided, covering the first electrode 360a and the pixel defining layer 354. The light-emitting layer 360b contacts the first electrode 360a in the opening of the pixel defining layer 354. That is, the light-emitting layer 360b can be formed to contact the upper surface of the first electrode 360a and the side and upper surfaces of the pixel defining layer 354.

[0226] For example, the light-emitting layer 360b may include a light-emitting material layer comprising a host and a dopant. Alternatively, the light-emitting material layer of the light-emitting layer 360b may include an inorganic light-emitting material, such as a quantum dot. The light-emitting layer 360b may also include at least one of a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer to have a multilayer structure.

[0227] A second electrode 360c is formed above the substrate 302 on which the light-emitting layer 360b is formed. The second electrode 360c covers the entire surface of the display area. The second electrode 360c may be formed of at least one of ITO, IZO, Al, Ag, Cu, Pb, magnesium (Mg), Mo, Ti and their alloys, and has a single-layer structure or a multi-layer structure. The second electrode 360c may have a thin profile (small thickness) to provide light transmission characteristics (or semi-transmission characteristics).

[0228] The second electrode 360c is disposed on the pixel defining layer 354 and is connected to the extension portion 382 of the step compensation layer 380 through the auxiliary contact hole 356 in the pixel defining layer 354 and the third insulating layer 350c.

[0229] Because the second electrode 360c has a thin profile and is formed on the entire surface of the substrate 202, a voltage drop problem may exist in the second electrode 360c depending on the position of the pixel. However, in the light-emitting diode display device 300 according to the third embodiment of the present disclosure, an extension 382, ​​which is configured to enhance the flatness of the first electrode 360a as part of the step compensation pattern 380, is connected to the second electrode 360c, reducing the resistance of the second electrode 260c, thereby minimizing or preventing the voltage drop problem.

[0230] In the LED display device 300 according to the third embodiment of the present disclosure, since the first signal line SL1, the second signal line SL2 and the third signal line SL3 are configured to intersect with the pixel P, the limitation on the width of the first signal line SL1, the second signal line SL2 and the third signal line SL3 can be minimized.

[0231] Furthermore, the LED display device 300 includes a step compensation pattern 380, which covers the first signal line SL1, the second signal line SL2, and the third signal line SL3 and is disposed below the first electrode 360a, thereby improving the flatness of the first electrode 360a. Therefore, the reduction in luminous efficiency and / or lifespan of the LED display device 300 caused by the non-uniformity of the first electrode 360a can be minimized or prevented.

[0232] Furthermore, in the LED display device 300 according to the third embodiment of the present disclosure, the extension portion 382 of the step compensation pattern 380 is connected to the second electrode 360c, and the resistance of the second electrode 260c is reduced, so that voltage drop problems can be minimized or prevented.

[0233] Figure 8 This is a schematic plan view showing a light-emitting diode display device according to the fourth embodiment of the present disclosure.

[0234] Reference Figure 8 According to the second embodiment of the present disclosure, the light-emitting diode display device 200 includes a first pixel P1, a second pixel P2, a third pixel P3, a second signal line SL2 and a third signal line SL3 that intersect the first pixel P1 and the third pixel P3 and extend in one direction, and a fourth signal line SL4 that intersects the second pixel P2 and extends parallel to the second signal line SL2 and the third signal line SL3.

[0235] For example, the first pixel P1 can be a red pixel, the second pixel P2 can be a green pixel, and the third pixel P3 can be a blue pixel. The light-emitting diode display device 400 may also include a fourth pixel as a white pixel.

[0236] The first pixel P1 and the third pixel P3 can have the same shape, and the second pixel P2 can have a different shape than the first pixel P1 and the third pixel P3. However, the shapes of the first pixel P1, the second pixel P2, and the third pixel P3 are not restricted.

[0237] The area of ​​the third pixel P3 can be larger than the area of ​​each of the first pixel P1 and the second pixel P2, and the area of ​​the first pixel P1 can be equal to or smaller than the area of ​​the second pixel P2. However, the areas of the first pixel P1, the second pixel P2, and the third pixel P3 are not limited.

[0238] First pixel P1 and third pixel P3 are arranged alternately along the first direction X. Second pixel P2 is spaced apart from the pixel column including first pixel P1 and third pixel P3 along the second direction Y and is arranged along the first direction X. The second direction Y intersects the first direction X. The second direction Y may be perpendicular to the first direction X.

[0239] The second to fourth signal lines SL2, SL3 and SL4 extend along the second direction Y and are spaced apart from each other in the first direction X. The second signal line SL2 and the third signal line SL3 overlap with the first electrode 460a and are spaced apart from each other, and the fourth signal line SL4 is located on one side of the second signal line SL2 and on one side of the third signal line SL3.

[0240] Each of the second signal line SL2 and the third signal line SL3 can be ( Figure 1 The data line DL, and each of the fourth signal lines SL4 can be used to apply ( Figure 2 (The reference signal line of the reference signal Vre)

[0241] ( Figure 2 The first electrode 460a of the light-emitting diode D is arranged in an island shape in each of the first pixel P1, the second pixel P2 and the third pixel P3.

[0242] Additionally, a step compensation pattern 480 corresponding to the first electrode 260a is provided in each of the first pixel P1, the second pixel P2, and the third pixel P3 and is provided below the first electrode 260a.

[0243] The step compensation pattern 480 includes an extension line portion 482 extending along the second direction Y. For example, the extension line portion 482 can extend from both ends of the step compensation pattern 480 along the second direction Y.

[0244] The extension portion 482 of the step compensation pattern 480 can be located between the second signal line SL2 and the third signal line SL3, and can be used as the first signal line SL1. For example, the extension portion 482 can be used to apply ( Figure 2 The high-level signal line Vdd is the high-level signal line.

[0245] exist Figure 8 In the first pixel P1, the second pixel P2, and the third pixel P3, a first signal line SL1, a second signal line SL2, and a third signal line SL3 are disposed in each of the first pixel P1 and the third pixel P3, and a fourth signal line SL4 is disposed in the second pixel P2. However, in the LED display device 200 of this disclosure, the arrangement of pixels P1, P2, and P3, as well as signal lines SL1, SL2, SL3, and SL4, is not limited.

[0246] Figure 9 This is a cross-sectional schematic diagram showing a light-emitting diode display device according to the fourth embodiment of the present disclosure. Figure 9 It shows along Figure 8 The cross-sectional view taken from line III-III'.

[0247] like Figure 9 As shown, the light-emitting diode display device 400 includes: a substrate 402 including a pixel P; a pixel circuit layer disposed above the substrate 402 and including a first transistor T1 and a second transistor T2; a first insulating layer 450a disposed above the pixel circuit layer; a first signal line SL1, a second signal line SL2, and a third signal line SL3 disposed above the first insulating layer 450a; a second insulating layer 450b covering the second signal line SL2 and the third signal line SL3; a step compensation pattern 480 disposed on the second insulating layer 450b and serving as the first signal line SL1; a third insulating layer 450c disposed on the step compensation pattern 480; and a light-emitting diode D disposed on the third insulating layer 450b. The pixel circuit layer corresponds to the pixel P.

[0248] Multiple pixels P are defined on substrate 402. Pixel P includes a light-emitting region EA and a non-light-emitting region NEA. The non-light-emitting region NEA may surround the light-emitting region EA. Substrate 402 may be a glass substrate or a plastic substrate. In embodiments of this disclosure, substrate 402 may have a three-layer structure, including a first polyimide (PI) layer, a second PI layer, and an interlayer inorganic layer located between the first PI layer and the second PI layer.

[0249] A first buffer layer 404 is disposed on the substrate 402. External moisture and / or oxygen can be blocked by the first buffer layer 404.

[0250] A first light-shielding pattern 406 is disposed on the first buffer layer 404. Light from one side of the substrate 402 can be blocked by the first light-shielding pattern 406.

[0251] The first capacitor electrode 408 is disposed on the first buffer layer 404. The first capacitor electrode 408 may be spaced apart from the first light-shielding pattern 406.

[0252] A second buffer layer 410 is disposed above the substrate 402 to cover the first light-shielding pattern 406 and the first capacitor electrode 408. External moisture and / or oxygen can be blocked by the second buffer layer 410.

[0253] A second capacitor electrode 412, corresponding to the first capacitor electrode 408, is disposed on the second buffer layer 410. The second capacitor electrode 412 overlaps with the first capacitor electrode 408. The first capacitor electrode 408, the second buffer layer 410, and the second capacitor electrode 412 constitute a storage capacitor Cst.

[0254] A third buffer layer 414 is disposed above the substrate 402 to cover the second capacitor electrode 412. External moisture and / or oxygen can be blocked by the third buffer layer 414.

[0255] The second light-shielding pattern 416 is disposed on the third buffer layer 414. Light from one side of the substrate 402 can be blocked by the second light-shielding pattern 416.

[0256] A fourth buffer layer 418 is disposed on the substrate 402 to cover the second light-shielding pattern 416. External moisture and / or oxygen can be blocked by the fourth buffer layer 418.

[0257] A first semiconductor layer 430 and a second semiconductor layer 432 spaced apart from the first semiconductor layer 430 are disposed on the fourth buffer layer 418. The first semiconductor layer 430 corresponds to the first light-shielding pattern 406, and the second semiconductor layer 432 corresponds to the second light-shielding pattern 416.

[0258] Each of the first semiconductor layer 430 and the second semiconductor layer 432 may include one of a polycrystalline semiconductor material, an amorphous semiconductor material, and an oxide semiconductor material.

[0259] In embodiments of this disclosure, each of the first semiconductor layer 430 and the second semiconductor layer 432 may include the aforementioned oxide semiconductor material.

[0260] In embodiments of this disclosure, each of the first semiconductor layer 430 and the second semiconductor layer 432 may include a polycrystalline semiconductor material such as polycrystalline silicon.

[0261] In embodiments of this disclosure, one of the first semiconductor layer 430 and the second semiconductor layer 432 may include an oxide semiconductor material, and the other of the first semiconductor layer 430 and the second semiconductor layer 432 may include a polycrystalline semiconductor material. In this case, the first semiconductor layer 430 and the second semiconductor layer 432 may be disposed at different layers.

[0262] The first semiconductor layer 430 includes a first channel region 430a, a first drain region 430b located on one side of the first channel region 430a, and a first source region 430c located on the other side of the first channel region 430a. Each of the first drain region 430b and the first source region 430c may be doped with impurities.

[0263] The second semiconductor layer 432 includes a second channel region 432a, a second drain region 432b located on one side of the second channel region 432a, and a second source region 432c located on the other side of the second channel region 432a. Each of the second drain region 432b and the second source region 432c may be doped with impurities.

[0264] A gate insulating layer 434 covering the first semiconductor layer 430 and the second semiconductor layer 432 is disposed above the fourth buffer layer 418.

[0265] A first gate electrode 436 corresponding to the first channel region 430a of the first semiconductor layer 430 and a second gate electrode 438 corresponding to the second channel region 432a of the second semiconductor layer 432 are disposed on the gate insulating layer 434.

[0266] A first interlayer insulating layer 440 covering the first gate electrode 436 and the second gate electrode 438 is disposed above the gate insulating layer 434. External moisture and / or oxygen can be blocked by the first interlayer insulating layer 440.

[0267] A first source electrode 442a, a first drain electrode 442b, a second source electrode 444a, and a second drain electrode 444b are disposed on the first interlayer insulating layer 440, which are spaced apart from each other.

[0268] The first source electrode 442a and the first drain electrode 442b are connected to the first source region 430c and the first drain region 430b of the first semiconductor layer 430 through contact holes in the first interlayer insulating layer 440 and the gate insulating layer 434, respectively. Furthermore, the first source electrode 442a is connected to the first capacitor electrode 408 through contact holes in the first interlayer insulating layer 440, the gate insulating layer 434, the fourth buffer layer 418, the third buffer layer 414, and the second buffer layer 410.

[0269] The second source electrode 444a and the second drain electrode 444b are connected to the second source region 432c and the second drain region 432b of the second semiconductor layer 432 through contact holes in the first interlayer insulating layer 440 and the gate insulating layer 434, respectively. Furthermore, the second source electrode 444a is connected to the second capacitor electrode 412 through contact holes in the first interlayer insulating layer 440, the gate insulating layer 434, the fourth buffer layer 418, and the third buffer layer 414.

[0270] The first semiconductor layer 430, the first gate electrode 436, the first source electrode 442a, and the first drain electrode 442b constitute the first transistor T1, and the second semiconductor layer 432, the second gate electrode 438, the second source electrode 444a, and the second drain electrode 444b constitute the second transistor T2. Each of the first transistor T1 and the second transistor T2 can be a thin-film transistor.

[0271] An insulating layer 450 covering the first source electrode 442a, the first drain electrode 442b, the second source electrode 444a, and the second drain electrode 444b is disposed on the first interlayer insulating layer 440. That is, the insulating layer 450 covers the first transistor T1 and the second transistor T2.

[0272] The insulating layer 450 may include a first insulating layer 450a on the first source electrode 442a, a second insulating layer 450b on the first insulating layer 450a, a third insulating layer 450c on the second insulating layer 450b, and a first insulating layer 450a on the first insulating layer 442a, a first drain electrode 442b, a second source electrode 444a, and a second drain electrode 444b.

[0273] The second signal line SL2 and the third signal line SL3 are disposed on the first insulating layer 450a. The second signal line SL2 and the third signal line SL3 extend along the second direction Y and are spaced apart from each other in the first direction X. Each of the second signal line SL2 and the third signal line SL3 can be (… Figure 1 (The) data cable DL.

[0274] A second insulating layer 450b covering the second signal line SL2 and the third signal line SL3 is disposed on the first insulating layer 450a.

[0275] A connection electrode 452 corresponding to the second source electrode 444a is disposed on the second insulating layer 450b. The connection electrode 452 can be connected to the second source electrode 444a through a contact hole formed in the second insulating layer 450b.

[0276] Additionally, a step compensation pattern 480 is disposed on the second insulating layer 450b. The step compensation pattern 480 corresponds to and covers the second signal line SL2 and the third signal line SL3, and is spaced apart from the connection pattern 452.

[0277] The second signal line SL2 and the third signal line SL3 are configured to correspond to pixel P, such that the second insulating layer 450b has an uneven surface. That is, the step difference between the second signal line SL2 and the third signal line SL3 is reflected on the second insulating layer 450b, thereby reducing the flatness of the second insulating layer 450b.

[0278] In the LED display device 400 of this disclosure, a step compensation pattern 480 corresponding to the second signal line SL2 and the third signal line SL3 covers the uneven surface of the second insulating layer 450b, thereby compensating for the unevenness of the second insulating layer 450b.

[0279] The end of the step compensation pattern 480 is along ( Figure 8 The second direction Y extends to form an extension portion 482, which serves as a signal line. For example, the extension portion 482 can be used for applying ( Figure 2 The first signal line of the high-level signal Vdd is located between the second signal line SL2 and the third signal line SL3.

[0280] exist( Figure 8 In the first direction X, the step compensation pattern 480 has a first width, and the extension line portion 482 has a second width smaller than the first width. For example, the width of the extension line portion 482 may be substantially the same as each of the second signal line SL2 and the third signal line SL3.

[0281] In the LED display device 400 according to the fourth embodiment of this disclosure, a second signal line SL2 and a third signal line SL3 are disposed below a second insulating layer 450b, and a first signal line SL1 (e.g., an extension line portion 482) extending from a step compensation pattern 480 and located between the second signal line SL2 and the third signal line SL3 is disposed on the second insulating layer 450b. That is, the first signal line SL1 is disposed on a different layer than the second signal line SL2 and the third signal line SL3. Therefore, the limitation on the width of the first signal line SL1, the second signal line SL2, and the third signal line SL3 can be minimized.

[0282] In embodiments of this disclosure, each of the second signal line SL2 and the third signal line SL3 may have a first thickness, and each of the step compensation pattern 480 and the extension line portion 482 may have a second thickness greater than the first thickness.

[0283] A third insulating layer 450c is disposed on the connecting electrode 452, the step compensation pattern 480, and the extension line portion 482, and a first electrode 460a is disposed on the third insulating layer 450c. The first electrode 460a is connected to the connecting electrode 452 through a contact hole formed in the third insulating layer 450c.

[0284] First electrodes 460a are formed in each pixel region P. The first electrode 460a may be an anode and may include a transparent conductive oxide (TCO) layer and a reflective layer, the transparent conductive oxide layer being formed of a conductive material (e.g., a transparent conductive oxide material) having a relatively high work function.

[0285] A pixel defining layer (e.g., a dam) 454 is formed on the third insulating layer 450c at the boundary of the pixel region. The pixel defining layer 454 covers the edge of the first electrode 460a and has an opening to expose the center of the first electrode 460a.

[0286] The step compensation pattern 480 can have a substantially similar shape. For example, the step compensation pattern 480 can have the same shape as the opening of the pixel defining layer 454. The step compensation pattern 480 can have an area larger than the opening of the pixel defining layer 454 and smaller than the area of ​​the first electrode 460a.

[0287] In the LED display device 400 according to the fourth embodiment of this disclosure, the step difference between the second signal line SL2 and the third signal line SL3 is compensated by a step compensation pattern 480, such that at least a portion of the first electrode 460a (e.g., the first electrode 460a in the opening of the pixel defining layer 454) has a flat (e.g., level) surface. Therefore, a reduction in the luminous efficiency and / or lifetime of the LED display device 400 can be minimized or prevented.

[0288] A light-emitting layer 460b is provided, covering the first electrode 460a and the pixel defining layer 454. The light-emitting layer 460b contacts the first electrode 460a in the opening of the pixel defining layer 454. That is, the light-emitting layer 460b can be formed to contact the upper surface of the first electrode 460a and the side and upper surfaces of the pixel defining layer 454.

[0289] A second electrode 460c is formed above the substrate 402 on which the light-emitting layer 460b is formed. The second electrode 460c covers the entire surface of the display area. The second electrode 460c can be formed of at least one of ITO, IZO, Al, Ag, Cu, Pb, magnesium (Mg), Mo, Ti, and alloys thereof, and has a single-layer structure or a multi-layer structure. The second electrode 460c can have a thin profile (small thickness) to provide light transmission characteristics (or semi-transmission characteristics).

[0290] The first electrode 460a, the organic light-emitting layer 460b, and the second electrode 460c constitute a light-emitting diode D. The light-emitting diode D can emit red light, green light, and blue light in the red pixel region, the green pixel region, and the blue pixel region, respectively.

[0291] In the light-emitting diode display device 400, light from the light-emitting layer 460b passes through the second electrode 460c to display an image. That is, the light-emitting diode display device 400 of this disclosure is a top-emitting type display device.

[0292] In embodiments of this disclosure, the first electrode 460a may be a transparent electrode. That is, the first electrode 460a may have a single-layer structure with a transparent conductive oxide layer.

[0293] In this configuration, the step compensation pattern 480 beneath the first electrode 460a serves as a reflective layer for light passing through the first electrode 460a. Therefore, although the first electrode 460a in the top-emitting diode display device 400 has a single-layer structure with a transparent conductive oxide layer, the efficiency of the diode display device 400 is not reduced.

[0294] In addition, since the first electrode 460a has a single-layer structure of a transparent conductive oxide layer, process defects that may occur during the patterning process of the first electrode 460a can be prevented.

[0295] An encapsulation layer (or encapsulation film) 462 is formed on the second electrode 460c to prevent moisture from penetrating into the light-emitting diode D. The encapsulation layer 462 may include, but is not limited to, a first inorganic insulating layer 462a, an organic insulating layer 462b, and a second inorganic insulating layer 462c stacked in sequence.

[0296] A fifth buffer layer 464 is disposed on the encapsulation layer 462 and above the entire substrate 402. External moisture and / or oxygen can be blocked by the fifth buffer layer 464.

[0297] The bridging pattern 466 is disposed on the fifth buffer layer 464. When the fifth buffer layer 464 is omitted, the bridging pattern 466 can be directly disposed on the encapsulation layer 462.

[0298] The second interlayer insulating layer 470 is disposed on the fifth buffer layer 464 and is disposed above the entire substrate 402.

[0299] Touch electrodes 472 are disposed on the second interlayer insulating layer 470. The touch electrodes include a first touch electrode 472a and a second touch electrode 472b. The first touch electrodes 472a are spaced apart from each other, and the second touch electrode 472b is disposed between the first touch electrodes 472a. The second touch electrode 472b is connected to the bridging pattern 466 through a contact hole formed in the second interlayer insulating layer 470.

[0300] The first protective layer 474 is disposed on the first touch electrode 472a and the second touch electrode 472b and on the entire substrate 402.

[0301] A black matrix 475 is disposed on the first protective layer 474. The black matrix 475 is disposed within the boundary of the pixel region P and has an opening corresponding to the light-emitting diode D. That is, the opening of the black matrix 475 can correspond to the opening of the pixel defining layer 454.

[0302] The opening of the black matrix 475 can have an area larger than that of the opening of the pixel defining layer 454. For example, the pixel defining layer 454 can have a first width, and the black matrix 475 can have a second width smaller than the first width. When the area of ​​the opening of the black matrix 475 is equal to or smaller than the area of ​​the opening of the pixel defining layer 454, the viewing angle of the light-emitting diode display device 400 can be reduced.

[0303] A color filter layer 477 corresponding to the opening of the black matrix 475 is disposed on the first protective layer 474. The color filter layer 477 may include a red color filter corresponding to a red pixel, a green color filter corresponding to a green pixel, and a blue color filter corresponding to a blue pixel.

[0304] The second protective layer 479 is disposed on the black matrix 475 and the color filter layer 477 and is disposed above the entire substrate 402.

[0305] In the LED display device 400 according to the fourth embodiment of the present disclosure, since the first signal line SL1, the second signal line SL2 and the third signal line SL3 are configured to intersect with the pixel P, the limitation on the width of the first signal line SL1, the second signal line SL2 and the third signal line SL3 can be minimized.

[0306] Furthermore, the LED display device 400 includes a step compensation pattern 480, which covers the second signal line SL2 and the third signal line SL3 and is disposed below the first electrode 460a, thereby improving the flatness of the first electrode 460a. Therefore, the reduction in luminous efficiency and / or lifespan of the LED display device 400 caused by the non-uniformity of the first electrode 460a can be minimized or prevented.

[0307] Furthermore, the second signal line SL2 and the third signal line SL3 are disposed below the second insulating layer 450b, and the first signal line SL1 (e.g., the extension line portion 482 extending from the step compensation pattern 480 and located between the second signal line SL2 and the third signal line SL3) is disposed on the second insulating layer 450b. Therefore, the limitation on the width of the first signal line SL1, the second signal line SL2, and the third signal line SL3 can be further minimized.

[0308] It will be apparent to those skilled in the art that various modifications and variations can be made to the implementation of this disclosure without departing from the spirit or scope thereof. Therefore, such modifications and variations are intended to cover this disclosure, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting diode display device, comprising: A substrate, the substrate including pixels, the pixels including light-emitting areas and non-light-emitting areas; A first insulating layer is disposed on the substrate; A step compensation pattern is disposed on the first insulating layer and corresponds to the light-emitting area; A second insulating layer covers the step compensation pattern; The first electrode is disposed on the second insulating layer and corresponds to the step compensation pattern; as well as A pixel defining layer is disposed on the second insulating layer and in the non-light-emitting area. The pixel defining layer covers the edge of the first electrode and has an opening corresponding to the center of the first electrode. The step compensation pattern has the same shape as the opening.

2. The light-emitting diode display device according to claim 1, wherein the area of ​​the step compensation pattern is larger than the area of ​​the opening and smaller than the area of ​​the first electrode.

3. The light-emitting diode display device according to claim 1, wherein the step compensation pattern has an island shape.

4. The light-emitting diode display device according to claim 1, further comprising: A light-emitting layer is located on the first electrode and within the opening; as well as The second electrode covers the light-emitting layer and the pixel-defining layer in the opening.

5. The light-emitting diode display device according to claim 4, wherein the step compensation pattern includes an extension portion, and The extended portion extends from at least one end of the step compensation pattern to the pixel defining layer and protrudes from the first electrode.

6. The light-emitting diode display device according to claim 5, wherein the second electrode is electrically connected to the extension portion of the step compensation pattern.

7. The light-emitting diode display device of claim 5, wherein the pixel defining layer and the second insulating layer include contact holes corresponding to the extension portion of the step compensation pattern, and the second electrode is connected to the extension portion of the step compensation pattern through the contact holes.

8. The light-emitting diode display device according to claim 1, wherein the step compensation pattern includes an extension line portion extending along a first direction.

9. The light-emitting diode display device according to claim 8, further comprising: A third insulating layer is located between the substrate and the first insulating layer; as well as A first signal line is disposed on the third insulating layer and extends along the first direction. The extension portion is spaced apart from the first signal line in a second direction, and the second direction intersects the first direction.

10. The light-emitting diode display device according to claim 9, further comprising: The second signal line is disposed on the third insulating layer and extends along the first direction. The extension line portion is spaced apart from the first signal line in the second direction, and the extension line portion is positioned between the first signal line and the second signal line.

11. The light-emitting diode display device according to claim 9, wherein the thickness of the step compensation pattern is greater than the thickness of the first signal line.

12. The light-emitting diode display device of claim 8, wherein the step compensation pattern has a first width in a second direction perpendicular to the first direction, and the extension line portion has a second width, and The second width is smaller than the first width.

13. The light-emitting diode display device according to claim 1, wherein the first electrode has a single-layer structure of a transparent conductive oxide layer, and The step compensation pattern thereon serves as a reflective layer for light passing through the first electrode.

14. The light-emitting diode display device according to claim 13, further comprising: A light-emitting layer is located on the first electrode and within the opening; The second electrode covers the light-emitting layer and the pixel defining layer in the opening; as well as The color filter layer is located above the second electrode.

15. The light-emitting diode display device according to claim 1, wherein the step compensation pattern has an uneven bottom surface and a flat top surface.

16. The light-emitting diode display device according to claim 1, further comprising: A transistor includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The first electrode is connected to the drain electrode, and the semiconductor layer comprises one of polycrystalline semiconductor material, amorphous semiconductor material, and oxide semiconductor material.

17. The light-emitting diode display device according to claim 1, further comprising: A third insulating layer is located between the substrate and the first insulating layer; as well as The signal line is disposed on the third insulating layer. The step compensation pattern thereon corresponds to the signal line.

18. The light-emitting diode display device according to claim 17, wherein the thickness of the step compensation pattern is greater than the thickness of the signal line.

19. The light-emitting diode display device of claim 17, wherein the first insulating layer has an uneven top surface and the step compensation pattern has a flat top surface.

20. A display panel, comprising: A substrate, the substrate including pixels, the pixels including light-emitting areas and non-light-emitting areas; A first insulating layer is disposed on the substrate; A step compensation pattern is disposed on the first insulating layer and corresponds to the light-emitting area; A second insulating layer covers the step compensation pattern; The first electrode is disposed on the second insulating layer and corresponds to the step compensation pattern; as well as A pixel defining layer is disposed on the second insulating layer and in the non-light-emitting area. The pixel defining layer covers the edge of the first electrode and has an opening corresponding to the center of the first electrode. The step compensation pattern has the same shape as the opening.

21. The display panel according to claim 20, further comprising: A third insulating layer is located between the substrate and the first insulating layer; as well as Multiple signal lines are arranged on the third insulating layer. The step compensation pattern thereon corresponds to the plurality of signal lines.

22. The display panel of claim 21, wherein the first insulating layer has an uneven top surface caused by step differences in the plurality of signal lines, and the step compensation pattern compensates for the uneven top surface of the first insulating layer to have an uneven bottom surface and a flat top surface.

23. The display panel according to claim 20, further comprising: A light-emitting layer is located on the first electrode and within the opening; as well as The second electrode covers the light-emitting layer and the pixel-defining layer in the opening.

24. The display panel of claim 23, wherein the step compensation pattern includes an extension portion. The extended portion extends from at least one end of the step compensation pattern to the pixel defining layer and protrudes from the first electrode. The second electrode is electrically connected to the extension portion of the step compensation pattern.

25. The display panel of claim 20, wherein the first electrode has a single-layer structure of a transparent conductive oxide layer, and The step compensation pattern thereon serves as a reflective layer for light passing through the first electrode.

26. The display panel according to claim 20, further comprising: A third insulating layer is located between the substrate and the first insulating layer; A first signal line is disposed on the third insulating layer and extends along a first direction; as well as The second signal line is disposed on the third insulating layer and extends along the first direction; The first signal line and the second signal line are spaced apart from each other in a second direction, and the second direction intersects the first direction. The step compensation pattern includes an extension line portion extending along the first direction, the extension line portion being positioned between the first signal line and the second signal line.

27. The display panel of claim 26, wherein in the second direction, the step compensation pattern has a first width, and the extension line portion has a second width, and The second width is less than the first width, and the second width is the same as the width of the first signal line and the second signal line.

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