Intelligent column address strobe (CAS) burst extension
By introducing the intelligent CAS burst continuation feature in the APU, the memory controller arbitrator prioritizes scheduling commands that fill data gaps, thus solving the data gap problem caused by the difference in memory bandwidth requirements between the CPU and GPU cores, and improving the efficiency of data bus utilization and memory access performance.
CN122270744APending Publication Date: 2026-06-23ADVANCED MICRO DEVICES INC
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ADVANCED MICRO DEVICES INC
- Filing Date
- 2024-06-17
- Publication Date
- 2026-06-23
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Figure CN122270744A_ABST
Abstract
A data processing system includes a data processor and a memory. The data processor is to issue memory commands including a first memory command to access a first size of data. The memory is to transfer the first size of data by separating a first portion of the data from a second portion of the data by a data gap. The data processor is operable to selectively prioritize and issue a second memory command after the first memory command is issued at a time to fill the data gap.
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