Method for address comparison checking of a packed launch queue, scalar processor, device

Abstract

This application provides an address comparison and checking method, scalar processor, and device for a compressed issue queue. The method acquires a first instruction and a second instruction from the compressed issue queue; and obtains an address comparison and checking result based on the address correlation between the first instruction and each second instruction. Furthermore, a comparison and checking result vector is formed, and this vector is updated in advance based on the instruction status in the compressed issue queue in the next cycle. This method, by obtaining the address comparison and checking result based on the address correlation between the first instruction and each second instruction, can flexibly support diverse memory access granularities with a small hardware area overhead while ensuring processor performance (timing). Additionally, by calculating the next state of the comparison and checking result in advance based on the enqueue / dequeue status of the issue queue determined in the current cycle, and updating it directly in the next cycle, it ensures a one-to-one correspondence between the address comparison and checking result and the new instruction position in the issue queue, while also optimizing timing.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, scalar processor, and device for address comparison and checking of a compressed transmit queue. Background Technology

[0002] In modern high-performance superscalar processor design, Instruction-Level Parallelism (ILP) is a core means of improving processor performance. To fully utilize ILP, processors typically employ out-of-order execution, allowing instructions to be executed out of program order, provided data dependencies are satisfied. This mechanism relies on a Reserve Station or Issue Queue—a key microarchitectural component used to cache decoded instructions, monitor the operand readiness status of instructions, and select ready instructions to issue to the execution unit. This is also the turning point for superscalar processors from sequential to out-of-order execution. Issue queues are divided into compressed and uncompressed types. In a compressed issue queue, when a corresponding entry is popped from the issue queue, it's equivalent to pulling a book from a stack of books; all the books above it will shift down to fill the empty slot. In an uncompressed issue queue, no shifting occurs.

[0003] In the processing of memory access instructions (including load and store instructions), the address comparison and checking circuit plays a crucial role. Its functions mainly include the following two aspects: First, there's the store-to-load forwarding detection. When a load instruction attempts to read data, the processor needs to check if there's an older store instruction with an overlapping address in the issue queue or store queue. If so, and the address matches exactly, the store data can be forwarded directly to the load instruction, avoiding access to the data cache and significantly reducing memory access latency.

[0004] Second, memory conflict detection. To ensure the correctness of program execution, when a Store instruction and a subsequent Load instruction access the same address (there is a true dependency or output dependency), the processor must ensure that they are executed in program order to avoid errors caused by data races.

[0005] As semiconductor technology advances into the deep submicron and even nanometer era, processor design complexity continues to increase, leading to greater depth and width of issue queues to support higher instruction throughput. However, traditional address comparison and checking circuit design faces increasingly severe challenges. First, in terms of timing, address comparison paths often become part of the chip's critical path, limiting the increase in processor clock speed. Second, in terms of area, fully interconnected comparison structures consume significant amounts of logic gates and routing resources. Finally, in terms of functionality, modern processors support various memory access granularities such as byte, half-word, word, and double-word; simple address equality comparisons are no longer sufficient to detect overlapping address ranges, requiring more complex circuit logic to support granularity-aware address checking.

[0006] Existing address comparison and checking methods for compressed transmit queues involve first compressing the queue and then performing address comparison and checking. This method leads to very tight timing in the subsequent arbitration circuit. Alternatively, the end address is calculated based on the memory access granularity and the start address, and then an overlap check is performed. This method results in a large number of large-bit-width comparators in the circuit, occupying a very large area. When the transmit queue depth is large, this overhead is enormous. Summary of the Invention

[0007] To address one of the aforementioned technical deficiencies, this application provides a method for address comparison and checking of a compressed transmit queue, a scalar processor, and a device.

[0008] The first aspect of this application provides a method for address comparison and checking of a compressed transmit queue, the method comprising: Retrieve the first instruction from the compressed launch queue; All instructions preceding the first instruction in the compressed launch queue are designated as the second instruction. Determine whether the addresses of the first instruction and each of the second instructions are related; If all second instructions are address-independent, the address comparison check result of the first instruction is determined to be a pass; otherwise, the address comparison check result of the first instruction is determined to be a fail.

[0009] A second aspect of this application provides a scalar processor that includes a compressed issue queue and an address comparator; Among them, the compressed issue queue is the issue queue of the scalar arithmetic unit and / or the issue queue of the memory access unit in the scalar processor; An address comparator is used to perform address comparison checks on a compressed transmit queue as described in the first aspect.

[0010] A third aspect of this application provides an electronic device, including: a memory, a scalar processor, and a vector processor; The scalar processor includes a compressed issue queue and an address comparator; Compressed issue queues are issue queues for scalar arithmetic units and / or memory access units in scalar processors. An address comparator is used to perform address comparison checks on the compressed transmit queue using the method described in the first aspect.

[0011] This application provides an address comparison and checking method, a scalar processor, and a device for a compressed issue queue. The method includes: acquiring a first instruction in the compressed issue queue; identifying all instructions preceding the first instruction in the compressed issue queue as second instructions; determining whether the addresses of the first instruction and each of the second instructions are related; if all the second instructions are address-independent, then the address comparison and checking result of the first instruction is determined to be passed; otherwise, the address comparison and checking result of the first instruction is determined to be failed. This method determines whether the addresses of the first instruction and each of the second instructions are related; if all the second instructions are address-independent, then the address comparison and checking result of the first instruction is determined to be passed; otherwise, the address comparison and checking result of the first instruction is determined to be failed. This allows for flexible support of diverse memory access granularities with a smaller hardware area overhead, while ensuring processor performance (timing). Furthermore, based on the enqueue and queuing status of the issue queue instructions determined in the current cycle, the next state of the comparison and checking result is calculated in advance and updated directly in the next cycle. This ensures a one-to-one correspondence between the address comparison and checking result and the new position of the instruction in the issue queue, while also optimizing timing. Attached Figure Description

[0012] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A flowchart illustrating an address comparison and checking method for a compressed transmit queue provided in an embodiment of this application; Figure 2 A schematic diagram of a compressed launch queue provided in an embodiment of this application; Figure 3 A schematic diagram of a fetch unit queue provided in an embodiment of this application; Figure 4 This is a schematic diagram of a queue in the instruction fetch unit provided in an embodiment of this application; Figure 5 This is a schematic diagram of another queue in the instruction fetch unit provided in the embodiments of this application; Figure 6 This is a schematic diagram of another compressed launch queue provided in an embodiment of this application; Figure 7A schematic diagram of an address comparison and check matrix provided in an embodiment of this application; Figure 8 This is a schematic diagram of another compressed launch queue provided in an embodiment of this application; Figure 9 This is a schematic diagram of another address comparison and check matrix provided in an embodiment of this application; Figure 10 A schematic diagram of the architecture of a scalar processor provided for an embodiment of this application; Figure 11 A schematic diagram of a synchronization unit provided in an embodiment of this application; Figure 12 A schematic diagram of the architecture of a vector processor provided in an embodiment of this application; Figure 13 A schematic diagram of the architecture of a vector processor provided in an embodiment of this application; Figure 14 This is a schematic diagram of the overall architecture of the scalar processor and vector processor provided in the embodiments of this application. Detailed Implementation

[0013] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0014] In developing this application, the inventors discovered that existing address comparison and checking methods for compressed transmit queues involve first compressing the queue and then performing address comparison and checking. This method leads to very tight timing in the subsequent arbitration circuit. Alternatively, the end address is calculated based on the memory access granularity and the start address, and whether there is overlap is determined. This method results in a large number of large-bit-width comparators in the circuit, occupying a very large area. When the transmit queue depth is large, this overhead is enormous.

[0015] To address the aforementioned issues, this application provides an address comparison and checking method, scalar processor, and device for a compressed issue queue. The method includes: acquiring a first instruction in the compressed issue queue; identifying all instructions preceding the first instruction in the compressed issue queue as second instructions; determining whether the addresses of the first instruction and each second instruction are related; if all second instructions are address-independent, then the address comparison and checking result of the first instruction is determined to be passed; otherwise, the address comparison and checking result of the first instruction is determined to be failed. This method determines whether the addresses of the first instruction and each second instruction are related; if all second instructions are address-independent, then the address comparison and checking result of the first instruction is determined to be passed; otherwise, the address comparison and checking result of the first instruction is determined to be failed. This allows for flexible support of diverse memory access granularities with minimal hardware area overhead, while ensuring processor performance (timing). Furthermore, based on the enqueue and queuing status of the issue queue instructions determined in the current cycle, the next state of the comparison and checking result is calculated in advance and updated directly in the next cycle. This ensures a one-to-one correspondence between the address comparison and checking result and the new position of the instruction in the issue queue, while also optimizing timing.

[0016] Example 1 See Figure 1 This embodiment provides an address comparison and checking method for a compressed transmit queue. The implementation process of this method is as follows: 101, Retrieve the first instruction in the compressed launch queue.

[0017] Among them, the compressed issue queue can be the issue queue of the scalar arithmetic unit and / or the issue queue of the memory access unit in the scalar processor.

[0018] Whenever an instruction is selected to leave the compressed launch queue, an empty area is left, similar to pulling a book out of a stack. All the other books on top of it shift downwards to fill the empty space due to gravity. At this point, all the instructions in the compressed launch queue are tightly packed together, one after another. Newly written instructions are written directly to the top. This design ensures that all instructions are naturally arranged from oldest to newest from bottom to top in the compressed launch queue.

[0019] Each image in a compressed emit queue needs to be newly written to the image, and then pass through itself and all the images above it, such as... Figure 2 As shown.

[0020] The scalar processor includes a detailed description of its specific structure in the subsequent scalar processor embodiment (i.e., embodiment 2), which will not be elaborated on here.

[0021] In addition, the instructions in the compressed launch queue are written according to existing implementation schemes, such as being allocated and written to the compressed launch queue after being fetched, decoded, and renamed.

[0022] In practice, the instructions in the compressed launch queue include branch instructions and non-branch instructions.

[0023] For branch instructions, a jump occurs based on the true / false condition. This jump interrupts instruction processing in the pipeline because the processor cannot determine the next instruction until the branch instruction is completed. The longer the pipeline, the longer the processor waits, as it must wait for the branch instruction to finish processing before determining the next instruction to enter the pipeline. To reduce the processing time of branch instructions, instructions can be fetched in steps 201 and 202 (in practice, steps 201 and 202 can be executed by the instruction fetch unit), and the fetched instructions are then written to a compressed issue queue.

[0024] 201, Determine the jump address for the branch instruction.

[0025] Branch instructions that appear in the program flow (such as...) Figure 3 The SEQ instruction in the instruction may be an upward jump, a downward jump, or an instruction executed out of order. Which case it is depends on the execution of the branch instruction, and only then can the jump address be determined. Therefore, branch instructions can be fetched from the sequential execution queue (which may be located within the instruction fetch unit), and the jump address is determined during the execution of the branch instruction.

[0026] In addition, current branch prediction technology can predict the jump direction of branch instructions in advance, speeding up the operation. Based on this, the jump address can also be determined through branch prediction.

[0027] 202. When the instruction corresponding to the jump address exists only in the branch optimization queue, retrieve the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue.

[0028] If the instruction corresponding to the jump address exists only in the branch optimization queue, the instruction corresponding to the jump address and subsequent instructions are retrieved from the branch optimization queue and written into the sequential execution queue of the instruction fetch unit so that the instruction corresponding to the jump address and subsequent instructions can be executed.

[0029] The branch optimization queue is also located within the instruction fetch unit. The initial value of the branch optimization queue is empty, and its fields are identical to those of the sequential execution queue. The instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when a branch instruction is fetched from the instruction cache.

[0030] like Figure 3As shown, the instruction fetch unit includes a branch optimization queue and a sequential execution queue. When the instruction corresponding to the jump address exists only in the branch optimization queue (i.e., the instruction corresponding to the jump address does not exist in the sequential execution queue included by the instruction fetch unit, but exists in the branch optimization queue), the instruction fetch unit will fetch the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue. In other words, when the instruction fetch unit does not have the instruction corresponding to the jump address in the branch optimization queue, it will not fetch the instruction from the instruction cache, but will fetch the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue. This avoids the reduction in processor power consumption and execution efficiency caused by the prior art, where the instruction fetch unit will fetch the instruction from the instruction cache whenever the instruction fetch unit does not have the instruction corresponding to the jump address in the branch optimization queue.

[0031] Furthermore, in practical implementation, the branch optimization queue can be further subdivided, such as a branch optimization queue including at least one upward jump optimization queue and at least one branch prefetch optimization queue (e.g. Figure 4 (As shown). Alternatively, a branch optimization queue, comprising at least one upward jump optimization queue, at least one branch prefetch optimization queue, and at least one maneuver queue (as shown). Figure 5 (As shown).

[0032] The aforementioned candidate branch optimization queue can be an upward jump optimization queue, or it can be a branch prefetch optimization queue.

[0033] The branch optimization queue does not actively initiate instruction fetch requests; it only passively receives instructions. The jump-up optimization queue only stores the jump address instructions for the previous branch, and the branch prefetch optimization queue only stores the jump address instructions for the next and longest branches.

[0034] The jump initial value is read from the register before executing steps 201 and 202. .in, The configuration is made in the register by the configuration instructions of the program to which the instruction belongs.

[0035] One of the multiple branch optimization queues is designated as the branch prefetch optimization queue. In other words, there must be at least one branch prefetch optimization queue.

[0036] like This indicates that the number of non-branch prefetch optimization queues in the branch optimization queue is insufficient, or that it is exactly equal to the jump initial value. If this happens, then all other branch optimization queues will be designated as upward jump optimization queues. At this point, the branch optimization queues will contain only one upward jump optimization queue and at least one branch prefetch optimization queue.

[0037] in, Optimize the total number of queues for branching.

[0038] like This indicates that the number of non-branch prefetch optimization queues in the branch optimization queue is greater than the jump initial value. Then the remaining branches will be optimized randomly in the queue. One queue is designated as the upward jump optimization queue, and the remaining branch optimization queue is designated as the maneuver queue. At this point, the branch optimization queue includes one upward jump optimization queue. One branch prefetch optimization queue and at least one maneuver queue.

[0039] The above process ensures that the hardware resource usage of the branch optimization queue is adapted to the program to which the instruction belongs. Using more branch optimization queues is wasteful when the loop frequency is low; therefore, unnecessary hardware overhead can be reduced while making full use of existing resources. Each branch optimization queue is accessed in parallel.

[0040] After executing step 201, it will be determined whether the queue has been hit based on the branch optimization mode and the jump address.

[0041] Specifically: If the branch optimization mode is upward jump and the jump address is upward, then check if the upward jump optimization queue has been hit. If the branch optimization mode is branch prefetch and the jump address is downward, then check if the branch prefetch optimization queue has been hit. If the branch optimization mode is both upward jump and branch prefetch and the jump address is upward, then check if the upward jump optimization queue has been hit. If the branch optimization mode is both upward jump and branch prefetch and the jump address is downward, then check if the branch prefetch optimization queue has been hit.

[0042] Among them, the hit queue contains instructions corresponding to the jump address.

[0043] The hit queue, in the branch optimization queue corresponding to the branch optimization mode, is the queue containing the instructions corresponding to the jump address. If a hit queue exists, it means that the branch optimization queue contains a queue storing the instructions corresponding to the jump address. The instructions corresponding to the jump address and subsequent instructions can be directly retrieved from this queue for execution, achieving fast instruction fetching for branch instructions that require a jump during the instruction execution phase.

[0044] If no hit queue is found, it means that no queue in the branch optimization queue stores the instruction corresponding to the jump address. A queue (i.e., the replacement queue) will be selected, and the instruction corresponding to the jump address and subsequent instructions will be stored in the replacement queue. Then, when the same branch instruction is found during the instruction execution phase, the instruction can be quickly fetched.

[0045] Among them, (a) the process of selecting a queue (i.e., replacing the queue) is as follows: If no hit queue exists, then if the branch optimization mode is an upward jump and the jump address is upward, the replacement queue is determined from the upward jump optimization queue. If the branch optimization mode is a branch prefetch and the jump address is downward, the replacement queue is determined from the branch prefetch optimization queue. If the branch optimization mode is both upward jump and branch prefetch and the jump address is upward, the replacement queue is determined from the upward jump optimization queue. If the branch optimization mode is both upward jump and branch prefetch and the jump address is downward, the replacement queue is determined from the branch prefetch optimization queue.

[0046] This process can determine the replacement queue from the branch optimization queue corresponding to the obtained branch optimization mode.

[0047] The process of determining the replacement queue in the upward jump optimization queue is as follows: If an empty upward jump optimization queue exists, it means that an empty upward jump optimization queue exists. In this case, an empty upward jump optimization queue can be randomly selected as the replacement queue. That is, an empty upward jump optimization queue is preferred as the replacement queue.

[0048] If there is no empty jump-up optimization queue, then: When there is only one queue for upward jump optimization, it is designated as the replacement queue.

[0049] When there are two upward jump optimization queues, the upward jump optimization queue that was not used as a replacement queue in the previous step is determined as the replacement queue.

[0050] When there are two or more upward jump optimization queues, the upward jump optimization queue with the smallest value will be selected as the replacement queue.

[0051] The selection value of any upward jump optimization queue is the sum of all elements in the corresponding row of the upward jump selection matrix for any upward jump optimization queue.

[0052] The upward jump selection matrix is ​​one Matrix, where, The total number of upward jump optimization queues is determined. Each row in the upward jump selection matrix uniquely corresponds to an upward jump optimization queue. The upward jump selection matrix is ​​initially a 0-matrix. When a certain upward jump optimization queue... When a queue is selected for replacement, jump up to the selection matrix. The elements in the first row are updated to 1, then the selection is moved up to the next element in the matrix. The elements of the column are then updated to 0, where the first element is... Behavior-based upward jump optimization queue Jump up to select the corresponding row in the matrix.

[0053] The process of determining the replacement queue in the branch prefetch optimization queue is as follows: If an empty branch prefetch optimization queue exists, it means that an empty branch prefetch optimization queue exists, and in this case, an empty branch prefetch optimization queue can be designated as the replacement queue. That is, an empty branch prefetch optimization queue is preferentially selected as the replacement queue.

[0054] If there is no empty branch prefetch optimization queue, then: When there is only one branch prefetch optimization queue, it is designated as the replacement queue.

[0055] When there are two branch prefetch optimization queues, the branch prefetch optimization queue that was not used as a replacement queue in the previous step is determined as the replacement queue.

[0056] When there are two or more branch prefetch optimization queues, the branch prefetch optimization queue with the smallest selection value is determined as the replacement queue.

[0057] The selection value of any branch prefetch optimization queue is the sum of all elements in the corresponding row of the branch prefetch selection matrix for any branch prefetch optimization queue.

[0058] The branch prefetch selection matrix is ​​one Matrix, where, This represents the total number of branch prefetch optimization queues. Each row in the branch prefetch selection matrix uniquely corresponds to a branch prefetch optimization queue. The branch prefetch selection matrix is ​​initially a 0-matrix. When a certain branch prefetch optimization queue... When a queue is identified as a replacement queue, the branch prefetch selection matrix is... The elements of the first row are updated to 1, and the branch prefetch selection matrix is ​​then used. The elements of the column are then updated to 0, where the first element is... Behavior branch prefetch optimization queue The corresponding row in the branch prefetch selection matrix.

[0059] (b) The process of storing the instruction corresponding to the jump address and subsequent instructions into the replacement queue is as follows: Retrieve the instruction and subsequent instructions corresponding to the jump address from the instruction cache, and store the instruction and subsequent instructions corresponding to the jump address into the replacement queue.

[0060] The process of storing the instruction corresponding to the jump address and subsequent instructions into the replacement queue is as follows: If the replacement queue is empty, the instruction corresponding to the jump address and subsequent instructions are sequentially stored in the replacement queue.

[0061] If the replacement queue is not empty, all instructions in the replacement queue are popped, and the instruction corresponding to the jump address and subsequent instructions are sequentially stored in the replacement queue.

[0062] Alternatively, if a hit queue exists, step 202 is executed, in which case instructions are fetched sequentially starting from the head of the hit queue.

[0063] By using steps 201 and 202, when the instruction corresponding to the jump address exists only in the branch optimization queue, the instruction corresponding to the jump address and subsequent instructions can be retrieved from the branch optimization queue. This means that when a branch jump occurs, only the instruction corresponding to the jump address and subsequent instructions need to be retrieved from the branch optimization queue, without having to start fetching instructions sequentially again. This reduces the processor's power consumption and improves execution efficiency.

[0064] 102. All instructions preceding the first instruction in the compressed launch queue are designated as the second instruction.

[0065] It should be noted that the first instruction and the second instruction in this embodiment and subsequent embodiments are both instructions in the compressed transmission queue. The first and second instructions are only added to distinguish the instruction being checked from the instruction being compared. That is, if an address comparison check is performed on an instruction in the compressed transmission queue, then that instruction is the first instruction, and the comparison instruction when performing the address comparison check is the second instruction.

[0066] Because address-related violations need to consider instruction age, the above logic is only used to compare and check each instruction in the compressed transmit queue with all instructions preceding it. For example, if the compressed transmit queue for a certain cycle is... Figure 6 As shown, Figure 6 In 3-A, "3" represents the instruction identifier, "A" represents the address region identifier, and "-" indicates a correspondence; 3-A means the address region for instruction 3 is A. Additionally, "?" indicates that the address calculation is incomplete; 4-?" means the address region for instruction 4 is incomplete. The meanings of other values ​​such as 0-A are similar to 3-A and will not be explained individually.

[0067] If an address comparison check is performed on a certain instruction (such as instruction 5) in the compressed transmit queue, then instruction 5 is the first instruction, and all instructions before instruction 5 in the compressed transmit queue (such as instructions 0, 1, 2, 3, and 4) are comparison instructions, i.e., the second instructions.

[0068] If an address comparison check is performed on a certain instruction (such as instruction 0) in the compressed launch queue, then instruction 0 is the first instruction. If there are no instructions before instruction 0 in the compressed launch queue, then the second instruction is empty.

[0069] 103. Determine whether the addresses of the first instruction and each of the second instructions are related.

[0070] If the second instruction is empty (e.g., the first instruction is instruction 0), since there is no comparison instruction, directly determining the address is irrelevant.

[0071] If there is only one second instruction (e.g., if the first instruction is instruction 1, then the second instruction is instruction 0), then step 103 will determine whether the addresses of instruction 1 and instruction 0 are related.

[0072] If there are multiple second instructions (e.g., if the first instruction is instruction 5, then the second instructions are instructions 0, 1, 2, 3, and 4), then for each second instruction, step 103 will be executed to determine whether instruction 5 is related to its address. For example, step 103 will determine whether instruction 5 is related to the address of instruction 0, whether instruction 5 is related to the address of instruction 1, whether instruction 5 is related to the address of instruction 2, whether instruction 5 is related to the address of instruction 3, and whether instruction 5 is related to the address of instruction 4.

[0073] For any second instruction, the implementation process of step 103 determining whether the addresses of the first instruction and any second instruction are related is as follows: If the address of any second instruction has not been calculated (i.e. the instruction is valid, but the address calculation is not complete), for safety reasons, the first instruction should be considered to be address-dependent with any second instruction (i.e., the first instruction and any second instruction are determined to be address-dependent).

[0074] The compressed launch queue of the current cycle, such as Figure 6 For example, if the first instruction is instruction 5 and any second instruction is instruction 4, and the address of instruction 4 has not yet been calculated, then it will be determined that the addresses of instruction 5 and instruction 4 are related.

[0075] If the address calculation for any second instruction is completed, then based on the starting address bits of the first instruction and the starting address bits of any second instruction, determine whether the addresses of the first instruction and any second instruction are related.

[0076] Still using the current cycle of compressed launch queues, such as Figure 6 For example, if the first instruction is instruction 5 and any second instruction is instruction 3, and the address of instruction 3 has been calculated, then the starting address bits of instruction 3 (such as iAddr0) and the starting address bits of instruction 3 (such as iAddr1) will be used to determine whether the addresses of instruction 5 and instruction 3 are related.

[0077] When determining whether the addresses of the first instruction and any second instruction are related based on the starting address bits of the first instruction and the starting address bits of any second instruction, it is possible to: 301. Based on the access granularity of the first instruction and the access granularity of any second instruction, obtain the granularity access mask.

[0078] For example, the granularity of access can be obtained based on the access granularity of instruction 5 and instruction 3.

[0079] The specific implementation process is as follows: Determine the largest granularity between the access granularity of the first instruction and the access granularity of any second instruction. Shift the 6-bit binary number, all of which is 1, left by BigGran bits to obtain the granularity access mask.

[0080] BigGran is the granularity code corresponding to the largest granularity. The width of BigGran can be 3 bits, i.e. BigGran[2:0], where 0 represents the least significant bit of BigGran and 2 represents the most significant bit of BigGran. BigGran consists of 3 bits, namely the 0th bit, the 1st bit, and the 2nd bit.

[0081] The processor supports multiple memory access granularities such as byte, half word, word, and double word. Simple address equality comparison can no longer meet the requirements for detecting overlapping address ranges. More complex circuit logic is needed to support granularity-aware address checking. Therefore, when obtaining the granularity access mask, the largest granularity between the access granularity of the first instruction and the access granularity of any second instruction is determined first.

[0082] Before executing step 301, the granularity code corresponding to each access granularity will also be set. For example, the granularity codes corresponding to each access granularity in a 32-bit system are shown in Table 1.

[0083] Table 1

[0084] Taking "3'b100" as an example, 3 represents the width of the granularity code, that is, the granularity code is 3 bits, 'b represents binary, and 100 is the granularity code. For the meaning of other granularity codes, please refer to 3'b100.

[0085] In addition, the access granularity, granularity encoding, and the correspondence between access granularity and granularity encoding in Table 1 are only examples. This embodiment does not impose any specific limitations. The actual implementation can be carried out according to the actual situation.

[0086] by Figure 6Taking instructions 5 and 3 as examples, if the access granularity of instruction 3 is "non-vector, word" and the access granularity of instruction 5 is "non-vector, byte", since a byte in a 32-bit system is 8 bits and a word is 32 bits, the largest granularity between the access granularities of instruction 3 and instruction 5 is determined to be 32 bits "non-vector, word". According to Table 1, the granularity code corresponding to the largest granularity "non-vector, word" is 3'b010 (i.e., BigGran[2:0] = 3'b010). Then, the 6-bit binary number (which can be represented as 6'b111111) is shifted left by 3'b010 bits to obtain the granularity access mask as 6'b111100. The width of the granularity access mask is 6 bits. If the granularity access mask is denoted as GranMask[5:0], then GranMask[5:0] = 6'b111100.

[0087] 302. Based on the starting address bit of the first instruction, the starting address bit of any second instruction, and the granularity access mask, determine whether the addresses of the first instruction and any second instruction are related.

[0088] For example, based on the starting address bits of instruction 5, the starting address bits of instruction 3, and the granularity access mask, it can be determined whether the addresses of instruction 5 and instruction 3 are related.

[0089] The specific implementation process is as follows: A 42-bit binary number consisting entirely of 1s is concatenated with a granular access mask to obtain the concatenation number Con. If the value of (iAddr0^iAddr1)&Con is 1, it is determined that the addresses of the first instruction and any second instruction are independent. If the value of (iAddr0^iAddr1)&Con is 0, it is determined that the addresses of the first instruction and any second instruction are dependent.

[0090] Where iAddr0 is the starting address bit accessed by the first instruction, iAddr1 is the starting address bit of any second instruction, ^ is the bitwise XOR operator, and & is the bitwise AND operator.

[0091] The width of the starting address bits can be 48 bits, such as iAddr0[47:0], iAddr1[47:0].

[0092] Still with Figure 6Taking instructions 5 and 3 as examples, a 42-bit binary number consisting entirely of 1s (denoted as 42{1'b1}, where 42 represents 42 bits, {} is the repetition operator, 1'b1 is a 1-bit binary number, and 42{1'b1} repeats the 1-bit binary number 42 times) is concatenated with the granularity access mask GranMask[5:0] to obtain the concatenated number Con. Thus, Con has a total of 48 bits, namely Con[47:0], where the lower 6 bits of Con (i.e., Con[5:0]) are GranMask[5:0], and the higher 42 bits of Con (Con[47:6]) are 42{1'b1}.

[0093] If (iAddr0[47:0]^iAddr1[47:0])&Con[47:0]=1, then it is determined that the addresses of instruction 5 and instruction 3 are not related. If (iAddr0[47:0]^iAddr1[47:0])&Con[47:0]=0, then it is determined that the addresses of instruction 5 and instruction 3 are related.

[0094] 104. If all second instructions are address-independent, then the address comparison check of the first instruction is considered passed. Otherwise, the address comparison check of the first instruction is considered failed.

[0095] If all second instructions are address-independent, it means that the addresses of the first instruction and all second instructions are not related, so the first instruction can be issued. Therefore, the address comparison check result of the first instruction is determined to be a pass.

[0096] In addition, other checks can be performed during implementation. In this case, if the addresses of all second instructions are irrelevant and all other checks determine that the instruction can be transmitted, the address comparison check of the first instruction is deemed to have passed. Otherwise, the address comparison check of the first instruction is deemed to have failed.

[0097] For ease of processing, an address comparison check matrix can be formed according to the order of instructions in the compressed issue queue. This matrix can then be used to determine whether all second instructions are address-independent. (Continuing with...) Figure 6 For example, the address comparison check matrix can be as follows: Figure 7 As shown. Figure 7 In the address comparison check matrix, both rows and columns represent instructions in the compressed issue queue. 1 indicates address-independent, and 0 indicates address-dependent. The value of a certain row x and column y in the address comparison check matrix is ​​used... This indicates that the first instruction in the first row and first column is instruction 0, and its second instruction is empty. In this case, the address is irrelevant, therefore the value in the first row and first column is... The value in row 2, column 1 indicates that the first instruction is instruction 1, and the second instruction is instruction 0. If the addresses of instruction 1 and instruction 0 are not related at this point, then the value in row 2, column 1 is... The value in row 4, column 1 indicates that the first instruction is instruction 3, and the second instruction is instruction 0. If the addresses of instruction 3 and instruction 0 are related, then the value in row 4, column 1 is... Since the second instruction comprises all instructions preceding the first instruction, the address relationship is not determined for the first instruction itself or for any instructions following it. Figure 7 The Chinese character "-" is used to represent this. Figure 7 For the meaning of other numbers in the text, please refer to the reference. The explanations provided are sufficient; I will not go into detail about each one.

[0098] Figure 7 In the address comparison check matrix shown, each row represents a structure indicating whether the address of the corresponding instruction (as the first instruction) is related to the addresses of its respective second instructions. Therefore, during step 104, a bitwise AND operation can be performed on all values ​​in the row corresponding to that instruction. If the result is 1, it means that all values ​​are 1, i.e., all second instructions are address-independent, and the address comparison check result for the first instruction is determined to be passed. Otherwise, it means that there is a value of 0, and the address comparison check result for the first instruction is determined to be failed.

[0099] based on Figure 7 The address comparison check matrix shown yields the address comparison check result CompPass= for each instruction. Where 0 indicates that the check failed and 1 indicates that the check passed.

[0100] Taking instruction 3 as an example, its failure to pass the check means that instruction 2 cannot be launched before instruction 0 is launched.

[0101] The compressed launch queue has a total of 4 stages: command dispatch → wake-up → address calculation → launch arbitration.

[0102] Instruction dispatch: Instructions are input from the previous stage circuit to the issue queue and stored in the empty entries. Since the issue queue is a compressed design, a write pointer needs to be maintained in the actual implementation.

[0103] Wake-up: Select two instructions with ready address registers from the compressed issue queue and read operands from the register file.

[0104] Address calculation: Calculate the memory access address and granularity based on the instruction type.

[0105] Launch arbitration: Arbitration is conducted in accordance with a set of launch rules.

[0106] In practical implementation, if the address comparison and checking method of the compressed transmit queue provided in this embodiment is executed after the address calculation stage (i.e., the transmit arbitration stage), and the address information in the compressed transmit queue is used for comparison and checking, along with other arbitration methods to select the instruction that can be transmitted, it may put a lot of pressure on the timing of the arbitration-level circuit, making it difficult to achieve high frequency and high performance. Furthermore, the depth of the compressed queue is also difficult to increase, which greatly limits the performance of out-of-order transmission. Therefore, considering the pipeline timing balance between the execution of the address comparison and checking method of the compressed transmit queue provided in this embodiment and the address calculation, the address comparison and checking method of the compressed transmit queue provided in this embodiment is executed during the address calculation stage. The address comparison and checking method of the compressed transmit queue provided in this embodiment checks each instruction in the queue pairwise, and generates a vector of comparison and checking results based on the queue compression situation in each iteration. Due to logic shifts, the following issues need to be considered when executing the address comparison and checking method of the compressed transmit queue provided in this embodiment: 1. The instructions involved in the comparison are not only those instructions whose address calculation has been completed in the queue, but also those instructions whose address calculation has just been completed in the current cycle.

[0107] 2. Since there are still some instructions that are about to be issued in the cycle, the issued instructions are considered to be address-independent of all instructions, and there is no need to perform address comparison checks.

[0108] 3. At the same time, in the next cycle, the queue will be compressed because an instruction is being sent out. The address comparison check matrix will also be compressed accordingly, corresponding one-to-one with the position of the compressed transmission queue.

[0109] Therefore, the address comparison and check method of the compressed transmission queue provided in this embodiment will be executed in real time to obtain real-time and accurate address comparison and check results.

[0110] In addition, in order to reduce the use of register resources, the entire address comparison check matrix is ​​not clocked during the address calculation stage. Instead, the final CompPass is clocked. The CompPass is a vector that corresponds one-to-one with the position of the transmit queue. Therefore, it needs to be compressed according to the transmit situation.

[0111] Considering the above issues, after obtaining the address comparison check results of each instruction (i.e. the first instruction) in the compressed launch queue, a comparison check result vector of the compressed launch queue will be formed; wherein, the comparison check result vector includes at least one address comparison check result, the number of address comparison check results included in the comparison check result vector is the same as the number of instructions in the compressed launch queue, and the order of the address comparison check results included in the comparison check result vector is the same as the order of instructions in the compressed launch queue.

[0112] For example, the compressed launch queue for a certain cycle is: Figure 8 At the CLK time shown, the address comparison check results for instructions 0, 1, 2, and 3 in the compressed transmit queue are all 0, and the address comparison check results for instructions 4, 5, and 6 are all 1, obtained through the address comparison check method provided in this embodiment. Therefore, the comparison check result vector is... The correspondence between the comparison and inspection result vector and the instructions in the compressed launch queue is shown in Table 2.

[0113] Table 2

[0114] If instruction 0 and instruction 1 are to be transmitted in the next clock cycle, then instruction 0 and instruction 1 will leave the compressed transmission queue in the next clock cycle. That is, the compressed transmission queue in the next clock cycle will be as follows: Figure 8 The comparison result vector is shown at time CLK+1. Since both instruction 0 and instruction 1 are first target instructions, the address comparison result corresponding to the first target instruction will be deleted from the comparison result vector, and the subsequent address comparison results in the comparison result vector will be compressed (i.e., instructions 1-6 will be shifted forward in sequence), resulting in the following comparison result vector: The correspondence between the comparison check result vector and the instructions in the compressed launch queue at this time is shown in Table 3.

[0115] Table 3

[0116] If instruction 7 is to be written in the next cycle, then instruction 7 will be written to the compressed transmit queue in the next cycle. In this case, instruction 7 is the second target instruction. The address comparison check result of instruction 7 will be determined using the address comparison check method of the compressed transmit queue provided in this embodiment (e.g., the address comparison check result of instruction 7 is 0). The address comparison check result corresponding to the second target instruction will be added to the comparison check result vector, resulting in the following comparison check result vector: The correspondence between the comparison check result vector and the instructions in the compressed launch queue at this time is shown in Table 4.

[0117] Table 4

[0118] If instruction 0 and instruction 1 are transmitted in the next clock cycle, and instruction 7 is written simultaneously, then instruction 0 and instruction 1 are both the first target instruction, and instruction 7 is the second target instruction. In this case, the address comparison check result corresponding to the first target instruction is deleted from the comparison check result vector, and subsequent address comparison check results in the comparison check result vector are compressed (i.e., instructions 1-6 are shifted forward in sequence). Simultaneously, the address comparison check result of instruction 7 is determined using the compressed transmission queue address comparison check method provided in this embodiment (e.g., the address comparison check result of instruction 7 is 0). The address comparison check result corresponding to the second target instruction is then added to the comparison check result vector, resulting in the following comparison check result vector: The correspondence between the comparison check result vector and the instructions in the compressed launch queue at this time is shown in Table 5.

[0119] Table 5

[0120] The above process obtains the address comparison and check results of each instruction in the compressed transmit queue in the current cycle using the address comparison and check method provided in this embodiment, resulting in a comparison and check result vector. Furthermore, based on the enqueue and queuing status of the transmit queue instructions determined in the current cycle, the next state of the comparison and check results is calculated in advance and updated directly in the next cycle. This ensures a one-to-one correspondence between the address comparison and check results and the new positions of the instructions in the transmit queue, while also optimizing timing.

[0121] Taking a compressed launch queue depth of 8 as an example, such as Figure 8 As shown, the implementation process of the address comparison and checking method for the compressed transmit queue provided in this embodiment will be explained again.

[0122] Initially, the compressed transmit queue is empty, and the compressed transmit queue write pointer points to 0; At time CLK, in the compressed issue queue, address region A is stored at position 0 of queue, address region B is stored at position 1 of queue, address region C is stored at position 2 of queue, address region A is stored at position 3 of queue, and address region A is stored at position 4 of queue, which is marked as a question mark because the address of instruction 4 has not yet been calculated. The other positions are similarly marked. The address comparison and checking method of the compressed issue queue provided in this embodiment is used to determine whether the addresses of each first instruction and each second instruction are related. Figure 7 The address comparison check matrix shown is used to obtain the address comparison check result CompPass=. .

[0123] At time CLK, instructions 0, 1, and 2 are the three oldest instructions that are unrelated to each other. Without further checks, instructions 0 and 1 can be issued. However, for the sake of illustrating matrix changes, we assume there are additional checks. Ultimately, it is determined that instructions 0 and 2 can be issued, but they haven't been dequeued (i.e., they haven't left the compressed issue queue, so they are not issued). They will be dequeued in the next cycle. Simultaneously, instruction 4 completes its calculation in time CLK – region B – but hasn't been written into the compressed issue queue (i.e., it hasn't been enqueued). It will be written in the next cycle. At this point, we can use the address comparison and checking method of the compressed issue queue provided in this embodiment again to obtain a new conclusion about whether the addresses of each first instruction and each second instruction are related, such as forming... Figure 9 The new address comparison check matrix shown yields the new address comparison check result CompPass= At this point, both the transmitted command and the command whose address calculation is complete should be considered. The transmitted command is considered to be address-independent of all commands, and no address comparison check is required.

[0124] At time CLK+1, instructions 0 and 2 are successfully issued and popped from the compressed issue queue. The computed address of instruction 4 is also written into the compressed issue queue. At this point, the compression of the compressed issue queue is complete. Specifically, the compression process is as follows: There is one empty space below instruction 1; move it down 1 space. There are two empty spaces below instructions 3, 4, 5, and 6; shift down 2 spaces. Meanwhile CompPass= It should correspond one-to-one with the command position in the launch queue, therefore it should shift according to the command, and CompPass should be updated accordingly. .

[0125] The address comparison and checking method of the compressed launch queue provided in this embodiment can flexibly support diverse memory access granularities with a small hardware area overhead while ensuring processor performance (timing). This overcomes the shortcomings of poor timing, large area and weak functional adaptability in the prior art.

[0126] This embodiment provides an address comparison and checking method for a compressed issue queue. The method involves obtaining a first instruction from the compressed issue queue; identifying all instructions preceding the first instruction as second instructions; determining whether the addresses of the first instruction and each second instruction are related; if all second instructions are address-independent, the address comparison and checking result of the first instruction is considered passed; otherwise, the address comparison and checking result of the first instruction is considered failed. This method determines whether the addresses of the first instruction and each second instruction are related; if all second instructions are address-independent, the address comparison and checking result of the first instruction is considered passed; otherwise, the address comparison and checking result of the first instruction is considered failed. This allows for flexible support of diverse memory access granularities with minimal hardware area overhead, while ensuring processor performance (timing). Furthermore, based on the enqueue and dequeue status of the issue queue instructions determined in the current cycle, the next state of the comparison and checking result is calculated in advance and updated directly in the next cycle. This ensures a one-to-one correspondence between the address comparison and checking result and the new position of the instruction in the issue queue, while also optimizing timing.

[0127] Example 2 Based on the same inventive concept as the above method, this embodiment provides a scalar processor, which includes a compressed issue queue and an address comparator.

[0128] Among them, the compressed issue queue is the issue queue of the scalar arithmetic unit and / or the issue queue of the memory access unit in the scalar processor.

[0129] An address comparator is used to perform address comparison checks on a compressed transmit queue using the address comparison check method for the compressed transmit queue shown in Example 1.

[0130] The execution process of the address comparison and checking method for the compressed transmission queue can be referred to in Example 1, and will not be explained in detail here.

[0131] In addition, a scalar processor also includes: an instruction fetch unit, a register renaming unit, an issue queue for the scalar arithmetic unit, an issue queue for the memory access unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit. A feasible structure of a scalar processor is as follows: Figure 10 As shown, Figure 10 The address comparator and memory access unit are not shown in the diagram.

[0132] In addition, a scalar processor may include one or more other units, such as one or more other functional modules, one or more instruction caches, one or more data stores, one or more special vector registers, one or more status flag registers, etc.

[0133] 1. Instruction Fetch Unit The instruction fetch unit is used to fetch and dispatch instructions.

[0134] Specifically, the instruction fetch unit generates an instruction fetch request address, outputs the fetch request address to the instruction cache for instruction fetching, receives instructions from the instruction cache, and stores them in the data storage. Each cycle, it sequentially reads qualified instructions from the data storage, decodes and performs relevant checks on the read instructions, and then dispatches the checked instructions sequentially.

[0135] 2. Register renaming unit The register renaming unit receives instructions and register renaming requests from the instruction fetch unit. After the address is fetched, the address is calculated, decoded, and the decoding information is saved. When the source register of any instruction is ready and the address decoding is complete, it is detected and dispatched to the memory access unit for execution.

[0136] Specifically, the register renaming unit receives and stores instructions dispatched by the instruction fetch unit, renames special vector registers, performs instruction conditional decoding, and generates pipeline congestion signals. It receives data from one or more of the following: the scalar arithmetic unit, memory access unit, program control unit, synchronization unit, special vector registers, condition registers, and flag registers, and writes it back. It sends instructions to one or more of the following: the issue queue of the scalar arithmetic unit, the issue queue of the memory access unit, the program control unit, and the synchronization unit.

[0137] 3. The issue queue of the scalar arithmetic unit The issue queue of the scalar arithmetic unit is used to receive instructions, dispatch and rename information from the register renaming unit, and push them into the queue. Ready instructions are popped into the scalar arithmetic unit for execution. Input instructions are decoded, and instruction type information is stored.

[0138] In other words, the issue queue of the scalar arithmetic unit receives instructions and related dispatch and renaming information from the register renaming unit and pushes them into the queue. It also pops ready instructions to the scalar arithmetic unit for execution. The issue queue of the scalar arithmetic unit decodes the input instructions and stores the instruction type information.

[0139] In practice, the depth of the emit queue of a scalar arithmetic unit can be flexibly adjusted, such as a depth of 8. Multiple scalar arithmetic units share the emit queue of one scalar arithmetic unit.

[0140] 4. Memory access unit issue queue The issue queue of the memory access unit is used to receive instructions and register renaming information from the register renaming unit and push them into the queue. When the instruction address register is ready, a read request is sent to the register renaming unit to save the read address operand.

[0141] In practice, the depth of the issue queue of a memory access unit can be flexibly adjusted, such as 16. Multiple memory access units share a single issue queue. The issue queue of a memory access unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the issue queue of a memory access unit is ready, a read request is sent to the register renaming unit, and the read address operand is saved to the queue. After the instruction in the issue queue of a memory access unit obtains the address, it can calculate the address and decode it, saving the resulting decoding information to the queue. When the source register of an instruction (such as a write instruction) is ready and the address decoding is complete in the issue queue of a memory access unit, it can be issued to the memory access unit for execution. Before issuance, a series of checks are performed, such as address type checking, address comparison checking, and address forward checking.

[0142] 5. Scalar Operation Unit In a practical implementation, there can be one or more scalar operation units.

[0143] The scalar arithmetic unit is used to receive instructions and data sent by the scalar arithmetic unit's transmit queue, perform operations on the data based on the instructions, and write the operation results back to the register renaming unit.

[0144] The scalar arithmetic unit is the computational unit of the scalar processor. It can perform various types of fixed-point and floating-point operations, such as addition, subtraction, multiplication, division, logical operations, comparison operations, and shifting. It receives instructions and data sent from the issue queue of the scalar arithmetic unit, performs the operations, and writes the results back to the register file of the register renaming unit or the special vector register file.

[0145] The instructions include, but are not limited to, one or more of the following: fixed-point addition and subtraction, logical instructions, shift instructions, fixed-point and floating-point comparison instructions, read / write Flag instructions, fixed-point and floating-point maximum and minimum instructions, ABS instructions, bit reversal instructions, selection instructions, special vector register dispatch instructions, read special vector register instructions, Byte reversal instructions, Merge instructions, immediate assignment instructions, FirstOne instructions, CRC instructions, floating-point classification instructions, floating-point partial field extraction, and Rounding instructions.

[0146] 6. Memory access unit In a practical implementation, there can be one or more memory access units.

[0147] The memory access unit is used to receive instructions, data, and register information sent by the transmit queue of the memory access unit, and to read and write the data based on the instructions and register information.

[0148] The memory access unit is a functional module that executes memory access-related instructions for the scalar processor. The memory access unit receives instructions and data, as well as register-related information, from its issue queue. It executes the instructions accordingly, interacts with other units for data reading and writing, and writes data back to the register renaming unit for read and write instructions. This includes register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector-level read and write instructions. Vector granularities include 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing times.

[0149] In addition, the memory access unit is responsible for providing the number of instructions required by the FENCE. The memory access unit interacts with the issue queue of the memory access unit to complete the data storage configuration.

[0150] 7. Program Control Unit In practice, there is only one program control unit.

[0151] The program control unit receives instructions and data from the register renaming unit, processes the data based on the instructions, and outputs the processing results.

[0152] The program control unit is a functional module that executes instructions related to the execution order of the scalar processor's control program. The program control unit receives instructions and data from the register renaming unit, processes the data accordingly, and outputs the processing results to other modules of the scalar processor. Different instructions have different processing times.

[0153] The program control unit is responsible for controlling the direction of program execution (such as stopping, interrupting, jumping, and function calling), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetching operation of the instruction cache, as well as the FENCE operation; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information, etc.

[0154] 8. Synchronization Unit In practice, there is only one synchronization unit.

[0155] The synchronization unit is used for synchronizing the scalar processor and the vector processor.

[0156] like Figure 11 As shown, the synchronization unit establishes communication connections with the pipeline control unit, register renaming unit, program control unit, and vector processor.

[0157] The instructions for the synchronization unit come from the register renaming unit, and the reading and writing of data in the synchronization unit are all done in interaction with the register renaming unit.

[0158] The synchronization unit is used to receive the pause signal sent by the pipeline control unit and send the execution-level pause signal generated during communication with the vector processor to the pipeline control unit in order to generate the execution pause signal of the scalar processor.

[0159] The synchronization unit is used to generate instructions and transmit them to the program control unit.

[0160] In other words, the synchronization unit is the unit that synchronizes the scalar processor and the vector processor. It receives instructions and data from the register renaming unit, reads data from the vector processor and writes it back to the register file, and reads data from the register file unit or special vector register file unit and sends it to the vector processor. It is responsible for the startup and status query of the vector processor, such as querying the read and write FIFO (First Input First Output) in the vector program control unit of the vector processor, the configuration of the register file, the read or write of scalar registers, the status query of the register file, reading the FIFO depth, reading the startup vector processor instruction counter, etc., and providing synchronization unit instruction information to the program control unit.

[0161] The synchronization unit interacts with the pipeline control unit, register renaming unit, and program control unit within the scalar processor, as well as with the external vector processor, scalar processor, and vector processor transfer queue module. Synchronization unit instructions originate from the register renaming unit, and data reads and writes require interaction with this unit. It receives blocking signals from the pipeline control unit, generates its own execution-level blocking signal when communicating with the vector processor, and sends it to the pipeline control unit to generate execution-level signals affecting the entire scalar processor. The synchronization unit generates the instructions to be executed in the next cycle and transmits them to the program control unit for use by the program control unit's counter instructions. The synchronization unit interacts with the vector processor, including but not limited to: configuring the register file using special vector registers or registers, reading and writing scalar registers, and querying the write status of the register file. The scalar processor interacts with the scalar processor and vector processor transfer queue module, including but not limited to: starting the vector processor, querying the vector processor status, reading and writing FIFO data in the vector processor's instruction fetch unit, reading the FIFO depth, and reading the start vector processor instruction counter.

[0162] Therefore, in a specific implementation, the synchronization unit can have the following functions (it should be noted that the following functions are only examples, and other functions may also be available. This embodiment and subsequent embodiments do not limit the specific functions of the synchronization unit): The Startup Vector Processor function is used to start the vector processor, including immediate start and register start, such as pipeline waiting until the start is successful, or writing the result of the start success or failure back to the destination register.

[0163] The query vector processor execution status function supports option B.

[0164] The read / write FIFO function is located in the instruction fetch unit of the vector processor. For example, the FIFO has a bit width of 32 bits. Reading / writing the FIFO will wait until success, or the result of reading / writing the FIFO will be written back to the register whether it is successful or not.

[0165] Write register file stack functionality, including special vector register write or register write.

[0166] The function allows reading and writing scalar registers, including reading and writing immediate indexes or register indexes.

[0167] The function queries the register file stack write-back status. If necessary, it waits until all writes to the register file stack are complete, or returns the result of whether the write to the register file stack is complete to the register.

[0168] When the relevant operation is not completed, a blocking signal is generated by the synchronization unit itself, and the unit blocks and waits. This signal is then sent to the pipeline control unit to generate a pipeline blocking signal.

[0169] A FIFO (such as a 32-bit deep FIFO) can be added between the scalar processor and the vector processor to store the vector processor start request. The read / write FIFO previously located in the vector processor is moved to the scalar processor and vector processor transfer queue module. The scalar processor and vector processor transfer queue module unit implements the functions of starting the vector processor, querying the vector processor execution status, reading and writing the FIFO, reading the FIFO depth, and reading the start vector processor instruction counter. The conditions for successfully starting the vector processor are that the start vector processor FIFO is not full, and the query of the vector processor execution status is successful. The conditions for the vector processor status to stop are that the vector processor has finished executing and the start vector processor FIFO is empty.

[0170] 9. Production line control unit The pipeline control unit is used to generate a pause signal for the pipeline and / or to generate start and stop signals for the scalar processor.

[0171] The pipeline control unit is the pipeline control unit of the scalar processor. It is connected to various units inside the scalar processor and is responsible for generating pipeline blocking signals, such as blocking in normal operation mode and blocking in debug mode.

[0172] The pipeline control unit also communicates with the communication and synchronization unit to generate signals for starting and stopping the scalar processor.

[0173] This scalar processor achieves synchronization between the scalar processor and the vector processor through a synchronization unit, thereby enabling efficient instruction execution.

[0174] In addition, such as Figure 12 As shown, the vector processor includes: a vector program control unit, multiple functional units, a register file stack, scalar registers, a private vector register of the vector interleaving unit, and a private vector register of the vector access unit. Figure 12 The private vector registers of the vector interleaving unit and the vector access unit are not shown in the figure.

[0175] 1. Vector Program Control Unit Vector program control unit, used for instruction fetching and instruction issuing.

[0176] That is, the vector program control unit is used to retrieve instructions, determine whether to execute them, and issue instructions to functional units based on the determination result.

[0177] The vector program control unit is also used to control instruction jumps.

[0178] The vector program control unit has scalar computation capabilities.

[0179] The vector program control unit interacts with the scalar register.

[0180] In practical implementation, the vector program control unit is an instruction fetch and instruction issue unit. It fetches instructions from the cache based on the PC value, and after determining whether to execute, issues instructions to each functional unit based on the wait value (configured by the wait instruction). It also controls instruction jumps and has some scalar computation capabilities.

[0181] In addition, the vector program control unit is also used to receive start commands from other processing processors and start the vector processor. It also returns an indication signal to other processing processors indicating whether the vector processor has finished.

[0182] 2. Functional Units Functional units are used to perform functional processing according to instructions.

[0183] For example, a functional unit receives instructions from a vector program control unit, processes the data accordingly, and outputs the processing results at the address specified in the instructions.

[0184] The functional units include: one or more vector operation units, one or more vector interleaving units, and one or more vector access units.

[0185] 1) Vector operation unit Any vector operation unit is used to perform vector operations according to instructions, including: floating-point multiply-add subunit, floating-point multiply-accumulate subunit, floating-point arithmetic subunit, tensor multiplication subunit, and intermediate result register.

[0186] 2) Vector interleaving unit Any vector interleaving unit is used to perform data interleaving and logical processing according to instructions.

[0187] The vector interleaving unit is the control and data processing unit within the vector processor. It is responsible for interleaving data, supporting logical and some fixed-point and floating-point calculations. It also supports numerous customized instructions, including table lookup, horizontal calculation, sparse matrix calculation, precision conversion, and FIFO functions. It executes instructions such as data broadcasting, extraction, and internal interleaving.

[0188] Each vector interleaving unit has a set of registers; therefore, the registers of each vector interleaving unit correspond one-to-one with the vector interleaving units.

[0189] Multiple vector interleaving units share a private vector register of a single vector interleaving unit.

[0190] The vector interleaving unit includes: a decoder for the vector interleaving unit, multiple execution modules, and a selector.

[0191] The decoder of the vector interleaving unit decodes the instructions generated by the vector program control unit to obtain the execution module identifier. The instructions are then sent to the execution module corresponding to the execution module identifier.

[0192] The execution module is used to execute instructions based on the execution module identifier.

[0193] The selector is used to select the execution result of the module and output the selected execution result.

[0194] 3) Vector Access Unit Each vector access unit is used to perform multi-mode memory access, address calculation, and scalar calculation according to instructions.

[0195] The vector access unit is the memory access unit within the vector processor, primarily responsible for reading / writing instructions and various scalar calculations.

[0196] The read / write instructions support multiple memory access modes, such as row mode, column mode, discrete mode, extended mode, and accumulation mode.

[0197] It supports multiple parameter configurations, with a maximum read / write instruction data width of up to 1024 bits. It executes instructions such as address calculation, load / store, etc.

[0198] All vector access units share a set of private vector registers, so the private vector registers of a vector access unit are shared by multiple vector access units.

[0199] 3. Register file stack The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0200] The register file stack is a general-purpose vector register stack, which is the main storage unit within the vector processor. It is responsible for receiving read and write requests and returning data. In some functions, it can rearrange the data before returning it to the requesting module.

[0201] The register file stack interacts with functional units within the vector processor (such as the floating-point multiply-accumulate subunit, floating-point arithmetic subunit, floating-point multiply-accumulate subunit, and tensor multiplication subunit), and also supports configuring the instruction fetch unit configuration register using data in the register file stack.

[0202] The register file is also used to write data to other processing units. It receives status messages from other processing units indicating whether the data has been written.

[0203] The depth of the register file heap is configurable.

[0204] Figure 13 A schematic diagram of a vector processor is shown, comprising four vector operation units, four vector interleaving units, and four vector access units.

[0205] When there are multiple execution modules in a vector interleaving unit, how should the vector registers be configured to achieve both iterative computation within a single unit and rapid transfer of computation results between different units before proceeding to the next step, resulting in good performance and flexibility? This requires both shared private vector registers for relatively simple tasks and registers corresponding one-to-one with each vector interleaving unit for more complex tasks. For example, if there are multiple execution modules in the interleaving unit and multiple output results are selected, multiple vector registers are needed in coordination.

[0206] When there are multiple vector access units, since the functions of the vector access units are relatively simple, it is sufficient to set a common private vector register, thus saving hardware resources.

[0207] The vector processor provided in this embodiment supports the VLIW (Very Long Instruction Word) instruction set. Each VLIW can consist of one or more instructions, and each instruction corresponds to a functional unit.

[0208] In addition, read FIFO units and write FIFO units are set up between the vector processor and other computing processors.

[0209] The vector program control unit and other arithmetic processors both perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0210] Other processing units perform read or write operations on scalar registers.

[0211] Taking other processing processors as examples, such as scalar processors, there are read FIFO and write FIFO units between the scalar processor and the vector processor for transmitting data. The scalar processor and the vector program control unit can perform read operations or write operations on the read and write FIFOs.

[0212] Meanwhile, the synchronization unit of the scalar processor can perform read or write operations on the scalar registers of the vector processor.

[0213] This vector processor can efficiently process vector data.

[0214] The connection relationship between the scalar processor and the vector processor mentioned above can be as follows: Figure 14 As shown.

[0215] This embodiment provides a scalar processor. The address comparator in this scalar processor acquires a first instruction from a compressed issue queue; identifies all instructions preceding the first instruction in the compressed issue queue as second instructions; determines whether the addresses of the first instruction and each of the second instructions are related; if all second instructions are address-independent, the address comparison check result of the first instruction is determined to be passed; otherwise, the address comparison check result of the first instruction is determined to be failed. This scalar processor determines whether the addresses of the first instruction and each of the second instructions are related; if all second instructions are address-independent, the address comparison check result of the first instruction is determined to be passed; otherwise, the address comparison check result of the first instruction is determined to be failed. This allows for flexible support of diverse memory access granularities with a smaller hardware area overhead, while ensuring processor performance (timing). Furthermore, based on the enqueue and dequeue status of the issue queue instructions determined in the current cycle, the next state of the comparison check result is calculated in advance and updated directly in the next cycle. This ensures a one-to-one correspondence between the address comparison check result and the new position of the instruction in the issue queue, while also optimizing timing.

[0216] Example 3 Based on the same inventive concept as the above method, this embodiment provides an electronic device, including: a memory, a scalar processor, and a vector processor.

[0217] The scalar processor includes a compressed issue queue and an address comparator.

[0218] A compressed issue queue is an issue queue for scalar arithmetic units and / or memory access units in a scalar processor.

[0219] An address comparator is used to perform address comparison checks on a compressed transmit queue using the address comparison check method for the compressed transmit queue shown in Example 1.

[0220] The execution process of the address comparison and checking method for the compressed transmission queue can be referred to in Example 1, and will not be explained in detail here.

[0221] The scalar processor also includes: an instruction fetch unit, a register renaming unit, an issue queue for the scalar arithmetic unit, an issue queue for the memory access unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0222] The instruction fetch unit is used to fetch and dispatch instructions.

[0223] The register renaming unit is used to receive instructions dispatched by the instruction fetch unit and to rename registers.

[0224] The scalar arithmetic unit is used to receive instructions and data sent by the scalar arithmetic unit's transmit queue, perform operations on the data based on the instructions, and write the operation results back to the register renaming unit.

[0225] The memory access unit is used to receive instructions, data, and register information sent by the transmit queue of the memory access unit, and to read and write the data based on the instructions and register information.

[0226] The program control unit receives instructions and data from the register renaming unit, processes the data based on the instructions, and outputs the processing results.

[0227] The synchronization unit is used for synchronizing the scalar processor and the vector processor. The synchronization unit establishes communication connections with the pipeline control unit, register renaming unit, program control unit, and vector processor.

[0228] The synchronization unit is used to generate instructions and transmit them to the program control unit.

[0229] The pipeline control unit is used to generate a pause signal for the pipeline and / or to generate start and stop signals for the scalar processor.

[0230] The specific structure of the scalar processor is described in detail in the above scalar processor embodiment (i.e., embodiment 2), and will not be elaborated further here.

[0231] The vector processor includes: a vector program control unit, multiple functional units, a register file stack, scalar registers, a private vector register of the vector interleaving unit, and a private vector register of the vector access unit.

[0232] The vector program control unit is used for instruction fetching and instruction issuance. The vector program control unit interacts with scalar registers.

[0233] Functional units are used to perform functional processing according to instructions.

[0234] The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0235] The private vector register of a vector interleaving unit is shared by multiple vector interleaving units.

[0236] The private vector register of a vector access unit is shared by multiple vector access units.

[0237] The specific structure of the vector processor is described in detail in the above scalar processor embodiment (i.e., embodiment 2), and will not be elaborated further here.

[0238] This embodiment provides an electronic device including a scalar processor. An address comparator in the scalar processor acquires a first instruction from a compressed issue queue; identifies all instructions preceding the first instruction in the compressed issue queue as second instructions; determines whether the addresses of the first instruction and each of the second instructions are related; if all second instructions are address-independent, the address comparison check result of the first instruction is determined to be passed; otherwise, the address comparison check result of the first instruction is determined to be failed. This electronic device determines whether the addresses of the first instruction and each of the second instructions are related; if all second instructions are address-independent, the address comparison check result of the first instruction is determined to be passed; otherwise, the address comparison check result of the first instruction is determined to be failed. This allows for flexible support of diverse memory access granularities with minimal hardware area overhead, while ensuring processor performance (timing). Furthermore, based on the enqueue and dequeue status of the issue queue instructions determined in the current cycle, the next state of the comparison check result is calculated in advance and updated directly in the next cycle. This ensures a one-to-one correspondence between the address comparison check result and the new position of the instruction in the issue queue, while also optimizing timing.

[0239] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0240] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0241] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0242] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0243] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0244] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0245] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for address comparison and checking of a compressed transmit queue, characterized in that, The method includes: Retrieve the first instruction from the compressed launch queue; All instructions preceding the first instruction in the compressed launch queue are designated as the second instruction; Determine whether the addresses of the first instruction and each of the second instructions are related; If all second instructions are address-independent, the address comparison check result of the first instruction is determined to be a pass; otherwise, the address comparison check result of the first instruction is determined to be a fail.

2. The method according to claim 1, characterized in that, For any second instruction, determining whether the addresses of the first instruction and any second instruction are related includes: If the address of any second instruction has not been calculated, then the first instruction and any second instruction are determined to be address-dependent. If the address calculation for any second instruction is completed, then based on the starting address bit of the first instruction and the starting address bit of any second instruction, it is determined whether the addresses of the first instruction and any second instruction are related.

3. The method according to claim 2, characterized in that, Determining whether the addresses of the first instruction and any second instruction are related based on the starting address bits of the first instruction and the starting address bits of any second instruction includes: Based on the access granularity of the first instruction and the access granularity of any of the second instructions, a granularity access mask is obtained; Based on the starting address of the first instruction, the starting address of any second instruction, and the granularity access mask, determine whether the addresses of the first instruction and any second instruction are related.

4. The method according to claim 3, characterized in that, The step of obtaining the granularity access mask based on the access granularity of the first instruction and the access granularity of any of the second instructions includes: Determine the largest granularity between the access granularity of the first instruction and the access granularity of any second instruction; Shift the 6-bit binary number, which is all 1s, left by BigGran bits to obtain the granularity access mask; BigGran is the granularity code corresponding to the largest granularity.

5. The method according to claim 3, characterized in that, Determining whether the addresses of the first instruction and the second instruction are related based on the starting address bits of the first instruction, the starting address bits of any second instruction, and the granularity access mask includes: By concatenating a 42-bit binary number consisting entirely of 1s with a granularity access mask, the concatenation number Con is obtained. If the value of (iAddr0^iAddr1)&Con is 1, then it is determined that the addresses of the first instruction and any of the second instructions are not related; if the value of (iAddr0^iAddr1)&Con is 0, then it is determined that the addresses of the first instruction and any of the second instructions are related. Where iAddr0 is the starting address bit accessed by the first instruction, iAddr1 is the starting address bit of any of the second instructions, ^ is the bitwise XOR operator, and & is the bitwise AND operator.

6. The method according to claim 1, characterized in that, If all second instructions are address-independent, then the address comparison check result of the first instruction is determined to be a pass; otherwise, after determining that the address comparison check result of the first instruction is a fail, the method further includes: A comparison check result vector is formed for the compressed launch queue; wherein the comparison check result vector includes at least one address comparison check result, the number of address comparison check results included in the comparison check result vector is the same as the number of instructions in the compressed launch queue, and the order of the address comparison check results included in the comparison check result vector is the same as the order of the instructions in the compressed launch queue; If a first target instruction exists, the address comparison check result corresponding to the first target instruction is deleted from the comparison check result vector, and subsequent address comparison check results in the comparison check result vector are compressed; and / or, if a second target instruction exists, the address comparison check result corresponding to the second target instruction is added to the comparison check result vector; wherein, the first target instruction leaves the compressed transmission queue in the next cycle, and the second target instruction is written into the compressed transmission queue in the next cycle.

7. The method according to claim 1, characterized in that, The instructions in the compressed launch queue include branch instructions.

8. The method according to claim 1, characterized in that, The compressed issue queue is the issue queue of the scalar arithmetic unit and / or the issue queue of the memory access unit in the scalar processor. The scalar processor includes: an instruction fetch unit, a register renaming unit, an issue queue for a scalar arithmetic unit, an issue queue for a memory access unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit. The instruction fetching unit is used to fetch instructions and dispatch instructions; The register renaming unit is used to receive instructions and register renaming dispatched by the instruction fetch unit; The scalar arithmetic unit is used to receive instructions and data sent by the transmit queue of the scalar arithmetic unit, perform calculations on the data based on the instructions, and write the calculation results back to the register renaming unit. The memory access unit is used to receive instructions, data, and register information sent by the transmit queue of the memory access unit, and to read and write the data based on the instructions and register information; The program control unit is used to receive instructions and data from the register renaming unit, process the data based on the instructions, and output the processing result. The synchronization unit is used for synchronizing the scalar processor and the vector processor; the synchronization unit establishes a communication connection with the pipeline control unit, the register renaming unit, the program control unit, and the vector processor. The synchronization unit is used to generate instructions and transmit them to the program control unit; The pipeline control unit is used to generate a pipeline pause signal and / or generate start and stop signals for the scalar processor.

9. The method according to claim 8, characterized in that, The vector processor includes: a vector program control unit, multiple functional units, a register file stack, scalar registers, a private vector register of the vector interleaving unit, and a private vector register of the vector access unit. The vector program control unit is used for instruction fetching and instruction issuing; the vector program control unit interacts with the scalar register. The functional unit is used to perform functional processing according to instructions; The register file stack is used to receive read / write requests and return data; rearrange the data and return it; perform read / write interactions with the functional units; and configure the configuration registers of the vector program control unit using the data in the register file stack. The private vector register of a vector interleaving unit is shared by multiple vector interleaving units; The private vector register of a vector access unit is shared by multiple vector access units.

10. A scalar processor, characterized in that, The scalar processor includes a compressed issue queue and an address comparator; The compressed issue queue is the issue queue of the scalar arithmetic unit and / or the issue queue of the memory access unit in the scalar processor. The address comparator is used to perform address comparison checks on the compressed transmit queue using the method described in any one of claims 1-9.

11. The scalar processor according to claim 10, characterized in that, The scalar processor further includes: an instruction fetch unit, a register renaming unit, an issue queue for a scalar arithmetic unit, an issue queue for a memory access unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit. The instruction fetching unit is used to fetch instructions and dispatch instructions; The register renaming unit is used to receive instructions and register renaming dispatched by the instruction fetch unit; The scalar arithmetic unit is used to receive instructions and data sent by the transmit queue of the scalar arithmetic unit, perform calculations on the data based on the instructions, and write the calculation results back to the register renaming unit. The memory access unit is used to receive instructions, data, and register information sent by the transmit queue of the memory access unit, and to read and write the data based on the instructions and register information; The program control unit is used to receive instructions and data from the register renaming unit, process the data based on the instructions, and output the processing result. The synchronization unit is used for synchronizing the scalar processor and the vector processor; the synchronization unit establishes a communication connection with the pipeline control unit, the register renaming unit, the program control unit, and the vector processor. The synchronization unit is used to generate instructions and transmit them to the program control unit; The pipeline control unit is used to generate a pipeline pause signal and / or generate start and stop signals for the scalar processor.

12. The scalar processor according to claim 11, characterized in that, The vector processor includes: a vector program control unit, multiple functional units, a register file stack, scalar registers, a private vector register of the vector interleaving unit, and a private vector register of the vector access unit. The vector program control unit is used for instruction fetching and instruction issuing; the vector program control unit interacts with the scalar register. The functional unit is used to perform functional processing according to instructions; The register file stack is used to receive read / write requests and return data; rearrange the data and return it; perform read / write interactions with the functional units; and configure the configuration registers of the vector program control unit using the data in the register file stack. The private vector register of a vector interleaving unit is shared by multiple vector interleaving units; The private vector register of a vector access unit is shared by multiple vector access units.

13. An electronic device, characterized in that, include: Memory, scalar processor, vector processor; The scalar processor includes a compressed issue queue and an address comparator; The compressed issue queue is the issue queue of the scalar arithmetic unit and / or the issue queue of the memory access unit in the scalar processor. The address comparator is used to perform address comparison checks on the compressed transmit queue using the method described in any one of claims 1-9.

14. The electronic device according to claim 13, characterized in that, The scalar processor further includes: an instruction fetch unit, a register renaming unit, an issue queue for a scalar arithmetic unit, an issue queue for a memory access unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit. The instruction fetching unit is used to fetch instructions and dispatch instructions; The register renaming unit is used to receive instructions and register renaming dispatched by the instruction fetch unit; The scalar arithmetic unit is used to receive instructions and data sent by the transmit queue of the scalar arithmetic unit, perform calculations on the data based on the instructions, and write the calculation results back to the register renaming unit. The memory access unit is used to receive instructions, data, and register information sent by the transmit queue of the memory access unit, and to read and write the data based on the instructions and register information; The program control unit is used to receive instructions and data from the register renaming unit, process the data based on the instructions, and output the processing result. The synchronization unit is used for synchronizing the scalar processor and the vector processor; the synchronization unit establishes a communication connection with the pipeline control unit, the register renaming unit, the program control unit, and the vector processor. The synchronization unit is used to generate instructions and transmit them to the program control unit; The pipeline control unit is used to generate a pipeline pause signal and / or generate start and stop signals for the scalar processor.

15. The electronic device according to claim 13, characterized in that, The vector processor includes: a vector program control unit, multiple functional units, a register file stack, scalar registers, a private vector register of the vector interleaving unit, and a private vector register of the vector access unit. The vector program control unit is used for instruction fetching and instruction issuing; the vector program control unit interacts with the scalar register. The functional unit is used to perform functional processing according to instructions; The register file stack is used to receive read / write requests and return data; rearrange the data and return it; perform read / write interactions with the functional units; and configure the configuration registers of the vector program control unit using the data in the register file stack. The private vector register of a vector interleaving unit is shared by multiple vector interleaving units; The private vector register of a vector access unit is shared by multiple vector access units.

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