Worst-case execution time analysis method for gpu kernel-oriented thread blocks

Abstract

This application discloses a method for worst-case execution time upper bound analysis of thread blocks for GPU kernels, relating to the field of computer system technology. The method includes: representing the execution path of each warp in a thread block executing GPU kernel functions as a path composed of basic block sequences; constructing an instruction model based on the instructions executed by the thread lockstep of the warp in the basic block according to the GPU pipeline; determining the execution path as a sequence of alternating critical and non-critical segments as a warp model based on the instruction model and the warp model; determining all candidate warp execution scenarios under branching based on the instruction model and the warp model, thereby analyzing the worst-case execution time of the thread block without specifying the execution path, and obtaining a work-constraint upper bound; and performing scheduling constraint modeling on the instruction model and the warp model to obtain a topology constraint upper bound. This application can accurately analyze the work-constraint upper bound and obtain a more compact topology constraint upper bound.

Description

Technical Field

[0001] This application relates to the field of computer system technology, and in particular to a method for worst-case execution time upper bound analysis of thread blocks for GPU kernels. Background Technology

[0002] Worst-Case Execution Time (WCET) analysis is a key technology for ensuring the timing accuracy of real-time systems. For CPU-based systems, WCET analysis is relatively mature. However, with the continuous development of artificial intelligence, graphics processing units (GPUs) are increasingly being integrated into embedded and real-time systems. GPUs employ a Single Instruction, Multiple Threads (SIMT) execution model, in which threads are organized into warps and execute the same instruction in locksteps. This fundamental difference makes CPU-based WCET analysis methods unsuitable for GPUs.

[0003] In the SIMT model, different threads within a warp may take different control paths, leading to variations in warp execution time. When a warp encounters a conditional branch, the threads within the warp may execute different control paths, creating branch divergence. This causes the warp to execute each selected branch sequentially, increasing the actual execution time of the warp. Since the branch results of threads are usually not statically deterministic, the execution path obtained by executing all branches sequentially is the longest possible path for the warp. However, even if all warps in a thread block are modeled as executing the longest path, it is still not feasible to obtain the WCET of the thread block by simulating them. This is because, in actual operation, warps executing non-longest paths may change the order in which warps compete for shared resources, introducing timing anomalies and actually prolonging the completion time of the thread block. Therefore, it is necessary to use static analysis methods to estimate the upper bound of the WCET of thread blocks under all possible paths for the warp. Adding to the complexity, the GPU's warp scheduler is a proprietary hardware implementation and is not externally visible. Therefore, realistic analysis can only adopt relatively relaxed scheduling assumptions, and the upper bound obtained under such assumptions is often overly pessimistic.

[0004] To mitigate path uncertainty caused by branching, related techniques presuppose that the execution path of each warp is known, and perform time analysis on thread blocks accordingly. However, this assumption is unrealistic because it requires precise knowledge of the branching conditions of each thread to deduce the specific execution path of the warp. Furthermore, to ensure the correctness of the analysis, this technique only assumes that scheduling is job-preserving and takes the worst-case scenario among all possible warp execution orders. This leads to extremely conservative and even unrealistic analysis results. Summary of the Invention

[0005] In view of this, embodiments of this application provide a method and related devices for worst-case execution time upper bound analysis of thread blocks for GPU kernels, so as to obtain a compact upper bound while overcoming the uncertainty caused by branch divergence.

[0006] One aspect of this application provides a method for worst-case execution time upper bound analysis of thread blocks for GPU kernels, the method comprising the following steps:

[0007] The execution path of each warp in a thread block executing the GPU kernel function is represented as a path composed of a sequence of basic blocks;

[0008] The instruction model is constructed based on the instructions executed by the thread lockstep of the warp in the basic block according to the GPU pipeline;

[0009] Based on the instruction model, the execution path is determined as a sequence of alternating critical and non-critical segments; wherein, the sequence of alternating critical and non-critical segments is used as a warp model;

[0010] Based on the instruction model and the warp model, all candidate warp execution scenarios under branching are determined, thereby analyzing the worst execution time of the thread block without setting the execution path and obtaining the working upper bound;

[0011] Scheduling constraints are modeled on the instruction model and the warp model to obtain the upper bound of the topological constraints.

[0012] In some embodiments, representing the execution path of each warp in a thread block executing a GPU kernel function as a path composed of a sequence of basic blocks includes the following steps:

[0013] The GPU kernel function is represented as a control flow graph constructed by the compiler, and each warp in the thread block is defined as executing each branch of the control flow graph sequentially, thereby representing the execution path of each warp in the thread block executing the GPU kernel function as a path composed of a sequence of basic blocks.

[0014] In some embodiments, determining the execution path as an alternating sequence of critical and non-critical segments based on the instruction model includes the following steps:

[0015] Based on the instruction model, the issuance time, exclusive resource time, resource release time, and completion time of each instruction in the basic block are obtained, and then the execution path is determined as a sequence of alternating critical and non-critical segments.

[0016] In some embodiments, determining all candidate warp execution scenarios under branching based on the instruction model and the warp model, thereby analyzing the worst-case execution time of the thread block without setting the execution path, and obtaining the working upper bound, includes the following steps:

[0017] Analyze the global non-critical segments and use the duration of the non-critical segment in the execution path that is the last executed segment in the thread block as the upper bound of the global non-critical segment duration.

[0018] The expression for maintaining the upper bound of the work is:

[0019] ;

[0020] in, To maintain an upper bound for the work, The set of all the aforementioned execution paths. The number of warps in the thread block. Indicates the execution path Execution time of the critical section Indicates the execution path Execution time of the critical segment in China and Africa.

[0021] In some embodiments, the step of performing scheduling constraint modeling on the instruction model and the warp model to obtain the upper bound of topological constraints includes the following steps:

[0022] Graph modeling is performed on the scheduling policy constraints that only follow work-holding scheduling to obtain the scheduling policy constraint graph;

[0023] The scheduling strategy constraint graph is converted into a directed acyclic graph;

[0024] Calculate the longest path in the directed acyclic graph, and use the set of nodes of the longest path as the upper bound of the topological constraint.

[0025] In some embodiments, the step of performing graph modeling on the scheduling policy constraints that only follow work-keeping scheduling to obtain a scheduling policy constraint graph includes the following steps:

[0026] Treating each warp as a node, a directed edge is added between every two adjacent critical and non-critical segments of each warp, and a bidirectional edge is added between every two critical segments of different warps to obtain the scheduling strategy constraint graph.

[0027] The process of converting the scheduling policy constraint graph into a directed acyclic graph includes the following steps:

[0028] Convert bidirectional edges within the same column into unidirectional edges pointing from nodes with smaller warp indices to nodes with larger warp indices;

[0029] Convert bidirectional edges between different columns into unidirectional edges that point from a node with a smaller column number to a node with a larger column number;

[0030] By removing redundant edges from the scheduling strategy constraint graph, the directed acyclic graph is obtained.

[0031] In some embodiments, calculating the longest path in the directed acyclic graph and using the set of nodes of the longest path as the upper bound of the topological constraints includes the following steps:

[0032] The upper bound of the topological constraints is calculated as follows:

[0033] ;

[0034] in, This is the upper bound of the topological constraints. Represents a node The duration of the key or non-key segment it represents.

[0035] Another aspect of this application embodiment provides a worst-case execution time upper bound analysis device for thread blocks targeting GPU kernels, the device comprising:

[0036] An execution path representation unit is used to represent the execution path of each warp in a thread block executing GPU kernel functions as a path composed of a sequence of basic blocks;

[0037] The instruction model construction unit is used to construct the instruction model based on the instructions executed by the thread lockstep of the warp in the basic block by the GPU pipeline.

[0038] The warp model construction unit is used to determine the execution path as a sequence of alternating critical and non-critical segments based on the instruction model; wherein the sequence of alternating critical and non-critical segments is used as the warp model.

[0039] The first upper bound analysis unit is used to determine all candidate warp execution scenarios under branching based on the instruction model and the warp model, thereby analyzing the worst execution time of the thread block without setting the execution path and obtaining the working upper bound;

[0040] The second upper bound analysis unit is used to perform scheduling constraint modeling on the instruction model and the warp model to obtain the upper bound of the topological constraints.

[0041] Another aspect of this application embodiment provides an electronic device, including a processor and a memory;

[0042] The memory is used to store programs;

[0043] The processor executes the program to implement any of the methods described above.

[0044] Another aspect of this application provides a computer-readable storage medium storing a program that is executed by a processor to implement the method described in any of the above embodiments.

[0045] This application includes at least the following beneficial effects:

[0046] This application represents the execution path of each warp in a thread block executing GPU kernel functions as a path composed of basic block sequences; constructs an instruction model based on the instructions executed by the thread lockstep of the warp in the basic block according to the GPU pipeline; determines the execution path as a sequence of alternating critical and non-critical segments based on the instruction model; the sequence of alternating critical and non-critical segments serves as the warp model; determines all candidate warp execution scenarios under branching based on the instruction model and warp model, thereby analyzing the worst-case execution time of the thread block without setting the execution path, and obtaining the upper bound of work preservation; and models scheduling constraints on the instruction model and warp model to obtain the upper bound of topological constraints. This application represents all possible warp execution scenarios under branching, thereby performing an accurate worst-case execution time analysis of the thread block without assuming the execution path of the warp, and obtaining its upper bound of work preservation; furthermore, modeling scheduling constraints and introducing implementable constraints can yield a more compact upper bound of topological constraints. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A flowchart illustrating the worst-case execution time upper bound analysis method for thread blocks targeting GPU kernels provided in this application embodiment;

[0049] Figure 2 An example flowchart of a worst-case execution time upper bound analysis method for thread blocks targeting GPU kernels provided in an embodiment of this application;

[0050] Figure 3 The following diagram illustrates three execution scenarios of warps in thread blocks under different execution paths and different scheduling strategies within worker-keeping scheduling constraints, as provided in the embodiments of this application.

[0051] Figure 4 A schematic diagram illustrating only the scheduling policy constraints of work-keeping scheduling provided for embodiments of this application;

[0052] Figure 5 A schematic diagram illustrating the scheduling policy constraints of work-keeping scheduling and topology-order execution provided for embodiments of this application;

[0053] Figure 6 This is a structural block diagram of a worst-case execution time upper bound analysis device for GPU kernel-oriented thread blocks, provided in an embodiment of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0055] Before providing a detailed description of the embodiments of this application, some related technologies involved in the embodiments of this application will be described first, as follows:

[0056] Terminology Explanation:

[0057] GPU Kernel: A GPU kernel refers to a parallel program (also known as a kernel function) running on a graphics processing unit (GPU). When executing a GPU application, the host dispatches the kernel function to the GPU and further schedules it to execute on a lower-level sub-core. This application focuses only on the worst-case execution time (WCET) analysis when a kernel function is executed by a thread block on a single sub-core.

[0058] Thread Block: A thread block is the scheduling unit in the GPU execution model, consisting of multiple warps (a warp typically consists of 32 threads). Each thread within a warp uses a lock-step execution mode of Single Instruction Multiple Threading (SIMT), meaning that the same instruction must be executed at any given time.

[0059] Branch divergence: Branch divergence refers to the phenomenon where threads within a warp execute different control flow paths during conditional checks. When branch divergence occurs, the warp executes each branch sequentially, maintaining a lockstep on each branch, and ultimately sums the execution times of all branches to form the warp's total execution time. Branch divergence is a major source of timing uncertainty in GPU real-time performance analysis. This application constructs an upper bound on execution time that is effective for all execution scenarios by analyzing all possible warp execution path combinations.

[0060] Functional Unit / Resource: A functional unit (FU) is a hardware component within a GPU subcore used to execute specific types of instructions. At any given time, each FU can typically only serve the instructions of one warp; other warps requiring that FU must wait. Since different warps may compete for the same type of functional unit, this application uses the term "resource" to describe functional units of the same type.

[0061] Critical Section / Non-Critical Section: A critical section refers to the time interval during which a warp exclusively uses a specific resource to execute instructions, during which that resource cannot simultaneously provide services to other warps. A non-critical section refers to the time interval during which a warp does not occupy any resources, and this interval will not block other warps.

[0062] Work-Conserving Scheduling: Work-conserving scheduling is a strategy that describes warp scheduling, meaning that as long as at least one executable warp exists, its required functional units will not be idle, thus ensuring maximum utilization of hardware resources during thread block execution. In this application, all theoretical derivations are based on work-conserving scheduling.

[0063] Execution Path: An execution path is the sequence of critical and non-critical segments that a warp actually executes under a specific branch result. Due to branching, each warp may have multiple feasible execution paths, thus there exists a set of feasible paths and the longest possible path.

[0064] Execution Scenario: An execution scenario refers to the combination of control flow paths and scheduling strategies chosen by all warps within a thread block during a single execution. Each execution scenario determines the sequence of critical segments, the sequence of non-critical segments, and the interactions between them, thus affecting the execution time of the entire thread block. The core idea of ​​this application is to construct a unified worst-case execution time upper bound that is effective for all possible execution scenarios without enumerating all execution scenarios, thereby avoiding the analytical infeasibility caused by the exponential explosion of path combinations.

[0065] Timing anomaly: A timing anomaly refers to the counterintuitive phenomenon where a localized event speeds up during processor execution, leading to an overall increase in execution time. In this application, a timing anomaly refers to the phenomenon where, when the execution path of a warp within a thread block is shorter than the longest path, the execution time of the thread block is longer than in a scenario where all warps execute the longest path.

[0066] Existing GPU thread block worst-case execution time (WCET) analysis methods mainly suffer from the following problems:

[0067] To mitigate path uncertainty caused by branch divergence, existing methods rely on the assumption that "the actual execution path of a warp can be statically determined in advance," thus basing all analyses on a known execution path model. However, in actual execution, the branch execution of threads within a warp depends on runtime data, making it difficult to accurately infer during static analysis. This assumption is often untenable in practical applications, resulting in analysis results that lack theoretical robustness and practical applicability.

[0068] Because the GPU scheduler is a black box, its internal strategies are not visible to the outside world. Existing methods only use the relaxed assumption of work-keeping to build the model. To ensure coverage of all potential execution scenarios, existing methods must choose the longest execution order from all possible execution orders of each warp in the thread block, leading to significant pessimism. While this strategy ensures safety, it greatly expands the upper bound of WCET, causing the results to deviate from reality and making it difficult to meet the "compact upper bound" requirement of real-time systems.

[0069] The purpose of this application is to provide a worst-case execution time analysis method for GPU thread blocks, which can improve analysis accuracy and reduce pessimism without relying on specific path assumptions. This technique has the following characteristics:

[0070] This scheme constructs a WCET derivation framework that does not require pre-determining warp paths, enabling analysis to be free from unrealistic path assumptions and achieving unified analysis of all possible execution scenarios. Under the work-keeping scheduling assumption, this framework provides a precise, worst-case execution time upper bound for thread blocks that covers all execution scenarios.

[0071] This approach, while maintaining the scheduling assumptions unchanged, introduces a practically implementable warp execution constraint, enabling the analysis to exclude some extreme execution sequences. While ensuring worst-case reachability, it effectively tightens the upper bound of WCET, significantly improving the practical usability and predictability of the analysis results.

[0072] Reference Figure 1 This application provides a method for worst-case execution time upper bound analysis of thread blocks for GPU kernels, specifically including the following steps S100~S140:

[0073] S100: Represent the execution path of each warp in the thread block to the GPU kernel function as a path composed of a sequence of basic blocks;

[0074] S110: Construct an instruction model based on the instructions executed by the thread lockstep of the warp in the basic block according to the GPU pipeline;

[0075] S120: Based on the instruction model, the execution path is determined as a sequence of alternating critical and non-critical segments; wherein, the sequence of alternating critical and non-critical segments is used as a warp model;

[0076] S130: Based on the instruction model and the warp model, determine all candidate warp execution scenarios under branching, thereby analyzing the worst execution time of the thread block without setting the execution path, and obtaining the working upper bound;

[0077] S140: Perform scheduling constraint modeling on the instruction model and the warp model to obtain the upper bound of the topology constraints.

[0078] Optionally, representing the execution path of each warp in a thread block executing the GPU kernel function as a path composed of a sequence of basic blocks includes the following steps:

[0079] The GPU kernel function is represented as a control flow graph constructed by the compiler, and each warp in the thread block is defined as executing each branch of the control flow graph sequentially, thereby representing the execution path of each warp in the thread block executing the GPU kernel function as a path composed of a sequence of basic blocks.

[0080] Optionally, determining the execution path as an alternating sequence of critical and non-critical segments based on the instruction model includes the following steps:

[0081] Based on the instruction model, the issuance time, exclusive resource time, resource release time, and completion time of each instruction in the basic block are obtained, and then the execution path is determined as a sequence of alternating critical and non-critical segments.

[0082] Optionally, the step of determining all candidate warp execution scenarios under branching based on the instruction model and the warp model, thereby analyzing the worst-case execution time of the thread block without setting the execution path, and obtaining the working upper bound, includes the following steps:

[0083] Analyze the global non-critical segments and use the duration of the non-critical segment in the execution path that is the last executed segment in the thread block as the upper bound of the global non-critical segment duration.

[0084] The expression for maintaining the upper bound of the work is:

[0085] ;

[0086] in, To maintain an upper bound for the work, The set of all the aforementioned execution paths. The number of warps in the thread block. Indicates the execution path Execution time of the critical section Indicates the execution path Execution time of the critical segment in China and Africa.

[0087] Optionally, the step of performing scheduling constraint modeling on the instruction model and the warp model to obtain the upper bound of topological constraints includes the following steps:

[0088] Graph modeling is performed on the scheduling policy constraints that only follow work-holding scheduling to obtain the scheduling policy constraint graph;

[0089] The scheduling strategy constraint graph is converted into a directed acyclic graph;

[0090] Calculate the longest path in the directed acyclic graph, and use the set of nodes of the longest path as the upper bound of the topological constraint.

[0091] Optionally, the step of performing graph modeling on the scheduling policy constraints that only follow work-holding scheduling to obtain a scheduling policy constraint graph includes the following steps:

[0092] Treating each warp as a node, a directed edge is added between every two adjacent critical and non-critical segments of each warp, and a bidirectional edge is added between every two critical segments of different warps to obtain the scheduling strategy constraint graph.

[0093] The process of converting the scheduling policy constraint graph into a directed acyclic graph includes the following steps:

[0094] Convert bidirectional edges within the same column into unidirectional edges pointing from nodes with smaller warp indices to nodes with larger warp indices;

[0095] Convert bidirectional edges between different columns into unidirectional edges that point from a node with a smaller column number to a node with a larger column number;

[0096] By removing redundant edges from the scheduling strategy constraint graph, the directed acyclic graph is obtained.

[0097] Optionally, calculating the longest path in the directed acyclic graph and using the set of nodes of the longest path as the upper bound of the topological constraints includes the following steps:

[0098] The upper bound of the topological constraints is calculated as follows:

[0099] ;

[0100] in, This is the upper bound of the topological constraints. Represents a node The duration of the key or non-key segment it represents.

[0101] The following section will provide a detailed introduction and explanation of the solutions in the embodiments of this application, using specific application examples.

[0102] For example, Figure 2 This is an example flowchart of the worst-case execution time upper bound analysis method for thread blocks targeting GPU kernels provided in this embodiment.

[0103] The system model of this embodiment is described below:

[0104] This embodiment will expand the execution path model of critical and non-critical segments based on the warp in the thread block.

[0105] A GPU kernel function can be represented as a control flow graph (CFG) constructed by the compiler. During preprocessing, the warp is always assumed to execute each branch in the CFG sequentially, thus representing the path of the warp executing the kernel function as a control path consisting of a sequence of basic blocks.

[0106] For instructions within a basic block (executed by thread locksteps within the warp), an instruction model can be constructed based on the GPU pipeline to obtain the issuance time, exclusive resource time, resource release time, and completion time of each instruction within the basic block. Based on this instruction model, the execution path of a warp can be abstracted as an alternating sequence of critical and non-critical segments. ,in This represents the set of all possible execution paths of a warp. Within the execution paths of a warp, if any resource within a time interval is exclusively occupied by a single thread within the warp, then that interval is a critical segment; if no resource is occupied by any thread within the warp, then that interval is a non-critical segment.

[0107] This system contains The specific execution scenario of a warp's thread block under keep-work scheduling constraints. (execution scenario) consists of each warp The execution path and scheduling policy are defined. If all unfinished warps in a thread block are executing non-critical sections within a certain time interval, then that interval is a globally non-critical section. Figure 3 These are three execution scenarios for warps within a thread block under different execution paths and different scheduling policies within keep-work scheduling constraints. Figure 3 Showing Three different execution scenarios for time-based thread blocks under work-hold scheduling constraints. Among them, , and The execution path of warp is different. and Different scheduling strategies are followed by different warps, resulting in different execution scenarios and execution times.

[0108] The system model can represent all possible warp execution scenarios under branching, thus enabling precise WCET analysis of thread blocks without assuming the execution path of the warp, and obtaining its working upper bound. Furthermore, by further modeling the scheduling constraints of the system and introducing implementable constraints, a more compact topological constraint upper bound can be obtained.

[0109] The specific operation steps and overall workflow of this embodiment include the following steps:

[0110] I. Analysis and calculation of the upper bound of the work.

[0111] Work stays above the limit It is the exact upper bound of the thread block WCET only under the job-keeping scheduling assumption, without assuming a specific warp execution path and scheduling policy.

[0112] 1. The execution scenario of the thread block is analyzed under the system model. This analysis uses the sum of the total duration of critical sections and global non-critical sections to represent the execution time of the execution scenario.

[0113] 2. Analysis of timing anomalies caused by branching. In this system model, timing anomalies manifest as a situation where the execution time of a warp in a thread block that does not follow the longest path is longer than the execution time of all warps that follow the longest path. Due to the resource mutual exclusion characteristics of critical sections, timing anomalies necessarily depend on the increase of global non-critical sections. This analysis transforms the WCET upper bound analysis problem into an upper bound analysis problem of the duration of global non-critical sections.

[0114] 3. Analyze global non-critical segments, using the duration of non-critical segments in the execution path of the last warp to finish within the thread block as the upper bound of the global non-critical segment duration. Since the completion order of each warp is unpredictable under static analysis, this upper bound represents the maximum non-critical segment duration among all possible execution paths of warps within the thread block. This analysis yields the work-preservation upper bound. One form of representation:

[0115] ;

[0116] in, Indicates the execution path Execution time of the critical section Indicates the execution path Execution time of the critical segment in China and Africa.

[0117] 4. The longest possible path that a warp can execute when using branching. The durations of critical and non-critical sections represent the maximum durations of critical and non-critical sections, respectively. The upper bound of the work is represented as follows:

[0118] ;

[0119] This analysis avoids enumerating all possible execution paths, thus enabling efficient calculation of effective upper bounds for different execution scenarios.

[0120] 5. Further analysis of the work-holding upper bound is conducted to prove its accuracy under any work-holding scheduling strategy.

[0121] II. Analysis and calculation of upper bounds of topological constraints.

[0122] Topological constraint upper bound It is a more compact upper bound resulting from the introduction of constraints that limit the execution order of warps.

[0123] 1. Perform graph modeling for scheduling policy constraints that only adhere to work-holding scheduling. Use blue / white nodes to represent the longest path. In critical and non-critical sections, a one-way edge indicates that the source node must be executed before the target node, while a two-way edge indicates that either connected node can be executed before the other. Figure 4 As shown.

[0124] Step 1: Add a directed edge between every two adjacent critical and non-critical segments in each warp to indicate the predefined execution order within the warp;

[0125] Step 2: Add a bidirectional edge between every two key segments of different warps to indicate that they are mutually exclusive during execution.

[0126] 2. Analyze the constraints of scheduling strategies that only follow work-holding scheduling. For example... Figure 4 As shown, the large number of bidirectional edges in this constraint allows for many possible execution orders between warps, leading to an overly pessimistic upper bound. To restrict the permissible execution order, a specific and achievable topological order needs to be enforced on the critical segments of different warps to impose a stricter constraint, thereby transforming it into a directed acyclic graph (DAG), such as... Figure 5 As shown.

[0127] Step 1: For bidirectional edges within the same column, convert them into unidirectional edges from nodes with smaller warp numbers to nodes with larger warp numbers;

[0128] Step 2: For bidirectional edges between different columns, convert them into unidirectional edges from the node with the smaller column number to the node with the larger column number;

[0129] Step 3: Remove redundant edges.

[0130] 3. Calculate the longest path in the DAG, and represent its node set as follows: The upper bound of the topological constraints is obtained. :

[0131] ;

[0132] in Represents a node The duration of the key or non-key segment it represents.

[0133] Experiments using synthesized thread blocks and benchmark tests show that the upper bound of topological constraints... Compared to keeping the upper limit of work Significantly tightened.

[0134] In summary, this application includes the following key technical solutions:

[0135] 1. A static analysis framework for GPU thread block WCET is proposed, which does not require pre-determining the warp execution path. This framework analyzes the timing anomalies caused by branching and constructs a unified upper bound expression based on critical segments and global non-critical segments, enabling the analysis to cover all possible execution scenarios without relying on warp path information that cannot be statically obtained.

[0136] 2. A graph-based method for describing warp scheduling constraints is proposed. This method abstracts critical and non-critical segments as nodes and uses directed and bidirectional edges to characterize the permissible execution order under work-maintaining scheduling, providing a structured model foundation for further imposing controllable execution constraints.

[0137] 3. A WCET compaction method based on directed acyclic graph (DAG) transformation is proposed. By systematically transforming the bidirectional edges in the original scheduling constraint graph into unidirectional edges, a DAG with a determined topological order is constructed, and its longest path is used as the new upper bound, thereby obtaining a significantly more compact WCET estimate for thread blocks.

[0138] 4. A WCET static analysis method for branching without assumptions and for determining paths. This method is based on a unified time model for constructing thread blocks by dividing them into critical and non-critical segments. By applying an upper bound to the duration of global non-critical segments, it achieves uniform coverage of all execution scenarios, avoids path combination explosion, and ensures the reachability and accuracy of the upper bound under work-keeping scheduling.

[0139] 5. A graph-based method for constructing warp scheduling constraints. This method constructs a scheduling constraint graph using critical and non-critical segments as nodes. By establishing sequential edges within warps and mutually exclusive bidirectional edges between different warps, it fully describes the resource contention relationship under work-holding scheduling, providing a formal model foundation for further shrinking the allowable execution order.

[0140] 6. A WCET compaction method based on topological order constraints. Building upon the scheduling constraint graph, this method transforms bidirectional edges into unidirectional edges using regularization to construct a directed acyclic graph (DAG). The longest path in the DAG is then used as a compact upper bound to effectively exclude extreme execution orders, thereby significantly reducing WCET pessimism and improving analytical predictability.

[0141] The beneficial effects of this application include at least the following:

[0142] This invention overcomes the limitations of the path determinism assumption. Existing technologies rely on the premise that warp execution paths can be statically determined, leading to a lack of practical feasibility in the analysis. The static analysis framework proposed in this application can cover all execution scenarios without pre-setting warp paths, achieving WCET derivation that better reflects actual operating characteristics.

[0143] This paper effectively reduces the pessimism caused by scheduling uncertainty. Existing methods, when using only the work-keeping scheduling assumption, need to take the worst-case scenario among all possible warp execution sequences, resulting in an extremely conservative upper bound. This application, by modeling the scheduling constraints in a graph and introducing realizable topological constraints, excludes some extreme and unreachable execution sequences, significantly tightening the upper bound of WCET while ensuring safety.

[0144] Reference Figure 6 This application provides a worst-case execution time upper bound analysis device for thread blocks targeting GPU kernels, including:

[0145] An execution path representation unit is used to represent the execution path of each warp in a thread block executing GPU kernel functions as a path composed of a sequence of basic blocks;

[0146] The instruction model construction unit is used to construct the instruction model based on the instructions executed by the thread lockstep of the warp in the basic block by the GPU pipeline.

[0147] The warp model construction unit is used to determine the execution path as a sequence of alternating critical and non-critical segments based on the instruction model; wherein the sequence of alternating critical and non-critical segments is used as the warp model.

[0148] The first upper bound analysis unit is used to determine all candidate warp execution scenarios under branching based on the instruction model and the warp model, thereby analyzing the worst execution time of the thread block without setting the execution path and obtaining the working upper bound;

[0149] The second upper bound analysis unit is used to perform scheduling constraint modeling on the instruction model and the warp model to obtain the upper bound of the topological constraints.

[0150] It is understood that the content of the above method embodiments is applicable to the present device embodiments. The specific functions implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0151] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0152] Furthermore, although this application is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the described functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding this application. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional technology for an engineer. Therefore, those skilled in the art can implement the application set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of this application, which is determined by the full scope of the appended claims and their equivalents.

[0153] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0154] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0155] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0156] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0157] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0158] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0159] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A method for worst-case execution time upper bound analysis of thread blocks for GPU kernels, characterized in that, The method includes the following steps: The execution path of each warp in a thread block executing the GPU kernel function is represented as a path composed of a sequence of basic blocks; The instruction model is constructed based on the instructions executed by the thread lockstep of the warp in the basic block according to the GPU pipeline; Based on the instruction model, the execution path is determined as a sequence of alternating critical and non-critical segments; wherein, the sequence of alternating critical and non-critical segments is used as a warp model; Based on the instruction model and the warp model, all candidate warp execution scenarios under branching are determined, thereby analyzing the worst execution time of the thread block without setting the execution path and obtaining the working upper bound; Scheduling constraints are modeled on the instruction model and the warp model to obtain the upper bound of the topological constraints.

2. The method for worst-case execution time upper bound analysis of thread blocks for GPU kernels according to claim 1, characterized in that, Representing the execution path of each warp in a thread block as a path composed of a sequence of basic blocks for executing GPU kernel functions includes the following steps: The GPU kernel function is represented as a control flow graph constructed by the compiler, and each warp in the thread block is defined as executing each branch of the control flow graph sequentially, thereby representing the execution path of each warp in the thread block executing the GPU kernel function as a path composed of a sequence of basic blocks.

3. The method for worst-case execution time upper bound analysis of thread blocks for GPU kernels according to claim 1, characterized in that, The step of determining the execution path as an alternating sequence of critical and non-critical segments based on the instruction model includes the following steps: Based on the instruction model, the issuance time, exclusive resource time, resource release time, and completion time of each instruction in the basic block are obtained, and then the execution path is determined as a sequence of alternating critical and non-critical segments.

4. The method for worst-case execution time upper bound analysis of thread blocks for GPU kernels according to claim 1, characterized in that, The step of determining all candidate warp execution scenarios under branching based on the instruction model and the warp model, and then analyzing the worst-case execution time of the thread block without setting the execution path, to obtain the working upper bound, includes the following steps: Analyze the global non-critical segments and use the duration of the non-critical segment in the execution path that is the last executed segment in the thread block as the upper bound of the global non-critical segment duration. The expression for maintaining the upper bound of the work is: ； in, To maintain an upper bound for the work, The set of all the aforementioned execution paths. The number of warps in the thread block. Indicates the execution path Execution time of the critical section Indicates the execution path Execution time of the critical segment in China and Africa.

5. The method for worst-case execution time upper bound analysis of thread blocks for GPU kernels according to claim 1, characterized in that, The process of performing scheduling constraint modeling on the instruction model and the warp model to obtain the upper bound of topological constraints includes the following steps: Graph modeling is performed on the scheduling policy constraints that only follow work-holding scheduling to obtain the scheduling policy constraint graph; The scheduling strategy constraint graph is converted into a directed acyclic graph; Calculate the longest path in the directed acyclic graph, and use the set of nodes of the longest path as the upper bound of the topological constraint.

6. The method for worst-case execution time upper bound analysis of thread blocks for GPU kernels according to claim 5, characterized in that, The process of performing graph modeling on the scheduling policy constraints that only follow work-keeping scheduling to obtain the scheduling policy constraint graph includes the following steps: Treating each warp as a node, a directed edge is added between every two adjacent critical and non-critical segments of each warp, and a bidirectional edge is added between every two critical segments of different warps to obtain the scheduling strategy constraint graph. The process of converting the scheduling policy constraint graph into a directed acyclic graph includes the following steps: Convert bidirectional edges within the same column into unidirectional edges pointing from nodes with smaller warp indices to nodes with larger warp indices; Convert bidirectional edges between different columns into unidirectional edges that point from a node with a smaller column number to a node with a larger column number; By removing redundant edges from the scheduling strategy constraint graph, the directed acyclic graph is obtained.

7. The method for worst-case execution time upper bound analysis of thread blocks for GPU kernels according to claim 5, characterized in that, The calculation of the longest path in the directed acyclic graph, using the set of nodes of the longest path as the upper bound of the topological constraints, includes the following steps: The upper bound of the topological constraints is calculated as follows: ； in, This is the upper bound of the topological constraints. Represents a node The duration of the key or non-key segment it represents.

8. A worst-case execution time upper bound analysis device for thread blocks targeting GPU kernels, characterized in that, The device includes: An execution path representation unit is used to represent the execution path of each warp in a thread block executing GPU kernel functions as a path composed of a sequence of basic blocks; The instruction model construction unit is used to construct the instruction model based on the instructions executed by the thread lockstep of the warp in the basic block by the GPU pipeline. The warp model construction unit is used to determine the execution path as a sequence of alternating critical and non-critical segments based on the instruction model; wherein the sequence of alternating critical and non-critical segments is used as the warp model. The first upper bound analysis unit is used to determine all candidate warp execution scenarios under branching based on the instruction model and the warp model, thereby analyzing the worst execution time of the thread block without setting the execution path and obtaining the working upper bound; The second upper bound analysis unit is used to perform scheduling constraint modeling on the instruction model and the warp model to obtain the upper bound of the topological constraints.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory; The memory is used to store programs; The processor executes the program to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a program that is executed by a processor to implement the method as described in any one of claims 1 to 7.

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