Thread identification method and related apparatus

Abstract

This application provides a thread identification method and related apparatus. The method includes: acquiring call stack information of each thread of a running application; if a thread can execute a task of the application through the function call chain indicated by its call stack information, then the thread is the key thread of the corresponding task of the application. A thread is the main body executing the application, and a key thread is the main body executing the application's task. A key thread can execute the application's task through the function call chain indicated by its call stack information. Each task of the application has a corresponding function call chain. This application determines the key thread of the application's task by using the function call chain indicated by the call stack information, thereby improving the accuracy and efficiency of identifying the key thread of the application's task.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a thread identification method and related apparatus. Background Technology

[0002] Electronic devices typically have multiple applications installed. Each application creates multiple threads during runtime. Application performance can be improved by identifying and optimizing key threads. Each application offers various tasks; for example, an application on a server might perform tasks such as calculating the sum of two numbers or processing images. Conventional thread identification methods often fail to identify key threads for application tasks, while manually identifying key threads based on experience is inefficient and inaccurate. Summary of the Invention

[0003] This application provides a thread identification method and related apparatus to improve the accuracy and efficiency of identifying critical threads of application tasks.

[0004] To achieve the above objectives, this application adopts the following technical solution:

[0005] In a first aspect, a thread identification method is provided, the method comprising: obtaining call stack information of each thread of a running application, the call stack information being used to indicate the function call chain of the corresponding thread; determining the key thread of a task of the application based on the call stack information, the key thread executing the task of the application through the function call chain indicated by the corresponding call stack information.

[0006] In this way, the electronic device obtains the call stack information of each thread in the application, and then determines the critical thread of the application's task based on the call stack information of each thread. The critical thread can execute the application's task through the function call chain indicated by its corresponding call stack information. Since the critical thread is the main body that executes the application's task, it executes the application's task through function calls. The call stack information corresponding to the critical thread is used to record the record of the function calls made by the critical thread (i.e., the function call chain). The electronic device uses the call stack information to identify the critical thread of the application's task, thereby improving the accuracy and efficiency of the identification of the critical thread of the application's task.

[0007] In some implementations of the first aspect, determining the key threads of the application's task based on the call stack information includes: determining the key threads of the application's task based on the call stack information and thread characteristic information, wherein the thread characteristic information includes at least one of the input / output I / O utilization of each thread and processor usage information, and the processor usage information includes the proportion of processor resources occupied by the thread during runtime or the time information of the thread being in a running state on the processor.

[0008] Thus, by using call stack information to identify threads related to the application's task, and by using thread characteristic information to identify the threads that perform the main computations or operations of the application's task (e.g., the thread with the most traffic assigned to the task among multiple threads), the critical threads identified by combining these two methods are both related to the application's task and can perform the main computations or operations of that task. Combining thread call stack information and thread characteristic information to identify the critical threads of the application's task improves the accuracy of the identified critical threads.

[0009] In some implementations of the first aspect, determining the critical thread of the application's task based on the call stack information and thread characteristic information includes: determining the critical thread of the application's task based on the call stack information, thread characteristic information, and task type information, wherein the task type information is used to indicate the task type of the application or the task type of the application's task, and the task type includes compute-intensive or I / O-intensive.

[0010] Optionally, in determining the critical threads of an application, the critical threads among multiple threads can also be identified based on the application's task type or the task type of the application's task. Task types include compute-intensive (also known as CPU-bound) and I / O-intensive. If the task type is compute-intensive, it relies on the processor for a large amount of computation; if the task type is I / O-intensive, its CPU consumption is low, and it spends most of its time waiting for I / O operations to complete. Combining task type, call stack information, and thread characteristic information can improve the accuracy of identifying the critical threads.

[0011] In some implementations of the first aspect, determining the critical thread of the application's task based on the call stack information includes: determining the target thread of the application based on the call stack information, wherein the target thread executes the application's task through the function call chain indicated by the call stack information; and determining the target thread as a critical thread if the task's execution efficiency improves after optimization. Since the purpose of determining the critical thread is to improve the application's task execution efficiency, the execution efficiency of the determined target thread can be verified during the determination process. If optimizing the target thread improves the application's task execution efficiency, then the target thread is determined as a critical thread of the application's task; if optimizing the target thread does not improve the application's task execution efficiency or decreases, then the target thread is determined as a non-critical thread of the application's task. By verifying the execution efficiency of the target thread, the accuracy of determining the critical thread of the application's task can be improved.

[0012] In some implementations of the first aspect, determining the critical threads of the application's tasks based on the call stack information includes: inputting the call stack information into a thread identification model to obtain the critical threads of the application's tasks. Identifying critical threads using a machine learning model improves the efficiency and accuracy of critical thread identification.

[0013] In some implementations of the first aspect, the method further includes: determining the target processor core of the key thread based on the memory access information of the key thread, wherein the memory access information indicates the size of the cache of the processor core accessed by the key thread when executing the task, and the cache access volume of the target processor core accessed by the key thread is greater than the cache access volume of other processor cores accessed by the key thread, and the processor cores accessed by the key thread when executing the task include the target processor core; and binding the key thread to the target processor core. Thus, when executing the application's task, if the cache access volume of the processor core accessed by the key thread is large, the key thread will have higher running efficiency on that processor core. By binding the key thread to that processor core, the running efficiency of the key thread is improved, thereby improving the running efficiency of the application's task.

[0014] In some implementations of the first aspect, the number of key threads is N, and the processor cores accessed by each key thread include first-type processor cores and second-type processor cores. The cache access volume of each key thread to the corresponding first-type processor core is greater than the cache access volume to the corresponding second-type processor core. The N key threads correspond to M first-type processor cores, where N is a positive integer greater than 1, M is a positive integer greater than 0, and N > M. The method further includes: binding M of the N key threads to the M first-type processor cores one-to-one; if the number of second-type processor cores corresponding to the N key threads is P, and P ≥ NM, then binding the NM key threads that are not bound to the first-type processor cores to the NM second-type processor cores; or if P < NM, then binding at least two of the NM key threads that are not bound to the first-type processor cores to one first-type processor core or one second-type processor core. Thus, since the cache access frequency of critical threads to their corresponding Type 1 processor cores is greater than their cache access frequency to their corresponding Type 2 processor cores, during thread binding, the thread can be bound to the Type 1 processor core to improve the data access hit rate and reduce data access latency, thereby improving the running efficiency of the task corresponding to the thread. If the number of Type 1 processor cores is less than the number of critical threads in the application, some critical threads can be bound one-to-one to Type 1 processor cores, and other critical threads can be bound one-to-one to Type 2 processor cores. This one-to-one binding of critical threads to processor cores improves the running efficiency of critical threads. If the sum of the number of Type 1 and Type 2 processor cores is less than the number of critical threads, at least two critical threads should be bound to the same target processor core or the same processor core.

[0015] In a second aspect, a thread identification device is provided, the device comprising a unit for performing the method described in any one of the first aspects.

[0016] In some implementations of the second aspect, the thread identification device includes an acquisition unit and a determination unit. The acquisition unit is used to acquire call stack information of each thread of the running application, the call stack information being used to indicate the call chain of functions corresponding to the thread. The determination unit is used to determine the key thread of the application's task based on the call stack information, the key thread being able to execute the application's task through the call chain of functions indicated by the call stack information.

[0017] In some implementations of the second aspect, determining the critical thread of the application's task based on the call stack information and thread characteristic information includes: determining the critical thread of the application's task based on the call stack information, thread characteristic information, and the task type of the application or the task, wherein the task type includes compute-intensive and I / O-intensive tasks.

[0018] In some implementations of the second aspect, the determining unit is used to determine the key threads of the application's task based on the call stack information and thread characteristic information, wherein the thread characteristic information includes at least one of the input / output I / O utilization of each thread and processor usage information, and the processor usage information includes the proportion of processor resources occupied by the thread during runtime or the time information of the thread being in a running state on the processor.

[0019] In some implementations of the second aspect, the determining unit is used to determine the target thread of the application based on the call stack information. The target thread can execute the application's task through the call chain of the function indicated by the call stack information. If the running efficiency of the task is improved after the target thread is optimized, the target thread is determined to be a critical thread.

[0020] In some implementations of the second aspect, the determining unit is used to input the call stack information into a thread identification model to obtain the key thread of the application's task. The identification device further includes a binding unit, which is used to determine the target processor core of the key thread based on the memory access information of the key thread. The memory access information indicates the size of the cache of the processor core accessed by the key thread when executing the task, wherein the cache access amount of the target processor core accessed by the key thread is greater than the cache access amount of other processor cores accessed by the key thread, and the processor core accessed by the key thread when executing the task includes the target processor core; and binds the key thread to the target processor core.

[0021] In some implementations of the second aspect, the number of key threads is N, and the processor cores accessed by each key thread include first-type processor cores and second-type processor cores. The cache access volume of each key thread to the corresponding first-type processor core is greater than the cache access volume to the corresponding second-type processor core. The N key threads correspond to M first-type processor cores, where N is a positive integer greater than 1, M is a positive integer greater than 0, and N > M. The binding unit is also used to bind M of the N key threads to the M first-type processor cores one-to-one. If the number of second-type processor cores corresponding to the N key threads is P, and P ≥ NM, then the NM key threads that are not bound to the first-type processor cores are bound to the NM second-type processor cores; or if P < NM, then at least two of the NM key threads that are not bound to the first-type processor cores are bound to one first-type processor core or one second-type processor core.

[0022] Thirdly, an electronic device is provided, comprising: a memory including computer-readable instructions; and a processor communicating with the memory, the processor being configured to execute the computer-readable instructions, causing the electronic device to perform the thread identification method described in any one of the first aspects.

[0023] Fourthly, a computer-readable storage medium is provided, including a program or instructions that, when executed by a processor, implement the thread identification method as described in any one of the first aspects.

[0024] Fifthly, a chip is provided, including a processor for retrieving and executing instructions stored in a memory, causing an electronic device on which the chip is mounted to perform the thread identification method described in any one of the first aspects.

[0025] In a sixth aspect, a computer program product is provided, the computer program product comprising instructions that, when executed by a computer, implement the method as described in any one of the first aspects.

[0026] The beneficial effects of each possible implementation of the thread identification device provided in the second aspect of the embodiments of this application, the electronic device provided in the third aspect, the computer-readable storage medium provided in the fourth aspect, the chip provided in the fifth aspect, and the computer program product provided in the sixth aspect can be referred to the descriptions of the various possible implementations in the first aspect, and will not be repeated here. Attached Figure Description

[0027] Figure 1 A schematic diagram illustrating the relationship between a processor and threads is provided in an embodiment of this application.

[0028] Figure 2 A flowchart illustrating a thread identification method provided in an embodiment of this application;

[0029] Figure 3 A schematic diagram of a thread identification device provided in an embodiment of this application;

[0030] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0031] The technical solutions in this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments in this specification, and not all of them.

[0032] Electronic devices can have multiple applications installed, each creating multiple threads during runtime. To improve application performance, critical threads can be identified and optimized, such as by binding them to high-performance processor (central process unit, CPU) cores to speed up application startup. Each application can provide multiple tasks, which are a series of operations or calculations performed by threads. For example, a task might be calculating the sum of two numbers, processing images, performing database queries, conducting network communication, writing data, or reading data. Conventional thread identification methods can identify critical threads within an application, but not the critical threads of its tasks. That is, optimizing critical threads can improve the efficiency of one or more aspects of the application, but not the efficiency of one or more of its tasks. Because each application has a large number of threads, manually identifying the critical threads of application tasks is both inaccurate and inefficient.

[0033] To address the aforementioned issues, this application provides a thread identification method that can obtain the call stack information of each thread in a running application. If a thread can execute an application task through the function call chain indicated by its call stack information, then that thread is a critical thread of the application task. A thread is the main body executing an application, and a critical thread is the main body executing an application task. A critical thread can execute an application task through the function call chain indicated by its call stack information. Each task of an application has a corresponding function call chain. This application determines the critical thread of an application task by using the function call chain indicated by the call stack information, thereby improving the accuracy and efficiency of identifying the critical thread of an application task.

[0034] Optionally, the execution subject of the thread identification method in this application embodiment can be an electronic device with a processor. The electronic device can be referred to as: a terminal, user equipment (UE), terminal device, access terminal, user unit, user station, mobile station, remote station, remote terminal, mobile device, user terminal, wireless communication device, user agent, or user device, etc. Specifically, the electronic device can be a mobile phone, augmented reality (AR) device, virtual reality (VR) device, tablet computer, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), etc. The electronic device can also be a server, etc. The server can be a single physical or logical server, or two or more physical or logical servers sharing different responsibilities and cooperating to implement various server functions. The execution subject of the thread identification method in this application embodiment can also be a processor, which can include one or more general-purpose central processing units (CPUs), or other general-purpose processors, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. Each general-purpose processor represents a CPU core, which can also be called a kernel.

[0035] Please see Figure 1 , Figure 1 A schematic diagram illustrating the relationship between a processor and threads is provided in the embodiment of the application. Figure 1 The processor includes two CPU cores: CPU core 1 and CPU core 2; application 1 can provide two types of tasks: task 1 and task 2, where thread 1 and thread 2 execute task 1 through the call chain of the function indicated by the corresponding call stack information. The functions called by thread 1 and thread 2 when executing task 1 are the same. Thread 3 executes task 2 through the call chain of the function indicated by its call stack information. Thread 1 is scheduled to be executed on CPU core 1, and threads 2 and 3 are scheduled to be executed on CPU core 2.

[0036] Figure 1 In this embodiment, the processor includes two CPU cores. In other embodiments, the processor may be a single-core processor, in which case all threads are executed on one CPU core. The processor may also be dual-core, quad-core, octa-core, 12-core, or 16-core, in which case multiple threads can be executed on the corresponding CPU cores according to actual needs. Figure 1The application can provide two tasks; in other embodiments, the application may also provide one task, three tasks, or more than three tasks. Figure 1 In an application, a task can be executed by one thread or two threads. In other embodiments, a task can also be executed by three or more threads. For example, a task can be divided into five subtasks, each of which is executed by one thread, so that task of the application is executed by five threads.

[0037] Please see Figure 2 , Figure 2 This is a flowchart illustrating a thread identification method provided in an embodiment of this application. Figure 2 The explanation will be based on the example of an electronic device executing the thread identification method. Figure 2 The methods for identifying threads include: S201 to S202.

[0038] S201. The electronic device obtains the call stack information of each thread of the running application. The call stack information is used to indicate the call chain of the functions of the corresponding thread.

[0039] Optionally, the running application may be an application that is performing relevant tasks on the electronic device, or an application that is currently interacting with the user, such as MySQL running in the foreground of the electronic device.

[0040] Optionally, an application is a standalone software package. Each application is allocated one or more processes at runtime. A process can contain multiple threads, each with its own call stack. A call stack is a stack-type data structure. A stack is a special linear list where data insertion and deletion operations can only be performed at one end. Stacks can be used to store function call information such as local variables, function parameters, and return addresses during thread runtime.

[0041] Optionally, during application execution, an application thread calls the main function, the main function calls another function, and that function calls other functions. This call relationship between functions is the thread's call stack information. The thread's call stack information is used to record the sequential relationship between functions during the thread's execution, i.e., the function call chain.

[0042] Optionally, the electronic device may obtain call stack information for each thread from event data of the performance monitoring unit (PMU).

[0043] Optionally, if the running application has multiple threads, and each thread has its corresponding call stack information, then the electronic device in S101 can obtain multiple call stack information of multiple threads.

[0044] S202. The electronic device determines the critical thread of the application's task based on the call stack information. The critical thread can execute the application's task through the call chain of functions indicated by the call stack information.

[0045] Optionally, during application execution, threads are the main entities executing the application, and critical threads are the main entities executing the application's tasks. Critical threads execute application tasks through the function call chain indicated by their corresponding call stack information. After obtaining the thread call stack information, the electronic device can determine whether each thread can execute the application's task through the function call chain indicated by its call stack information. If a thread can execute the application's task through the function call chain indicated by its corresponding call stack information, then that thread is a critical thread for that task of the application; if a thread cannot execute the application's task through the function call chain indicated by its corresponding call stack information, then that thread is a non-critical thread of the application.

[0046] For example, when thread 1 executes task A of the application, thread 1 calls function 1, function 1 calls function 2, function 2 calls function 3, and then returns the execution result of task A. The call stack information of thread 1 can record the function call chain when thread 1 executes task A: thread 1 calls function 1, function 1 calls function 2, function 2 calls function 3. After the electronic device obtains the call stack information, it determines that thread 1 can execute task A of the application by calling function 1, function 1 calls function 2, and function 2 calls function 3. Therefore, thread 1 is the critical thread for task A of the application.

[0047] Optionally, since each application can provide multiple tasks—for example, application A can provide tasks such as image processing—and each task of the application is implemented by a corresponding key thread through a specific function call chain, meaning each task of the application has a corresponding function call chain, the electronic device can establish a correspondence between the application's tasks and the function call chains. After obtaining the call stack information of each thread, the electronic device can determine the call stack information corresponding to each task of the application based on the call stack information and the correspondence, and thus determine that the thread corresponding to the call stack information is the key thread of the corresponding task of the application.

[0048] Optionally, since each application can provide multiple tasks, the electronic device in S202 can be used to determine the critical thread of one task of the application, or it can be used to determine the critical threads of multiple tasks of the application. If the electronic device is used to determine the critical thread of one task of the application, after obtaining the call stack information of each thread, if the thread can execute the task through the call chain of the function indicated by its corresponding call stack information, then the electronic device determines that the thread is the critical thread of that task of the application. The task can be the core task of the application or any task specified by the user. If the electronic device is used to determine the critical threads of multiple tasks of the application, after obtaining the call stack information of each thread, if the thread can execute any task through the call chain of the function indicated by the call stack information, then the thread is determined to be the critical thread of that task of the application. Since each task can be executed by at least one thread through the call chain of the function indicated by its corresponding call stack information, the electronic device can obtain multiple critical threads corresponding to multiple tasks of the application. These multiple tasks can be all the tasks that the application can provide, or some of the tasks that the application can provide. For example, if the application can provide 5 tasks, then the critical threads of 3 specified tasks can be identified.

[0049] In this way, the electronic device obtains the call stack information of each thread in the application, and then determines the critical thread of the application's task based on the call stack information of each thread. The critical thread can execute the corresponding task of the application through the function call chain indicated by its corresponding call stack information. Since the critical thread is the main body for executing the corresponding task of the application, each critical thread executes the corresponding task of the application through function calls. The call stack information corresponding to the critical thread is used to record the record of function calls made by the critical thread (i.e., the function call chain). The electronic device uses the call stack information to quickly identify the critical thread of the application's task, thereby improving the accuracy and efficiency of the identification of the critical thread of the application's task.

[0050] Optionally, to improve application throughput and responsiveness, multiple threads can concurrently process the same task of the application. These multiple threads execute the same task of the business program through the same function call chain. For example, a task can be divided into multiple identical subtasks, which are executed by multiple threads through the same function call chain. Then, the function call chains indicated by the multiple call stack information of these multiple threads are the same. The electronic device can determine the number of critical threads for each task of the application based on the function call chains indicated by the call stack information. That is, each task of the application can have multiple critical threads or only one critical thread.

[0051] Optionally, if multiple threads can execute the same task of the application through the function call chain indicated by their corresponding call stack information, the electronic device may use all multiple threads as the key threads of the application task; the electronic device may also select a specific number of threads from the multiple threads as the key threads of the application task, wherein the specific number may be one or more.

[0052] In this embodiment, the electronic device determines the critical thread for an application's task to improve the application's task execution efficiency. If multiple threads can execute the same task of the application through the function call chain indicated by their corresponding call stack information, the electronic device can optimize the critical thread among the multiple threads. The critical thread can be the thread with the most traffic assigned to that task. For example, if three threads are all used to execute the application's read / write tasks, and the traffic allocated to these three threads for handling read / write tasks is 5Mb, 1Mb, and 1Mb respectively, then the electronic device can set the thread with the allocated traffic of 5Mb as the critical thread.

[0053] Optionally, the electronic device can use thread characteristic information to determine which thread receives the most bandwidth among multiple threads. Thread characteristic information includes at least one of the following: input / output I / O utilization for each thread, and processor usage information, whereby the processor usage information indicates the proportion of processor resources occupied by the thread during runtime or the time the thread is in a running state on the processor.

[0054] Thread input / output (I / O) utilization refers to the proportion of time a thread occupies I / O resources while performing I / O operations (such as reading and writing to disk, network communication, etc.). A high I / O utilization rate indicates that the thread spends more time performing I / O operations and less time on actual computation, potentially impacting the efficiency of the task being executed by that thread. Electronic devices can use thread I / O utilization to identify threads that are likely to handle a large volume of application traffic.

[0055] Optionally, one possible implementation of the electronic device determining the critical threads of the application's task based on call stack information in S202 is as follows: the electronic device determines the critical threads of the application's task based on call stack information and the I / O utilization of each thread. In this way, the electronic device determines the threads related to the application's task through call stack information, and determines the threads handling the application's task with high traffic through the I / O utilization of each thread. The critical threads determined by combining these two methods are both related to the application's task and can handle a significant amount of traffic from that task, thereby improving the accuracy of the determined critical threads.

[0056] Optionally, the electronic device first determines the target thread corresponding to the application's task based on the call stack information. This target thread can execute the application's task through the call chain of the function indicated by its corresponding call stack information. If there is only one target thread for the same task in the application, then that target thread is the critical thread for the application's task. If there are multiple target threads for the same task in the application, the electronic device determines the critical thread among the multiple target threads based on their I / O utilization. For example, the electronic device can set the target thread with the higher I / O utilization among the multiple target threads as the critical thread.

[0057] Optionally, if the electronic device determines that the number of target threads of the application's task is multiple based on the call stack information, the electronic device can obtain task type information and determine the key thread among the multiple target threads based on the task type information and the I / O utilization of the multiple target threads. The task type information is used to indicate the task type of the application or the task type of the application's task.

[0058] Optionally, if the task type information is used to indicate the task type of the application, the task type of the application includes compute-intensive (also known as CPU-bound) and I / O-intensive. If the task type of the application is compute-intensive, then the application relies on the processor to perform a large number of computational tasks; if the task type of the application is I / O-intensive, then the application consumes very little CPU and spends most of its time waiting for I / O operations to complete.

[0059] Optionally, the electronic device determines, based on the call stack information, that the number of target threads for the application's tasks is multiple. If the application's task type is compute-intensive, the target threads with lower I / O utilization are designated as critical threads. If the application's task type is I / O-intensive, the target threads with higher I / O utilization are designated as critical threads.

[0060] Each application includes multiple tasks. The task types of the application can be the same as or different from the task types of the multiple tasks within the application. For example, an application can provide task A and task B. The task type of the application is compute-intensive, and the task type of task A is also compute-intensive, which is the same as the task type of the application. However, the task type of task B is I / O-intensive, which is different from the task type of the application.

[0061] Optionally, if the task type information is used to indicate the task type of the application's task, and if the electronic device determines, based on the call stack information, that the number of target threads for the application's task is multiple, the electronic device obtains the task type of the task and determines the critical thread among the multiple target threads based on the task type and the I / O utilization of the multiple target threads.

[0062] Optionally, the task type includes compute-intensive and I / O-intensive. If the task type of the application is compute-intensive, the task relies on the processor to perform a large number of computational tasks; if the task type is I / O-intensive, the CPU consumption of the task is very low, and most of the time is spent waiting for I / O operations to complete.

[0063] Optionally, if the electronic device determines, based on the call stack information, that there are multiple target threads for an application task, and that the task type is I / O intensive, then the I / O utilization of the critical thread among the multiple target threads is higher than the I / O utilization of the other target threads. Since multiple target threads all serve as the main body executing the same task of the application, and that task is I / O intensive, if one target thread has a high I / O utilization, then that thread is allocated relatively more traffic for that task. Optimizing that thread can improve the running efficiency of that task in the application on the electronic device.

[0064] Optionally, if the task type is I / O intensive, the electronic device can set the target thread with the highest I / O utilization among multiple target threads as the critical thread. In other embodiments, the electronic device can also set the target thread with I / O utilization greater than a preset threshold as the critical thread; in other embodiments, the electronic device can also set a preset number of target threads as critical threads among multiple target threads, wherein the I / O utilization of the preset number of target threads is greater than the I / O utilization of other target threads.

[0065] Optionally, if the electronic device determines, based on the call stack information, that there are multiple target threads for an application task, and that the task is computationally intensive, then the I / O utilization of the critical thread among the multiple target threads is lower than the I / O utilization of the other target threads. Since multiple target threads all serve as the main body executing the same task of the application, and that task is computationally intensive, if the I / O utilization of one target thread is low, then that thread is allocated relatively more bandwidth for that task. Optimizing that thread can improve the running efficiency of that task in the application on the electronic device.

[0066] Optionally, if the task type is computationally intensive, the electronic device can set the target thread with the lowest I / O utilization among multiple target threads as the critical thread. In other embodiments, the electronic device can also set target threads with I / O utilization less than a preset threshold as critical threads; in other embodiments, the electronic device can also set a preset number of target threads as critical threads among multiple target threads, wherein the I / O utilization of the preset number of target threads is less than the I / O utilization of other target threads.

[0067] The CPU resource usage of threads affects the running efficiency of an application, and the CPU resource usage of critical threads affects the running efficiency of application tasks. Electronic devices can use thread processor usage information to determine the main computational or operational threads of an application's tasks, such as the thread with the highest workload assigned to that task among multiple threads.

[0068] Optionally, one possible implementation of the electronic device determining the critical threads of the application's task based on the call stack information in S202 is as follows: The electronic device determines the critical threads of the application's task based on the call stack information and the processor usage information of each thread. In this way, the electronic device determines the threads related to the application's task through the call stack information, and determines the threads with higher traffic to the application's task through the processor usage information of each thread. The critical threads determined by combining these two methods are both related to the main body of the application's task and have higher traffic to execute, thereby improving the accuracy of the determined critical threads.

[0069] Optionally, processor usage information includes the proportion of processor resources used by a thread while it is running or the time a thread is in a running state (on-CPU) on the processor.

[0070] Optionally, CPU utilization can be used to describe the proportion of processor resources used by a thread during runtime. CPU utilization refers to the proportion of CPU time occupied by a thread while it is executing computational tasks. In other words, it's the proportion of CPU time occupied by a thread while it is executing application tasks.

[0071] Optionally, the time a thread spends executing on the processor or the time a thread is in a running state on the processor can be described by its on-CPU time and / or off-CPU time. A thread's on-CPU time is the time it spends executing instructions on the CPU. On-CPU time includes the time a thread spends performing computational tasks, processing data, etc. In the on-CPU state, a thread can fully utilize CPU resources for efficient computation and processing. A thread's off-CPU time is the time a thread is blocked waiting for events such as I / O operations, locks, counters, and page swapping. In the off-CPU state, a thread cannot utilize CPU resources and is in a waiting or idle state. Therefore, a longer on-CPU time means more time for the thread to perform effective computations or processing tasks, which improves the efficiency of the corresponding task. Conversely, a longer off-CPU time means the thread needs to wait for certain resources or events during execution, slowing down the execution rate of the corresponding business logic.

[0072] Optionally, the electronic device first determines the target thread corresponding to the application's task based on the call stack information. This target thread can execute the application's task through the call chain of the function indicated by its corresponding call stack information. If there is only one target thread for the same task of the application, then this target thread is the critical thread of the application's task. If there are multiple target threads for the same task of the application, the electronic device determines the critical thread among the multiple target threads based on the processor usage information of the multiple target threads.

[0073] Optionally, if the application has multiple target threads for the same task, and the processor usage information includes the CPU utilization of the threads and the task type is compute-intensive, then the CPU utilization of the critical thread among the multiple target threads is higher than the CPU utilization of the other target threads among the multiple target threads.

[0074] If the number of target threads for the same task in an application is multiple, the processor usage information includes the CPU utilization of the threads, and the task type is I / O intensive, then the CPU utilization of the critical thread among the multiple target threads is lower than the CPU utilization of the other target threads among the multiple target threads.

[0075] If the processor usage information includes the on-CPU time of threads and the task type is compute-intensive, then the on-CPU time of the critical thread among the multiple target threads is greater than the on-CPU time of the other target threads among the multiple target threads; if the task type is I / O-intensive, then the on-CPU time of the critical thread among the multiple target threads is less than the on-CPU time of the other target threads among the multiple target threads.

[0076] If the processor usage information includes the off-CPU time of the threads and the task type is compute-intensive, then the off-CPU time of the critical thread among the multiple target threads is less than the off-CPU time of the other target threads among the multiple target threads; if the task type is I / O intensive, then the off-CPU time of the critical thread among the multiple target threads is greater than the off-CPU time of the other target threads among the multiple target threads.

[0077] The application may have multiple target threads for the same task, meaning that multiple target threads all serve as the main body executing the same task. By analyzing the task type and CPU usage information of the multiple target threads, the thread with the relatively higher CPU usage allocated to that task can be selected. Optimizing this thread can improve the running efficiency of the application for that task on the electronic device.

[0078] Optionally, one possible implementation of the electronic device in S202 determining the critical threads of an application task based on call stack information is as follows: The electronic device determines the critical threads of the application task based on call stack information, the I / O utilization of each thread, and the processor usage information of each thread. By using thread call stack information, I / O utilization, and processor usage information to determine the critical threads of the application task, the determined critical threads are not only related to the application task but also perform the main computations or main operations of the application task (e.g., the task assigned to them has high throughput). Combining thread call stack information, I / O utilization, and processor usage information to determine the critical threads of the application task improves the accuracy of the determined critical threads.

[0079] Because thread I / O utilization and CPU usage information (such as CPU utilization, on-CPU time, or off-CPU time) are interdependent, when a thread performs I / O operations, the CPU may be idle, waiting for the I / O operation to complete; conversely, when a thread executes instructions on the CPU, the I / O device may be idle, waiting for CPU instructions. The following explanation uses CPU usage information, including CPU utilization, as an example. If the task type of the application corresponding to the thread is compute-intensive, compute-intensive tasks primarily consume CPU resources, resulting in higher CPU utilization and relatively lower I / O utilization for the thread. Conversely, if the task type of the application corresponding to the thread is I / O-intensive, I / O-intensive tasks primarily consume I / O resources, resulting in higher I / O utilization and relatively lower CPU utilization for the thread.

[0080] Optionally, the electronic device first determines the target thread corresponding to the application's task based on the thread's call stack information. This target thread can execute the application's task through the function call chain indicated by the call stack information. If there is only one target thread for the same task in the application, then this target thread is the critical thread of the application's task. If there are multiple target threads for the same task in the application, the electronic device obtains the task type of the application's task, and then determines the critical thread among the multiple target threads based on the task type, I / O utilization, and CPU usage information.

[0081] Optionally, the electronic device determines the number of target threads corresponding to the application task based on the thread's call stack information. If the task type is computationally intensive, the target thread with higher CPU utilization and relatively lower IO utilization among the multiple target threads is identified as the critical thread, that is, the CPU utilization of the critical thread among the multiple target threads is greater than the CPU utilization of other target threads and / or the IO utilization of the critical thread among the multiple target threads is less than the IO utilization of other target threads.

[0082] Optionally, the electronic device determines the number of target threads corresponding to the application task based on the thread's call stack information. If the task type is I / O intensive, the target thread with higher I / O utilization and relatively lower CPU utilization among the multiple target threads is identified as the critical thread, that is, the CPU utilization of the critical thread among the multiple target threads is lower than the CPU utilization of other target threads and / or the I / O utilization of the critical thread among the multiple target threads is higher than the I / O utilization of other target threads.

[0083] Optionally, after determining the critical threads of an application's task, the electronic device can optimize the critical threads to improve the running efficiency of the application's task. For example, by optimizing the critical threads, the time required for the application's task to run once can be reduced, or the number of times the application's task can run per unit time can be increased.

[0084] Optionally, if the critical thread has high I / O utilization, the critical thread can be optimized by: optimizing the program code corresponding to the critical thread, reducing unnecessary I / O operations, improving the efficiency of I / O operations, thereby reducing the I / O utilization of the critical thread and improving the running efficiency of the application tasks corresponding to the critical thread.

[0085] Optionally, if the critical thread has high I / O utilization or high CPU utilization, optimization of the critical thread can include: binding the critical thread to a specific CPU core to reduce the context saving and restoring operations required when the thread switches between different CPU cores. Since the thread runs on a specific CPU core, it can better utilize the cache resources of that CPU core. This reduces cache misses and cache coherency issues, thereby improving the running efficiency of the critical thread.

[0086] In other embodiments, the electronic device may also optimize the critical thread using other methods, such as increasing its priority. When allocating CPU resources, a higher priority for the critical thread means the electronic device will allocate resources to higher-priority critical threads first, thereby improving the efficiency of the tasks corresponding to the critical thread. Alternatively, the frequency of the CPU core where the critical thread resides can be increased to improve the CPU core's performance, thus improving the critical thread's operating efficiency.

[0087] Optionally, the purpose of the electronic device identifying the critical threads of an application's tasks is to improve the execution efficiency of these critical threads. The electronic device first determines the target thread of the application based on the thread's call stack information or based on both the call stack information and thread characteristic information. The target thread executes the application's tasks through the function call chain indicated by its corresponding call stack information. Then, the target thread is optimized, and the execution efficiency of the optimized business program's tasks is obtained. If the execution efficiency of the application's tasks improves, the target thread is determined to be a critical thread; if the execution efficiency of the application's tasks decreases or remains unchanged, the target thread is determined to be a non-critical thread. The thread characteristic information includes at least one of the following: input / output I / O utilization and processor usage information for each thread.

[0088] For example, an electronic device determines the target thread A corresponding to task B of an application. If optimizing target thread A reduces the time required for task B to run once and improves the running efficiency of task B, then target thread A is determined to be a critical thread of task B. If optimizing target thread A increases the time required for task B to run once and improves the running efficiency of task B, then target thread A is determined to be a non-critical thread of task B.

[0089] In other embodiments, the change in the running efficiency of the optimized critical thread can be determined based on the specific type of the application's task. For example, for an application's data reading task, the running efficiency can be determined by the number of times data is queried per unit time. If the number of data queries per unit time decreases after the electronic device optimizes the target thread of the data reading task, the running efficiency of the read-only task decreases, and the target thread is determined to be a non-critical thread. If the number of data queries per unit time increases after the electronic device optimizes the target thread of the data reading task, the running efficiency of the read-only task improves, and the target thread is determined to be a critical thread.

[0090] Optionally, if the electronic device in S202 is used to determine the critical thread of a task in the application, the electronic device first determines the target thread of the task and optimizes the target thread; if the running efficiency of the optimized task is improved, then the target thread is the critical thread of the task in the application; if the running efficiency of the optimized task remains unchanged or decreases, then the target thread is the critical thread of the task in the application.

[0091] Optionally, if the electronic device in S202 is used to determine the critical threads of multiple tasks of an application, then the electronic device first determines multiple target threads of the multiple tasks and optimizes the multiple target threads; if the running efficiency of one or more tasks of the application is improved after the optimization of the multiple target threads, then the target thread is the critical thread of the corresponding task; if the running efficiency of one or more tasks of the running program remains unchanged or decreases, then the target thread is the non-critical thread of the corresponding task.

[0092] Thread binding to a CPU core refers to binding a thread to a specific CPU core for execution, preventing the thread from switching between different CPU cores. Memory access refers to the process of a thread reading data from or writing data to the CPU core's cache during runtime. The CPU core's cache is also known as the CPU's local memory. When a thread is running on a CPU core, it preferentially accesses that CPU core's cache. If the data or instructions needed by the thread are in the CPU core's cache, the access speed is fast. If the data or instructions needed by the thread are not in the current CPU core's cache, they need to be retrieved from the electronic device's main memory, which typically requires longer latency and higher power consumption. If a thread is not bound to a CPU core, it can run on multiple CPU cores. If a thread frequently accesses the cache of one CPU core while executing an application's task, it can be bound to that CPU core to improve the thread's data access hit rate, reduce data access latency, and thus improve the running efficiency of the corresponding task.

[0093] Optionally, after the electronic device determines the critical thread of the application's task, the method further includes: the electronic device determining the target CPU core corresponding to the critical thread based on the memory access information of the critical thread. The memory access information indicates the size of the cache of the CPU core accessed by the critical thread when executing the corresponding task, and the cache access volume of the target CPU core accessed by the critical thread is greater than the cache access volume of other CPU cores accessed by the critical thread; binding the critical thread to the target CPU core. The processor cores accessed by the critical thread when executing the task include the target processor core. The other processor cores refer to CPU cores in the electronic device other than the target CPU core, or other processor cores can be referred to as non-target CPU cores, i.e., other processor cores are not the target CPU core. Thus, in order to improve the running efficiency of the thread, the thread can be bound to a specific CPU core. When a thread executes a task, it can access the cache of multiple CPU cores. If the cache access volume of one of the CPU cores accessed by the thread when executing the application's task is large, binding the CPU core to the thread can improve the running efficiency of the critical thread after binding the CPU core, thereby improving the running efficiency of the application task corresponding to the critical thread.

[0094] Optionally, before binding a critical thread to a CPU core, the electronic device may first determine a set of CPU cores, which includes at least one CPU core, none of which are bound to a critical thread of the application. Then, a target CPU core is selected from the set, and the critical thread is bound to that target CPU core, where the cache access volume of the target CPU core in the set accessed by the critical thread is greater than the cache access volume of other CPU cores in the set accessed by the critical thread.

[0095] Optionally, each CPU core can be bound to multiple threads, or to multiple threads of multiple applications.

[0096] Optionally, if the application has multiple critical threads, each critical thread has a corresponding target CPU core. The target CPU core corresponding to each critical thread is determined by the electronic device based on the memory access information of the multiple critical threads. The memory access information is used to indicate the size of the cache of the CPU core accessed when the critical thread executes its task. The cache access volume of the target CPU core accessed by the critical thread is greater than the cache access volume of other CPU cores accessed by the critical thread. The CPU cores accessed by the critical thread when executing its task include the target CPU core. Different critical threads correspond to different target CPU cores, thus each critical thread can be bound to its corresponding target CPU core in a one-to-one manner.

[0097] Optionally, if the number of critical threads is N, the CPU cores accessed by each critical thread include first-type processor cores and second-type processor cores, where the first-type processor cores are different from the second-type processor cores, and the cache access volume of each critical thread to the corresponding first-type processor core is greater than the cache access volume to the corresponding second-type processor core; N critical threads correspond to M first-type processor cores, where N is a positive integer greater than 1, M is a positive integer greater than 0, and N > M; the method further includes: binding M critical threads out of the N critical threads to M first-type processor cores one-to-one; if the number of second-type processor cores corresponding to the N critical threads is P, and P ≥ NM, then binding the NM critical threads that are not bound to first-type processor cores to NM second-type processor cores one-to-one; or if P < NM, then binding at least two critical threads out of the NM critical threads that are not bound to first-type processor cores to one first-type processor core or one second-type processor core. Critical threads, as the main entities executing application tasks, are bound to processor cores to prevent them from switching between different CPU cores during execution, thus avoiding impacts on their efficiency. Since critical threads access the cache of the first-type processor cores significantly when executing application tasks, they can be bound one-to-one to these cores to improve data access hit rate, reduce data access latency, and thus improve the efficiency of the corresponding task. If the number of first-type processor cores is less than the number of critical threads in the application tasks, and the sum of the number of first-type and second-type processor cores is greater than the number of critical threads, then multiple critical threads are bound one-to-one to both first-type and second-type processor cores. If the sum of the number of first-type and second-type processor cores is less than the number of critical threads, then at least two critical threads are bound to one first-type or one second-type processor core.

[0098] For example, if the application has 5 critical threads, each corresponding to 4 Type I processor cores, and 1 Type II processor core, then 4 of the 5 critical threads can be bound one-to-one with the 4 Type I processor cores, and the 1 critical thread not bound to a Type I processor core can be bound to one Type II processor core. As another example, if the application has 6 critical threads, each corresponding to 4 Type I processor cores, and 1 Type II processor core, then 4 of the 6 critical threads can be bound one-to-one with 3 Type I processor cores and 1 Type II processor core, and the 2 critical threads not bound to a processor core can be bound to one Type I processor core.

[0099] Optionally, if the sum of the number of first-type processor cores and the number of second-type processor cores of the application is less than the number of critical threads of the application's task, then the time percentage of CPU resources of multiple critical threads is obtained. If the sum of the time percentages of CPU resources of two or more critical threads is less than or equal to 100%, then the two or more critical threads can be bound to the same first-type processor core or the same second-type processor core.

[0100] Optionally, if two or more critical threads are bound to the same processor core, the electronic device may schedule the two or more critical threads according to time-slice scheduling.

[0101] Optionally, the application has N critical threads, where N is a positive integer greater than 1, and the N critical threads correspond to M type I processor cores, where M is a positive integer greater than 0. If N is greater than M, then the M critical threads are bound one-to-one with the M type I processor cores. If the number of type II processor cores is greater than or equal to NM, then each of the NM critical threads that is not bound to a type I processor core is bound to a type II processor core in the Non-Unified Memory Access (NUMA) node to which its corresponding type I processor core belongs. Since the performance of CPU cores within the same NUMA node is similar, critical threads are bound to other processor cores in the NUMA node to which their corresponding type I processor core belongs, in order to improve the running efficiency of that thread.

[0102] If NM out of N critical threads are not bound to a first-type processor core, and the MUMA node to which the first-type processor core belongs does not have a second-type processor core to which the critical thread can be bound, then the critical thread can be bound to a second-type processor core of another NUMA node. Alternatively, at least two of the NM out of N critical threads that are not bound to a first-type processor core can be bound to the same first-type processor core, that is, multiple critical threads are bound to the same processor core (e.g., a first-type processor core or a second-type processor core).

[0103] Optionally, if the application has multiple critical threads, N critical threads correspond to the same first-type processor core, and the N critical threads are used to execute at least two tasks of the application, then the priorities of at least two tasks can be obtained, and then the critical thread corresponding to the task with the highest priority among the N critical threads can be bound to the first-type processor core, and the other critical threads among the N critical threads can be bound to other CPU cores (such as second-type processor cores).

[0104] Optionally, if at least two critical threads are bound to the same CPU core (e.g., a first-type processor core or a second-type processor core), the priorities of the tasks corresponding to the at least two critical threads are obtained, and the priorities of the at least two critical threads in the CPU core are determined based on the priorities of the at least two tasks. For example, if the priority of task A is greater than the priority of task B, then the priority of critical thread C corresponding to task A is greater than the priority of critical thread D corresponding to task B.

[0105] Optionally, the electronic device can pre-train a machine learning model, such as a thread identification model; then the electronic device can input the call stack information of each thread into the thread identification model, and the thread identification model processes the call stack information of each thread to obtain the key threads of the application's task, wherein the thread identification model can identify the key threads among multiple threads of the application through the call stack information of each thread.

[0106] Alternatively, the thread identification model can be a decision tree model, a neural network model, etc.

[0107] Optionally, the electronic device collects a dataset, which may include key threads for each business function of the application and the call stack information of each key thread. The electronic device then preprocesses the dataset and divides it into training, validation, and test sets. Next, the electronic device trains a selected machine learning model (e.g., a neural network model) based on the dataset to obtain a thread identification model. After the thread identification model is trained, it can identify key threads of the application based on the call stack information of each thread. The identified key threads are then optimized to obtain the running efficiency of the optimized application tasks. If the running efficiency improves, the dataset is enriched with key thread-related information, and the thread identification model is trained again based on the enriched dataset. If the running efficiency deteriorates or remains unchanged, the key threads of the application are identified again based on the thread identification model. This process is repeated to improve the accuracy of the thread identification model.

[0108] Optionally, the electronic device can input call stack information and thread characteristic information of each thread into the thread identification model to obtain the critical threads of the application's task, wherein the thread characteristic information includes at least one of thread IO utilization and thread characteristic information, and the thread identification identifies the critical threads among multiple threads of the application based on the call stack information and the thread characteristic information of each thread.

[0109] Please see Figure 3 , Figure 3 This is a schematic diagram of a thread identification device provided in an embodiment of this application. This thread identification device can be deployed in the electronic equipment described in the foregoing embodiments. Figure 3 As shown, the thread identification device includes an acquisition unit and a determination unit.

[0110] The acquisition unit is used to execute S201 in the aforementioned embodiments; the determination unit is used to execute S202 in the aforementioned embodiments.

[0111] Optionally, the acquisition unit is used to acquire the call stack information of each thread of the running application, the call stack information being used to indicate the call chain of the function corresponding to the thread;

[0112] The determining unit is used to determine the key thread of the application's task based on the call stack information. The key thread can execute the application's task through the call chain of the function indicated by the call stack information.

[0113] Optionally, determining the critical thread of the application's task based on the call stack information and thread characteristic information includes:

[0114] The critical threads of the application's task are determined based on the call stack information, thread characteristic information, and the task type of the application or the task. The task type includes compute-intensive and I / O-intensive tasks.

[0115] Optionally, the determining unit is used to determine the key threads of the application's task based on the call stack information and thread characteristic information, wherein the thread characteristic information includes at least one of the input / output I / O utilization of each thread and processor usage information, and the processor usage information includes the proportion of processor resources occupied by the thread during runtime or the time information of the thread being in a running state on the processor.

[0116] Optionally, the determining unit is configured to determine the target thread of the application based on the call stack information, wherein the target thread can execute the application's tasks through the call chain of the functions indicated by the call stack information;

[0117] If the running efficiency of the task improves after the target thread is optimized, then the target thread is determined to be a critical thread.

[0118] Optionally, the determining unit is used to input the call stack information into the thread identification model to obtain the key threads of the application's tasks.

[0119] Optionally, the identification device further includes a binding unit, which is used to determine the target processor core of the key thread based on the memory access information of the key thread. The memory access information is used to indicate the size of the cache of the processor core accessed by the key thread when executing the task. The cache access volume of the target processor core accessed by the key thread is greater than the cache access volume of other processor cores accessed by the key thread. The processor core accessed by the key thread when executing the task includes the target processor core. The key thread is then bound to the target processor core.

[0120] Optionally, the number of key threads is N, and the processor cores accessed by each key thread include first-type processor cores and second-type processor cores. The cache access volume of each key thread to the corresponding first-type processor core is greater than the cache access volume to the corresponding second-type processor core. The N key threads correspond to M first-type processor cores, where N is a positive integer greater than 1, M is a positive integer greater than 0, and N > M. The binding unit is used to: bind M of the N key threads to the M first-type processor cores one-to-one; if the number of second-type processor cores corresponding to the N key threads is P, and P ≥ NM, then bind the NM key threads that are not bound to the first-type processor cores to the NM second-type processor cores one-to-one; or if P < NM, then bind at least two of the NM key threads that are not bound to the first-type processor cores to one first-type processor core or one second-type processor core.

[0121] It should be understood that the above description is merely to help those skilled in the art better understand the embodiments of this application, and is not intended to limit the scope of the embodiments of this application. Based on the examples given above, those skilled in the art can obviously make various equivalent modifications or changes. For example, some steps in the various methods described above may be unnecessary, or new steps may be added. Alternatively, any combination of two or more of the above embodiments may be used. Such modifications, changes, or combinations also fall within the scope of the embodiments of this application.

[0122] It should also be understood that the methods, situations, categories, and classifications of embodiments in this application are for the convenience of description only and should not constitute a special limitation. Various methods, categories, situations, and features in embodiments can be combined without contradiction.

[0123] It should also be understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its task and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0124] It should also be understood that the above description of the embodiments of this application focuses on highlighting the differences between the various embodiments. Any similarities or differences not mentioned can be referred to each other. For the sake of brevity, they will not be repeated here.

[0125] The above combination Figures 1-3 The embodiments of the methods and apparatus provided in this application have been described. The electronic devices provided in the embodiments of this application are described below.

[0126] This embodiment can divide the electronic device into functional units according to the above method. For example, each function can be divided into different task units, or two or more tasks can be integrated into one processing unit. The integrated unit can be implemented in hardware. It should be noted that the unit division in this embodiment is illustrative and only represents one logical task division; other division methods may be used in actual implementation.

[0127] It should be noted that the relevant content of each step involved in the above method embodiments can be referenced from the task description of the corresponding task unit, and will not be repeated here.

[0128] The electronic device provided in this application embodiment is used to execute the thread identification method provided in the above method embodiment, and thus can achieve the same effect as the above implementation method.

[0129] In other embodiments, when using integrated units, the electronic device may include a processing unit, a storage unit, and a communication unit. The processing unit can be used to control and manage the actions of the electronic device. For example, it can be used to support the electronic device in executing steps performed by the processing unit. The storage unit can be used to store program code and data, etc. The communication unit can be used to support communication between the electronic device and other electronic devices.

[0130] The processing unit can be a processor or a controller. It can be a set of various exemplary logic blocks, units, and circuits that implement or execute the descriptions in conjunction with the disclosure of this application. The processor can also be a combination of components that perform computational tasks, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage unit can be a memory. The communication unit can specifically be a radio frequency circuit, a Bluetooth chip, a Wi-Fi chip, or a device that interacts with other electronic devices or electronic devices.

[0131] Based on the same concept, this application also provides an electronic device, see [link to relevant documentation]. Figure 4 , Figure 4 A schematic diagram of the structure of an exemplary electronic device according to this application is shown. Figure 4 The electronic device shown can execute the steps of the thread identification method performed by any of the electronic devices provided in the embodiments of this application.

[0132] The electronic device 400 includes at least one processor 401, a memory 403, and at least one network interface 404.

[0133] Processor 401 may be, for example, a general-purpose CPU, a digital signal processor (DSP), a network processor (NP), a GPU, a neural network processing unit (NPU), a data processing unit (DPU) for deploying decoy files, a microprocessor, or one or more integrated circuits or application-specific integrated circuits (ASICs) used to implement the scheme of this application, a programmable logic device (PLD), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A PLD may be, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute the various logic blocks, modules, and circuits described in connection with the disclosure of this application. A processor may also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0134] Optionally, the electronic device 400 also includes a bus 402. The bus 402 is used to transmit information between the various components of the electronic device 400. The bus 402 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 402 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0135] Memory 403 may be, for example, read-only memory (ROM) or other types of storage devices capable of storing static information and instructions; random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions; electrically erasable programmable read-only memory (EEPROM); compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile optical discs, Blu-ray discs, etc.); magnetic disk storage media or other magnetic storage devices; or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Memory 403 may exist independently and be connected to processor 401 via bus 402. Memory 403 may also be integrated with processor 401.

[0136] Network interface 404 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), or wireless local area network (WLAN). Network interface 404 can include wired network interfaces and wireless network interfaces. Specifically, network interface 404 can be an Ethernet interface, such as Fast Ethernet (FE), Gigabit Ethernet (GE), Asynchronous Transfer Mode (ATM), WLAN, cellular network, or combinations thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In some embodiments of this application, network interface 404 can be used by electronic device 400 to communicate with other devices.

[0137] In specific implementations, as some embodiments, processor 401 may include one or more CPUs. Each of these processors may be a single-core processor or a multi-core processor. Here, "processor" may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0138] In specific implementations, as some embodiments, electronic device 400 may include multiple processors. Each of these processors may be a single-core processor or a multi-core processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0139] In some embodiments, memory 403 is used to store program instructions for executing the present application solution, and processor 401 can execute the program instructions stored in memory 403. That is, electronic device 400 can implement the method provided in the above embodiments through processor 401 and program instructions in memory 403. The program instructions may include one or more software modules. Optionally, processor 401 itself may also store program instructions for executing the present application solution.

[0140] In specific implementation, the processor 401 in the electronic device 400 of this application reads instructions from the memory 403, causing... Figure 4 The electronic device 400 shown is capable of performing all or part of the steps in the thread identification method performed by the electronic device in the above embodiments.

[0141] In the above embodiments, each step of the method is implemented through integrated logic circuits in the hardware of the processor of the electronic device 400 or through software instructions. The steps of the method embodiments disclosed in this application can be directly implemented by the hardware processor, or implemented by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. Since the storage medium is located in memory, the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method embodiments; to avoid repetition, these will not be described in detail here.

[0142] It should be understood that the aforementioned processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors can be microprocessors or any conventional processor. It is worth noting that the processor can be a processor supporting the Advanced Reduced Instruction Set Computing (RISC) machine (ARM) architecture.

[0143] Furthermore, in an alternative embodiment, the memory described above may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may also include non-volatile random access memory. For example, the memory may also store device type information.

[0144] The memory can be volatile or non-volatile, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which serves as an external cache. Many forms of RAM are available by way of example, but not limitation. Examples include static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0145] The electronic device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, so they will not be described again here.

[0146] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the methods described in the above-described method embodiments.

[0147] This application also provides a computer program product that, when run on an electronic device, causes the electronic device to implement the method described in the above-described method embodiments.

[0148] This application provides a chip, including a processor, for calling and executing instructions stored in a memory, causing a communication device with the chip installed to execute the method described in the above-described method embodiments of any electronic device provided in this application.

[0149] This application also provides a chip system including a processor coupled to a memory. The processor executes a computer program stored in the memory to implement the method described in the above-described method embodiments. The chip system may be a single chip or a chip module composed of multiple chips.

[0150] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, or magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0151] Those skilled in the art will understand that implementing all or part of the processes in the above embodiments can be accomplished by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium can include various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0152] The naming or numbering of steps in this application does not mean that the steps in the method flow must be executed in the time / logical order indicated by the naming or numbering. The execution order of the named or numbered process steps can be changed according to the technical purpose to be achieved, as long as the same or similar technical effect can be achieved.

[0153] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0154] In the embodiments provided in this application, it should be understood that the disclosed apparatus / devices and methods can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0155] It should be understood that in the description of this application and the appended claims, the terms "comprising," "including," "having," and any variations thereof are intended to cover a non-exclusive inclusion and mean "including but not limited to," unless otherwise specifically emphasized. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not necessarily limited to those steps or modules that are explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0156] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is used to describe the relationship between the related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.

[0157] Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0158] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0159] Furthermore, in the description of this application and the appended claims, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein; features defined as "first" or "second" may explicitly or implicitly include at least one of those features.

[0160] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0161] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A thread identification method characterized by, The method comprises: obtaining call stack information of each thread of a running application, the call stack information being used to indicate a call chain of functions corresponding to the thread; determining a key thread of a task of the application according to the call stack information, the key thread being capable of executing the task of the application through the call chain of functions indicated by the call stack information.

2. The method of claim 1, wherein, The determining of the key thread of the task of the application according to the call stack information comprises: determining the key thread of the task of the application according to the call stack information and thread characteristic information, wherein the thread characteristic information comprises at least one of input / output (IO) utilization of each thread and processor usage information, and the processor usage information comprises a proportion of processor resources occupied by the thread when running or time information of the thread in a running state on a processor.

3. The method of claim 2, wherein, The determining of the key thread of the task of the application according to the call stack information and thread characteristic information comprises: determining the key thread of the task of the application according to the call stack information, thread characteristic information and task type information, the task type information being used to indicate a task type of the application or a task type of the task of the application, and the task type comprising computation-intensive or IO-intensive.

4. The method according to any one of claims 1 to 3, characterized in that, The determining of the key thread of the task of the application according to the call stack information comprises: determining a target thread of the application according to the call stack information, the target thread being capable of executing a task of the application through the call chain of functions indicated by the call stack information; after the target thread is processed, if running efficiency of the task is improved, determining that the target thread is a key thread of the task of the application.

5. The method according to any one of claims 1 to 4, characterized in that, The determining of the key thread of the task of the application according to the call stack information comprises: inputting the call stack information into a thread identification model to obtain the key thread of the task of the application.

6. The method according to any one of claims 1 to 5, characterized in that, The method further comprises: determining a target processor core corresponding to the key thread according to memory access information of the key thread, the memory access information being used to indicate a size of a cache of a processor core accessed by the key thread when executing the task, a cache access amount of the target processor core accessed by the key thread being greater than cache access amounts of other processor cores accessed by the key thread, and the processor core accessed by the key thread when executing the task comprising the target processor core; binding the key thread with the target processor core.

7. The method according to any one of claims 1 to 5, characterized in that, The number of the key threads is N, and the processor core accessed by each key thread comprises a first type of processor core and a second type of processor core, a cache access amount of the first type of processor core corresponding to each key thread being greater than a cache access amount of the second type of processor core corresponding to each key thread; N key threads correspond to M first type of processor cores, N is a positive integer greater than 1, M is a positive integer greater than 0, and N>M. The method further comprises: binding one-to-one M of the N critical threads with the M first-type processor cores; if the number of the second-type processor cores corresponding to the N critical threads is P, and P≥N-M, then binding one-to-one N-M of the N critical threads which are not bound with the first-type processor cores with N-M of the second-type processor cores; or if P 8. A thread identification apparatus, characterized by comprising: The apparatus comprises units for performing the method of any one of claims 1 to 7.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the method of any one of claims 1 to 7.

10. An electronic device, comprising: comprising: a memory comprising computer readable instructions; a processor in communication with the memory, the processor configured to execute the computer readable instructions to cause the electronic device to perform the method of any one of claims 1-7.

11. A computer program product, characterised in that, The computer program product comprises instructions which, when executed by an electronic device, implement the method of any one of claims 1 to 7.

Images