A multi-representation unified intermediate representation data model and construction method for hardware design
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN ZHISU XINQING TECHNOLOGY CO LTD
- Filing Date
- 2026-03-19
- Publication Date
- 2026-06-26
Smart Images
Figure CN122287503A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic design automation technology, and in particular to a unified intermediate representation data mold for hardware design and a method for its construction. Background Technology
[0002] In the design process of modern integrated circuits and Field-Programmable Gate Arrays (FPGAs) / System-on-Chips (SoCs), engineers need to simultaneously manipulate multiple design representations, such as schematics, Hardware Description Language (HDL) code, Abstract Syntax Trees (ASTs), simulation waveforms, register configuration tables, and design documents. Each of these representations carries a facet of the hardware design semantics, collectively forming the complete semantic space of the design. However, in existing Electronic Design Automation (EDA) toolchains, these representations are typically processed by independent dedicated tools, lacking a structured semantic association mechanism, leading to the following technical problems: Semantic fragmentation between representations: After an engineer modifies any representation, the remaining representations must be manually synchronized, which is inefficient and prone to human error. According to industry surveys, engineers spend more than 30% of their work time on manual synchronization between representations, and about 20% of their design time is spent troubleshooting functional errors caused by inconsistencies in representations.
[0003] AI interaction is inefficient: Existing tools lack structured, multi-dimensional semantic interfaces for artificial intelligence (AI) models. AI can only receive single design representations (such as HDL code) in plain text form and cannot access global semantics. Furthermore, approximately 60%-70% of the tokens in HDL code are syntactic elements (such as keywords, begin / end tags), resulting in an effective utilization rate of less than 30% for the AI context window, severely limiting the coverage and reasoning depth of AI-assisted design.
[0004] Lack of incremental interaction capability: In multi-step AI Agent autonomous design tasks, each step requires reloading the complete design data, causing token consumption to increase linearly with the number of steps, which is not feasible in terms of economic cost and response latency.
[0005] Design verification relies on manual intervention: AI-generated design code lacks an automatic semantic verification mechanism and still requires manual review to confirm functional correctness, making it impossible to achieve automated closed-loop iterative correction.
[0006] Existing technical solutions, such as intermediate representations in compilers (e.g., MLIR / CIRCT), cross-probing in EDA tools, traditional netlists, register description standards (IP-XACT), and graphical hardware description languages (HMRs), all utilize SVG tags to construct graphical hardware description languages. This enables visual drag-and-drop design of circuit components, functional definitions (truth tables / logic expressions / latches, etc.), and real-time visual interaction of graphical structures during simulation. Essentially, these solutions represent a new type of hardware description language and its accompanying design tools, focusing on graphical design input and simulation visualization. Therefore, none of these existing technologies fundamentally solve the aforementioned problems. They are either limited to a unidirectional compilation process, rely on fragile string matching, or only cover a single semantic dimension, failing to provide a unified data infrastructure that can connect all design representations, support bidirectional synchronization, and offer an efficient interface for AI. Summary of the Invention
[0007] To address the aforementioned technical problems, the present invention provides the following three technical solutions: According to a first aspect of this disclosure, the present invention provides a unified intermediate representation data model for multiple representations in hardware design, comprising: A unified representation base class, which is a language-independent unified data structure used to cover all types of hardware design entities, is provided. The unified representation base class includes the following fields: globally unique identifier, entity name, parameter definition, port list, internal node set, relation edge set, submodule instance list, graphical layout information, timing behavior data, and extended metadata.
[0008] The structural relationship graph representation, obtained by instantiating the structural data, is used to abstract the structural semantics of the hardware design into a relationship graph (such as a directed attribute graph) composed of nodes and edges. Nodes represent modules, ports, signals, registers, or logic function entities in the hardware design, while edges represent connections, dependencies, or instantiation relationships between entities, describing "which elements constitute the design" and "how the parts are related."
[0009] The temporal behavior representation, which is instantiated from the temporal data, is used to record the value changes of the node on the time axis as a time-value sequence, describing the behavior of the design during simulation.
[0010] A formal semantic consistency constraint, defined between the structural relationship graph representation and the temporal behavior representation, requires that at any given time point, the value changes of nodes in the temporal behavior representation must conform to the logical dependency function defined by the corresponding relationships in the structural relationship graph representation. This constraint constitutes the fundamental guarantee of design correctness.
[0011] A semantic association architecture is used to establish a bidirectional semantic mapping between various scenario representations oriented towards engineering scenarios and a unified representation base class. The scenario representations include at least two of the following: hardware description language code representation, schematic representation, simulation waveform representation, register table representation, and design document representation. Through this architecture, all scenario representations are associated and synchronized around a unified data core.
[0012] According to a second aspect of this disclosure, the present invention provides a method for constructing a data model based on the above, including an incremental synchronization process, the incremental synchronization process comprising the following steps: Step 1, Record Modification Increment: When any element in the scene representation is modified, capture the change event and generate a change descriptor. The change descriptor includes the change type (an enumeration value for addition, modification, or deletion), the globally unique identifier of the change node, the change content (recording the attribute name, previous value, and subsequent value in key-value pairs), and a logical timestamp (a monotonically increasing integer sequence number).
[0013] Step 2, Unified Representation Synchronization: Locate all elements in other scene representations affected by the change descriptor through cross-representation mapping indexes. Based on the change type and characteristics of the target scene representation, convert the change descriptor into a corresponding unified representation update operation and execute it using predefined change propagation rules.
[0014] Step 3, Synchronize all representations: Execute update operations for each target scene representation and refresh the cross-representation mapping index to complete the incremental propagation of all affected representations.
[0015] According to a third aspect of this disclosure, the present invention provides an artificial intelligence-assisted hardware design method based on the above-described data model, comprising: The multi-dimensional context window construction steps are as follows: Centered on the globally unique identifier of the target semantic node, associated nodes and relation edges are collected according to a configurable neighborhood depth to construct a semantic slice that integrates multiple representation dimensions. These multiple representation dimensions include structural topology dimension, hardware description language code dimension, waveform dimension, logic function dimension, and design document dimension.
[0016] Functional semantic serialization step: Perform syntactic stripping processing on the hardware description language code representation in the semantic slice, remove syntactic placeholder elements that are irrelevant to functional semantics, retain functional semantic information, and generate structured serialized output for artificial intelligence models.
[0017] Incremental Interaction Steps: An incremental interaction protocol is used to implement incremental context transfer in the multi-step workflow of the artificial intelligence model. The incremental interaction protocol includes: a precise slice request message, used to request a multi-dimensional semantic slice centered on a specified semantic node and with a specified neighborhood depth; an incremental difference update message, used to transmit incremental update data containing only the design modification differences; and a semantic state checkpoint message, used to record and restore the semantic state in the multi-step workflow.
[0018] The automated closed-loop verification process involves converting the design scheme generated by the AI model back into the data model. Using the formal semantic consistency constraints, the simulation output behavior of the design scheme is automatically compared with the predefined expected behavior. If the comparison is inconsistent, discrepancy description information is generated and fed back to the AI model to drive design correction. This process is repeated iteratively until consistency is achieved.
[0019] Compared with the prior art, the present invention has the following beneficial effects: This invention establishes a bidirectional semantic mapping between multiple scenario representations and a unified representation base class through a semantic association architecture. It achieves automatic propagation of any modification to any associated representation through change capture, cross-representation mapping index location, and change propagation rule execution in the incremental synchronization process. This eliminates the burden of manual synchronization between multiple representations for engineers, reduces document synchronization time by 20%-50%, and reduces functional errors and troubleshooting time caused by representation inconsistencies by 10%-30%.
[0020] This invention constructs a multi-dimensional context window, using the globally unique identifier of the target semantic node as the center, and collecting associated nodes and relational edges at configurable neighborhood depths to build a multi-dimensional semantic slice that integrates structural topology, HDL code, waveforms, logic functions, design documents, and more. Through a token compression mechanism based on globally unique identifiers for deduplication, when multiple representation dimensions reference the same semantic node, only one copy of the node data is retained, and the globally unique identifier replaces the duplicate content. By only changing the encoding method, the temporal behavior representation only records the time points when signal values change and their corresponding values. Through syntax stripping, keywords, block markers, operators, and format indentation in the HDL code are removed, eliminating syntactic placeholder elements that do not substantially contribute to the functional semantics. This reduces the amount of AI input tokens by 50%-80% compared to traditional multi-file concatenation methods, increases the proportion of effective functional inference tokens from approximately 30% to over 90%, and improves functional design accuracy by 20%-50%, thereby significantly improving the token utilization efficiency and inference accuracy of AI-assisted design.
[0021] 3. Incremental context passing is achieved in multi-step workflows through an incremental interaction protocol, including precise slice request messages, incremental difference update messages, and semantic state checkpoint messages. This protocol reduces cumulative token consumption from an order of magnitude proportional to the product of the number of steps and the total amount of data to an order of magnitude proportional to the sum of the single-step input and the product of the number of steps and the incremental data. The incremental interaction protocol reduces the cumulative token consumption of a 10-step agent workflow from approximately 450,000 to approximately 61,200, a saving of approximately 86%, making end-to-end autonomous hardware design tasks engineering feasible in terms of API call costs and response latency.
[0022] 4. This invention achieves automatic verification and iterative correction of AI design output through an automated closed-loop verification process. This process includes: acquiring the expected temporal behavior representation, generating HDL code from the AI design scheme through a language adapter, driving simulation tools to acquire the actual temporal behavior representation, automatically comparing signal-by-signal and time-step by time, and feeding back difference description information to the AI model to drive design correction. Combined with formal semantic consistency constraints (requiring that at any time point, the value change of nodes in the temporal behavior representation must conform to the logical dependency function defined by the corresponding relationship in the structural relationship graph representation), the AI can autonomously iteratively correct the design logic based on waveform comparison results, forming a closed-loop verification process without human intervention: "AI generation → UIR simulation → waveform comparison → difference feedback → AI correction". Attached Figure Description
[0023] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.
[0024] Figure 1 This is a system architecture diagram of the data model of the present invention.
[0025] Figure 2 This is a schematic diagram illustrating the composition of the unified representation of the data model of this invention.
[0026] Figure 3 This is a schematic diagram illustrating the transformation between the unified representation of the data model of this invention and other main representations.
[0027] Figure 4 for Figure 3 A schematic diagram of an editable waveform rendering graph.
[0028] Figure 5 This is a schematic diagram illustrating the successful consistency check verification of the present invention.
[0029] Figure 6 This is a schematic diagram illustrating a failure of the consistency check verification as described in this invention.
[0030] Figure 7 This is a schematic diagram illustrating the interaction between humans and AI, using the UIR data model of the present invention as a semantically symmetric interface for human-computer collaboration.
[0031] Figure 8 This is a schematic diagram of the incremental modification process under Mode A - Centralized Star Topology.
[0032] Figure 9 This is a schematic diagram of the incremental modification process in the C-main representation driven tree topology pattern.
[0033] Figure 10 This is a schematic diagram of the concurrent conflict detection and resolution process under Mode A - centralized star topology mode. Detailed Implementation
[0034] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Example 1
[0035] Please refer to Figure 1 This technical solution discloses a unified intermediate representation data model for hardware design, consisting of three layers: the bottom layer is the basic tool layer, including various input / output functions, incremental synchronization engines, AI semantic interfaces, etc.; the middle layer is the unified representation core, containing the unified representation base class and its instantiated structural relationship graph representation and temporal behavior representation; the top layer is the scene representation layer, containing various engineering-oriented specific scene representations, such as HDL code, schematics, waveform diagrams, register tables, design documents, etc. Each scene representation is connected to the unified representation core through a configurable semantic association architecture.
[0036] Please refer to Figures 1 to 4 Specifically, the data model includes: A unified representation base class is a language-independent unified data structure used to cover all types of hardware design entities. The unified representation base class contains the following fields: globally unique identifier, entity name, parameter definition, port list, internal node set, relation edge set, submodule instance list, graphical layout information, timing behavior data, and extended metadata. The structural relationship graph representation, which is instantiated from the structural data, is used to abstract the structural semantics of the hardware design into a relationship graph composed of nodes and edges. Temporal behavior representation, which is instantiated from the temporal data, is used to record the value changes of the node on the time axis as a time-value sequence; Formal semantic consistency constraints, defined between the structural graph representation and the temporal behavior representation, require that changes in node values in the temporal behavior representation must conform to the logical dependency function defined by the corresponding relationship in the structural graph representation; and... A semantic association architecture is used to establish a bidirectional semantic mapping between various scenario representations oriented towards engineering scenarios and the unified representation base class. The scenario representation includes at least two of the following: hardware description language code representation, schematic representation, simulation waveform representation, register table representation, and design document representation.
[0037] Furthermore, the unified representation base class has built-in hardware semantic methods, which include at least one of the following: hardware description language code generation method, schematic generation method, waveform generation method, driver source query method, load query method, completeness check method, and consistency check method.
[0038] Please refer to Figure 1 , Figures 8 to 10 Furthermore, the semantic association architecture includes at least one of the following: Mode A - Centralized Star Topology, Mode B - Distributed Mesh Topology, and Mode C - Master Representation-Driven Tree Topology. Specifically, the centralized star topology uses the unified representation base class as the core semantic anchor point, and all scene representations establish a bidirectional mapping with the core semantic anchor point. When any scene representation is modified, the changes are propagated to other scene representations through the core semantic anchor point. The distributed mesh topology establishes a pairwise bidirectional mapping between scene representations. The master representation-driven tree topology designates one scene representation as the master representation, and other scene representations are derived directly or indirectly from the master representation. When a subordinate representation is modified, a reverse transformation is first performed to map the modification to the master representation, and then the master representation generates updates for each subordinate representation in a forward direction.
[0039] Furthermore, the data model also includes a scene representation input function, which is used to convert scene representation data from different sources into instances of the unified representation base class, including at least two of the following: Hardware description language code is converted into a unified representation function, which is used to parse hardware description language source code through a pluggable language adapter, extract at least one structured semantic information from module hierarchy, port declaration, signal definition, logic function and connection relationship, and generate an instance of the unified representation base class. The language adapter supports any hardware description language by implementing a standardized interface. A logic block diagram is converted into a unified representation function, which is used to parse graphical schematic data, extract at least one graphical semantic information from module nodes, ports and connection relationships, and map it to an instance of the unified representation base class; Waveform files or timing diagrams are converted into unified representation functions, used to parse simulation waveform format files or user-described timing requirements, extract timing behavior information in time-value sequence form, and populate the timing data fields in the unified representation base class; and... Document or table conversion functions are used to parse register configuration tables, interrupt tables, connection tables, or design specification documents, extract structured semantic information, and supplement it to the extended metadata or relational edge fields of the unified representation base class.
[0040] Specifically, the hardware description language code is converted into a unified representation function through a pluggable language adapter. Each adapter needs to implement a standardized interface, including: the parse method for lexical analysis and syntax analysis to generate an AST; extract_hierarchy to extract the module hierarchy; extract_ports_signals to extract port and signal declarations; extract_connections to extract instantiation and connection relationships between modules; and extract_logic to extract logical functions described by always blocks, assign statements, etc., and convert them into relational edge attributes of the unified intermediate representation UIR. Finally, this information is filled into the nodes, edges, ports, and other fields of the unified intermediate representation UIR instance.
[0041] The logic block diagram is converted into a unified representation function. The graphical schematic data (such as Draw.io XML and open-source JSON diagram format) is parsed, and the graphical nodes representing modules and the graphical edges representing connections are identified. For each graphical node, its name, type, and port label are extracted to generate the corresponding UIR node, and the graphical layout information is recorded in the layout field. For each graphical edge, the ports of its source node and target node are identified, and the relationship edge of the unified intermediate representation UIR is generated.
[0042] Waveform files or timing diagrams are converted into unified representation functions. Simulation waveform files such as VCD and FSDB are parsed, and the value sequence of each signal changing over time is extracted. The identifier of each signal is mapped to the globally unique identifier UID of the corresponding node in the unified intermediate representation UIR. The time-value sequence is stored in the waveform_data field of the unified intermediate representation UIR instance in a change-only encoding format. For timing requirements described by users in a visual manner, the waveforms they draw are parsed and converted into timing behavior representations.
[0043] Documents or tables are converted into unified representation functions, parsing register configuration tables (Excel / CSV / IP-XACT / SystemRDL), interrupt tables, DMA connection tables, PAD tables, design specification documents, etc. For structured tables, rows and columns are parsed to identify register names, address offsets, bit field definitions, reset values, etc., generating corresponding register nodes and connecting them to bus interface nodes through relational edges. For unstructured design documents, natural language processing technology is used to help extract key information and store it in the metadata field.
[0044] Furthermore, the data model also includes a scene representation output function, which is used to convert instances of the unified representation base class into different forms of scene representations, including at least two of the following: A unified representation to hardware description language code function is used to call the target language adapter to serialize the nodes and relation edges in the structural relationship graph representation into the target hardware description language code; A unified representation to logic block diagram function is used to map the nodes and relational edges into graphical schematic data, which can be exported to scalable vector graphics format or structured graph data format. A unified representation-to-editable timing graph function is provided to convert the timing behavior representation into interactively editable waveform data, and supports writing edits back to the timing data fields and triggering consistency checks; and, Unified representation to register or table functions are used to export register nodes and address mappings into register configuration tables in standard register description format or table format.
[0045] Specifically, the unified representation is converted into hardware description language code functions through a target language adapter. The adapter traverses the nodes and edges of the unified intermediate representation (UIR) instance. For each module node, a module / endmodule framework is generated; for each port node, a port declaration is generated; for each submodule instance node and its corresponding instantiation edge, a module instantiation statement is generated; and for edges describing logic functions, the corresponding assign statement or always procedure block is generated based on its logic_function attribute.
[0046] The function that converts a unified representation to a logic block diagram reads the layout field of the unified intermediate representation (UIR) instance. If it contains pre-stored layout information, it uses it directly; otherwise, it calls the automatic layout algorithm to calculate the node positions, selects the corresponding graphic symbol according to the node type, and draws the connection lines according to the relationship edges to generate a Scalable Vector Graphics (SVG) file or interactive canvas data.
[0047] The Unified Representation to Editable Timing Diagram function reads the time-value sequence of each signal node from the waveform_data field, plots the waveform of high and low level changes, and generates an interactive interface that allows engineers to modify signal edges or level values by dragging and dropping with the mouse. After the engineer completes the modification, the function captures these modifications and calls the incremental synchronization engine to write the modifications back to the UIR instance in the form of a change descriptor, automatically triggering a consistency check.
[0048] The unified representation to register or table function traverses all nodes marked "register" or "register bit field" and their associated edges in the unified intermediate representation UIR instance, extracts information such as address mapping, bit width, attributes, reset value, and description, and outputs it as an IP-XACT XML file, a SystemRDL file, or a table in Excel / CSV format.
[0049] In this embodiment, based on the two fundamental representations of structural relationship graph representation and temporal behavior representation, the design semantics can be further presented through various specific representation forms oriented towards engineering scenarios (such as...). Figure 2 As shown), including but not limited to: graphical schematics (as one of the various scenario representations of UIR, semantic mapping is performed through structured data fields of a unified representation base class, rather than by defining a new graphical hardware description language), abstract syntax trees (AST), HDL text, simulation waveforms, hierarchical tree, structured tables (register / address mapping / interrupt table / DMA link table / PAD table, etc.), and design documents. In this technical solution, the above-mentioned specific representations for engineering scenarios are collectively referred to as "scenario representations". Example 2
[0050] Please refer to Figures 1 to 10 This technical solution discloses a method for constructing a unified intermediate representation data model for hardware-oriented design, which includes an incremental synchronization process. The incremental synchronization process includes the following steps: Step 1, record the modification increment: When any element in the scene representation is modified, capture the change event and generate a change descriptor. The change descriptor contains the change type, the globally unique identifier of the change node, the change content, and the logical timestamp. The change type is an enumeration value of addition, modification, or deletion. The change content records the attribute name, previous value, and next value in key-value pairs. The logical timestamp is a monotonically increasing integer sequence number. Step 2, Unified Representation Synchronization: Locate all elements in other scene representations affected by the change descriptor through cross-representation mapping index; Based on the change type and characteristics of the target scene representation, convert the change descriptor into the corresponding unified representation update operation and execute it through predefined change propagation rules; Step 3, Synchronize all representations: Execute update operations for each target scene representation and refresh the cross-representation mapping index to complete the incremental propagation of all affected representations.
[0051] Furthermore, the cross-representation mapping index adopts a two-level index structure, including a hash table for constant time complexity queries and an ordered tree index for logarithmic time complexity range queries. The underlying implementation of the cross-representation mapping index adopts one of the following methods: in-memory hash table method, graph database persistent storage method, relational database storage method, or distributed caching method.
[0052] Furthermore, the change propagation rules include: New propagation rules: When a new node or relation edge is added, corresponding semantic elements are created in the representation of each target scenario based on the type and attributes of the new element; Modify propagation rules: When modifying the attributes of nodes or relation edges, selectively update the affected semantic elements in the representation of each target scene based on the type of attribute being modified; Deletion propagation rule: When a node or relation edge is deleted, the corresponding semantic element is removed in each target scene representation, and the dangling references generated by the deletion are processed in a cascade manner.
[0053] Furthermore, the incremental synchronization process also includes a concurrent conflict detection and resolution step, which includes at least one of the following conflict resolution strategies: Finally, the write priority strategy is to compare the logical timestamps of concurrent change descriptors and use the newer timestamp as the basis for modification. Operation transformation strategy: Perform semantic transformation on concurrent operations so that all replicas eventually converge to a consistent state; Conflict-free replication data type strategy: Model node attributes as last-written priority registers and relationship edge sets as observation-removal sets to achieve automatic semantic convergence of distributed multi-replicas.
[0054] Furthermore, depending on the different patterns of the semantic association architecture, the incremental synchronization process adopts one of the following methods: In Mode A - Centralized Star Topology Mode, changes are synchronized to the core semantic anchor point, and then propagated from the core anchor point to all scene representations; In Mode B - Distributed Mesh Topology Mode, pairwise synchronization is performed directly between the representations of each scenario; In the C-mode master representation driven tree topology mode, the change increment of non-master representations is recorded, the change is reversed to the master representation, the corresponding unified representation base class instance in the master representation is modified, and the incremental update of each subordinate representation is generated from the master representation in the forward direction.
[0055] Please refer to Figure 8 Here is an example of the three-step propagation process of the incremental synchronization engine in the centralized star topology mode A: Step 1, record the modification increment on the modified representation (such as representation 3); Step 2, synchronize the change to the central unified representation; Step 3, propagate the update from the unified representation to all other representations to complete the synchronization of all representations.
[0056] Please refer to Figure 9 Here is a four-step propagation process of the incremental synchronization engine under pattern C: Step 1, record the incremental modification of non-master representations (such as representation 7); Step 2, reverse the transmission of the changed parameters to the master representation (unified representation); Step 3, modify the unified representation; Step 4, generate updates for each slave representation from the unified representation.
[0057] Please refer to Figure 10 Here is the conflict detection and resolution process when multiple representations (such as representation 7 and representation 5) are concurrently modified under enumeration mode A: Step 1, record the incremental changes of multiple concurrent modifications and mark the conflict nodes (identified by mesh filling); Step 2, determine the conflict attribution according to the configured conflict resolution strategy (LWW / OT / CRDT); Step 3, propagate the update to all representations with the consistent state after conflict resolution.
[0058] It should be noted that the construction of the data model includes an initial data model construction step. This initial step involves calling a transfer function to convert external data into an internal format, which is a standard operation in the field of data modeling and will not be elaborated upon here. The innovation of this embodiment lies in the structure of the converted data model and how to maintain the synchronous updating of multiple representations incrementally.
[0059] Through the above embodiments, a bidirectional semantic mapping between multiple scenario representations and a unified representation base class is established through a semantic association architecture. By capturing changes, locating cross-representation mapping indexes, and executing change propagation rules in the incremental synchronization process, the automatic propagation of any representation modification to all related representations is achieved, which helps to eliminate the operational burden of manual synchronization between multiple representations for engineers.
[0060] It should be noted that the incremental synchronization engine, as the core functional entity for executing the incremental synchronization process, together with the unified representation base class and cross-representation mapping index, constitutes the dynamic maintenance mechanism of the data model. It is responsible for capturing changes, locating their impact, and propagating updates to ensure semantic consistency among multiple representations. Example 3
[0061] Please refer to Figures 1 to 10 This technical solution discloses an AI-assisted hardware design method based on the aforementioned multi-representation unified intermediate representation data model for hardware design, which includes the following steps: Multidimensional context window construction steps: Centered on the globally unique identifier of the target semantic node, collect associated nodes and relation edges according to the configurable neighborhood depth, and construct a semantic slice that integrates multiple representation dimensions, including structural topology dimension, hardware description language code dimension, waveform dimension, logic function dimension and design document dimension. Functional semantic serialization step: Perform syntactic stripping processing on the hardware description language code representation in the semantic slice, remove syntactic placeholder elements that are irrelevant to functional semantics, retain functional semantic information, and generate structured serialized output for artificial intelligence models; Incremental interaction steps: An incremental interaction protocol is used to realize incremental context transmission in the multi-step workflow of the artificial intelligence model. The incremental interaction protocol includes: a precise slice request message, used to request a multi-dimensional semantic slice centered on a specified semantic node and with a specified neighborhood depth; an incremental difference update message, used to transmit incremental update data containing only the design modification difference part; and a semantic state checkpoint message, used to record and restore the semantic state in the multi-step workflow.
[0062] The automated closed-loop verification process involves converting the design scheme generated by the AI model back into the data model. Using the formal semantic consistency constraints, the simulation output behavior of the design scheme is automatically compared with the predefined expected behavior. If the comparison is inconsistent, discrepancy description information is generated and fed back to the AI model to drive design correction. This process is repeated iteratively until the comparison is consistent. Specifically, the discrepancy description information includes at least the mismatched signal identifier, time point, expected value, and actual value.
[0063] Furthermore, in the multi-dimensional context window construction step, a token compression mechanism based on deduplication using globally unique identifiers is adopted. When multiple representation dimensions reference the same semantic node, only one copy of the node data is retained and the duplicate content is replaced by a globally unique identifier.
[0064] Furthermore, in the multi-dimensional context window construction step, the temporal behavior representation adopts a change-only encoding method, which only records the time points when the signal value changes and the corresponding values, omitting the time intervals that remain unchanged.
[0065] Furthermore, the functional semantic serialization step also includes syntactic stripping processing to remove syntactic placeholder elements from the hardware description speech code. These syntactic placeholder elements include keywords, block markers, operators, and parts of format indentation in the hardware description language that do not substantially contribute to the functional semantics.
[0066] Furthermore, the output format of the functional semantic serialization step adopts one of the following formats: JSON-Graph, Protocol Buffers, GraphQL interface, or a custom compact text format.
[0067] Specifically, the automatic closed-loop verification step includes: Step 1: Obtain the predefined expected behavior output waveform stored in the data model in the form of a time-series behavior representation, and parse it into a time-series behavior representation format as the expected time-series behavior representation; Step two: Apply the design scheme generated by the artificial intelligence model to the data model, and generate hardware description language code through a language adapter; Step 3: Drive the simulation tool to perform simulation on the hardware description language code, obtain the simulation output waveform file, parse it into a timing behavior representation format, and use it as the actual timing behavior representation; Step four: Perform automatic comparison of the actual temporal behavior representation and the expected temporal behavior representation on a signal-by-signal and time-by-time basis; Step 5: If the comparison results are consistent, the iteration is complete and the final design is output; if the comparison results are inconsistent, difference description information is generated, and the difference description information along with the relevant structural context is automatically fed back to the artificial intelligence model to drive the artificial intelligence model to perform design correction, and return to step 2 to execute the next round of iteration, forming a closed-loop verification process without human intervention.
[0068] Furthermore, in the automatic closed-loop verification step, the automatic comparison employs at least one of the following waveform comparison strategies: A complete waveform sequence precise comparison strategy is employed, which performs precise matching of the values of all signals at each simulation time step; A key timing constraint point sampling and comparison strategy involves sampling and comparing signal values at predefined key timing constraint time points; and... The coverage-guided stochastic simulation strategy automatically generates random excitation signals, with the functional coverage reaching a preset threshold as the convergence criterion.
[0069] Furthermore, in the incremental interaction step, the cooperation between the precise slice request message and the incremental difference update message reduces the cumulative token consumption of the multi-step workflow from an order of magnitude proportional to the product of the number of steps and the single-step input to an order of magnitude proportional to the sum of the single-step input plus the product of the number of steps and the incremental data volume.
[0070] In this embodiment, an automated closed-loop verification process is used to automatically verify and iteratively correct the AI design output. This process includes: obtaining the expected temporal behavior representation; generating HDL code from the AI design scheme through a language adapter; driving simulation tools to obtain the actual temporal behavior representation; automatic comparison of each signal and time step; and feeding back the difference description information to the AI model to drive design correction. Combined with formal semantic consistency constraints (requiring that at any time point, the value change of nodes in the temporal behavior representation must conform to the logical dependency function defined by the corresponding relationship in the structural relationship graph representation), the AI can autonomously iteratively correct the design logic based on the waveform comparison results, forming a closed-loop verification process without human intervention: "AI generation → UIR simulation → waveform comparison → difference feedback → AI correction".
[0071] Please refer to Figures 3 to 7 This is a concrete example of a formal consistency constraint between the structural relationship diagram representation and the temporal behavior representation. Engineers describe the port list and the temporal behavior (expected input / output waveforms) of each port according to protocol specifications or design requirements. Before the internal logic is completed, this information, along with the incomplete unified representation, can be passed to the AI model. The AI supplements the internal nodes and logical relationships and returns a complete unified representation. The system generates HDL code, executes the simulation using an EDA simulation tool, and outputs a VCD format waveform file. After parsing the VCD waveform into a temporal behavior representation, it is compared with the expected output waveform described in the design requirements. If they are inconsistent, the difference information and related structural context are automatically fed back to the AI model, triggering iterative modification. If they are consistent, the iteration is complete, achieving a closed-loop iterative verification of AI without human intervention. Figure 5 The consistency test was passed through an example using the D3 module, meaning that the values of all signals in each cycle completely correspond to the logical dependency functions in the structural relationship. Figure 6 The example using the D3 module demonstrates that the consistency check fails, meaning that the D1 and D2 signals pass the comparison but the out signal fails. This indicates that there are problems with the dependency signals and dependencies in the structural relationship representation or with the temporal behavior representation.
[0072] By constructing a multi-dimensional context window, centered on the globally unique identifier of the target semantic node, associated nodes and relational edges are collected at configurable neighborhood depths to build multi-dimensional semantic slices that integrate structural topology, HDL code, waveforms, logic functions, and design documents. Through a token compression mechanism based on globally unique identifiers for deduplication, when multiple representation dimensions reference the same semantic node, only one copy of the node data is retained, and duplicate content is replaced by a globally unique identifier reference. By only changing the encoding method, the temporal behavior representation only records the time points when signal values change and their corresponding values. Through syntax stripping, keywords, block markers, operators, and format indentation in the HDL code—syntactic placeholders that do not substantially contribute to functional semantics—are removed. This reduces the amount of AI input tokens by 50%-80% compared to traditional multi-file concatenation methods, increases the proportion of effective functional inference tokens from approximately 30% to over 90%, and improves functional design accuracy by 20%-50%, thereby significantly improving the token utilization efficiency and inference accuracy of AI-assisted design.
[0073] The parts not described in detail in this technical solution specification are obvious to those skilled in the art and can be supplemented and improved based on existing technical knowledge. At the same time, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the present invention. For those skilled in the art, several improvements and modifications can be made without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A unified intermediate representation data model for multiple representations in hardware design, characterized in that, include: A unified representation base class is a language-independent unified data structure used to cover all types of hardware design entities. The unified representation base class contains the following fields: globally unique identifier, entity name, parameter definition, port list, internal node set, relation edge set, submodule instance list, graphical layout information, timing behavior data, and extended metadata. The structural relationship graph representation, which is instantiated from the structural data, is used to abstract the structural semantics of the hardware design into a relationship graph composed of nodes and edges. Temporal behavior representation, which is instantiated from the temporal data, is used to record the value changes of the node on the time axis as a time-value sequence; Formal semantic consistency constraints are defined between the structural relationship graph representation and the temporal behavior representation, requiring that the value changes of nodes in the temporal behavior representation must conform to the logical dependency function defined by the corresponding relationship in the structural relationship graph representation. as well as, A semantic association architecture is used to establish a bidirectional semantic mapping between various scenario representations oriented towards engineering scenarios and the unified representation base class. The scenario representation includes at least two of the following: hardware description language code representation, schematic representation, simulation waveform representation, register table representation, and design document representation.
2. The multi-representation unified intermediate representation data model for hardware design according to claim 1, characterized in that, The unified representation base class has built-in hardware semantic methods, which include at least one of the following: Methods for generating hardware description language code, schematic diagrams, waveforms, driver source lookup, load lookup, completeness checks, and consistency checks.
3. The multi-representation unified intermediate representation data model for hardware design according to claim 1, characterized in that, The semantic association architecture includes at least one of the following patterns: A centralized star topology pattern is used, with the unified representation base class as the core semantic anchor point. All scene representations are mapped bidirectionally to the core semantic anchor point. When any scene representation is modified, the changes are propagated to other scene representations through the core semantic anchor point. A distributed mesh topology pattern, wherein the distributed mesh topology pattern establishes a direct pairwise bidirectional mapping between the various scene representations; The main representation drives the tree topology pattern, which specifies a scene representation as the main representation, and other scene representations are derived directly or indirectly from the main representation. When modifying a subordinate representation, a reverse transformation is first performed to map the modification to the main representation, and then the main representation generates updates for each subordinate representation in a forward manner.
4. The multi-representation unified intermediate representation data model for hardware design according to claim 1, characterized in that, It also includes a scene representation input function, which is used to convert scene representation data from different sources into instances of the unified representation base class, including at least two of the following: Hardware description language code is converted into a unified representation function, which is used to parse hardware description language source code through a pluggable language adapter, extract at least one structured semantic information from module hierarchy, port declaration, signal definition, logic function and connection relationship, and generate an instance of the unified representation base class. The language adapter supports any hardware description language by implementing a standardized interface. A logic block diagram is converted into a unified representation function, which is used to parse graphical schematic data, extract at least one graphical semantic information from module nodes, ports and connection relationships, and map it to an instance of the unified representation base class; Waveform files or timing diagrams are converted into unified representation functions, which are used to parse simulation waveform format files or user-described timing requirements, extract timing behavior information in the form of time-value sequences, and fill the timing data fields in the unified representation base class. as well as, Document or table conversion functions are used to parse register configuration tables, interrupt tables, connection tables, or design specification documents, extract structured semantic information, and supplement it to the extended metadata or relational edge fields of the unified representation base class.
5. The multi-representation unified intermediate representation data model for hardware design according to claim 1, characterized in that, It also includes a scene representation output function, which is used to convert instances of the unified representation base class into different forms of scene representations, including at least two of the following: A unified representation to hardware description language code function is used to call the target language adapter to serialize the nodes and relation edges in the structural relationship graph representation into the target hardware description language code; A unified representation to logic block diagram function is used to map the nodes and relational edges into graphical schematic data, which can be exported to scalable vector graphics format or structured graph data format. A unified representation to editable timing diagram function is used to convert the timing behavior representation into interactively editable waveform data, and supports writing the edited changes back to the timing data field and triggering consistency verification; as well as, Unified representation to register or table functions are used to export register nodes and address mappings into register configuration tables in standard register description format or table format.
6. A method for constructing a unified intermediate representation data model for hardware design based on any one of claims 1 to 5, characterized in that, This includes an incremental synchronization process, which comprises the following steps: Step 1, record the modification increment: When any element in the scene representation is modified, capture the change event and generate a change descriptor. The change descriptor contains the change type, the globally unique identifier of the change node, the change content, and the logical timestamp. The change type is an enumeration value of addition, modification, or deletion. The change content records the attribute name, previous value, and next value in key-value pairs. The logical timestamp is a monotonically increasing integer sequence number. Step 2, Unified Representation Synchronization: Locate all elements in other scene representations affected by the change descriptor through cross-representation mapping index; Based on the change type and characteristics of the target scene representation, convert the change descriptor into the corresponding unified representation update operation and execute it through predefined change propagation rules; Step 3, Synchronize all representations: Execute update operations for each target scene representation and refresh the cross-representation mapping index to complete the incremental propagation of all affected representations.
7. The method for constructing a unified intermediate representation data model for hardware design according to claim 6, characterized in that, The cross-representation mapping index adopts a two-level index structure, including a hash table for constant time complexity queries and an ordered tree index for logarithmic time complexity range queries. The underlying implementation of the cross-representation mapping index adopts one of the following methods: in-memory hash table method, graph database persistent storage method, relational database storage method, or distributed caching method.
8. The method for constructing a unified intermediate representation data model for hardware design according to claim 6, characterized in that, The change propagation rules include: New propagation rules: When a new node or relation edge is added, corresponding semantic elements are created in the representation of each target scenario based on the type and attributes of the new element; Modify propagation rules: When modifying the attributes of nodes or relation edges, selectively update the affected semantic elements in the representation of each target scene based on the type of attribute being modified; Deletion propagation rule: When a node or relation edge is deleted, the corresponding semantic element is removed in each target scene representation, and the dangling references generated by the deletion are processed in a cascade manner.
9. The method for constructing a unified intermediate representation data model for hardware design according to claim 6, characterized in that, The incremental synchronization process further includes a concurrent conflict detection and resolution step, which includes at least one of the following conflict resolution strategies: Finally, the write priority strategy is to compare the logical timestamps of concurrent change descriptors and use the newer timestamp as the basis for modification. Operation transformation strategy: Perform semantic transformation on concurrent operations so that all replicas eventually converge to a consistent state; Conflict-free replication data type strategy: Model node attributes as last-written priority registers and relationship edge sets as observation-removal sets to achieve automatic semantic convergence of distributed multi-replicas.
10. The method for constructing a unified intermediate representation data model for hardware design according to claim 6, characterized in that, Depending on the different patterns of the semantic association architecture, the incremental synchronization process adopts one of the following methods: In a centralized star topology model, changes are synchronized to the core semantic anchor point, and then propagated from the core anchor point to all scene representations; In the distributed mesh topology mode, direct pairwise synchronization is performed between the scene representations; In the master representation-driven tree topology mode, the incremental changes of non-master representations are recorded, the changes are reversed and propagated to the master representation, the corresponding unified representation base class instance in the master representation is modified, and the incremental updates of each subordinate representation are generated from the master representation in the forward direction.
11. An AI-aided hardware design method based on the multi-representation unified intermediate representation data model for hardware design as described in any one of claims 1 to 5, characterized in that, include: Multidimensional context window construction steps: Centered on the globally unique identifier of the target semantic node, collect associated nodes and relation edges according to the configurable neighborhood depth, and construct a semantic slice that integrates multiple representation dimensions, including structural topology dimension, hardware description language code dimension, waveform dimension, logic function dimension and design document dimension. Functional semantic serialization step: Perform syntactic stripping processing on the hardware description language code representation in the semantic slice, remove syntactic placeholder elements that are irrelevant to functional semantics, retain functional semantic information, and generate structured serialized output for artificial intelligence models; Incremental interaction steps: An incremental interaction protocol is used to realize incremental context transmission in the multi-step workflow of the artificial intelligence model. The incremental interaction protocol includes: a precise slice request message, used to request a multi-dimensional semantic slice centered on a specified semantic node and with a specified neighborhood depth; an incremental difference update message, used to transmit incremental update data containing only the design modification difference part; and a semantic state checkpoint message, used to record and restore the semantic state in the multi-step workflow. Automatic closed-loop verification steps: The design scheme generated by the artificial intelligence model is converted back to the data model. Through the formal semantic consistency constraints, the simulation output behavior of the design scheme is automatically compared with the predefined expected behavior. If the comparison is inconsistent, difference description information is generated and fed back to the artificial intelligence model to drive design correction. The process is repeated iteratively until the comparison is consistent.
12. The artificial intelligence-assisted hardware design method according to claim 11, characterized in that, In the multidimensional context window construction step, a token compression mechanism based on global unique identifier deduplication is adopted. When multiple representation dimensions reference the same semantic node, only one copy of the node data is retained and the duplicate content is replaced by a globally unique identifier.
13. The artificial intelligence-assisted hardware design method according to claim 11, characterized in that, In the multidimensional context window construction step, the temporal behavior representation adopts a change-only encoding method, which only records the time points when the signal value changes and the corresponding values, omitting the time intervals that remain unchanged.
14. The artificial intelligence-assisted hardware design method according to claim 11, characterized in that, The functional semantic serialization step further includes syntactic stripping, which removes syntactic placeholders from the hardware description speech code. These syntactic placeholders include keywords, block markers, operators, and parts of format indentation in the hardware description language that do not substantially contribute to the functional semantics.
15. The artificial intelligence-assisted hardware design method according to claim 11, characterized in that, The output format of the functional semantic serialization step can be one of the following: JSON-Graph, Protocol Buffers, GraphQL interface, or a custom compact text format.
16. The artificial intelligence-assisted hardware design method according to claim 11, characterized in that, The automatic closed-loop verification steps specifically include: Step 1: Obtain the predefined expected behavior output waveform stored in the data model in the form of a time-series behavior representation, and parse it into a time-series behavior representation format as the expected time-series behavior representation; Step two: Apply the design scheme generated by the artificial intelligence model to the data model, and generate hardware description language code through a language adapter; Step 3: Drive the simulation tool to perform simulation on the hardware description language code, obtain the simulation output waveform file, parse it into a timing behavior representation format, and use it as the actual timing behavior representation; Step four: Perform automatic comparison of the actual temporal behavior representation and the expected temporal behavior representation on a signal-by-signal and time-by-time basis; Step 5: If the comparison results are consistent, the iteration is complete and the final design is output; if the comparison results are inconsistent, difference description information is generated, and the difference description information along with the relevant structural context is automatically fed back to the artificial intelligence model to drive the artificial intelligence model to perform design correction, and return to step 2 to execute the next round of iteration, forming a closed-loop verification process without human intervention.
17. The artificial intelligence-assisted hardware design method according to claim 11, characterized in that, In the automatic closed-loop verification step, the automatic comparison employs at least one of the following waveform comparison strategies: A complete waveform sequence precise comparison strategy is employed, which performs precise matching of the values of all signals at each simulation time step; The key timing constraint point sampling and comparison strategy samples and compares the signal values at predefined key timing constraint time points. as well as, The coverage-guided stochastic simulation strategy automatically generates random excitation signals, with the functional coverage reaching a preset threshold as the convergence criterion.
18. The artificial intelligence-assisted hardware design method according to claim 17, characterized in that, The difference description information includes at least the mismatched signal identifier, time point, expected value, and actual value.