Chip metal density verification method, device and product based on image features

Abstract

This application provides a chip metal density verification method, device, and product based on image features. The method includes: generating a device netlist and gate-level netlist for the chip based on a chip layout file; drawing an image to generate single-layer distribution maps of each layer of the chip; then, for each single-layer distribution map of the chip, determining the effective structure and auxiliary structure of that layer by identifying image features; then determining the regional metal density of that region by calculating the ratio between the effective structure area and the target region area; and finally, obtaining the single-layer metal density of the chip based on the calculated regional metal density of each target region, thus completing the chip metal density verification; this solves the problem of inaccurate results for verifying the metal density of each layer of the chip in existing technologies.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip metal density verification method, device and product based on image features. Background Technology

[0002] As the integration level of integrated circuits increases, the density of metal lines in the later stages of chip design manufacturing becomes increasingly dense, leading to uneven metal density distribution. Furthermore, the process weaknesses caused by uneven metal density distribution can lead to failures in subsequent tests.

[0003] In existing technologies, the metal density of a chip is often verified and determined in the later stages of chip design to ensure a uniform distribution of metal density in different areas of the chip, thereby improving the reliability of chip testing and ultimately increasing the chip production yield.

[0004] However, in the existing technology, the method of verifying and determining the metal density of each layer of the chip is to extract and calculate the entire graphic structure diagram of the chip's device netlist, which leads to the problem of inaccurate verification results of the metal density of each layer of the chip. Summary of the Invention

[0005] This application provides a chip metal density verification method, device, and product based on image features to solve the problem of inaccurate results for verifying the metal density of each layer of a chip.

[0006] In a first aspect, embodiments of this application provide a chip metal density verification method based on image features, comprising: acquiring a layout file of a chip; generating a device netlist of the chip based on the layout file; generating a gate-level netlist of the chip based on the layout file; performing image rendering based on the device netlist and the gate-level netlist to generate single-layer distribution maps of each layer of the chip; wherein, the single-layer distribution map includes a graphic structure map and at least one set of connection point structure maps; for each single-layer distribution map of the chip, identifying image features, classifying the graphic structure map through the at least one set of connection point structure maps to obtain one or more effective structure maps and one or more auxiliary structure maps. For the single-layer distribution map, the regions corresponding to the multiple effective structure maps are grouped according to the one or more auxiliary structure maps to obtain at least two target computing regions; wherein, the target computing region includes at least one of the effective structure maps; for each target computing region, the area of ​​all effective structure maps in the target computing region is calculated according to the device netlist to obtain the effective structure area; the area of ​​the target computing region is calculated to obtain the target region area; the ratio of the effective structure area to the target region area is calculated to obtain the region metal density; based on the region metal density corresponding to each target computing region, the single-layer metal density of the chip is obtained.

[0007] In one possible implementation, the step of grouping the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two target calculation regions includes: S21, grouping the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two initial division regions; S22, calculating the area of ​​each initial division region to obtain the area of ​​the initial division region; S23, determining the relationship between the area of ​​the initial division region and a preset area threshold, including: S231, if the area of ​​the initial division region is less than or equal to the preset area threshold, then the corresponding... S232: If the area of ​​the initial partitioned region is greater than the preset area threshold, and there is only one valid structure graph in the corresponding initial partitioned region, then the corresponding initial partitioned region is determined as a target calculation region; S233: If the area of ​​the initial partitioned region is greater than the preset area threshold, and there are two or more valid structure graphs in the corresponding initial partitioned region, then the corresponding initial partitioned region is divided to obtain two or more new initial partitioned regions, and the corresponding area of ​​the initial partitioned region is obtained; S24: Repeat step S23 until all target calculation regions are confirmed.

[0008] In one possible implementation, the step of dividing the initial partitioned region into two or more new initial partitioned regions and obtaining the area of ​​the corresponding initial partitioned region if the area of ​​the initial partitioned region is greater than the preset area threshold and there are two or more valid structural diagrams in the corresponding initial partitioned region includes: calculating the multiple relationship between the area of ​​the initial partitioned region and the preset area threshold if the area of ​​the initial partitioned region is greater than the preset area threshold and there are two or more valid structural diagrams in the corresponding initial partitioned region; determining the number of partitions to be divided in the corresponding initial partitioned region based on the multiple relationship and the number of valid structural diagrams in the corresponding initial partitioned region; dividing the corresponding initial partitioned region into two or more new initial partitioned regions based on the shape of the structural diagrams of each valid structural diagram in the corresponding initial partitioned region and the number of partitions; and calculating the area of ​​each new initial partitioned region to obtain the area of ​​the corresponding new initial partitioned region.

[0009] In one possible implementation, the step of grouping the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two target computation regions includes: grouping the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two initial partitioned regions; for each initial partitioned region, dividing each effective structure diagram into edge effective structure diagrams and non-edge effective structure diagrams according to the position of each effective structure diagram in the initial partitioned region; and correcting the edges of the initial partitioned regions according to the structure diagram shape of the edge effective structure diagrams to obtain the target computation region.

[0010] In one possible implementation, the step of grouping the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two initial partitioned regions includes: grouping the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two grouped partitioned regions; for each grouped partitioned region, calculating the edge distance between adjacent edges of each effective structure diagram; determining the magnitude relationship between the edge distance and a preset distance threshold; if all edge distances are less than or equal to the preset distance threshold, then determining the corresponding grouped partitioned region as the initial partitioned region; if any one or more edge distances are greater than the preset distance threshold, then dividing the corresponding grouped partitioned region into at least two new grouped partitioned regions according to the edge center position corresponding to the edge distance, and determining the new grouped partitioned regions as the initial partitioned regions.

[0011] In one possible implementation, the method further includes: for each of the single-layer distribution maps of the chip, performing image processing on the single-layer distribution map according to the corresponding single-layer metal density to generate a metal density distribution map.

[0012] Secondly, embodiments of this application provide a chip metal density verification device based on image features, comprising:

[0013] The first processing module is used to obtain the layout file of the chip; generate the device netlist of the chip based on the layout file; and generate the gate-level netlist of the chip based on the layout file.

[0014] The second processing module is used to perform image rendering based on the device netlist and the gate-level netlist to generate single-layer distribution maps of each layer of the chip; wherein, the single-layer distribution map includes a graphic structure map and at least one set of connection point structure maps; for each single-layer distribution map of the chip, image features are identified, and the graphic structure map is classified through the at least one set of connection point structure maps to obtain one or more effective structure maps and one or more auxiliary structure maps; for each single-layer distribution map, the regions corresponding to the multiple effective structure maps are grouped according to the one or more auxiliary structure maps to obtain at least two target computation regions; wherein, the target computation region includes at least one of the effective structure maps; for each target computation region, the area of ​​all effective structure maps within the target computation region is calculated according to the device netlist to obtain the effective structure area; the area of ​​the target computation region is calculated to obtain the target region area; the ratio of the effective structure area to the target region area is calculated to obtain the region metal density;

[0015] The determination module is used to calculate the single-layer metal density of the chip based on the regional metal density corresponding to each of the target calculation regions.

[0016] In one possible implementation, when the second processing module groups the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two target calculation regions, it specifically performs the following steps: S21, grouping the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two initial division regions; S22, calculating the area of ​​each initial division region to obtain the area of ​​the initial division region; S23, determining the relationship between the area of ​​the initial division region and a preset area threshold, including: S231, if the area of ​​the initial division region is less than or equal to the preset area threshold... If the area of ​​the initial partitioned region is greater than the preset area threshold, and there is only one valid structure graph in the corresponding initial partitioned region, then the corresponding initial partitioned region is determined as a target calculation region; if the area of ​​the initial partitioned region is greater than the preset area threshold, and there are two or more valid structure graphs in the corresponding initial partitioned region, then the corresponding initial partitioned region is divided to obtain two or more new initial partitioned regions, and the area of ​​the corresponding initial partitioned region is obtained; S24: Repeat step S23 until all target calculation regions are confirmed.

[0017] In one possible implementation, if the area of ​​the initial partitioned region is greater than the preset area threshold, and there are two or more valid structural diagrams within the corresponding initial partitioned region, then the second processing module, when dividing the corresponding initial partitioned region to obtain two or more new initial partitioned regions and obtaining the area of ​​the corresponding initial partitioned region, specifically performs the following steps: if the area of ​​the initial partitioned region is greater than the preset area threshold, and there are two or more valid structural diagrams within the corresponding initial partitioned region, calculate the multiple relationship between the area of ​​the initial partitioned region and the preset area threshold; determine the number of partitions to be performed on the corresponding initial partitioned region based on the multiple relationship and the number of valid structural diagrams within the corresponding initial partitioned region; divide the corresponding initial partitioned region according to the shape of the structural diagram of each valid structural diagram in the corresponding initial partitioned region and the number of partitions, to obtain the two or more new initial partitioned regions; calculate the area of ​​each of the new initial partitioned regions to obtain the area of ​​the corresponding new initial partitioned region.

[0018] In one possible implementation, when the second processing module groups the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two target computation regions, it specifically performs the following steps: grouping the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two initial partitioned regions; for each initial partitioned region, dividing each effective structure diagram into edge effective structure diagrams and non-edge effective structure diagrams according to the position of each effective structure diagram in the initial partitioned region; and correcting the edges of the initial partitioned regions according to the structure diagram shape of the edge effective structure diagrams to obtain the target computation region.

[0019] In one possible implementation, when the second processing module groups the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two initial division regions, it specifically performs the following steps: grouping the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two grouped division regions; for each grouped division region, calculating the edge distance between adjacent edges of each effective structure diagram; determining the relationship between the edge distance and a preset distance threshold; if all edge distances are less than or equal to the preset distance threshold, then determining the corresponding grouped division region as the initial division region; if any one or more edge distances are greater than the preset distance threshold, then dividing the corresponding grouped division region into at least two new grouped division regions according to the edge center position corresponding to the edge distance, and determining the new grouped division regions as the initial division regions.

[0020] In one possible implementation, the image feature-based chip metal density verification device is further configured to: for each of the single-layer distribution maps of the chip, perform image processing on the single-layer distribution map according to the corresponding single-layer metal density to generate a metal density distribution map.

[0021] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0022] The memory stores computer-executed instructions;

[0023] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0024] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0025] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0026] The chip metal density verification method, device, and product based on image features provided in this application embodiment obtain a chip layout file; generate a device netlist for the chip based on the layout file; generate a gate-level netlist for the chip based on the layout file; perform image rendering based on the device netlist and the gate-level netlist to generate single-layer distribution maps of each layer of the chip; wherein, the single-layer distribution map includes a graphic structure map and at least one set of connection point structure maps; for each single-layer distribution map of the chip, image features are identified, and the graphic structure map is classified through the at least one set of connection point structure maps to obtain one or more effective structure maps and one or more auxiliary structure maps; For the single-layer distribution map, the regions corresponding to the multiple effective structure maps are grouped according to the one or more auxiliary structure maps to obtain at least two target computing regions; wherein, the target computing region includes at least one of the effective structure maps; for each target computing region, the area of ​​all effective structure maps in the target computing region is calculated according to the device netlist to obtain the effective structure area; the area of ​​the target computing region is calculated to obtain the target region area; the ratio of the effective structure area to the target region area is calculated to obtain the region metal density; and the single-layer metal density of the chip is obtained according to the region metal density corresponding to each target computing region. Based on the device netlist and gate-level netlist generated from the chip's layout file, image rendering is performed using these netlists to generate single-layer distribution maps for each layer of the chip. Then, for each single-layer distribution map, the effective and auxiliary structures of that layer are determined by identifying image features. The regional metal density of that region is determined by calculating the ratio between the effective structure area and the target region area. Finally, the single-layer metal density of the chip is obtained by calculating the regional metal density of each target region, thus completing the verification of the chip's metal density. This solves the problem of inaccurate metal density verification results for each layer of the chip in existing technologies. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0028] Figure 1 A schematic diagram illustrating an application scenario of the chip metal density verification method based on image features provided in this application;

[0029] Figure 2 A flowchart of a chip metal density verification method based on image features provided in one embodiment of this application;

[0030] Figure 3 This application provides a schematic diagram illustrating a process for determining a target computational region based on an auxiliary structure diagram.

[0031] Figure 4 for Figure 2 A schematic diagram illustrating the specific implementation steps of step S104 in the illustrated embodiment;

[0032] Figure 5 This application provides a metal density distribution map obtained by image processing based on the metal density of each region.

[0033] Figure 6 A flowchart of a chip metal density verification method based on image features provided in another embodiment of this application;

[0034] Figure 7 This is a schematic diagram illustrating the determination of a target computational region based on edge correction, provided in an embodiment of this application.

[0035] Figure 8 This is a schematic diagram illustrating how to determine an initial region division based on edge distance, as provided in an embodiment of this application.

[0036] Figure 9 A schematic diagram of the structure of a chip metal density verification device based on image features provided in one embodiment of this application;

[0037] Figure 10 A schematic diagram of the structure of the electronic device provided in this application.

[0038] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0039] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0040] The technical solution of this application involves the collection, storage, use, processing, transmission, provision and disclosure of user personal information and data, which comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0041] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0042] The application scenarios of the embodiments of this application are explained below:

[0043] Figure 1 A schematic diagram illustrating an application scenario of the chip metal density verification method based on image features provided in this application, such as... Figure 1 As shown, the specific application scenario of this application is the calculation and verification of the metal density of each layer of a chip. The execution subject of the method provided in this application embodiment can be an electronic control unit, a server, or a terminal device. In the later stage of chip design, it is necessary to verify the metal density of each layer of the chip to determine the metal density distribution of each layer of the chip. For cases where the metal density distribution is uneven, it is necessary to generate corresponding calculation and verification results and feed them back to the chip designer so as to adjust the arrangement of metal lines on the chip, thereby achieving a uniform metal density distribution in each region of each layer of the chip, so as to improve the reliability of chip testing and improve the chip production yield. Using a terminal device as the execution subject, the terminal device, based on the method provided in the embodiments of this application, identifies and processes the obtained chip layout file to generate a device netlist and a gate-level netlist for the chip. Then, it performs image rendering based on the device netlist and gate-level netlist to generate single-layer distribution maps of each layer of the chip. Furthermore, for each single-layer distribution map of the chip, it determines the effective structure and auxiliary structure of that layer by identifying image features. Then, by calculating the ratio between the effective structure area corresponding to the effective structure and the target area area of ​​the corresponding region, the regional metal density of that region can be determined. Finally, based on the regional metal density corresponding to each target area, the single-layer metal density of the chip is obtained, thus completing the verification of the chip's metal density.

[0044] Based on the above scenario, it can be seen that in the existing technology, the method for verifying and determining the metal density of each layer of the chip is to extract and calculate the entire graphic structure diagram of the chip's device netlist. The entire graphic structure diagram includes the effective structure diagram corresponding to the effective structure and the auxiliary structure diagram corresponding to the auxiliary structure. Since the graphic area corresponding to the entire graphic structure diagram includes the graphic area of ​​the auxiliary structure diagram, the metal density calculated based on the graphic area corresponding to the entire graphic structure diagram has an error, which leads to the problem of inaccurate verification results of the metal density of each layer of the chip.

[0045] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings. It should be noted that step designations such as S21, S22, S23, S231, and S232 are used herein for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. Those skilled in the art may execute S232 first and then S231, etc., in specific implementations, but these should all be within the protection scope of this application.

[0046] Figure 2 A flowchart of a chip metal density verification method based on image features provided in one embodiment of this application is shown below. Figure 2 As shown, the execution subject of the chip metal density verification method based on image features provided in this embodiment can be an electronic control unit, a server, or a terminal device. For example, this embodiment uses a terminal device as the execution subject for the method. The chip metal density verification method based on image features provided in this embodiment includes the following steps:

[0047] Step S101: Obtain the chip layout file; generate the chip device netlist based on the layout file; generate the chip gate-level netlist based on the layout file.

[0048] For example, a chip layout file describes the physical layout of the devices in the chip, including the location, size, and interconnections of each device. The terminal device can obtain and process the chip's layout file to generate a device netlist and a gate-level netlist. The device netlist describes the location, size, and layer information of each device on the chip, while the gate-level netlist describes the interconnections between devices, such as the connections between gate-level devices.

[0049] Step S102: Based on the device netlist and gate netlist, perform image drawing to generate single-layer distribution diagrams of each layer of the chip; wherein, the single-layer distribution diagram includes a graphic structure diagram and at least one set of connection point structure diagrams.

[0050] For example, the terminal device performs image rendering based on the device netlist and gate-level netlist, thereby generating a single-layer distribution map of each layer of the chip; wherein, the single-layer distribution map includes a graphic structure map and at least one set of connection point structure maps. Specifically, the terminal device groups the various devices of the chip according to their respective layers based on the hierarchical information corresponding to the device netlist; then, for each device of a certain layer of the chip, image rendering is performed based on the position and size information of the device corresponding to the device netlist, thus obtaining the graphic structure map in the single-layer distribution map; furthermore, based on the connection relationships between the various devices on the chip described by the gate-level netlist, at least one set of connection point structure maps is generated, wherein the connection point structure maps are used to indicate the connection relationship between the devices in the current layer and the devices in the next layer.

[0051] Step S103: For each single-layer distribution map of the chip, identify image features, classify the graphic structure map through at least one set of connection point structure maps, and obtain one or more effective structure maps and one or more auxiliary structure maps.

[0052] For example, for each single-layer distribution map of the chip, the terminal device classifies the graphic structure map based on image feature recognition using at least one set of connection point structure maps to obtain one or more valid structure maps and one or more auxiliary structure maps. Specifically, a valid structure map corresponds to a device in the current layer that has a connection relationship with a device in the next layer, and this device is defined as a valid structure. An auxiliary structure map corresponds to a structure in the current layer that does not have a connection relationship with a device in the next layer, and this structure is defined as an auxiliary structure.

[0053] Step S104: For a single-layer distribution map, group the regions corresponding to multiple effective structure maps according to one or more auxiliary structure maps to obtain at least two target computation regions; wherein, the target computation region includes at least one effective structure map.

[0054] For example, for a single-layer distribution map, image features are identified, and based on the relative positional relationship between one or more auxiliary structure maps and multiple effective structure maps, the regions corresponding to the multiple effective structure maps are grouped to obtain at least two target computational regions. Specifically, for example, Figure 3 This application provides a schematic diagram of a process for determining a target computational region based on an auxiliary structure diagram, as shown in the embodiments of this application. Figure 3As shown, the single-layer distribution map includes three auxiliary structure maps (F_1, F_2) corresponding to three auxiliary structures and four effective structure maps (Y_1, Y_2, Y_3, Y_4) corresponding to four effective structures. In each effective structure map, the black circle represents the connection point structure map. The terminal device determines the effective structure map based on the graphic structure map of the corresponding region using the black circle. Furthermore, by recognizing image features, the terminal device uses the positions of the auxiliary structure maps (F_1, F_2) as grouping reference positions, and then groups the regions corresponding to the effective structure maps (Y_1, Y_2, Y_3, Y_4), thus obtaining the target calculation region area_1, target calculation region area_2, and target calculation region area_3. Target calculation region area_1 includes the effective structure map Y_1, target calculation region area_2 includes effective structure maps Y_2 and Y_3, and target calculation region area_3 includes the effective structure map Y_4.

[0055] Furthermore, in another possible implementation, Figure 4 for Figure 2 The schematic diagram of the specific implementation steps of step S104 in the embodiment shown is as follows: Figure 4 As shown, the specific implementation steps of step S104 include:

[0056] Step S1041: Group the regions corresponding to multiple valid structure diagrams according to one or more auxiliary structure diagrams to obtain at least two initial partitioned regions.

[0057] Step S1042: For each initially divided region, calculate the area of ​​the initially divided region to obtain the area of ​​the initially divided region.

[0058] Step S1043: Determine the relationship between the area of ​​the initially divided region and the preset area threshold.

[0059] Step S1044: If the area of ​​the initially divided region is less than or equal to the preset area threshold, then the corresponding initially divided region is determined as a target calculation region.

[0060] Step S1045: If the area of ​​the initial partitioned region is greater than the preset area threshold, and there is only one valid structure graph in the corresponding initial partitioned region, then the corresponding initial partitioned region is determined as a target calculation region.

[0061] Step S1046: If the area of ​​the initial division region is greater than the preset area threshold, and there are two or more valid structure diagrams in the corresponding initial division region, then the corresponding initial division region is divided to obtain two or more new initial division regions and the area of ​​the corresponding initial division region is obtained, and the process returns to step S1043 until all target calculation regions are confirmed.

[0062] For example, the single-layer distribution map includes three auxiliary structure maps (F_1, F_2) corresponding to three auxiliary structures and four effective structure maps (Y_1, Y_2, Y_3, Y_4) corresponding to four effective structures. Then, the terminal device identifies image features and uses the positions of the auxiliary structure maps (F_1, F_2) as grouping reference positions to group the regions corresponding to the effective structure maps (Y_1, Y_2, Y_3, Y_4), thus obtaining two initial partitioned regions (initial partitioned region AR_1 and initial partitioned region AR_2). Initial partitioned region AR_1 includes effective structure maps Y_1, Y_2, and Y_3, and initial partitioned region AR_2 includes effective structure map Y_4. Then, the area of ​​initial partitioned region AR_1 is calculated to obtain the initial partitioned region area data_1, and the area of ​​initial partitioned region AR_2 is calculated to obtain the initial partitioned region area data_2. Further... The algorithm first determines the relationship between the area of ​​the initial partitioned region and a preset area threshold. For example, if the area of ​​the initial partitioned region data_2 is less than the preset area threshold, then the corresponding initial partitioned region AR_2 is determined as a target calculation region. If the area of ​​the initial partitioned region data_1 is greater than the preset area threshold, then the initial partitioned region AR_1 is divided, for example, into two new initial partitioned regions (initial partitioned region AR_1_1 and initial partitioned region AR_1_2), and the corresponding initial partitioned region areas data_1_1 and data_1_2 are obtained. Then, the algorithm returns to step S1043 to determine the relationship between the area of ​​the initial partitioned region data_1_1 and the preset area threshold, and the relationship between the area of ​​the initial partitioned region data_1_2 and the preset area threshold, in order to determine whether the new initial partitioned regions (initial partitioned region AR_1_1 and initial partitioned region AR_1_2) can be determined as target calculation regions.

[0063] If the area of ​​the initial partitioned region is greater than the preset area threshold, but there is only one valid structure graph in the corresponding initial partitioned region, then the initial partitioned region is determined as a target calculation region.

[0064] Furthermore, in yet another possible implementation, step S1045 is specifically implemented as follows:

[0065] Step S10451: If the area of ​​the initially divided region is greater than the preset area threshold, and there are two or more valid structure diagrams in the corresponding initially divided region, then calculate the multiple relationship between the area of ​​the initially divided region and the preset area threshold.

[0066] Step S10452: Based on the multiple relationship and the number of valid structure diagrams in the corresponding initial division region, determine the number of divisions to be made for the corresponding initial division region.

[0067] Step S10453: Based on the shape and number of divisions of each valid structural diagram in the corresponding initial division region, the corresponding initial division region is divided to obtain two or more new initial division regions.

[0068] Step S10454: Calculate the area of ​​each new initial partition region to obtain the corresponding new initial partition region area.

[0069] For example, the terminal device calculates the ratio between the area of ​​the initial partitioned region and the preset area threshold, based on the premise that the area of ​​the initial partitioned region is greater than a preset area threshold and that there are two or more valid structural diagrams within the corresponding initial partitioned region. Then, based on the ratio and the number of valid structural diagrams within the corresponding initial partitioned region, the device determines the number of partitions to be made for the corresponding initial partitioned region. Specifically, for example, if the area of ​​the initial partitioned region is 160 and the preset area threshold is 50, the ratio is 3.2. If there are two valid structural diagrams within the corresponding initial partitioned region, the number of partitions to be made for the corresponding initial partitioned region is determined to be two based on the ratio of 3.2 and the number of valid structural diagrams. If there are six valid structural diagrams within the corresponding initial partitioned region, the number of partitions to be made for the corresponding initial partitioned region is determined to be four based on the ratio of 3.2 and the number of valid structural diagrams. Furthermore, based on the shape and number of divisions of each valid structural diagram in the corresponding initial division region, the corresponding initial division region is divided to obtain a new initial division region with the corresponding number of divisions; then the area of ​​each new initial division region is calculated to obtain the area of ​​the corresponding new initial division region, so as to return to step S1043.

[0070] In this embodiment, based on grouping the regions corresponding to multiple effective structure diagrams according to one or more auxiliary structure diagrams to obtain at least two initial division regions, the method of determining the target calculation region by judging the relationship between the area of ​​the initial division region and the preset area threshold improves the accuracy of the target calculation region division, thereby improving the accuracy of the subsequent steps for verifying the single-layer metal density of the chip.

[0071] Step S105: For each target computational region, calculate the area of ​​all effective structure patterns within the target computational region based on the device netlist to obtain the effective structure area; calculate the area of ​​the target computational region to obtain the target region area; calculate the ratio of the effective structure area to the target region area to obtain the region metal density.

[0072] For example, for each target computational region, since the device netlist describes the size information of each device on the chip, the terminal device calculates the area of ​​all effective structural patterns within the target computational region based on the device netlist, thus obtaining the effective structural area. Specifically, for example, if there is one effective structural pattern within the target computational region, the terminal device calculates the area of ​​that effective structural pattern based on the device netlist, thus obtaining the effective structural area; if there are three effective structural patterns within the target computational region, the terminal device calculates the sum of the areas of these three effective structural patterns based on the device netlist, thus obtaining the effective structural area. Further, the terminal device calculates the area of ​​the target computational region to obtain the target region area; based on this, the terminal device calculates the ratio of the effective structural area to the target region area to obtain the region's metal density.

[0073] Step S106: Calculate the metal density of the corresponding region based on each target region to obtain the single-layer metal density of the chip.

[0074] For example, the terminal device calculates the average metal density based on the regional metal density corresponding to each target calculation region, obtaining an average metal density, which is the single-layer metal density of the chip; or, the terminal device generates a metal density data list based on the regional metal density corresponding to each target calculation region, which is the single-layer metal density of the chip, wherein the metal density data list includes the location information and regional metal density of each target calculation region. Further, based on obtaining the single-layer metal density of the chip, the terminal device summarizes the various single-layer metal densities of the chip, thus obtaining multiple single-layer metal densities of the chip.

[0075] In this embodiment, the chip layout file is obtained; a device netlist for the chip is generated based on the layout file; a gate-level netlist for the chip is generated based on the layout file; image rendering is performed based on the device netlist and gate-level netlist to generate single-layer distribution maps for each layer of the chip; wherein, the single-layer distribution map includes a graphic structure map and at least one set of connection point structure maps; for each single-layer distribution map of the chip, image features are identified, and the graphic structure map is classified through at least one set of connection point structure maps to obtain one or more effective structure maps and one or more auxiliary structure maps; for the single-layer distribution map, the regions corresponding to multiple effective structure maps are grouped according to one or more auxiliary structure maps to obtain at least two target computation regions; wherein, the target computation region includes at least one effective structure map; for each target computation region, the area of ​​all effective structure maps within the target computation region is calculated based on the device netlist to obtain the effective structure area; the area of ​​the target computation region is calculated to obtain the target region area; the ratio of the effective structure area to the target region area is calculated to obtain the region metal density; and the single-layer metal density of the chip is obtained based on the region metal density corresponding to each target computation region. Based on the device netlist and gate-level netlist generated from the chip's layout file, image rendering is performed using these netlists to generate single-layer distribution maps for each layer of the chip. Then, for each single-layer distribution map, the effective and auxiliary structures of that layer are determined by identifying image features. The regional metal density of that region is determined by calculating the ratio between the effective structure area and the target region area. Finally, the single-layer metal density of the chip is obtained by calculating the regional metal density of each target region, thus completing the verification of the chip's metal density. This solves the problem of inaccurate metal density verification results for each layer of the chip in existing technologies.

[0076] Furthermore, the method in this embodiment further includes: for each single-layer distribution map of the chip, performing image processing on the single-layer distribution map according to the corresponding single-layer metal density to generate a metal density distribution map. Specifically, for example, if the image processing is image rendering, the terminal device renders the corresponding target calculation area according to the metal density of each region corresponding to the single-layer metal density, thereby generating a metal density distribution map, wherein, for example, in areas with high metal density, the rendered lines are dense, and in areas with low metal density, the rendered lines are sparse; or, Figure 5 This application provides a metal density distribution map based on the metal density rendering of various regions, as shown in the embodiments of this application. Figure 5The metal density distribution map shown indicates that structures filled with gray represent effective structures; structures filled with green represent auxiliary structures; and structures filled with blue represent connection point structures. Rendering from low (blue) to high (red) metal density displays the metal density of the corresponding areas. However, due to color overlay, the image color of the effective structures may change during rendering, for example, in… Figure 5 In the rendering process, the gray fill color of the effective structure changes because it is covered by a red layer. In this embodiment, a metal density distribution map is generated by processing the single-layer distribution map based on the single-layer metal density. This allows chip designers (or other relevant personnel) to visually observe the metal density distribution. If adjustments to the metal line arrangement are needed, this helps chip designers (or other relevant personnel) optimize the chip design and adjust the metal line arrangement.

[0077] Figure 6 A flowchart of a chip metal density verification method based on image features provided in another embodiment of this application is shown below. Figure 6 As shown, the chip metal density verification method based on image features provided in this embodiment... Figure 2 Based on the image feature-based chip metal density verification method provided in the illustrated embodiment, step S104 is further refined. Therefore, the image feature-based chip metal density verification method provided in this embodiment includes the following steps:

[0078] Step S201: Obtain the chip layout file; generate the chip device netlist based on the layout file; generate the chip gate-level netlist based on the layout file.

[0079] Step S202: Based on the device netlist and gate netlist, perform image drawing to generate single-layer distribution diagrams of each layer of the chip; wherein, the single-layer distribution diagram includes a graphic structure diagram and at least one set of connection point structure diagrams.

[0080] Step S203: For each single-layer distribution map of the chip, identify image features, classify the graphic structure map through at least one set of connection point structure maps, and obtain one or more effective structure maps and one or more auxiliary structure maps.

[0081] Step S204: Group the regions corresponding to multiple valid structure diagrams according to one or more auxiliary structure diagrams to obtain at least two initial partitioned regions.

[0082] Step S205: For each initially partitioned region, based on the position of each effective structure graph in the initially partitioned region, divide each effective structure graph into edge effective structure graphs and non-edge effective structure graphs.

[0083] Step S206: Correct the edges of the initially divided region according to the shape of the structure map of the effective edge structure map to obtain the target calculation region.

[0084] For example, Figure 7 This application provides a schematic diagram of determining a target computational region based on edge correction, as shown in the embodiments of this application. Figure 7 As shown, after grouping the regions corresponding to multiple effective structure diagrams according to one or more auxiliary structure diagrams to obtain at least two initial partitioned regions, taking one of the initial partitioned regions as an example, this initial partitioned region includes 5 effective structure diagrams (Y_5, Y_6, Y_7, Y_8, Y_9). Based on the position of each effective structure diagram in the initial partitioned region, effective structure diagrams Y_5, Y_6, and Y_7 are determined as edge effective structure diagrams, and effective structure diagrams Y_8 and Y_9 are determined as non-edge effective structure diagrams. Then, the edges of the initial partitioned region are corrected according to the structure diagram shape of the edge effective structure diagrams to obtain the target computation region corresponding to the initial partitioned region. For example, before correction, the distance between the edge of the initial partitioned region and the edge of the edge effective structure diagram fluctuates between 10 and 15 (e.g., the distance between the left edge is 12, the distance between the right edge is 15, the distance between the top edge is 11, and the distance between the bottom edge is 10). After correction, the edge distance is reduced and unified to 5, thus obtaining the target computation region. Furthermore, by summarizing the target computation regions determined based on each initial partitioned region, all target computation regions are obtained.

[0085] In this embodiment, since the regional metal density is determined by the ratio of the effective structural area to the target area, directly calculating the target area based on the initial division of the region would result in a large error in the calculated regional metal density. For example, if the effective structural area is 120 and the target area calculated based on the initial division of the region is 200, after correcting the initial division of the region, the target area corresponding to the target calculation region is 180. Therefore, the regional metal density determined based on the initial division of the region is 60%, and the regional metal density determined based on the target calculation region is 66.7%, resulting in an error of 6.7%. That is, by using edge correction, the error in the regional metal density calculated in subsequent steps is reduced, thereby improving the accuracy of the results of metal density verification for each layer of the chip.

[0086] Furthermore, in another possible implementation, step S204 is specifically implemented as follows:

[0087] Step S2041: Group the regions corresponding to multiple valid structure diagrams according to one or more auxiliary structure diagrams to obtain at least two grouped regions.

[0088] Step S2042: For each grouped region, calculate the edge distance between adjacent edges of each valid structure diagram.

[0089] Step S2043: Determine the relationship between the edge distance and the preset distance threshold.

[0090] Step S2044: If all edge distances are less than or equal to a preset distance threshold, then the corresponding grouped region is determined as the initial region.

[0091] Step S2045: If any one or more edge distances are greater than a preset distance threshold, then according to the edge center position corresponding to the edge distance, the corresponding group division region is divided into at least two new group division regions, and the new group division regions are determined as the initial division regions.

[0092] For example, Figure 8 This application provides a schematic diagram of determining an initial region division based on edge distance, as shown in the embodiment of the present application. Figure 8 As shown, after grouping the regions corresponding to multiple valid structure diagrams according to one or more auxiliary structure diagrams to obtain at least two grouped regions, taking one grouped region as an example, which includes three valid structure diagrams (Y_11, Y_12, Y_13), the edge distance between adjacent edges of each valid structure diagram is calculated. For example, the edge distance between valid structure diagrams Y_11 and Y_12 is 15, and the edge distance between valid structure diagrams Y_12 and Y_13 is 5. Then, the relationship between the edge distance and a preset distance threshold is determined, for example, the preset distance threshold is 6. If all edge distances are less than or equal to the preset distance threshold, the corresponding grouped region is determined as the initial region. If any one or more edge distances are greater than the preset distance threshold, the corresponding grouped region is divided into at least two new regions according to the edge center position corresponding to the edge distance. The effective structure graphs Y_11 and Y_12 are divided into groups, and the new grouped regions are determined as the initial division regions. The edge distance between effective structure graphs Y_11 and Y_12 is 15, and the edge distance between effective structure graphs Y_12 and Y_13 is 5. Since the edge distance between effective structure graphs Y_11 and Y_12 is 15, which is greater than the preset distance threshold of 6, the division is based on the edge center positions corresponding to the edge distance between effective structure graphs Y_11 and Y_12, resulting in two new grouped regions. Since the edge distance between effective structure graphs Y_12 and Y_13 is 5, which is less than the preset distance threshold of 6, the grouped regions corresponding to effective structure graphs Y_12 and Y_13 are determined as the initial division regions. Based on the above processing, the initial division region AR_11 determined by effective structure graph Y_11 and the initial division region AR_12_13 determined by effective structure graphs Y_12 and Y_13 are obtained.

[0093] In this embodiment, by identifying the regions between the edges of the effective structural diagrams in the grouped division region, if the edge distance is greater than a preset distance threshold, the grouped division region is further divided; if the edge distance is less than or equal to the preset distance threshold, the grouped division region is not further divided. This reduces the error in the calculated regional metal density in subsequent steps caused by the area between the edges of the effective structural diagrams, thereby improving the accuracy of the results of metal density verification for each layer of the chip.

[0094] Step S207: For each target computational region, calculate the area of ​​all effective structural patterns within the target computational region based on the device netlist to obtain the effective structural area; calculate the area of ​​the target computational region to obtain the target region area; calculate the ratio of the effective structural area to the target region area to obtain the region metal density.

[0095] Step S208: Calculate the metal density of the corresponding region based on each target region to obtain the single-layer metal density of the chip.

[0096] In this embodiment, the implementation methods of steps S201-S203 and S207-S208 are the same as those in this application. Figure 2 The implementation methods of steps S101-S103 and steps S105-S106 in the illustrated embodiment are the same, and will not be described in detail here.

[0097] Figure 9 This is a schematic diagram of the structure of a chip metal density verification device based on image features provided in one embodiment of this application, as shown below. Figure 9 As shown, the chip metal density verification device 3 based on image features provided in this embodiment includes:

[0098] The first processing module 31 is used to obtain the layout file of the chip; generate the device netlist of the chip based on the layout file; and generate the gate-level netlist of the chip based on the layout file.

[0099] The second processing module 32 is used to draw images based on the device netlist and gate-level netlist to generate single-layer distribution maps of each layer of the chip; wherein, the single-layer distribution map includes a graphic structure map and at least one set of connection point structure maps; for each single-layer distribution map of the chip, image features are identified, and the graphic structure map is classified through at least one set of connection point structure maps to obtain one or more effective structure maps and one or more auxiliary structure maps; for the single-layer distribution map, the regions corresponding to multiple effective structure maps are grouped according to one or more auxiliary structure maps to obtain at least two target computation regions; wherein, the target computation region includes at least one effective structure map; for each target computation region, the area of ​​all effective structure maps within the target computation region is calculated according to the device netlist to obtain the effective structure area; the area of ​​the target computation region is calculated to obtain the target region area; the ratio of the effective structure area to the target region area is calculated to obtain the region metal density;

[0100] The determination module 33 is used to calculate the regional metal density corresponding to each target region to obtain the single-layer metal density of the chip.

[0101] In one possible implementation, when the second processing module 32 groups the regions corresponding to multiple valid structure diagrams according to one or more auxiliary structure diagrams to obtain at least two target calculation regions, it specifically performs the following steps: S21, grouping the regions corresponding to multiple valid structure diagrams according to one or more auxiliary structure diagrams to obtain at least two initial division regions; S22, calculating the area of ​​each initial division region to obtain the area of ​​the initial division region; S23, determining the relationship between the area of ​​the initial division region and a preset area threshold, including: S231, if the area of ​​the initial division region is less than or equal to the preset area threshold, then determining the corresponding initial division region as a target calculation region; S232, if the area of ​​the initial division region is greater than the preset area threshold, and there is only one valid structure diagram in the corresponding initial division region, then determining the corresponding initial division region as a target calculation region; S233, if the area of ​​the initial division region is greater than the preset area threshold, and there are two or more valid structure diagrams in the corresponding initial division region, then dividing the corresponding initial division region to obtain two or more new initial division regions, and obtaining the corresponding area of ​​the initial division region; S24: repeating step S23 until all target calculation regions are confirmed.

[0102] In one possible implementation, if the area of ​​the initial partitioned region is greater than a preset area threshold, and there are two or more valid structural diagrams within the corresponding initial partitioned region, then the second processing module 32, when dividing the corresponding initial partitioned region to obtain two or more new initial partitioned regions and obtaining the area of ​​the corresponding initial partitioned region, specifically performs the following: if the area of ​​the initial partitioned region is greater than a preset area threshold, and there are two or more valid structural diagrams within the corresponding initial partitioned region, calculate the multiple relationship between the area of ​​the initial partitioned region and the preset area threshold; determine the number of partitions to be performed on the corresponding initial partitioned region based on the multiple relationship and the number of valid structural diagrams within the corresponding initial partitioned region; divide the corresponding initial partitioned region according to the shape of the structural diagram and the number of partitions of each valid structural diagram in the corresponding initial partitioned region to obtain two or more new initial partitioned regions; calculate the area of ​​each new initial partitioned region to obtain the area of ​​the corresponding new initial partitioned region.

[0103] In one possible implementation, when the second processing module 32 groups the regions corresponding to multiple effective structure diagrams according to one or more auxiliary structure diagrams to obtain at least two target computation regions, it specifically performs the following steps: grouping the regions corresponding to multiple effective structure diagrams according to one or more auxiliary structure diagrams to obtain at least two initial partitioned regions; for each initial partitioned region, dividing each effective structure diagram into edge effective structure diagrams and non-edge effective structure diagrams according to the position of each effective structure diagram in the initial partitioned region; and correcting the edges of the initial partitioned regions according to the structure diagram shape of the edge effective structure diagrams to obtain the target computation region.

[0104] In one possible implementation, when the second processing module 32 groups the regions corresponding to multiple effective structure diagrams according to one or more auxiliary structure diagrams to obtain at least two initial division regions, it specifically performs the following steps: grouping the regions corresponding to multiple effective structure diagrams according to one or more auxiliary structure diagrams to obtain at least two grouped division regions; for each grouped division region, calculating the edge distance between adjacent edges of each effective structure diagram; determining the relationship between the edge distance and a preset distance threshold; if all edge distances are less than or equal to the preset distance threshold, then determining the corresponding grouped division region as the initial division region; if any one or more edge distances are greater than the preset distance threshold, then dividing the corresponding grouped division region into at least two new grouped division regions according to the edge center position corresponding to the edge distance, and determining the new grouped division regions as the initial division regions.

[0105] In one possible implementation, the chip metal density verification device 3 based on image features is further used to: perform image processing on the single-layer distribution map for each single-layer distribution map of the chip according to the corresponding single-layer metal density, and generate a metal density distribution map.

[0106] The first processing module 31, the second processing module 32, and the determination module 33 are connected sequentially. The chip metal density verification device 3 based on image features provided in this embodiment can perform the following... Figures 2-8 The technical solutions of any of the method embodiments shown are similar in implementation principle and technical effect, and will not be described again here.

[0107] Figure 10 A schematic diagram of the structure of the electronic device provided in this application. Figure 10 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus 504.

[0108] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.

[0109] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0110] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0111] The memory may include random access memory (RAM) and also non-volatile memory (NVM).

[0112] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0113] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0114] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0115] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, and flash memory. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0116] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0117] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0118] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0119] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0120] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), and random access memory (RAM).

[0121] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM and RAM.

[0122] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A chip metal density verification method based on image features, characterized in that, The method includes: Obtain the chip's layout file; Based on the layout file, generate the device netlist for the chip; Based on the layout file, generate the gate-level netlist for the chip; Based on the device netlist and the gate-level netlist, an image is drawn to generate a single-layer distribution map of each layer of the chip; wherein, the single-layer distribution map includes a graphic structure map and at least one set of connection point structure maps; For each single-layer distribution map of the chip, image features are identified, and the graphic structure map is classified through the at least one set of connection point structure maps to obtain one or more effective structure maps and one or more auxiliary structure maps; For the single-layer distribution map, the regions corresponding to the multiple effective structure maps are grouped according to the one or more auxiliary structure maps to obtain at least two target computation regions; wherein, the target computation region includes at least one of the effective structure maps; For each target computational region, based on the device netlist, the area of ​​all effective structure patterns within the target computational region is calculated to obtain the effective structure area; the area of ​​the target computational region is calculated to obtain the target region area; the ratio of the effective structure area to the target region area is calculated to obtain the region metal density. The single-layer metal density of the chip is obtained based on the regional metal density corresponding to each target calculation region.

2. The method according to claim 1, characterized in that, The step of grouping the regions corresponding to the multiple effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two target computation regions includes: S21, group the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two initial partitioned regions; S22, For each initially divided region, calculate the area of ​​the initially divided region to obtain the area of ​​the initially divided region; S23, determining the relationship between the area of ​​the initially divided region and the preset area threshold, including: S231, if the area of ​​the initial partitioned region is less than or equal to the preset area threshold, then the corresponding initial partitioned region is determined as a target calculation region; S232, if the area of ​​the initial partitioned region is greater than the preset area threshold, and there is only one valid structure diagram in the corresponding initial partitioned region, then the corresponding initial partitioned region is determined as a target calculation region. S233, if the area of ​​the initial division region is greater than the preset area threshold, and there are two or more valid structure diagrams in the corresponding initial division region, then the corresponding initial division region is divided to obtain two or more new initial division regions, and the area of ​​the corresponding initial division region is obtained. S24: Repeat step S23 until the entire target calculation area is confirmed.

3. The method according to claim 2, characterized in that, If the area of ​​the initial partitioned region is greater than the preset area threshold, and there are two or more valid structure diagrams within the corresponding initial partitioned region, then the corresponding initial partitioned region is partitioned to obtain two or more new initial partitioned regions, and the area of ​​the corresponding initial partitioned region is obtained, including: If the area of ​​the initial partitioned region is greater than the preset area threshold, and there are two or more valid structure diagrams within the corresponding initial partitioned region, then the multiple relationship between the area of ​​the initial partitioned region and the preset area threshold is calculated. Based on the multiple relationship and the number of valid structure diagrams within the corresponding initial partition region, determine the number of partitions to be made for the corresponding initial partition region; Based on the shape of the structure diagram of each effective structure diagram in the corresponding initial partition region and the number of partitions, the corresponding initial partition region is divided to obtain the two or more new initial partition regions. Calculate the area of ​​each of the new initial partitioned regions to obtain the corresponding new initial partitioned region area.

4. The method according to claim 1, characterized in that, The step of grouping the regions corresponding to the multiple effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two target computation regions includes: Based on the one or more auxiliary structure diagrams, the regions corresponding to the multiple effective structure diagrams are grouped to obtain at least two initial partitioned regions; For each initial partitioned region, based on the position of each effective structure graph in the initial partitioned region, the effective structure graphs are divided into edge effective structure graphs and non-edge effective structure graphs; The edges of the initially divided region are corrected based on the shape of the structure map of the effective edge structure map to obtain the target calculation region.

5. The method according to claim 4, characterized in that, The step of grouping the regions corresponding to the plurality of effective structure diagrams according to the one or more auxiliary structure diagrams to obtain at least two initial partitioned regions includes: Based on the one or more auxiliary structure diagrams, the regions corresponding to the multiple effective structure diagrams are grouped to obtain at least two grouped regions. For each grouped region, calculate the edge distance between adjacent edges of each valid structure graph; Determine the relationship between the edge distance and the preset distance threshold; If all edge distances are less than or equal to the preset distance threshold, then the corresponding grouped region is determined as the initial region. If any one or more edge distances are greater than the preset distance threshold, then based on the edge center position corresponding to the edge distance, the corresponding grouping region is divided into at least two new grouping regions, and the new grouping regions are determined as the initial division region.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: For each of the single-layer distribution maps of the chip, image processing is performed on the single-layer distribution map according to the corresponding single-layer metal density to generate a metal density distribution map.

7. A chip metal density verification device based on image features, characterized in that, include: The first processing module is used to obtain the layout file of the chip; and generate the device netlist of the chip based on the layout file. Based on the layout file, generate the gate-level netlist for the chip; The second processing module is used to perform image rendering based on the device netlist and the gate-level netlist to generate single-layer distribution maps of each layer of the chip; wherein, the single-layer distribution map includes a graphic structure map and at least one set of connection point structure maps; for each single-layer distribution map of the chip, image features are identified, and the graphic structure map is classified through the at least one set of connection point structure maps to obtain one or more effective structure maps and one or more auxiliary structure maps; for each single-layer distribution map, the regions corresponding to the multiple effective structure maps are grouped according to the one or more auxiliary structure maps to obtain at least two target computation regions; wherein, the target computation region includes at least one of the effective structure maps; for each target computation region, the area of ​​all effective structure maps within the target computation region is calculated according to the device netlist to obtain the effective structure area; the area of ​​the target computation region is calculated to obtain the target region area; the ratio of the effective structure area to the target region area is calculated to obtain the region metal density; The determination module is used to calculate the single-layer metal density of the chip based on the regional metal density corresponding to each of the target calculation regions.

8. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the chip metal density verification method based on image features as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The method includes a computer program that, when executed by a processor, implements the chip metal density verification method based on image features as described in any one of claims 1 to 6.

Images