Display panel and display device

Abstract

This disclosure provides a display panel and display device, relating to the field of display technology. The display panel includes multiple pixel circuit rows, each pixel circuit row including multiple pixel driving circuits. Each pixel driving circuit is at least configured to receive a light emission control signal, which is configured to control the light-emitting elements to emit light. The light emission control signal corresponding to at least one pixel circuit row includes N first effective pulse signals, at least two of which have different pulse widths, where N ≥ 2. Within one frame, at least two of the light-emitting elements corresponding to at least one pixel circuit row have different gray levels, and the light-emitting elements with different gray levels respectively receive the first effective pulse signals. Thus, the effect of PWM and PAM modulation can be achieved without the need for two separate PWM and PAM circuits, simplifying the circuit structure and improving the display effect.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops, smart wearable devices, and splicing display devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] At present, improving the display effect of display products has become one of the most pressing technical problems to be solved. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a display panel and a display device to improve display performance.

[0005] In a first aspect, this disclosure provides a display panel including multiple pixel circuit rows, each pixel circuit row including multiple pixel driving circuits; the pixel driving circuits are electrically connected to light-emitting elements, and the pixel driving circuits are at least configured to receive light-emitting control signals, the light-emitting control signals being configured to control the light-emitting elements to emit light;

[0006] The light emission control signal corresponding to at least one of the pixel circuit rows includes N first effective pulse signals, at least two of the first effective pulse signals have different pulse widths, and N≥2; within one frame, among the light emission elements corresponding to at least one pixel circuit row, at least two light emission elements have different gray levels, and the light emission elements with different gray levels respectively receive the first effective pulse signals.

[0007] Secondly, based on the same inventive concept, this disclosure also provides a display device, including the display panel provided in the first aspect of this disclosure.

[0008] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0009] In the display panel and display device provided in this embodiment, at least two first effective pulse signals in the light emission control signal corresponding to a pixel circuit row have different pulse widths. This modulates the light emission time of light-emitting elements with different grayscale requirements by the light emission time of the first effective pulse signals with different pulse widths. This allows light-emitting elements with high grayscale requirements to have higher brightness, while light-emitting elements with low grayscale requirements do not emit light or have lower brightness, thereby improving contrast and display effect. Furthermore, the effect of PAM+PWM co-modulation can be achieved without introducing two separate PAM and PWM circuits; only the first effective pulse signals with different pulse widths are needed, thus simplifying the structure of the pixel driving circuit. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 The diagram shown is a schematic of a pixel driving circuit in the related art;

[0013] Figure 2 The image shown is a pulse diagram of a light emission control signal in related technologies;

[0014] Figure 3 The diagram shown is a schematic of another pixel driving circuit in the related technology;

[0015] Figure 4 The diagram shown is a structural schematic of a display panel provided in an embodiment of this disclosure;

[0016] Figure 5 The diagram shows a pulse of the light emission control signal corresponding to a row of pixel driving circuits.

[0017] Figure 6 The diagram shows the pulses of the light emission control signal and the reset control signal corresponding to the row pixel driving circuit.

[0018] Figure 7 The diagram shown is a partial schematic of a pixel driving circuit provided in an embodiment of this disclosure;

[0019] Figure 8 The diagram shown is a partial schematic of another pixel driving circuit provided in an embodiment of this disclosure;

[0020] Figure 9 The diagram shown is a schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure.

[0021] Figure 10 As shown Figure 9 A timing diagram of a mid-pixel driving circuit;

[0022] Figure 11 The diagram shown is a partial schematic of another pixel driving circuit provided in an embodiment of this disclosure;

[0023] Figure 12 The diagram shown is a partial schematic of another pixel driving circuit provided in an embodiment of this disclosure;

[0024] Figure 13 The diagram shown is a timing relationship diagram of the light emission control signal, reset control signal, and precharge control signal.

[0025] Figure 14 The diagram shown is another schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure.

[0026] Figure 15 As shown Figure 14 A timing diagram of a mid-pixel driving circuit;

[0027] Figure 16 The figure shows a timing diagram of the light emission control signal and reset control signal corresponding to the Nth pixel circuit row;

[0028] Figure 17 The diagram shown is a timing diagram of the light emission control signal, reset control signal, and precharge control signal corresponding to the Nth pixel circuit row.

[0029] Figure 18 The figure shows another timing diagram of the light emission control signal and reset control signal corresponding to the Nth pixel circuit row;

[0030] Figure 19 The figure shown is a timing diagram illustrating the change in anode voltage of a light-emitting element under different current conditions;

[0031] Figure 20 The diagram shows another timing sequence for the light emission control signal, reset control signal, and precharge control signal corresponding to the Nth pixel circuit row.

[0032] Figure 21 The figure shown is a timing diagram of the change of anode voltage of the light-emitting element under different current conditions after the introduction of the pre-charging module;

[0033] Figure 22The figure shown is another timing diagram of the change of anode voltage of the light-emitting element under different current conditions after the introduction of the pre-charging module;

[0034] Figure 23 The diagram shown is a structural schematic of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0035] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0036] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0037] Figure 1 The diagram shown is a schematic of a pixel driving circuit in the related art. Figure 2 The diagram shows a pulse diagram of the light emission control signal EM in the related technology. In this pixel driving circuit, the light emission control transistor M0 is a P-type transistor. When the light emission control signal EM is a low-level signal, the light emission control transistor M0 is turned on, and the constant current source flows through the light emission control transistor M0 into the light emission element D, driving the light emission element D to emit light. Figure 2 The pulses of the light emission control signals corresponding to the three rows of pixel driving circuits are shown, namely EM. <1> EM <2> EM <3> Within one or several frames, the luminous emission control signal EM turns on and off regularly and uniformly. By adjusting the proportion of the low-level on-time of the luminous emission control signal EM to the total time, the overall brightness of the screen can be adjusted. However, in the entire display product, the luminous emission control signal turns on and off line by line. When the luminous emission control signal is low, all grayscale pixels emit light together, and when the luminous emission control signal is high, all grayscale pixels turn off together. This only achieves full-screen brightness adjustment, and the luminous emission control signal can only act as a switch for the current source, unable to adjust the emission time of different grayscale levels.

[0038] Figure 3The diagram shows another pixel driving circuit in the related art. This pixel driving circuit includes a pulse width modulation circuit (PWM) and a pulse amplitude modulation circuit (PAM) electrically connected to the PWM circuit. The PAM circuit is electrically connected to the light-emitting element D. The luminous duration and brightness can be adjusted through the cooperation of the PWM circuit and the PAM circuit. However, the PWM circuit and the PAM circuit are two separate circuits, and each circuit needs to receive data signals separately, which increases the complexity of the circuit structure and the transmission of data signals.

[0039] Therefore, this disclosure provides a display panel and display device that, while achieving a combined adjustment effect of pulse width modulation and pulse amplitude modulation, also simplifies the circuit structure and data signal transmission method, thereby improving the display effect. The present disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] Figure 4 The diagram shown is a structural schematic of a display panel provided in an embodiment of this disclosure. Figure 5 The diagram shows a pulse representation of the light emission control signal EM corresponding to pixel drive circuit 00 in a row. Please refer to the diagram. Figure 4 and Figure 5 This disclosure provides a display panel 100, including multiple pixel circuit rows 80, each pixel circuit row 80 including multiple pixel driving circuits 00. In this embodiment, the multiple pixel circuit rows 80 are arranged along the Y direction, and the pixel driving circuits in the pixel circuit rows 80 are arranged along the X direction. However, this is not a limitation. In some other embodiments of this disclosure, the multiple pixel circuit rows 80 may also be arranged along the X direction, and the pixel driving circuits in the pixel circuit rows 80 may be arranged along the Y direction. It should be noted that... Figure 4 The number of pixel circuit rows 80 and the number of pixel driving circuits 00 contained in the pixel circuit rows 80 are for illustrative purposes only and do not limit the actual number of pixel circuit rows 80 and pixel driving circuits 00 contained in the display panel.

[0041] In this disclosure, the pixel driving circuit 00 is electrically connected to the light-emitting element D0 and is used to provide a driving signal to the light-emitting element D0 to drive it to emit light. The light-emitting element D0 in this disclosure can be, for example, an organic light-emitting device, such as an OLED (Organic Light-Emitting Diode), or an inorganic light-emitting device, such as an LED, Micro LED, or MiniLED, etc., and this disclosure does not specifically limit it. The pixel driving circuit 00 is at least used to receive a light-emitting control signal EM, which is configured to control the light-emitting element D0 to emit light. When a valid pulse signal of the light-emitting control signal EM is transmitted to the pixel driving circuit 00, the light-emitting element D0 can be controlled to emit light.

[0042] In the display panel, multiple pixel driving circuits 00 in row 80 of a pixel circuit are connected to the same light emission control signal line EM-L and receive the same light emission control signal EM; it should be noted that... Figure 4 Only the light emission control signal line EM-L and the reset control signal line RST-L corresponding to the first pixel circuit row 80 are shown. In fact, the other pixel circuit rows 80 are also provided with light emission control signal lines EM-L and reset control signal lines RST-L. The connection relationship between the pixel driving circuit 00 in the other pixel circuit rows 80 and the light emission control signal line EM-L and the reset control signal line RST-L can be referred to the first pixel circuit row 80. This disclosure will not illustrate this further.

[0043] Figure 5 The illustrated embodiment shows the light emission control signals EM corresponding to the three pixel circuit rows 80 in the display panel, which are EM... <1> EM <2> EM <3> Please continue to refer to this. Figure 5In the light emission control signal EM corresponding to a pixel circuit row 80, at least two first effective pulse signals S1 have different pulse widths. That is, in this embodiment, in the light emission control signal EM corresponding to a pixel circuit row 80, there are at least two first effective pulse signals S1 with different pulse widths. The pulse width of the first effective pulse signal S1 is at least related to the light emission duration of the light-emitting element D0; the larger the pulse width, the longer the light emission duration, and vice versa. For light-emitting elements with different grayscale requirements, when the grayscale is high, providing either a first effective pulse signal S1 with a smaller pulse width or a larger pulse width can drive the light-emitting element D0 to achieve the expected brightness; while when the grayscale is low, a first effective pulse signal S1 with a larger pulse width is required to drive the light-emitting element D0 to achieve the expected brightness, and providing a first effective pulse signal S1 with a smaller pulse width will not drive the light-emitting element D0 to emit light or will not achieve the expected brightness. Therefore, for light-emitting elements D0 with different grayscale requirements, if the first effective pulse signal S1 with a larger pulse width is used for control, the light-emitting duration of light-emitting elements D0 with different grayscale requirements will be the same and they will all emit light, which will make it difficult to further improve the contrast of the display product. Therefore, in this embodiment of the present disclosure, when a first effective pulse signal S1 with a different pulse width is introduced, the light emission time of the light-emitting element D0 with different grayscale requirements is modulated by the light emission time of the first effective pulse signal S1 with a different pulse width. For the light-emitting element D0 with high grayscale requirements, it can still emit light normally after receiving the control of the first effective pulse with a lower pulse width. For the light-emitting element D0 with low grayscale requirements, it will not emit light or the light emission time will be shorter after receiving the first effective pulse signal S1 with a smaller pulse width. This makes the light emission brightness of the light-emitting element D0 with high grayscale requirements higher, while the light-emitting element D0 with low grayscale requirements will not emit light or the brightness will be lower. This is beneficial to improving the contrast of the display panel and improving the display effect. At the same time, the effect of PAM+PWM co-modulation can be achieved without introducing two sets of PAM and PWM circuits. This can be achieved by introducing a first effective pulse signal S1 with a different pulse width, which is beneficial to simplifying the structure of the pixel driving circuit 00. Furthermore, this disclosure introduces first effective pulse signals with different pulse widths to achieve modulation of the luminous time and luminous brightness of light-emitting elements with different grayscale requirements. Therefore, it is not necessary to introduce PWM circuits for luminous time modulation and PAM circuits for luminous brightness modulation separately. Thus, it is not necessary to transmit data signals twice. Only one data signal transmission is required to achieve modulation of the luminous time and luminous brightness of the light-emitting elements. Therefore, compared with the related technologies that simultaneously introduce PWM circuits and PAM circuits, the display panel of this disclosure is beneficial to simplifying the data transmission logic, reducing the amount of data transmitted, thereby reducing bandwidth and increasing the maximum luminous time.

[0044] Figure 6 The diagram shows the pulses of the light-emitting control signal EM and the reset control signal RST corresponding to the pixel driving circuit 00 in one row. Please refer to the diagram. Figures 4 to 6 In some optional embodiments of this disclosure, the pixel driving circuit 00 is further configured to receive a reset control signal RST, which is configured to reset the anode of the light-emitting element D0. The reset control signal corresponding to at least one pixel circuit row includes N second valid pulse signals S2. The pixel driving circuit includes N pulse periods H0, each pulse period H0 including a first valid pulse signal S1 and a second valid pulse signal S2, wherein in each pulse period, the second valid pulse signal S2 precedes the first valid pulse signal S1. Multiple pixel driving circuits 00 in a pixel circuit row 80 are connected to the same reset control signal line RST-L and receive the same reset control signal RST. The reset control signal RST includes both valid and invalid pulse signals. When the valid pulse signal of the reset control signal RST is transmitted to the pixel driving circuit 00, the anode of the light-emitting element D0 is reset, restoring the anode of the light-emitting element D0 to its initial state and completely turning off the light-emitting element D0.

[0045] Figure 6 The illustrated embodiment shows the light emission control signal EM and the reset control signal RST corresponding to the three pixel circuit rows 80 in the display panel, which are respectively EM <1> EM <2> EM <3> and RST <1> RST <2> RST <3> The light emission control signal EM corresponding to at least one pixel circuit row 80 includes N first valid pulse signals S1, where N ≥ 2. In this embodiment, a low-level signal in the light emission control signal EM is used as a valid pulse signal, and a high-level signal is used as an invalid pulse signal for explanation. The reset control signal RST corresponding to at least one pixel circuit row 80 includes N second valid pulse signals S2. That is, the number of first valid pulse signals S1 in the light emission control signal EM corresponding to one pixel circuit row 80 and the number of second valid pulse signals S2 in the reset control signal RST are the same. In this embodiment, a low-level signal in the reset control signal RST is used as a valid level signal, and a high-level signal is used as an invalid level signal for explanation.

[0046] Please continue to refer to this. Figure 6 The pixel driving circuit 00 in this embodiment includes N pulse periods H0, each pulse period H0 including a first valid pulse signal S1 and a second valid pulse signal S2. In each pulse period H0, the second valid pulse signal S2 is located before the first valid pulse signal S1. It should be noted that the pulse period mentioned in this embodiment is described using one pixel circuit row as an example, corresponding to... Figure 6In the middle, the reset control signal RST in the first row <1> The starting time of the nth second pulse signal S2 to the first row of light emission control signal EM <1> The end time of the nth pulse signal S1 corresponds to one pulse period H0. The reset control signal RST in the second row... <2> The starting time of the nth second pulse signal S2 to the light emission control signal EM of the second row <2> The end time of the nth pulse signal S1 corresponds to one pulse period H0. The reset control signal RST in the third row... <3> The starting time of the nth second pulse signal S2 to the light emission control signal EM in the third row <3> The end time of the nth pulse signal S1 corresponds to one pulse period H0.

[0047] In this disclosure, before providing a first valid pulse signal S1 to the pixel driving circuit 00 to control the light-emitting element D0 to emit light, a second valid pulse signal S2 is first provided to the pixel driving circuit 00 to reset the anode of the light-emitting element D0. The reset signal is written to the anode of the light-emitting element D0, so that the light-emitting element D0 is completely turned off. In this way, the anode of the light-emitting element D0 can emit light accurately under the same state based on the driving current, which is beneficial to improving the display accuracy of the display panel.

[0048] Figure 7 The diagram shown is a partial schematic of a pixel driving circuit provided in an embodiment of this disclosure. Please refer to it. Figure 7 In one optional embodiment of this disclosure, the pixel driving circuit 00 includes a driving transistor M1 and a first light-emitting control transistor M6. The first terminal of the driving transistor M1 is coupled to the first power supply voltage terminal ELVDD, and the second terminal of the driving transistor M1 is electrically connected to the first terminal of the first light-emitting control transistor M6. The second terminal of the first light-emitting control transistor M6 is electrically connected to the anode of the light-emitting element D0. The gate of the first light-emitting control transistor M6 is used to receive the light-emitting control signal EM, and the cathode of the light-emitting element D0 is connected to the second power supply voltage terminal ELVSS. This embodiment uses P-type transistors as an example for illustration, but it does not limit the specific type of transistor. In some other embodiments of this disclosure, at least one of the driving transistor M1 and the first light-emitting control transistor M6 may also be an N-type transistor. When the first light-emitting control transistor M6 is a P-type transistor, it turns on in response to a low-level signal in the light-emitting control signal EM, that is, the first effective pulse signal in the light-emitting control signal EM is a low-level signal. When an invalid pulse signal in the light emission control signal EM is transmitted to the first light emission control transistor M6, the first light emission control transistor M6 will not be able to conduct, thereby preventing the light-emitting element from conducting during the non-light emission stage.

[0049] Figure 8The diagram shown is a partial schematic of another pixel driving circuit provided in an embodiment of this disclosure. Please refer to [the diagram]. Figure 8 In one optional embodiment of this disclosure, the pixel driving circuit 00 further includes a first reset transistor M7, the first terminal of the first reset transistor M7 is connected to the first reset signal terminal VREF1, the second terminal of the first reset transistor M7 is connected to the anode Anode of the light-emitting element D0, and the gate of the first reset transistor M7 is used to receive the reset control signal RST.

[0050] It should be noted that, Figure 8 The illustrated embodiment uses P-type transistors as an example, where the driving transistor M1, the first light-emitting control transistor M6, and the first reset transistor M7 are all P-type transistors. The gate of a P-type transistor turns on in response to a low-level signal and turns off in response to a high-level signal. In some other embodiments of this disclosure, at least one of the driving transistor M1, the first light-emitting control transistor M6, and the first reset transistor M7 may also be an N-type transistor. This disclosure does not specifically limit this; the gate of an N-type transistor turns on in response to a high-level signal and turns off in response to a low-level signal. Please refer to... Figure 8 and Figure 6 In actual driving, the second valid pulse signal S2 in the reset control signal RST is first provided to the gate of the first reset transistor M7 to turn on the first reset transistor M7. The reset signal transmitted at the first reset signal terminal resets the anode of the light-emitting element D0. After the anode is reset, the first valid pulse signal S1 in the light-emitting control signal EM is provided to the anode of the first light-emitting control transistor M6 to turn on the first light-emitting control transistor M6. The driving current can then be transmitted to the light-emitting element D0 through the first light-emitting control transistor M6 to drive the light-emitting element D0 to emit light.

[0051] Figure 9 The diagram shown is a schematic of a pixel driving circuit 00 provided in an embodiment of this disclosure. Please refer to it. Figure 9 Optionally, the pixel driving circuit 00 provided in this embodiment further includes a second reset transistor M4. The first terminal of the second reset transistor M4 is connected to the second reset signal terminal VREF2, and the second terminal is connected to the gate of the driving transistor M1. The gate of the second reset transistor M4 is connected to the first control terminal Gate. <n-1>This embodiment uses a P-type transistor as an example to illustrate the second reset transistor M4. The gate of the second reset transistor M4 responds to the first control terminal Gate. <n-1>The transistor is turned on by a low-level signal. After being turned on, the reset signal of the second reset signal terminal VREF2 is transmitted to the gate of the driving transistor M1 through the second reset transistor M4, thereby resetting the gate of the driving transistor M1. It should be noted that the first terminal of the transistor mentioned in the embodiments of this disclosure generally refers to the input terminal of the corresponding transistor, and the second terminal of the transistor generally refers to the output terminal of the corresponding transistor.

[0052] Please continue to refer to this. Figure 9 Optionally, the pixel driving circuit 00 further includes a data writing transistor M2 and a threshold compensation transistor M3. This embodiment uses P-type transistors as an example to illustrate this. The first terminal of the data writing transistor M2 is connected to the data signal terminal Data, and the second terminal is connected to the first terminal of the driving transistor M1. The gate of the data writing transistor M2 is connected to the second control terminal Gate. <n>The first and second terminals of the threshold compensation transistor M3 are connected to the second terminal and gate of the driving transistor M1, respectively. The gate of the threshold compensation transistor M3 is connected to the second control terminal. <n>The gates of data write transistor M2 and threshold compensation transistor M3 are both connected to the second control terminal, Gate. <n>When the second control terminal Gate <n>When a valid pulse signal is provided, both the data writing transistor M2 and the threshold compensation transistor M3 are turned on. The signal at the data signal terminal Data is written to the first terminal of the driving transistor M1 and transmitted to the gate of the driving transistor M1 through the threshold compensation transistor M3 to perform threshold compensation on the driving transistor M1, thereby reducing or avoiding the influence of threshold voltage drift on the driving current.

[0053] Optionally, the pixel driving circuit 00 provided in this embodiment further includes a second light-emitting control transistor M5. The first terminal of the second light-emitting control transistor M5 is connected to the first power supply voltage terminal ELVDD, and the second terminal is connected to the first terminal of the driving transistor M1. The gates of the second light-emitting control transistor M5 and the first light-emitting control transistor M6 are connected to the same light-emitting control signal terminal EM. It should be noted that, for the sake of simplicity, the same reference numerals are used to represent the same signal terminal and the signal transmitted by the signal terminal in this embodiment. Both the second light-emitting control transistor M5 and the first light-emitting control transistor M6 are P-type transistors. The light-emitting control signal terminal EM is used to transmit the light-emitting control signal EM mentioned in the foregoing embodiment. When the low-level signal in the light-emitting control signal EM is transmitted to the gates of the first light-emitting control transistor M6 and the second light-emitting control transistor M5, the first light-emitting control transistor M6 and the second light-emitting control transistor M5 are turned on, and a current path is formed between the first power supply voltage terminal ELVDD and the second power supply voltage terminal ELVSS connected to the cathode of the light-emitting element D0. When a second light-emitting control transistor M5 is introduced between the first power supply voltage terminal ELVDD and the first terminal of the driving transistor M1, the second light-emitting control transistor M5 is turned on only during the light-emitting phase and remains off during other periods. This helps to prevent the signal of the first power supply voltage terminal ELVDD from being transmitted to the driving transistor M1 during unnecessary periods, thus affecting the final driving current.

[0054] Figure 10 As shown Figure 9 A timing diagram of the middle pixel driving circuit 00 is shown below. Figure 10 right Figure 9 The operation of the pixel driving circuit 00 in the illustrated embodiment will be described. This pixel driving circuit 00 includes nine operating periods, as detailed below:

[0055] Stage 1: Light-emitting element D0 begins to turn off: The light-emitting control signal EM jumps from low level to high level, and the light-emitting element D0 controlled by the light-emitting control signal EM begins to enter the non-light-emitting stage. Since there are parasitic capacitances at both ends of the light-emitting element D0 and stray capacitances in the driving circuit, the light-emitting element D0 gradually turns off in Stage 1 as shown in the figure.

[0056] Phase 2: Pixel Reset: First Control Signal Gate <n-1>The transition from high to low level is used to reset the gate of the driving transistor M1 in the pixel driving circuit 00, thus ensuring better pixel current uniformity.

[0057] Phase 3: Pixel compensation and data writing, and anode reset of the light-emitting element: Second control signal Gate <n>When the signal transitions from high to low, both the data writing transistor M2 and the threshold compensation transistor M3 are turned on. The data signal to be emitted is written to the Data terminal. Simultaneously, the unidirectional conduction of the threshold compensation transistor M3 compensates for the threshold voltage Vth of the driving transistor M1. The reset control signal RST also turns on the first reset transistor M7, writing the reset signal VREFN from the first reset signal terminal to the anode Anode of the light-emitting element D0, thus completely turning off the light-emitting element D0.

[0058] Phase 4: High Emission Control Signal EM Maintenance Phase: This phase is the maintenance phase from the anode reset of the light-emitting element D0 until the light-emitting control signal EM goes low.

[0059] Stage 5: The light-emitting element D0 starts to emit light: In this stage, the light-emitting control signal EM changes from high level to low level, which is equivalent to the appearance of the first valid pulse signal S1. The light-emitting current generated by the driving transistor M1 begins to flow through the anode of the light-emitting element D0. Due to the stray capacitance inside the pixel and the parasitic capacitance of the light-emitting element D0, the voltage of the anode of the light-emitting element D0 will gradually rise until it reaches the forward conduction voltage of the light-emitting element D0, and then the voltage of the anode of the light-emitting element D0 will tend to stabilize.

[0060] Stage 6: The light-emitting element D0 emits light stably.

[0061] Phase 7: The light-emitting control signal EM transitions from low to high again. This phase repeats the operation of Phase 1, and the light-emitting element D0 gradually turns off.

[0062] Phase 8: The pulse high level of the light emission control signal EM is maintained during this phase, which is a repetition of Phase 4.

[0063] Stage 9: The pulse of the light-emitting control signal EM changes from high to low, which is equivalent to the appearance of another first effective pulse signal S1. The operation of this stage is the same as that of stage 5. During this stage, the light-emitting element D0 will gradually turn on.

[0064] Please continue to refer to this. Figure 9 and Figure 10 When using a pixel driving circuit to drive the light-emitting element to emit light, the corresponding pixel driving circuit only includes one data writing transistor M2. During the data writing stage, only one data writing is required to the data writing transistor M2. No other data writing transistors are introduced, so there is no need to perform two data writing processes. In other words, when driving the light-emitting element to emit light, only one data writing process needs to be performed. Compared with the related technology, which introduces both PWM circuit and PAM circuit to perform two data writing processes, the display panel disclosed in this invention simplifies the data transmission logic, reduces the amount of data transmitted, and thus helps to reduce bandwidth and increase the maximum light-emitting time.

[0065] Figure 11 The diagram shown is a partial schematic of another pixel driving circuit 00 provided in an embodiment of this disclosure. Please refer to [the diagram]. Figure 11 In one optional embodiment of this disclosure, the pixel driving circuit 00 includes a driving transistor M1, a first light-emitting control transistor M6, and a pre-charging module 10, wherein the connection method of the driving transistor M1 and the first light-emitting control transistor M6 is the same as... Figure 8 The embodiments shown are the same; for specific connection relationships, please refer to [reference needed]. Figure 7 Description of the illustrated embodiments, Figure 11 The illustrated embodiment is equivalent to in Figure 7 Based on the illustrated embodiment, a pre-charging module 10 is added. The first end of the pre-charging module 10 is connected to the pre-charging voltage terminal VREFP, the second end of the pre-charging module 10 is connected to the anode of the light-emitting element D0, and the control terminal of the pre-charging module 10 is connected to the pre-charging control signal terminal PCG. When the pre-charging module 10 is introduced into the pixel driving circuit 00 of this embodiment, the anode of the light-emitting element D0 can be pre-charged by the pre-charging module 10 before the light-emitting element D0 emits light, that is, before sending the first effective pulse signal S1 to the first light-emitting control transistor M6, thereby increasing the potential of the anode of the light-emitting element D0. For the light-emitting element D0, its anode voltage needs to reach a preset voltage value to achieve light emission. When current is supplied to the light-emitting element D0, the voltage of the anode of the light-emitting element D0 usually has a ramp-up process, gradually increasing until it reaches the preset voltage value before emitting light. In this embodiment of the invention, when a pre-charging module is introduced, the anode of the light-emitting element D0 can be pre-charged before light emission, thereby increasing the potential of the anode of the light-emitting element D0. In this way, during the light emission stage, the time to charge the potential of the anode of the light-emitting element D0 to a preset voltage value can be shortened, which helps to shorten the waiting time from when the pixel driving circuit 00 receives the first valid pulse signal S1 to when the light-emitting element D0 emits light stably.

[0066] Figure 12 The diagram shown is a partial schematic of another pixel driving circuit 00 provided in an embodiment of this disclosure. Please refer to [the diagram]. Figure 12 In one optional embodiment of this disclosure, the pixel driving circuit 00 includes a driving transistor M1, a first light-emitting control transistor M6, a first reset transistor M7, and a pre-charge module 10, which is equivalent to... Figure 11 The embodiment shown is based on the addition of a first reset transistor M7, and... Figure 11 The similarities in the embodiments will not be repeated. In actual driving, the first reset transistor M7 is first turned on to reset the anode of the light-emitting element D0. Then, the pre-charge module 10 is turned on to pre-charge the anode of the light-emitting element D0 to a preset voltage. Finally, the first light-emitting control transistor M6 is turned on to drive the light-emitting element D0 to emit light. Due to the introduction of the pre-charge module 10, the waiting time from when the pixel driving circuit 00 receives the first valid pulse signal S1 to when the light-emitting element D0 emits light stably is effectively shortened, which helps to extend the duration of stable light emission of the light-emitting element D0, thereby improving the brightness.

[0067] Figure 13 The diagram shown illustrates the timing relationship between the light emission control signal EM, the reset control signal RST, and the precharge control signal PCG. Please refer to the diagram. Figure 12 and Figure 13 In one optional embodiment of this disclosure, the pixel driving circuit 00 is further configured to receive a precharge control signal PCG via a precharge control signal terminal PCG. The precharge control signal PCG includes N third effective pulse signals S3; each pulse period also includes one third effective pulse signal S3. In each pulse period H0, the third effective pulse signal S3 is located between the first effective pulse signal S1 and the second effective pulse signal S2. It should be noted that the pulse period H0 is also for a pixel circuit row. The definition of the pulse period H0 can be referred to the aforementioned embodiments, and will not be repeated in this embodiment. Among them, the first effective pulse signal S1 is a signal that controls the first light-emitting control transistor M6 to turn on, thereby causing the light-emitting element D0 to emit light; the second effective pulse signal S2 is a signal that controls the first reset transistor M7 to turn on, thereby resetting the anode of the light-emitting element D0; and the third effective pulse signal S3 is a signal that controls the precharge module 10 to turn on, thereby precharging the anode of the light-emitting element D0.

[0068] Please continue to combine Figure 12 and Figure 13 In each pulse cycle H0, the second effective pulse signal S2 comes first, the third effective pulse signal S3 is in the middle, and the first effective pulse signal S1 comes last. That is, in actual operation, the anode of the light-emitting element D0 is first reset, completely turning off D0. Then, the pre-charging module 10 pre-charges the anode of D0, raising its potential to a fixed voltage value. Finally, the first light-emitting control transistor M6 is turned on, allowing the driving current to flow to the anode of D0, further raising its potential until it reaches the preset voltage value, at which point light emission is achieved. It is evident that by introducing the pre-charging module 10, the time from receiving the first effective pulse signal S1 to charging the anode of D0 to the preset voltage value for stable light emission is reduced. Thus, within the time corresponding to the first effective pulse signal S1 with a preset pulse width, the stable light emission time of the light-emitting element D0 is effectively increased, thereby improving the overall display effect of the display panel.

[0069] Optionally, the pre-charge module 10 includes a pre-charge transistor M8. The first terminal of the pre-charge transistor M8 is connected to the pre-charge voltage terminal VREFP, the second terminal is connected to the anode of the light-emitting element D0, and the gate is connected to the pre-charge control signal terminal PCG. This embodiment uses a P-type transistor as an example. For a P-type transistor, the low-level signal in the pre-charge control signal provided by the pre-charge control signal terminal PCG is a valid pulse signal, and the high-level signal is an invalid pulse signal. In some other embodiments of this disclosure, the pre-charge transistor M8 may also be an N-type transistor, and this disclosure does not specifically limit it to this type.

[0070] Figure 14 The diagram shown is another schematic diagram of the pixel driving circuit provided in the embodiment of this disclosure. The difference between this circuit and the embodiment shown in 9 is that a pre-charging module 10 is added. The other structures are the same, and the structural similarities will not be described again. Figure 15 As shown Figure 14 A timing diagram of the middle pixel driving circuit 00 is shown below. Figure 15 right Figure 14 The operation of the pixel driving circuit 00 in the illustrated embodiment will be described. This pixel driving circuit 00 includes nine operating periods, as detailed below:

[0071] Phase 1: Light-emitting element D0 begins to turn off: The light-emitting control signal EM transitions from low to high. Controlled by the high-level signal in EM, light-emitting element D0 enters the non-light-emitting stage. Due to parasitic capacitance across light-emitting element D0 and stray capacitance in the pixel drive circuit 00, therefore... Figure 15 Phase 1 shown is gradually closing.

[0072] Phase 2: Pixel Reset: First Control Signal Gate <n-1>The transition from high to low level is used to reset the gate of the driving transistor M1 in the pixel driving circuit 00, thus ensuring better pixel current uniformity.

[0073] Phase 3: Pixel compensation and data writing, and anode reset of light-emitting element D0: Second control signal Gate <n>When the signal transitions from high to low, both the data writing transistor M2 and the threshold compensation transistor M3 are turned on. The data signal to be emitted is written to the Data terminal, while the threshold voltage Vth of the driving transistor M1 is compensated by the unidirectional conduction of the threshold compensation transistor M3. Simultaneously, the reset control signal RST turns on the first reset transistor M7, writing the reset signal VREFN voltage to the Anode, thus completely turning off the light-emitting element D0.

[0074] Phase 4: The light emission control signal EM is in a high-sustaining phase, and pre-charging is performed: This phase is the sustaining phase from the anode reset of the light emission element D0 to the low-sustaining phase before the light emission control signal EM goes low. Just before the light emission control signal EM is about to transition from high to low, the pre-charge control signal PCG transitions from high to low, and the third valid pulse signal S3 appears. The pre-charge control transistor is turned on, and the pre-charge voltage signal of the pre-charge voltage terminal VREFP is written to the anode Anode of the light emission element D0. This can reduce the voltage difference of the anode Anode of the light emission element D0 during the subsequent light emission phase from low to high charging, and reduce the waiting time from the output of the first valid pulse signal S1 of the light emission control signal EM to the stable light emission phase of the light emission element D0.

[0075] Stage 5: Light-emitting element D0 begins to emit light: In this stage, the light-emitting control signal EM changes from high to low, equivalent to the appearance of the first valid pulse signal S1. The light-emitting current generated by driving transistor M1 begins to flow through the anode of light-emitting element D0. Due to the stray capacitance inside the pixel and the parasitic capacitance of light-emitting element D0, the voltage of the anode of light-emitting element D0 will gradually rise until it reaches the forward conduction voltage of light-emitting element D0, after which the voltage of the anode of light-emitting element D0 will tend to stabilize. Because of the introduction of the pre-charge module 10, Figure 15 The time required for Phase 5 will be less than Figure 10 The time required for stage 5 in the timing sequence is reduced, which means reducing the time required from the first light-emitting control transistor M6 being turned on to the light-emitting element D0 emitting stable light.

[0076] Stage 6: The light-emitting element D0 emits light stably.

[0077] Stage 7: The light-emitting control signal EM transitions from low to high again, and the reset control signal RST transitions from high to low, controlling the first reset transistor M7 to turn on, writing the reset signal VREFN voltage at the first reset signal terminal to Anode, and the light-emitting element D0 is completely turned off.

[0078] Phase 8: High-level pulse maintenance phase of the light emission control signal EM. This phase repeats the operation of phase 4. Pre-charging is performed before the arrival of the first valid pulse signal S1 of the light emission control signal EM to reduce the waiting time before stable light emission.

[0079] Stage 9: The pulse of the light-emitting control signal EM changes from high to low, which is equivalent to the appearance of another first effective pulse signal S1. The operation of this stage is the same as that of stage 5. During this stage, the light-emitting element D0 will gradually turn on.

[0080] Please refer to Figure 14 and Figure 15 When a pre-charge module is introduced into the pixel driving circuit, it is similar to... Figure 9 and Figure 10 Compared to the previous embodiment, the present embodiment adds a pre-charging process for the anode of the light-emitting element before the light-emitting stage. However, the corresponding pixel driving circuit also only includes one data writing transistor M2. During the data writing stage, only one data writing is required to the data writing transistor M2. No other data writing transistors are introduced, and there is no need to perform two data writing processes. That is to say, when driving the light-emitting element to emit light, only one data writing process needs to be performed. Compared to the related technology's scheme of simultaneously introducing PWM circuits and PAM circuits to perform two data writing processes, the display panel of this disclosure simplifies the data transmission logic, reduces the amount of data transmitted, and thus helps to reduce bandwidth and increase the maximum light-emitting time.

[0081] Please continue to refer to this. Figure 14 In one optional embodiment of this disclosure, the voltage value of the pre-charge voltage terminal VREFP is greater than the voltage value of the first reset signal terminal VREFN. After resetting the anode of the light-emitting element D0 using the signal from the first reset signal terminal VREFN, the potential of the anode of the light-emitting element D0 will be reflected as the potential corresponding to the voltage value of the first reset signal terminal VREFN, assuming it is V0. Assuming the voltage value of the pre-charge voltage terminal is V1, and the preset voltage value required for the light-emitting element D0 to emit light is V2, then V0 < V2, V1 < V2. In this embodiment of the disclosure, V0 < V1 < V2 is further set, which is equivalent to raising the potential of the anode of the light-emitting element D0 from voltage V0 to voltage V1 through the pre-charge module 10, making it closer to the preset voltage value V2 required for the light-emitting element D0 to emit light. Thus, during the light-emitting stage, when the first light-emitting control transistor M6 is turned on and the driving current is transmitted to the anode of the light-emitting element D0 to further charge the anode, it is only necessary to increase the voltage of the anode from V1 to V2, without having to increase it from V0 to V2. Since the difference between V2 and V1 is smaller than the difference between V2 and V0, it is beneficial to shorten the time required from receiving the first effective pulse signal S1 from the pixel driving circuit 00 to the stable light emission of the light-emitting element D0.

[0082] Please refer to Figure 9 and Figure 10 In one optional embodiment of this disclosure, the pulse widths of the different second effective pulse signals S2 are the same. The second effective pulse signal S2 is a pulse that controls the first reset transistor M7 to turn on. In the reset control signal RST corresponding to a row pixel driving circuit, setting the pulse widths of the different second effective pulse signals S2 to be the same ensures that the duration of each reset of the anode of the light-emitting element D0 is the same. This helps to ensure the reliability of the anode reset and ensure that the light-emitting element D0 is reliably turned off, and also helps to simplify the anode reset control timing.

[0083] Please refer to Figure 14 and Figure 15 In one optional embodiment of this disclosure, the pulse widths of the different third effective pulse signals S3 are the same. The third effective pulse signal S3 is a pulse that controls the pre-charge module 10 to be turned on. In the pre-charge control signal PCG corresponding to the row pixel driving circuit 00, the widths of the different third effective pulse signals S3 are set to be the same, so that the time for pre-charging the anode of the light-emitting element D0 is the same each time. This makes the potential of the anode of the light-emitting element D0 the same before it emits light. During the light-emitting stage, the anode of the light-emitting element D0 corresponding to the row pixel driving circuit is charged based on the same initial potential to achieve light emission, which is beneficial to improving the accuracy of light emission of the light-emitting element D0.

[0084] Figure 16 The diagram shown is a timing diagram of the light emission control signal and reset control signal corresponding to the Nth pixel circuit row. Please refer to it. Figure 4 , Figure 9 and Figure 16 In one optional embodiment of this disclosure, the first effective pulse signal S1 corresponding to the pixel circuit row 80 includes a first type of pulse signal S11 and a second type of pulse signal S12, wherein the pulse width of the first type of pulse signal S11 is greater than the pulse width of the second type of pulse signal S12; the output current of different pixel driving circuits 00 corresponding to the pixel circuit row 80 includes a first type of current and a second type of current, wherein the current value of the first type of current is greater than the current value of the second type of current. When the display panel actually emits light, the grayscale of different light-emitting elements D0 corresponding to a pixel row may differ. This embodiment takes as an example that some light-emitting elements D0 with low grayscale require less current, while some light-emitting elements D0 with high grayscale require more current. It should be noted that, in this embodiment, the first type of current and the second type of current output by different pixel driving circuits 00 in a pixel circuit row 80 can refer to the fact that, among the different pixel driving circuits 00 corresponding to a pixel row, some pixel driving circuits 00 output the same current value, which is a larger current, while other pixel driving circuits 00 output the same current value, which is a smaller current; it can also refer to dividing the current values ​​output by different pixel driving circuits 00 in a pixel circuit row into two categories: the first type of current includes multiple currents with all larger current values, and the second type of current includes multiple currents with smaller current values. In other words, at least two pixel driving circuits 00 in a pixel driving circuit 00 output different current values, which are of different magnitudes. The currents with larger current values ​​belong to the first type of current, and the currents with smaller current values ​​belong to the second type of current.

[0085] In this embodiment, the light-emitting element D0 receiving the first type of current emits light in response to the first type of pulse signal S11 or the second type of pulse signal S12, and the light-emitting element D0 receiving the second type of current emits light in response to the first type of pulse signal S11. Considering that the grayscale requirements and current requirements of different light-emitting elements D0 in a pixel circuit row are not exactly the same, in this embodiment, the pulse widths of the multiple first effective pulse signals S1 of the light emission control signal EM corresponding to the pixel circuit row 80 are set to be not exactly the same. The first effective pulse signals S1 include the first type of pulse signal S11 with a larger pulse width and the second type of pulse signal S12 with a smaller pulse width. Thus, when each pixel driving circuit 00 in the pixel circuit row 80 receives the first type of pulse signal S11 with a larger pulse width, since the charging time for the anode of the light-emitting element D0 is longer, each light-emitting element D0 receiving the first type of current and the second type of current can emit light. When the grayscale requirement of the light-emitting element D0 receiving the second type of current is low, when each pixel driving circuit 00 in the pixel circuit row 80 receives the second type of pulse signal S12 with a smaller pulse width, the charging time for the anode of the light-emitting element D0 is short, and the current value of the first type of current is large. The light-emitting element D0 receiving the first type of current can still respond to the second type of effective pulse signal and emit light. However, because the current value of the second type of current is small, the light-emitting element D0 receiving the second type of current may not be able to charge to the voltage that makes it emit light in a short time, or the charging time to the voltage that makes it emit light may be short. Therefore, the light-emitting element D0 receiving the second type of current may not emit light or the emission time may be short. Thus, by introducing the first effective pulse signal S1 with different pulse widths, the light-emitting element D0 with high grayscale requirement can have higher brightness, and the light-emitting element D0 with low grayscale requirement can have lower brightness or no light emission. Therefore, it is beneficial to improve the contrast of the display panel.

[0086] Figure 17 The diagram shown is a timing diagram of the light emission control signal, reset control signal, and precharge control signal corresponding to the Nth pixel circuit row. Please refer to... Figure 4 , Figure 14 and Figure 17 In one optional embodiment of this disclosure, the pixel driving circuit 00 is further configured to receive a precharge control signal PCG, which includes N third effective pulse signals S3; each pulse period also includes a third effective pulse signal S3, and in each pulse period, the third effective pulse signal S3 is located between the first effective pulse signal S1 and the second effective pulse signal S2; the light-emitting element D0 receiving the second type of current emits light in response to the second type of pulse signal S12.

[0087] When a pre-charge module 10 is introduced into the pixel driving circuit 00, after resetting the anode of the light-emitting element D0 and before sending the first effective pulse signal S1 to the first light-emitting control transistor N7, the pre-charge module 10 is first turned on by the pre-charge control signal PCG to pre-charge the anode of the light-emitting element D0, thereby increasing the potential of the anode of the light-emitting element D0. After receiving the first effective pulse signal S1, the potential of the anode of the light-emitting element D0 can be increased to the potential that makes it emit light in a shorter time, that is, the time from receiving the first effective pulse signal S1 to the light-emitting element D0 stabilizing to emit light can be saved. At this time, for the light-emitting element D0 with low grayscale requirements, although the charging time of the anode of the light-emitting element D0 in the light-emitting stage is shortened after receiving the second type of pulse signal S12 with a smaller pulse width, the light-emitting element D0 can respond to the second type of pulse signal S12 and emit light because the light-emitting element D0 enters the stable light-emitting stage in the light-emitting stage for a shorter time. However, because the light-emitting duration is short, the low grayscale requirement of the light-emitting element D0 can still be met.

[0088] Figure 18 The diagram shows another timing diagram of the light emission control signal and reset control signal corresponding to the Nth pixel circuit row. Figure 19 The diagram shown is a timing diagram illustrating the change in anode voltage of a light-emitting element under different current conditions. Please refer to... Figure 4 , Figure 9 , Figure 18 and Figure 19 In one optional embodiment of this disclosure, the first effective pulse signal S1 corresponding to the pixel circuit row 80 includes a first type pulse signal S11, a second type pulse signal S12, and a third type pulse signal S13. The pulse width of the first type pulse signal S11 is greater than the pulse width of the second type pulse signal S12, and the pulse width of the second type pulse signal S12 is greater than the pulse width of the third type pulse signal S13. The output current of the different pixel driving circuits 00 corresponding to the pixel circuit row 80 includes a first type current, a second type current, and a third type current. The current value of the first type current is greater than the current value of the second type current, and the current value of the second type current is greater than the current value of the third type current. The light-emitting element D0 receiving the first type current emits light in response to the first type pulse signal S11, the second type pulse signal S12, or the third type pulse signal S13. The light-emitting element D0 receiving the second type current emits light in response to the first type pulse signal S11 or the second type pulse signal S12. The light-emitting element D0 receiving the third type current emits light in response to the first type pulse signal S11.

[0089] In this embodiment, a first type of pulse signal S11, a second type of pulse signal S12, and a third type of pulse signal S13 are introduced. This is equivalent to dividing the multiple first effective pulse signals S1 corresponding to the pixel circuit row 80 into three categories according to their pulse widths. Among them, the pulse width corresponding to the first type of pulse signal S11 is the largest, the pulse width corresponding to the second type of pulse signal S12 is in the middle, and the pulse width corresponding to the third type of pulse signal S13 is the smallest. Correspondingly, the output current of different pixel driving circuits 00 in the pixel circuit row 80 is also divided into three categories. Among them, the current value corresponding to the first type of current is the largest, the current value corresponding to the second type of current is in the middle, and the current value corresponding to the third type of current is the smallest. Referring to the table below, assuming that different pixel driving circuits 00 in a pixel circuit row 80 simultaneously output the above three levels of current, when these currents are modulated by the above three levels of first effective pulse signals S1, the following three situations will exist:

[0090] In the first type of current, i.e., under high current conditions, the pixel driving circuit 00 can complete the charging of the internal parasitic capacitance of the corresponding light-emitting element D0 within the time corresponding to the first effective pulse signal S1 of the above three levels, and can charge the anode voltage of the light-emitting element D0 to a value greater than the preset voltage value required for the light-emitting element D0 to emit light.

[0091] In the second type of current, i.e., the medium current condition, the pixel driving circuit 00 can complete the charging of the internal parasitic capacitance of the corresponding light-emitting element D0 within the time corresponding to the first type of pulse signal S11 and the second type of pulse signal S12, and can charge the anode voltage of the light-emitting element D0 to a value greater than the preset voltage value required for the light-emitting element D0 to emit light. However, because the pulse width of the third type of pulse signal S13 is small and the charging time is short, the corresponding light-emitting element D0 does not emit light. Thus, the light-emitting time of the light-emitting element D0 receiving the second type of current can be modulated by the first type of pulse signal S11 and the second type of pulse signal S12.

[0092] In the third type of current, i.e., under low current conditions, the pixel driving circuit 00 can complete the charging of the internal parasitic capacitance of the corresponding light-emitting element D0 within the time corresponding to the first type of pulse signal S11, and can charge the anode voltage of the light-emitting element D0 to a value greater than the preset voltage value required for the light-emitting element D0 to emit light. However, due to the small pulse widths of the second type of pulse signal S12 and the third type of pulse signal S13, the corresponding light-emitting element D0 does not emit light during the charging time compared to the first type of pulse signal S11. Thus, the light-emitting time of the light-emitting element D0 receiving the third type of current is modulated by the first type of pulse signal S11. At this time, the grayscale of the light-emitting element D0 receiving the third type of current can be lowered, thereby improving the contrast of the display panel.

[0093] Table 1 Light emission status

[0094]

[0095] Figure 20 The diagram shown is another timing diagram of the light emission control signal, reset control signal, and precharge control signal corresponding to the Nth pixel circuit row. Figure 21 The figure shown is a timing diagram illustrating the change in anode voltage of the light-emitting element under different current conditions after the introduction of the pre-charging module. Figure 22 The diagram shown is another timing diagram illustrating the change in anode voltage of the light-emitting element under different current conditions after the introduction of the pre-charging module. Please refer to it. Figure 4 , Figure 14 , Figure 20 , Figure 21 and Figure 22 In one optional embodiment of this disclosure, the pixel driving circuit 00 is further configured to receive a precharge control signal PCG, the precharge control signal PCG including N third effective pulse signals S3; each pulse period H0 also includes a third effective pulse signal S3, and in each pulse period, the third effective pulse signal S3 is located between the first effective pulse signal S1 and the second effective pulse signal S2; the light-emitting element D0 receiving the second type of current emits light in response to the third type of pulse signal S13; and / or, the pixel driving circuit 00 receiving the third type of current emits light in response to the second type of pulse signal S12 or the third type of pulse signal S13.

[0096] When a pre-charge module 10 is introduced into the pixel driving circuit 00, after resetting the anode of the light-emitting element D0 and before sending the first valid pulse signal S1 to the first light-emitting control transistor T7, the pre-charge module 10 is first turned on by the pre-charge control signal PCG to pre-charge the anode of the light-emitting element D0, thereby increasing the potential of the anode of the light-emitting element D0. After receiving the first valid pulse signal S1, the potential of the anode of the light-emitting element D0 can be increased to the potential required for it to emit light within a short time, thus saving the time from receiving the first valid pulse signal S1 to the stable emission of the light-emitting element D0. At this time, for the light-emitting element D0 with low grayscale requirements, after receiving the second type of pulse signal S12 or the third type of pulse signal S13 with a smaller pulse width, although the charging time of the anode of the light-emitting element D0 during the light-emitting stage becomes shorter, the light-emitting element D0 can still emit light in response to the third type of pulse signal S13 because the time for the light-emitting element D0 to enter the stable light-emitting stage during the light-emitting stage is also shorter. The pixel driving circuit 00 that receives the third type of current can also emit light in response to the second type of pulse signal S12 or the third type of pulse signal S13, which can still meet the medium or low grayscale requirements of these light-emitting elements D0.

[0097] Referring to the table below, assuming that different pixel driving circuits 00 in row 80 of a pixel circuit simultaneously output the current at the above three levels, and these currents are modulated by the first effective pulse signal S1 of the above three levels, the following three situations will exist:

[0098] In the first type of current, i.e., under high current conditions, the pixel driving circuit 00 can complete the charging of the internal parasitic capacitance of the corresponding light-emitting element D0 within the time corresponding to the first effective pulse signal S1 of the above three levels, and can charge the anode voltage of the light-emitting element D0 to a value greater than the preset voltage value required for the light-emitting element D0 to emit light. Moreover, due to the introduction of the pre-charging module, the time from receiving the first effective pulse control signal to the light-emitting element D0 stabilizing to emit light is effectively shortened.

[0099] In the second type of current, i.e., the medium current condition, the pixel driving circuit 00 can complete the charging of the internal parasitic capacitance of the corresponding light-emitting element D0 within the time corresponding to the first type of pulse signal S11 and the second type of pulse signal S12, and can charge the anode voltage of the light-emitting element D0 to a value greater than the preset voltage value required for the light-emitting element D0 to emit light. Because of the introduction of the pre-charging module, even though the pulse width of the third type of pulse signal S13 is small and the charging time is short, the pre-charging module has already raised the anode potential of the light-emitting element D0. The time from receiving the first light-emitting control signal EM to the light-emitting element D0 stabilizing to emit light can be determined by setting the voltage value of the pre-charging voltage signal provided by the pre-charging module to the anode of the light-emitting element D0. Therefore, for the light-emitting element D0 receiving the second type of current, if the pre-charging voltage signal is large, its turn-on time is relatively short, and it can emit light when the third type of pulse signal S13 is received; if the pre-charging voltage signal is small, its turn-on time is relatively long, and it cannot emit light when the third pulse signal is received. Thus, the light-emitting time of the light-emitting element D0 that receives the second type of current can be modulated by the first type of pulse signal S11 and the second type of pulse signal S12. At the same time, it can be determined whether it can respond to the third type of pulse signal S13 and emit light based on the electrostatic value of the precharge voltage.

[0100] In the third type of current, i.e., under low current conditions, the pixel driving circuit 00 can complete the charging of the internal parasitic capacitance of the corresponding light-emitting element D0 within the time corresponding to the first type of pulse signal S11, and can charge the anode voltage of the light-emitting element D0 to a value greater than the preset voltage value required for the light-emitting element D0 to emit light. Because of the introduction of the pre-charging module 10, even though the pulse widths of the second type of pulse signal S12 and the third type of pulse signal S13 are both smaller than the pulse width of the first type of pulse signal S11, resulting in a shorter charging time, the pre-charging module has already raised the anode potential of the light-emitting element D0. Therefore, the time from receiving the first light-emitting control signal EM to the stable light emission of the light-emitting element D0 can be determined by setting the voltage value of the pre-charging voltage signal provided by the pre-charging module to the anode of the light-emitting element D0. Therefore, for the light-emitting element D0 receiving the third type of current, if the pre-charge voltage signal is relatively large, its turn-on time is relatively short, and it can emit light upon receiving the second type of pulse signal S12 or the third type of pulse signal S13; if the pre-charge voltage signal is relatively small, its turn-on time is relatively long, and it cannot emit light upon receiving the second type of pulse signal S12 or the third type of pulse signal. Thus, the light-emitting time of the light-emitting element D0 receiving the third type of current can be modulated by the first type of pulse signal S11, and the ability to emit light in response to the second type of pulse signal S12 and the third type of pulse signal S13 can be determined based on the electrophoretic value of the pre-charge voltage. In other words, the magnitude of the pre-charge voltage signal can determine whether the light-emitting element D0 corresponding to a small current emits light, thereby improving the modulation accuracy.

[0101] Table 2 Light emission status

[0102]

[0103] Based on the same inventive concept, this disclosure provides a display device. Figure 23 The diagram shows a structural schematic of a display device provided in an embodiment of this disclosure. The display device 200 includes the display panel 100 provided in the above embodiments of this disclosure. The display device 200 provided in the embodiments of this disclosure can be any electronic device with display function, such as a tablet computer, mobile phone, television, or vehicle display device with touch and display functions. The display device 200 provided in the embodiments of this disclosure has the beneficial effects of the display panel 100 provided in the embodiments of this disclosure. For details, please refer to the specific descriptions of the display panel 200 in the above embodiments, which will not be repeated here.

[0104] Understandable Figure 23 The display device is illustrated only with a rectangular structure. In some other embodiments of this disclosure, the display device 200 may also be embodied as a rounded rectangle, a circle, an ellipse or any other feasible shape, and this disclosure does not specifically limit it in this way.

[0105] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0106] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A display panel, characterized in that, The device includes multiple rows of pixel circuits, each row of pixel circuits including multiple pixel driving circuits; the pixel driving circuits are electrically connected to the light-emitting element, and the pixel driving circuits are at least used to receive a light-emitting control signal, the light-emitting control signal being configured to control the light-emitting element to emit light; The light emission control signal corresponding to at least one of the pixel circuit rows includes N first effective pulse signals, at least two of the first effective pulse signals have different pulse widths, and N≥2; within one frame, among the light emission elements corresponding to at least one of the pixel circuit rows, at least two of the light emission elements have different gray levels, and the light emission elements with different gray levels respectively receive the first effective pulse signals.

2. The display panel according to claim 1, characterized in that, The pixel driving circuit is also used to receive a reset control signal, which is configured to reset the anode of the light-emitting element; The reset control signal corresponding to at least one of the pixel circuit rows includes N second valid pulse signals; The pixel driving circuit includes N pulse cycles, each pulse cycle including a first effective pulse signal and a second effective pulse signal, wherein in each pulse cycle, the second effective pulse signal is located before the first effective pulse signal.

3. The display panel according to claim 2, characterized in that, The pulse widths of the different second effective pulse signals are the same.

4. The display panel according to claim 2, characterized in that, The pixel driving circuit includes a driving transistor and a first light-emitting control transistor. The first terminal of the driving transistor is coupled to a first power supply voltage terminal, the second terminal of the driving transistor is electrically connected to the first terminal of the first light-emitting control transistor, the second terminal of the first light-emitting control transistor is electrically connected to the anode of the light-emitting element, the gate of the first light-emitting control transistor is used to receive the light-emitting control signal, and the cathode of the light-emitting element is connected to a second power supply voltage terminal.

5. The display panel according to claim 4, characterized in that, The pixel driving circuit further includes a first reset transistor, the first terminal of which is connected to a first reset signal terminal, the second terminal of which is connected to the anode of the light-emitting element, and the gate of which is used to receive the reset control signal.

6. The display panel according to claim 4 or 5, characterized in that, The pixel driving circuit further includes a pre-charge module, the first end of which is connected to a pre-charge voltage terminal, the second end of which is connected to the anode of the light-emitting element, and the control terminal of which is connected to a pre-charge control signal terminal.

7. The display panel according to claim 6, characterized in that, When the pixel driving circuit includes both the pre-charge module and the first reset transistor, the voltage value of the pre-charge voltage terminal is greater than the voltage value of the first reset signal terminal.

8. The display panel according to claim 6, characterized in that, The pixel driving circuit is further configured to receive a precharge control signal via the precharge control signal terminal, the precharge control signal comprising N third effective pulse signals; each pulse period further comprising one third effective pulse signal, wherein in each pulse period, the third effective pulse signal is located between the first effective pulse signal and the second effective pulse signal.

9. The display panel according to claim 8, characterized in that, The pulse widths of the different third effective pulse signals are the same.

10. The display panel according to claim 2, characterized in that, The first effective pulse signal corresponding to the pixel circuit row includes a first type of pulse signal and a second type of pulse signal, wherein the pulse width of the first type of pulse signal is greater than the pulse width of the second type of pulse signal; The output current of the different pixel driving circuits corresponding to the pixel circuit row includes a first type of current and a second type of current, wherein the current value of the first type of current is greater than the current value of the second type of current. The light-emitting element receiving the first type of current emits light in response to the first type of pulse signal or the second type of pulse signal, and the light-emitting element receiving the second type of current emits light in response to the first type of pulse signal.

11. The display panel according to claim 10, characterized in that, The pixel driving circuit is also used to receive a precharge control signal, which includes N third effective pulse signals; each pulse period also includes one third effective pulse signal, and in each pulse period, the third effective pulse signal is located between the first effective pulse signal and the second effective pulse signal; the pixel driving circuit receiving the second type of current can also emit light in response to the second type of pulse signal.

12. The display panel according to claim 2, characterized in that, The first effective pulse signal corresponding to the pixel circuit row includes a first type of pulse signal, a second type of pulse signal, and a third type of pulse signal. The pulse width of the first type of pulse signal is greater than the pulse width of the second type of pulse signal, and the pulse width of the second type of pulse signal is greater than the pulse width of the third type of pulse signal. The output current of the different pixel driving circuits corresponding to the pixel circuit row includes a first type of current, a second type of current, and a third type of current. The current value of the first type of current is greater than the current value of the second type of current, and the current value of the second type of current is greater than the current value of the third type of current. The light-emitting element receiving the first type of current emits light in response to the first type of pulse signal, the second type of pulse signal, or the third type of pulse signal; the light-emitting element receiving the second type of current emits light in response to the first type of pulse signal or the second type of pulse signal; and the light-emitting element receiving the third type of current emits light in response to the first type of pulse signal.

13. The display panel according to claim 12, characterized in that, The pixel driving circuit is also used to receive a precharge control signal, which includes N third effective pulse signals; each pulse period also includes one third effective pulse signal, and in each pulse period, the third effective pulse signal is located between the first effective pulse signal and the second effective pulse signal; The light-emitting element that receives the second type of current emits light in response to the third type of pulse signal; And / or, the light-emitting element that outputs the third type of current emits light in response to the second type of pulse signal or the third type of pulse signal.

14. A display device, characterized in that, Includes the display panel described in any one of claims 1 to 13.

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