Display device

Abstract

In some examples, the display device includes: a display panel including a display area and a non-display area located outside the display area; a connection area disposed in the non-display area, to which a flexible circuit board is attached; a data link line disposed in the non-display area and connected to the display area; and a pad electrode disposed in the non-display area and electrically connected to the flexible circuit board. The connection area may include a first area adjacent to the display area and a second area located between the first area and an edge of the display panel, with the data link line and the pad electrode connected to the second area of ​​the connection area.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0195682, filed in Korea on December 24, 2024, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices, and more particularly to display devices having a minimum bezel area. Background Technology

[0004] With the advancement of multimedia technology over the years, various display devices have been applied in various settings to achieve various purposes. Various display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays have been developed.

[0005] Since display devices are already used in small mobile electronic devices such as smartphones or tablet PCs, there is a need to minimize the surface area of ​​the bezel or to achieve a bezel-less structure in order to achieve a relatively large display area and a good appearance in a small area. Summary of the Invention

[0006] Therefore, one or more embodiments of this disclosure relate to a display device that substantially eliminates one or more problems caused by limitations and disadvantages attributable to the related art.

[0007] One aspect of this disclosure is to provide a display device with a minimum bezel area.

[0008] Additional features and aspects will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the disclosed concepts provided herein. Other features and aspects of the disclosed concepts may be realized and obtained, or may be derived, from the structures particularly pointed out in the specification and its claims and drawings.

[0009] To achieve these and other aspects of the inventive concept, as embodied and broadly described, in one aspect, this disclosure provides a display device comprising: a display panel including a display area and a non-display area located outside the display area; a connection area disposed in the non-display area of ​​the display panel, to which a flexible circuit board is attached; a data link line disposed in the non-display area of ​​the display panel and connected to the display area; and a pad electrode disposed in the non-display area of ​​the display panel and electrically connected to the flexible circuit board, wherein the connection area includes a first area adjacent to the display area and a second area between the first area and an edge of the display panel, and the data link line and the pad electrode are connected to the second area of ​​the connection area.

[0010] In one embodiment, at least a portion of the data link line may be positioned to overlap with the pad electrode. The display device may also include a shielding electrode disposed between the data link line and the pad electrode. The data link line may be electrically connected to the pad electrode via a contact portion.

[0011] In another embodiment, the data link line may include the same material as the gate electrode, the shield electrode may include the same material as the source electrode and the drain electrode, and / or the pad electrode may include the same material as the connection pattern.

[0012] In another aspect, this disclosure provides a display device, comprising: a display panel including a display area and a non-display area located outside the display area; a flexible circuit board attached to the non-display area of ​​the display panel; a data link line disposed in the non-display area of ​​the display panel and connected to the display area; and a pad electrode disposed in the non-display area of ​​the display panel and electrically connected to the flexible circuit board, wherein the data link line extends to the inside of the flexible circuit board, and at least a portion of the data link line is positioned to overlap with the pad electrode, and an insulating layer is provided between the data link line and the pad electrode.

[0013] In one or more embodiments, the contact portions connecting the data link lines and the pad electrodes for the flexible circuit board are arranged in an area adjacent to the edge of the display panel. A portion of the connection area attached to the flexible circuit board can be used as space for arranging the data link lines. The area of ​​the non-display region around the perimeter of the display panel can be minimized, thus enabling a narrow bezel.

[0014] In addition, since display devices can minimize screen size in the same area, power consumption can be reduced with high efficiency and low power consumption can be implemented.

[0015] It should be understood that the above general description and the following detailed description are illustrative and intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0016] The accompanying drawings, which provide a further understanding of this disclosure, are incorporated in and constitute a part of this application, illustrating embodiments of the disclosure and serving together with the description to explain the principles of the disclosure.

[0017] Figure 1 A schematic block diagram of a display device according to one or more embodiments of the present disclosure is shown.

[0018] Figure 2 A schematic block diagram illustrating sub-pixels in a display device according to one or more embodiments of the present disclosure is shown.

[0019] Figure 3A schematic circuit diagram of a sub-pixel in a display device according to one or more embodiments of the present disclosure is shown.

[0020] Figure 4 A schematic plan view of a display device according to one or more embodiments of the present disclosure is shown.

[0021] Figure 5 Show Figure 4 An enlarged plan view of area "A" in the diagram.

[0022] Figure 6A A schematic display device showing a contact portion located in the upper region of the connection area to which a flexible circuit board is attached.

[0023] Figure 6B A schematic display device showing a contact portion located in the lower region of a connection area attached to a flexible circuit board, according to one or more embodiments of the present disclosure.

[0024] Figure 7 Show along Figure 4 A schematic cross-sectional view of the display device taken by line I-I' in the diagram.

[0025] Figure 8A Show along Figure 5 A schematic cross-sectional view of the display device taken from line II-II' in the diagram.

[0026] Figure 8B Show along Figure 5 A schematic cross-sectional view of the display device taken from line III-III' in the diagram. Detailed Implementation

[0027] The advantages and features of this disclosure, as well as the methods for implementing them, will become clear from the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure is thorough and complete and will fully convey the scope of this disclosure to those skilled in the art to which it pertains.

[0028] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings for describing embodiments of this disclosure are merely illustrative examples, and therefore this disclosure is not limited to the examples shown. Unless otherwise stated, the same reference numerals refer to the same parts throughout this disclosure. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted or briefly discussed if they might unnecessarily obscure the essential points of this disclosure.

[0029] Where terms such as “comprising,” “having,” or “including” are used in this disclosure, additional parts may be added, unless more restrictive terms such as “only” are used herein. Furthermore, unless otherwise stated, where a part is expressed in the singular, the plural is also included, and vice versa.

[0030] When analyzing components, even if not explicitly described, the range of error should be interpreted as included.

[0031] When describing positional relationships, for example, where the positional relationship between two parts / layers is described as "above", "on", "above", "below", "below", "next", etc., one or more additional parts / layers may be provided between the two parts / layers, unless more restrictive terms such as "immediately" or "directly" are used together.

[0032] When describing temporal relationships, such as when the temporal sequence is described as “after,” “following,” “next,” “before,” etc., discontinuous or sequential situations may also be included unless more restrictive terms such as “immediately” or “directly” are used.

[0033] Although the terms first, second, etc., can be used to describe various components, these components are not substantially limited by these terms. These terms are used only to refer to a component separate from another component and may not define any particular order or sequence. Therefore, within the technical spirit of this disclosure, the first component described below can be substantially the second component, and vice versa.

[0034] In describing the components of this disclosure, terms such as first, second, A, B, (a), (b) may be used. These terms are intended only to distinguish a component from other components, and the nature, order, sequence, or number of components is not limited by these terms. When a component is described as being “connected,” “joined,” or “coupled” to another component, it should be understood that the component may be directly connected or attached to another component, but other components may also be “inserted” between the components, or the components may be “connected,” “joined,” or “coupled” through other components.

[0035] Features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, various interlocks and drives are technically possible, and the various embodiments may be implemented independently of each other or together in an interdependent relationship.

[0036] All components of each display device according to all embodiments of this disclosure are operatively coupled and configured.

[0037] As used herein, "display device" or "display apparatus" can include display devices in a narrow sense, such as display modules that include a display panel and driving units for driving the display panel. Furthermore, a display device can also include a set of electronic devices or apparatuses, such as notebook computers, televisions, computer monitors, automotive displays, or displays for other forms of vehicles, which are complete products (or end products) including display modules, equipped displays, mobile electronic devices (such as smartphones or tablets), etc.

[0038] Therefore, the display device in this disclosure may include the display device itself in a narrow sense, such as a display module, and a set of means including the display module as an application product or end consumer device.

[0039] This disclosure is applicable to a variety of display devices. For example, it is applicable to organic light-emitting display devices, liquid crystal display devices, electrophoretic display devices, quantum dot display devices, micro-LED (light-emitting diode) display devices, and mini-LED display devices. For ease of explanation, an organic light-emitting display device may be described as an example of a display device. However, this disclosure is not limited to organic light-emitting display devices.

[0040] Reference will now be made in detail to various aspects of this disclosure, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0041] Figure 1 A schematic block diagram of a display device according to the present disclosure is shown. Figure 2 A schematic block diagram of a subpixel in a display device according to the present disclosure is shown.

[0042] Reference Figure 1 The display device 100 may include an image processor 102, a timing controller 104, a gate driver 106, a data driver 107, a power supply 108, and a display panel PNL.

[0043] The image processor 102 outputs drive signals for driving various components and image data provided from the outside. For example, the drive signals output from the image processor 102 may include, but are not limited to, data enable signals, vertical synchronization signals, horizontal synchronization signals, clock signals, etc.

[0044] The timing controller 104 receives drive signals and image data from the image processor 102. Based on the drive signals input from the image processor 102, the timing controller 104 generates and outputs a gate timing control signal GDC for controlling the operating timing of the gate driver 106 and a data timing control signal DDC for controlling the operating timing of the data driver 107.

[0045] Gate driver 106 outputs a scan signal to display panel PNL in response to a gate timing control signal GDC supplied from timing controller 104. Gate driver 106 outputs the scan signal through multiple gate lines GL1 to GLm (m is an integer greater than or equal to 2). In one embodiment, gate driver 106 may be formed as an integrated circuit (IC), but is not limited thereto.

[0046] Data driver 107 outputs a data voltage to display panel PNL in response to a data timing control signal DDC input from timing controller 104. Data driver 107 samples and latches a digital data signal DATA provided from timing controller 104, and converts the digital data signal DATA into an analog data voltage based on gamma voltage. Data driver 107 outputs the data voltage through multiple data lines DL1-DLn (n is an integer greater than or equal to 2). In one embodiment, data driver 107 may be formed as an integrated circuit (IC), but is not limited thereto.

[0047] Power supply 108 outputs a high-level voltage VDD and a low-level voltage VSS and supplies VDD and VSS to the display panel PNL. The high-level voltage VDD is supplied to the display panel PNL through a first power line EVDD, and the low-level voltage VSS is supplied to the display panel PNL through a second power line EVSS. Alternatively or additionally, the voltage output from power supply 108 may be output to gate driver 106 and / or data driver 107 to drive these drivers 106 and 107.

[0048] The display panel PNL displays images in response to a scan signal supplied from the gate driver 106, a data voltage supplied from the data driver 107, and power supplied from the power supply 108.

[0049] The display panel PNL includes a plurality of subpixels SP for displaying images. In one embodiment, the subpixel SP may include red (R) subpixels, green (G) subpixels, and blue (B) subpixels. Alternatively, the subpixel SP may include white (W) subpixels, red (R) subpixels, green (G) subpixels, and blue (B) subpixels. In one embodiment, the white (W), red (R), green (G), and blue (B) subpixels may have substantially the same area. Alternatively, the white (W), red (R), green (G), and blue (B) subpixels may have different areas.

[0050] Reference Figure 2 Each sub-pixel SP can be connected to gate line GL1, data line DL1, first power line EVDD, and second power line EVSS. The number of transistors and capacitors and the driving method can be determined by the pixel circuit configuration in the sub-pixel SP.

[0051] Figure 3 A schematic circuit diagram of a sub-pixel in a display device according to the present disclosure is shown.

[0052] Reference Figure 3 The display device 100 includes gate lines GL, data lines DL, and power lines PL that intersect each other to define sub-pixels SP. Switching thin-film transistors Ts, driving thin-film transistors Td, storage capacitors Cst, and light-emitting diodes D can be disposed in the sub-pixels SP.

[0053] The switching thin-film transistor Ts is connected to the gate line GL and the data line DL. The driving thin-film transistor Td and the storage capacitor Cst are connected between the switching thin-film transistor Ts and the power line PL. The light-emitting diode D is connected to the driving thin-film transistor Td.

[0054] In the display device 100, when the switching thin-film transistor Ts is turned on by the gate signal applied to the gate line GL, the data signal applied to the data line DL is applied to the gate electrode 114 through the switching thin-film transistor Ts. Figure 7 ) and one electrode of the storage capacitor Cst.

[0055] When a data signal is applied to the gate electrode 114 of the driving thin-film transistor Td, the transistor is turned on, causing a current proportional to the data signal to be supplied from the power line PL to the light-emitting diode D through the driving thin-film transistor Td. At this time, the light-emitting diode D emits light with a brightness proportional to the current flowing through the driving thin-film transistor Td. In this situation, the storage capacitor Cst is charged with a voltage proportional to the data signal, so that the voltage at the gate electrode 114 in the driving thin-film transistor Td remains constant during one frame. Therefore, the display device 100 can display the desired image.

[0056] exist Figure 3 In the present invention, display device 100 includes two thin-film transistors Ts and Td and a storage capacitor Cst in sub-pixels SP. However, display device 100 may include three or more thin-film transistors and two or more storage capacitors.

[0057] Figure 4 A schematic plan view of a display device according to one or more embodiments of the present disclosure is shown.

[0058] Reference Figure 4 The display device 100 according to this disclosure includes a display area AA for displaying an image and a non-display area NA located outside the display area AA.

[0059] Pixel P, comprising multiple sub-pixels SP1, SP2, and SP3, is arranged in display area AA. In one embodiment, sub-pixels SP1, SP2, and SP3 may be red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, respectively. Alternatively or additionally, pixel P may also include white (W) sub-pixels.

[0060] Multiple gate lines and multiple data lines can be arranged in the display area AA, and sub-pixels SP1, SP2, and SP3 can be arranged in the area where the gate lines and data lines intersect. Switching elements such as thin-film transistors and display diodes / elements for realizing the image can be arranged in each sub-pixel SP1, SP2, and SP3.

[0061] Display elements can include a variety of display elements. For example, display elements can include, but are not limited to, organic light-emitting diodes, liquid crystal displays, quantum dot display diodes, micro-LED display diodes, and mini-LED display diodes.

[0062] The gate driver 106, which provides scan signals to sub-pixels SP1, SP2, and SP3, can be placed in the non-display areas NA on both sides of the display area AA. The gate driver 106 applies the scan signals to the sub-pixels SP1, SP2, and SP3 through gate lines to turn on the thin-film transistors arranged in the sub-pixels SP1, SP2, and SP3.

[0063] In one embodiment, the gate driver 106 may be a GIP (Gate-in-Panel) circuit where the driving circuitry is directly integrated onto the substrate, but it is not limited to this. The gate driver 106 is connected to the gate line of the display area AA via a gate link line GLL and applies a scan signal to the gate line. Figure 4 In one embodiment, the gate driver 106 is placed in the non-display areas NA on both sides of the display area AA. In another embodiment, the gate driver 106 may be placed only in the non-display area NA on one side of the display area AA.

[0064] One end of the flexible printed circuit board (FPC) is attached to the end of the non-display area NA below the display area AA, and the other end of the FPC is attached to the printed circuit board (PCB). Multiple data drivers 107 are arranged on the FPC. The data drivers 107 can be configured as integrated circuit (IC) chips and can be mounted on the FPC.

[0065] In addition, multiple signal lines are arranged on the flexible printed circuit board (FPC) so that signals are input from the outside to the data driver 107, and signals output from the data driver 107 are provided to the display panel PNL. The timing controller 104 and the power supply 108 are arranged on the printed circuit board (PCB) to apply various signals and voltages to the data driver 107 and the display panel PNL.

[0066] Additionally, the gate wiring GRL is arranged at the bottom of the non-display area NA below the display area AA to apply various signals to the gate driver 106.

[0067] Figure 5 Show Figure 4 An enlarged plan view of area "A" in the diagram.

[0068] Reference Figure 5 The connection area FAU attached to one end of the flexible printed circuit board (FPC) is formed in the non-display area NA below the display area AA. The connection area FAU can be formed at a certain distance from the lower edge PNLE of the display panel PNL. Furthermore, the connection area FAU can be formed to have a set width L.

[0069] The pad electrodes (PADs) are located within the connection area (FAU). The pad electrodes (PADs) are the electrodes to which the signal lines of the flexible printed circuit board (FPC) are electrically connected when the FPC is attached to the display panel (PNL).

[0070] As described below, multiple insulating layers 146 and 148 are present between the pad electrode PAD and the data link line DLL. Figure 8A and Figure 8B The pad electrode PAD is positioned in this manner. The pad electrode PAD can be electrically connected to the data link line DLL via the contact portion CNT. Therefore, the data signal output from the data driver 107 mounted on the flexible circuit board FPC can be applied to the data line of the display area AA via the signal line of the flexible circuit board FPC, the pad electrode PAD, the contact portion CNT, and the data link line DLL.

[0071] The upper region of the connection area FAU is the first region FAU1, adjacent to the display area AA, and the lower region of the connection area FAU is the second region FAU2, adjacent to the lower edge PNLE of the display panel PNL. The contact portion CNT between the data link line DLL and the pad electrode PAD is arranged in the second region FAU2, which is the lower region of the connection area FAU. That is, the contact portion CNT is arranged adjacent to the lower edge PNLE of the display panel PNL.

[0072] Because the contact portion CNT is arranged adjacent to the lower edge PNLE of the display panel PNL, both the pad electrode PAD and the data link line DLL are arranged in the connection area FAU. In one embodiment, at least a portion of the pad electrode PAD overlaps with the data link line DLL in the connection area FAU. Interference may occur between the signals flowing through the data link line DLL and the pad electrode PAD, resulting in signal distortion.

[0073] To prevent this signal distortion, a shielding electrode 190 can be arranged in the PNL of the display panel. Figure 8B In one embodiment, the shielding electrode 190 may be positioned between the data link line DLL and the pad electrode PAD. Figure 8B In this configuration, the shielding electrode 190 is arranged in a rectangular shape with a predetermined width in the non-display area NA below the display area AA of the display panel PNL. However, it is not limited to this arrangement, and the shielding electrode 190 can be formed in various widths and shapes. For example, the shielding electrode 190 can be formed only in the area where the data link line DLL and the pad electrode PAD overlap. In this case, the bezel area can be minimized by arranging the contact portion CNT in the second area FAU2 adjacent to the lower edge PNLE of the display panel PNL, as described below.

[0074] Figure 6A A schematic display device showing a contact portion located in the upper region of the connection area to which a flexible circuit board is attached. Figure 6B A schematic display device showing a contact portion located in the lower region of a connection area attached to a flexible circuit board, according to one or more embodiments of the present disclosure.

[0075] refer to Figure 6A When the contact portion (CNT) is arranged in the first region FAU1 of the upper region of the connection region FAU, the data link line (DLL) is arranged between the contact portion CNT and the display region AA. In this case, since the width of the flexible circuit board (FPC) is smaller than the width of the display panel (PNL), the area of ​​the contact portion CNT forming the pad electrode PAD that contacts the signal line of the flexible circuit board FPC is much smaller than the width of the display region AA. Therefore, the data link line (DLL) arranged in the central region of the display panel PNL extends along the vertical direction (i.e., the y-axis direction), and the data link line (DLL) arranged in the left and right regions of the display panel PNL extends at an angle inclined relative to the y-axis direction. The multiple data link lines (DLL) in the region between the area forming the contact portion CNT and the display region AA are arranged in a fan shape.

[0076] In this case, in order to electrically connect the pad electrode PAD and the data line of the display area AA through the data link line DLL, a space for placing the data link line DLL is required. That is, the pad electrode PAD should be spaced apart from the display area AA by a set distance a1 so that the pad electrode PAD and the data line of the display area AA are electrically connected through the data link line DLL.

[0077] On the contrary, referring to Figure 6B , when the contact portion CNT is disposed in the second region FAU2 of the lower region of the connection region FAU, since the connection region FAU serves as a space for disposing the data link line DLL, the distance a2 between the pad electrode PAD and the display area AA is reduced (a2 < a1). Therefore, compared with the frame width d1 of the display device having a structure in which the contact portion CNT is disposed in the first region FAU1 of the upper region of the connection region FAU, the frame width d2 of the display device 100 according to the present disclosure is significantly reduced (d2 < d1).

[0078] Hereinafter, the display device 100 according to the present disclosure will be described in more detail with reference to the accompanying drawings. Figure 7 Shows a schematic cross-sectional view of the display device taken along the line I-I' in Figure 4 . Figure 8A Shows a schematic cross-sectional view of the display device taken along the line II-II' in Figure 5 . Figure 8B Shows a schematic cross-sectional view of the display device taken along the line III-III' in Figure 5 .

[0079] Referring to Figure 7 , Figure 8A and Figure 8B , the substrate 140 includes a display area AA and a non-display area NA. The substrate 140 may include a flexible material. For example, the substrate 140 may include a plurality of base layers 140a and 140c and an intermediate layer 140b between the base layers 140a and 140c. In Figure 7 , Figure 8A and Figure 8B , the substrate 140 includes two base layers 140a and 140c and one intermediate layer 140b, but is not limited thereto. Alternatively or additionally, the substrate 140 may include three or more base layers and two or more intermediate layers.

[0080] Each of the base layers 140a and 140c may include a plastic material. For example, each of the base layers 140a and 140c may include, but is not limited to, polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyethersulfone (PES), polycarbonate (PC), and combinations thereof.

[0081] The intermediate layer 140b may include an inorganic material. For example, the intermediate layer 140b may include, but is not limited to, silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2).

[0082] When the substrate 140 includes the base layers 140a and 140c made of a plastic material and the intermediate layer 140b made of an inorganic material, moisture can be prevented from penetrating into the display device 100 from the outside. Generally, although organic materials (such as plastics) are vulnerable to moisture penetration, inorganic materials can block moisture penetration. In the present disclosure, moisture penetration into the display device 100 is prevented by disposing the intermediate layer 140b made of an inorganic material between the base layers 140a and 140c made of an organic material.

[0083] The buffer layer 142 may be disposed on the substrate 140. The buffer layer 142 may be disposed over the entire substrate 140 to improve the adhesion between the layers disposed on the substrate 140 and the substrate 140 and to prevent leakage of alkaline components and the like from the substrate 140. In addition, the buffer layer 142 may delay the diffusion of moisture or oxygen that has penetrated into the substrate 140.

[0084] In one embodiment, the buffer layer 142 may include an insulating material. For example, the buffer layer 142 may include, but is not limited to, inorganic insulating materials such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2). The buffer layer 142 may have a single-layer structure or a multi-layer structure. For example, the buffer layer 142 may have a laminated structure of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer. However, embodiments of the present disclosure are not limited thereto. In some embodiments, the buffer layer 142 may be omitted depending on the type and material of the substrate 140 and the structure and / or type of the thin film transistor.

[0085] The thin film transistor T is disposed on the buffer layer 142 in the display area AA. For ease of explanation, only the driving thin film transistor T among the various thin film transistors that may be disposed in the display area AA is shown in Figure 7 , but other thin film transistors such as switching thin film transistors may be provided. Additionally, in Figure 7 , a thin film transistor having a top-gate structure is shown, and the structure of the thin film transistor T is not limited thereto, and a thin film transistor T having other structures such as a bottom-gate structure may be implemented.

[0086] The thin film transistor T may include a semiconductor layer 112 disposed on the buffer layer 142, a gate insulating layer 144 disposed on the semiconductor layer 112, a gate electrode 114 disposed on the gate insulating layer 144, an interlayer insulating layer 146 disposed on the gate electrode 114, and source and drain electrodes 115 and 116 disposed on the interlayer insulating layer 146.

[0087] In one embodiment, the semiconductor layer 112 may include a polycrystalline semiconductor. For example, the polycrystalline semiconductor may include, but is not limited to, low-temperature polycrystalline silicon (LTPS) with excellent mobility.

[0088] In another embodiment, the semiconductor layer 112 may include an oxide semiconductor. For example, the oxide semiconductor may include, but is not limited to, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), indium gallium oxide (IGO), and combinations thereof. In some embodiments, the semiconductor layer 112 may include a channel region 112a in a central region, and source regions 112b and drain regions 112c that are doped regions on both sides of the channel region 112a.

[0089] In one embodiment, the gate insulating layer 144 may be disposed in both the display area AA and the non-display area NA. In another embodiment, the gate insulating layer 144 may be provided only in the display area AA. For example, the gate insulating layer 144 may include an inorganic insulating material such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2). The gate insulating layer 144 may have a single-layer structure or a multi-layer structure. However, the embodiments of the present disclosure are not limited thereto.

[0090] In one embodiment, the interlayer insulating layer 146 may be disposed in both the display area AA and the non-display area NA. In another embodiment, the interlayer insulating layer 146 may be disposed only in the display area AA. For example, the interlayer insulating layer 146 may include, but is not limited to, an organic material such as photoacrylic resin or an inorganic insulating material such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2). The interlayer insulating layer 146 may have a single-layer structure or a multi-layer structure. In another embodiment, the interlayer insulating layer 146 may have a multi-layer structure including at least one organic layer and at least one inorganic layer. However, the embodiments of the present disclosure are not limited thereto.

[0091] In one embodiment, each of the source electrode 115 and the drain electrode 116 may include, but is not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), combinations thereof, or alloys thereof. Each of the source electrode 115 and the drain electrode 116 may have a single-layer structure or a multi-layer structure. However, the embodiments of the present disclosure are not limited thereto. The source electrode 115 and the drain electrode 116 may be in contact with the source region 112b and the drain region 112c of the semiconductor layer 112 through contact holes formed in the gate insulating layer 144 and / or the interlayer insulating layer 146, respectively.

[0092] In another embodiment, a bottom shielding metal layer may be disposed between the substrate 140 and the semiconductor layer 112. The bottom shielding metal layer can be arranged to minimize back-channel phenomena caused by charges trapped in the substrate 140 and to prevent image retention or transistor performance degradation. For example, the bottom shielding metal layer may include, but is not limited to, titanium (Ti), molybdenum (Mo), and alloys thereof. The bottom shielding metal layer may have a single-layer structure or a multi-layer structure.

[0093] A first planarization layer 148 is disposed on a substrate 140 on which a thin-film transistor T is disposed. In one embodiment, the first planarization layer 148 may include, but is not limited to, an organic material such as photoacrylic resin. In another embodiment, the first planarization layer 148 may have a multilayer structure including at least one inorganic layer and at least one organic layer.

[0094] A connection pattern 154 is disposed on the first planarization layer 148. The connection pattern 154 can be electrically connected to the drain electrode 116 of the thin-film transistor T through contact holes formed in the first planarization layer 148. For example, the connection pattern 154 may include a metallic component.

[0095] A second planarization layer 150 is disposed on a first planarization layer 148 having a connection pattern 154. In one embodiment, the second planarization layer 150 may include, but is not limited to, an organic material such as photopolymer acrylic resin. In another embodiment, the second planarization layer 150 may have a multilayer structure including at least one inorganic layer and at least one organic layer. In one embodiment, the second planarization layer 150 may include the same material as the first planarization layer 148. In another embodiment, the second planarization layer 150 may include a different material than the first planarization layer 148.

[0096] By arranging two or more planarization layers 148 and 150, various electrodes and lines can be arranged between the first planarization layer 148 and the second planarization layer 150. In this case, since the electrodes can be arranged vertically, the area caused by the electrodes and lines in the sub-pixels can be reduced. Therefore, the area of ​​the sub-pixels can be reduced and a display device 100 with high resolution can be manufactured.

[0097] The light-emitting diode / element D is disposed on the second planarization layer 150 in the display area AA. The light-emitting diode D may include a first electrode 132, a light-emitting layer 134, and a second electrode 136 sequentially disposed on the second planarization layer 150.

[0098] The first electrode 132 is disposed on the second planarization layer 150. The first electrode 132 can be electrically connected to the connection pattern 154 through a contact hole formed in the second planarization layer 150. In other words, the first electrode 132 can be electrically connected to the drain electrode 116 of the thin-film transistor T through the connection pattern 154.

[0099] For example, the first electrode 132 may include, but is not limited to, a metal component such as silver (Ag), aluminum (Al), molybdenum (Mo), tungsten (W), chromium (Cr), a combination thereof, or an alloy thereof. In another embodiment, the first electrode 132 may include, but is not limited to, a transparent metal oxide layer such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0100] In one embodiment, when the display device 100 is a top emission type, the first electrode 132 may further include an opaque conductive material serving as a reflective electrode. In another embodiment, when the display device 100 is a bottom emission type, a transparent conductive material such as ITO and / or IZO may be used to form the first electrode 132.

[0101] The bank layer BNK is provided on the second planarization layer 150 at the boundary of each sub-pixel. The bank layer BNK may be a partition wall that defines each sub-pixel. The bank layer BNK divides each sub-pixel and may prevent light of a specific color output from adjacent sub-pixels from being mixed and output.

[0102] For example, the bank layer BNK may include, but is not limited to, an inorganic material such as silicon oxide (SiOx, where O < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2); an organic material such as an acrylate-containing resin, an epoxy-containing resin, a phenol-containing resin, a polyamide-containing resin, and / or a polyimide-containing resin; a photosensitizer containing a black pigment and / or a dye; and a combination thereof.

[0103] The light-emitting layer 134 may be disposed on the first electrode 132, the inclined surface of the bank layer BNK, and the bank layer BNK in the display area AA and extend into the non-display area NA.

[0104] In one embodiment, the light-emitting layer 134 may include, but is not limited to, a red light-emitting layer that emits red and is provided in a red sub-pixel, a green light-emitting layer that emits green and is provided in a green sub-pixel, and a blue light-emitting layer that emits blue and is provided in a blue sub-pixel. For example, the light-emitting layer 134 may include, but is not limited to, an organic light-emitting layer or an inorganic light-emitting layer such as a nanoscale material layer, a quantum dot, a micro-LED light-emitting layer, or a mini-LED light-emitting layer.

[0105] In one embodiment, the light-emitting layer 134 may include a light-emitting material layer. In another embodiment, the light-emitting layer 134 may further include a hole injection layer, a hole transport layer, and / or an electron blocking layer provided between the first electrode 132 and the light-emitting material layer, and an electron injection layer, an electron transport layer, and / or a hole blocking layer provided between the light-emitting material layer and the second electrode 136.

[0106] The second electrode 136 is disposed on the light-emitting layer 134. In one embodiment, the second electrode 136 may have a single-layer or multi-layer structure of a metal component or its alloy. In another embodiment, the second electrode 136 may include a transparent metal oxide, such as ITO and / or IZO. However, the embodiments disclosed herein are not limited thereto.

[0107] In one embodiment, when the display device 100 is a top-emitting type, a transparent or semi-transparent conductive material can be used to arrange the second electrode 136. For example, the second electrode 136 may include, but is not limited to, alloys such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, LiF / Ca:Ag, and combinations thereof.

[0108] In another embodiment, when the display device 100 is bottom-emitting, an opaque conductive material can be used to arrange the second electrode 136. For example, the second electrode 136 may include, but is not limited to, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), and / or alloys thereof.

[0109] In another embodiment, the light-emitting diode D may have a series structure. The series structure includes a plurality of light-emitting portions and at least one charge-generating layer disposed between the light-emitting portions. The charge-generating layer is used to connect the plurality of light-emitting portions. In one embodiment, multiple charge-generating layers, including a first charge-generating layer and a second charge-generating layer, may be provided. In one embodiment, the charge-generating layer may include an N-type charge-generating layer and a P-type charge-generating layer. For example, the charge-generating layer may include, but is not limited to, an organic layer doped with an alkali metal such as Li, Na, K, and / or Cs and / or an alkaline earth metal such as Mg, Sr, Ba, and / or Ra.

[0110] An encapsulation layer 180 is disposed within the display area AA and the non-display area NA to encapsulate the light-emitting diode D. When the light-emitting diode D is exposed to moisture or oxygen, pixel shrinkage (shrinkage of the light-emitting area) or defects such as dark spots forming within the light-emitting area may occur. Furthermore, moisture or oxygen can oxidize the electrodes made of metallic components. The encapsulation layer 180 prevents moisture and oxygen from penetrating from the outside to prevent defects in the light-emitting diode D and its various electrodes.

[0111] In one embodiment, the encapsulation layer 180 may include, but is not limited to, a first encapsulation layer 182, a second encapsulation layer 184, and a third encapsulation layer 186. In another embodiment, the encapsulation layer 180 may include two, four, or more layers.

[0112] In one embodiment, each of the first encapsulation layer 182 and the third encapsulation layer 186 may include an inorganic material, such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2). Each of the first encapsulation layer 182 and the third encapsulation layer 186 may have a single-layer structure or a multi-layer structure. In another embodiment, each of the first encapsulation layer 182 and the third encapsulation layer 186 may further include at least one organic layer disposed between the inorganic layers. The second encapsulation layer 184 may include an epoxy-containing resin. However, embodiments of the present disclosure are not limited thereto.

[0113] Although not shown in Figure 7 , Figure 8A and Figure 8B a touch member may be disposed on the encapsulation layer 180. The touch member may be disposed in the display area AA and sense a touch input. The touch member may sense external touch information using a user's finger or a stylus.

[0114] A plurality of data link lines DLL spaced apart from each other at a set interval are disposed on the gate insulating layer 144 in the non-display area NA. For example, the data link lines DLL may be arranged using the same metal component as the gate electrode 114 of the thin film transistor T through the same process, but is not limited thereto.

[0115] A plurality of pad electrodes PAD spaced apart from each other at a set interval are disposed on the first planarization layer 148. For example, the pad electrodes PAD may be arranged using the same metal component as the connection pattern 154 through the same process, but is not limited thereto.

[0116] Although not shown in Figure 8A and Figure 8B when manufacturing the display panel PNL, the pad electrodes PAD are exposed to the outside, and when the flexible printed circuit board FPC is attached to the display panel PNL, the signal lines of the flexible printed circuit board FPC contact the exposed pad electrodes PAD, so that the display panel PNL is electrically connected to the flexible printed circuit board FPC.

[0117] The interlayer insulating layer 146 and the first planarization layer 148 are disposed between the data link lines DLL and the pad electrodes PAD. The data link lines DLL are electrically connected to the pad electrodes PAD through contact portions CNT (i.e., contact holes) formed in the interlayer insulating layer 146 and the first planarization layer 148.

[0118] The shielding electrode 190 is disposed on the interlayer insulating layer 146 between the data link lines DLL and the pad electrodes PAD, thereby preventing interference between the data link lines DLL and the pad electrodes PAD and preventing signal distortion of the data link lines DLL and the pad electrodes PAD.

[0119] In another embodiment, the data link line DLL, pad electrode PAD, and shield electrode 190 can be arranged in various different layers. For example, the data link line DLL can be arranged on the interlayer insulating layer 146. In this case, the data link line DLL can be formed using the same metal composition as the source electrode 115 and drain electrode 116 of the thin-film transistor T through the same process. In another embodiment, the first planarization layer 148 is formed as a double-layer structure with an upper and a lower layer. In this case, the data link line DLL is arranged below the lower layer of the first planarization layer 148, the shield electrode 190 is arranged on the lower layer of the first planarization layer 148, and the pad electrode PAD is arranged on the upper layer of the first planarization layer 148. In other words, the data link line DLL and the shield electrode 190 are arranged such that the lower layer of the first planarization layer 148 is located between them, and the shield electrode 190 and the pad electrode PAD are arranged such that the upper layer of the first planarization layer 148 is located between them.

[0120] As described in detail above, the contact portion CNT connecting the data link line DLL and the pad electrode PAD is placed in the second region FAU2 adjacent to the lower edge PNLE of the display panel PNL. Since the area of ​​the non-display area NA below the display panel PNL can be minimized, a narrow bezel can be achieved.

[0121] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its scope. Therefore, this disclosure is intended to cover such modifications and variations as long as they fall within the scope of the appended claims.

Claims

1. A display device, comprising: A display panel includes a display area and a non-display area located outside the display area; A connection area is provided in the non-display area of ​​the display panel, and a flexible circuit board is attached to the connection area; A data link cable, which is disposed in the non-display area of ​​the display panel and connected to the display area; as well as The pad electrodes are disposed in the non-display area of ​​the display panel and electrically connected to the signal lines of the flexible circuit board. The connection area includes a first area adjacent to the display area and a second area between the first area and the edge of the display panel. The data link line and the pad electrode are connected to the second region of the connection area.

2. The display device of claim 1, wherein, At least a portion of the data link line is positioned to overlap with the pad electrode.

3. The display device according to claim 2 further includes a shielding electrode disposed between the data link line and the pad electrode.

4. The display device of claim 2, wherein, The data link line is electrically connected to the pad electrode via a contact portion.

5. The display device of claim 4, wherein, The contact portion is disposed between the data link line and the pad electrode and the edge of the display panel.

6. The display device according to claim 4, further comprising a thin-film transistor and a light-emitting diode disposed in each of the plurality of sub-pixels in the display area.

7. The display device of claim 6, wherein, The thin-film transistor includes: A semiconductor layer disposed on a substrate; A gate insulating layer disposed on the semiconductor layer; Gate electrode disposed on the gate insulating layer; An interlayer insulating layer disposed on the gate electrode; and The source electrode and drain electrode are disposed on the interlayer insulating layer.

8. The display device according to claim 7, further comprising: Multiple insulating layers disposed on the thin-film transistor; as well as A connection pattern is disposed on the plurality of insulating layers and electrically connects the thin-film transistor to the light-emitting diode.

9. The display device of claim 8, wherein, The light-emitting diode includes: Electrically connected to the first electrode of the connection pattern; The second electrode facing the first electrode; and A light-emitting layer is disposed between the first electrode and the second electrode.

10. The display device of claim 8, wherein, The data link line comprises the same material as the gate electrode, the shield electrode comprises the same material as the source electrode and the drain electrode, and the pad electrode comprises the same material as the connection pattern.

11. The display device of claim 8, wherein, The contact portion is the contact hole in the plurality of insulating layers.

12. A display device, comprising: A display panel includes a display area and a non-display area located outside the display area; A flexible circuit board is attached to the non-display area of ​​the display panel; A data link cable, which is disposed in the non-display area of ​​the display panel and connected to the display area; as well as The pad electrodes are disposed in the non-display area of ​​the display panel and electrically connected to the signal lines of the flexible circuit board. The data link line extends to the inside of the flexible circuit board, and at least a portion of the data link line is positioned to overlap with the pad electrode, with an insulating layer between the data link line and the pad electrode.

13. The display device of claim 12, wherein, The data link line is electrically connected to the pad electrode through a contact portion on the insulating layer.

14. The display device according to claim 13, further comprising a shielding electrode disposed between the data link line and the pad electrode.

15. The display device of claim 14, further comprising a thin-film transistor and a light-emitting diode disposed in each of a plurality of sub-pixels in the display area.

16. The display device of claim 15, wherein, The thin-film transistor includes: A semiconductor layer disposed on a substrate; A gate insulating layer disposed on the semiconductor layer; Gate electrode disposed on the gate insulating layer; An interlayer insulating layer disposed on the gate electrode; and The source electrode and drain electrode are disposed on the interlayer insulating layer.

17. The display device according to claim 16, further comprising: Multiple insulating layers disposed on the thin-film transistor; as well as A connection pattern is disposed on the plurality of insulating layers and electrically connects the thin-film transistor to the light-emitting diode.

18. The display device of claim 17, wherein, The light-emitting diode includes: Electrically connected to the first electrode of the connection pattern; The second electrode facing the first electrode; and A light-emitting layer is disposed between the first electrode and the second electrode.

19. The display device of claim 17, wherein, The data link line comprises the same material as the gate electrode, the shield electrode comprises the same material as the source electrode and the drain electrode, and the pad electrode comprises the same material as the connection pattern.

20. The display device of claim 17, wherein, The contact portion is the contact hole in the plurality of insulating layers.

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