Method of writing data to memory and memory controller, system

Abstract

This invention provides a method for writing data to a memory, as well as a memory controller and system. During memory write operations, based on the results of programming verification, a programming and pressure application method is used to simultaneously program and pressure the memory's write area for every n memory cells that need programming, thus completing the entire write process. In other words, in this invention, the size of a single programming range is actually calculated based on the number of memory cells n that need programming, excluding memory cells that do not require programming. Therefore, during memory write operations, the size of a single programming range can be maximized within a limited power consumption, making the memory's programming range adjustable compared to existing technologies. Consequently, with the same data input as existing technologies, the number of programming operations in memory write operations can be effectively reduced, improving memory write efficiency.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a method for writing data to a memory and a memory controller and system. Background Technology

[0002] Non-volatile memories such as flash memory retain data even after power loss and are widely used in automotive, industrial, and consumer electronics applications. Improving the write speed of flash memory and other non-volatile memories within existing power supply designs is one of the most pressing issues in this field. Summary of the Invention

[0003] The purpose of this invention is to provide a method for writing data to a memory, as well as a memory controller and system, which can effectively reduce the number of programming operations and improve the memory's write efficiency when writing data to the memory.

[0004] To achieve the above objectives, the present invention provides a method for writing data to a memory, comprising the following steps:

[0005] The memory is programmed and verified to determine the location and number of memory cells that need to be programmed in the write area of ​​the memory;

[0006] Based on the results of the programming verification, the area to be written is programmed and pressured by simultaneously performing programming and pressure operations on every n memory cells that need to be programmed, so as to complete the entire data writing process of the memory. Here, n is greater than 1 and is an integer.

[0007] Optionally, the step of verifying the programming of the memory includes:

[0008] The data to be written in the memory is cached in the programming cache;

[0009] The programming buffer is read, and it is verified whether the stored data in each storage unit in the write area is consistent with the corresponding write data read from the programming buffer. If they are consistent, the storage unit does not need to be programmed; if they are inconsistent, the storage unit is the storage unit that needs to be programmed.

[0010] Optionally, the step of verifying the programming of the memory further includes: caching the result of the programming verification into the programming cache.

[0011] Optionally, programming and pressure application to the write area can begin only after programming verification of all memory cells in the write area has been completed; or, programming verification of the corresponding memory cells in the write area can be performed while programming and pressure application is applied to the memory cells in the write area that have been identified as needing programming.

[0012] Optionally, the step of programming and pressurizing the memory's writable region includes:

[0013] The memory cells that need to be programmed in the results of the programming verification are counted in address order;

[0014] Determine whether the current count value has reached n, where n is the number of memory units that need to be programmed that can be programmed and pressurized simultaneously in one operation;

[0015] If the target is reached, then the programming pressure operation is performed simultaneously on the n memory units that need to be programmed in this round of counting, so as to write the corresponding data to be written into the n memory units that need to be programmed, and then the count value is cleared to prepare for the start of the next round of counting.

[0016] If not, determine whether the current count has reached the last memory cell that needs to be programmed in the write area. If yes, stop counting and simultaneously perform programming pressure operation on all memory cells that need to be programmed in this round of counting to write the corresponding data to be written into each memory cell that needs to be programmed in this round of counting. If not, continue counting in this round.

[0017] Optionally, the step of programming and pressurizing the memory to be written area further includes: whenever the count value of the current round reaches n or the last memory cell to be programmed in the memory to be written area is counted, the address of the last memory cell to be programmed in the current round is recorded, and it is further determined whether the recorded address is the address of the last memory cell to be programmed in the memory to be written area. If so, the entire data writing process of the memory is ended after the programming and pressurizing operation of the current round is completed.

[0018] Based on the same inventive concept, the present invention also provides a memory controller, which includes:

[0019] The programming verification module is configured to perform programming verification on the memory to determine the location and number of memory cells that need to be programmed in the write area of ​​the memory;

[0020] The programming pressure module is coupled to the programming verification module and is configured to program and pressure the area to be written by simultaneously performing programming pressure operations on every n memory units that need to be programmed, based on the programming verification results of the programming verification module, so as to complete the entire data writing process of the memory. Here, n is greater than 1 and is an integer.

[0021] Optionally, the memory controller further includes a programming cache configured to cache the data to be written in the memory; the programming verification module is coupled to the programming cache and is further configured to: read the programming cache and verify whether the stored data in each memory cell in the write area is consistent with the corresponding write data read from the programming cache; if they are consistent, the memory cell does not need to be programmed; if they are inconsistent, the memory cell is the memory cell that needs to be programmed.

[0022] Optionally, the programming verification module is further configured to cache the result of the programming verification in the programming cache.

[0023] Optionally, the memory controller further includes a programming counter, which is coupled to the programming verification module and the programming pressure module, and is configured to count the memory cells to be programmed in the write area according to the programming verification result of the programming verification module, and the count value does not exceed n, so that the count value is cleared when n is counted to start the next round of counting.

[0024] The programming pressure module is configured to simultaneously program and pressure each of the memory units that need to be programmed corresponding to the current count result of the programming counter, so as to write the corresponding data to be written into each of the memory units that need to be programmed corresponding to the current count result of the programming counter.

[0025] Optionally, the memory controller further includes a programming determination module coupled to the programming counter and the programming pressure module, and configured to:

[0026] Determine whether the current count value of the programming counter has reached n. If it has, clear the count value of the programming counter to end the current round of counting and start the next round of counting. If it has not reached n, further determine whether the programming counter has counted to the last memory unit that needs to be programmed in the area to be written. If it has, end the current round of counting of the programming counter. If not, let the programming counter continue counting.

[0027] Based on the same inventive concept, the present invention also provides a system comprising a memory and a coupled memory controller, wherein the memory controller writes data into the memory using the memory write data method as described in the present invention;

[0028] Alternatively, the system may include a memory and a memory controller as described in this invention, the memory controller being coupled to the memory and controlling read and write operations of the memory.

[0029] Compared with the prior art, the technical solution of the present invention, when performing write data operations on the memory, can simultaneously perform programming and pressure operations on the memory's write area based on the results of programming verification, using n memory cells that need to be programmed at the same time, to complete the entire write data process of the memory. In other words, in the present invention, the size of the single programming range of the memory is actually calculated according to the number of memory cells that need to be programmed, n, and this n does not include memory cells that do not need to be programmed. Therefore, during the write data operation of the memory, the size of the single programming range can be increased to the maximum extent within the limited power consumption, making the programming range of the memory adjustable compared with the prior art. Thus, under the same data input as the prior art, the number of programming operations in the memory write data operation can be effectively reduced, improving the write efficiency of the memory. Attached Figure Description

[0030] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0031] Figure 1 This is a basic flowchart of the existing Flash data writing method.

[0032] Figure 2 yes Figure 1 The diagram shows the programming range of Flash in each write data method flow.

[0033] Figure 3 and Figure 4 These are schematic diagrams illustrating two basic processes of writing data to a memory according to a specific embodiment of the present invention.

[0034] Figure 5 yes Figure 4 The diagram illustrates a specific example of a method for writing data to a memory.

[0035] Figures 6 to 8 These are schematic diagrams illustrating the range of each programming iteration of the memory under the memory write data method of a specific embodiment of the present invention.

[0036] Figure 9 This is a schematic diagram of the architecture of the memory controller and system according to a specific embodiment of the present invention. Detailed Implementation

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0038] Please refer to Figure 1 The basic data writing process of existing non-volatile memory such as Flash memory is mainly divided into a verification stage and a programming stage. The verification stage is used to determine the location and number of memory cells that need to be programmed in the write area of ​​the memory, while the programming stage is used to perform programming pressure operations on the memory cells that need to be programmed in the write area. In the verification stage, the user-input data is first verified to check whether the data in the current memory cell is consistent with the user-input data to be written (or the "expected value") (e.g., ...). Figure 1 As shown in step S11), the result of the programming verification is written into the programming buffer (e.g., Figure 1 As shown in step S12). In the programming phase, the programming verification results stored in the programming buffer are first read (e.g., ...). Figure 1 As shown in step S13), it determines whether the existing data in the current storage unit is consistent with the user's expected value (i.e., the data to be written) (i.e., whether the current storage unit needs to be programmed, such as...). Figure 1 If the steps are consistent (as shown in step S14), the current memory cell needs to be programmed, and then a programming and pressurization operation is performed (e.g., ...). Figure 1 If the steps are inconsistent (as shown in step S15), then the current storage unit does not need to be programmed and pressurized. This process is repeated until the last address of the data to be written by the user completes the programming and pressurization operation.

[0039] like Figure 2 As shown, all memory cells in this memory are located at the intersection of the word line (WL) and the bit line (BL). During programming and voltage application, information can be written to selected memory cells by applying voltage to different WL and BL values. Figure 2 In the diagram, solid black dots indicate that the data in the storage unit is inconsistent with the user's expected value and requires programming, while empty circles indicate that the data in the storage unit is consistent with the user's expected value and does not require programming.

[0040] Existing technical solutions such as Figure 2 As shown in line WL126 (the area to be written), the programming range selected for each programming pressurization operation is the same. That is, the total number of memory cells to be programmed and the number of memory cells not to be programmed are equal in each programming range. Assuming power consumption limitations, the existing scheme sets the programming range for one programming pressurization operation to 4, meaning it can program a maximum of four memory cells. The first programming pressurization operation reads the programming buffers corresponding to the four memory cells in programming range Q1. After identification, it finds that there are 3 memory cells to be programmed within programming range Q1. Therefore, in subsequent programming pressurization operations, only the BL corresponding to these 3 memory cells is pressurized simultaneously. After writing the information of these 3 memory cells, the second programming operation reads the programming buffers corresponding to the 4 memory cells in programming range Q2 and identifies and pressurizes the 4 memory cells in Q2. This process continues until all memory cells in the last programming range Qm of the memory's write area have been identified and pressurized.

[0041] As shown above, the existing solution requires m programming and pressurization operations to complete the write data operation for WL126 lines. Moreover, because the existing solution programs the same range each time, it wastes the capacity of a single programming and pressurization operation because there are memory units within some programming ranges that do not need to be programmed.

[0042] Based on this, the present invention provides a method for writing data to a memory, as well as a memory controller and system. The core idea is to fix the number n (an integer greater than 1) of memory cells to be programmed within the programming range selected for each programming pressure operation. A programming pressure operation is only performed after determining that the number of memory cells to be programmed has reached n; otherwise, the programming verification result of the next memory cell is read. This process is repeated until all memory cells to be programmed in the write area of ​​the memory have been programmed. Here, n can be set according to the capability of a single programming pressure operation (i.e., the number of memory cells that can be programmed simultaneously at one time). n is an integer and not less than 1, and its maximum value does not exceed the upper limit of a single programming pressure operation (i.e., the maximum number of memory cells that can be programmed simultaneously at one time). Preferably, n is the upper limit of a single programming pressure operation.

[0043] Therefore, in the technical solution of the present invention, the actual size of each programming range is determined by the start address and end address of n memory units that need to be programmed. It includes not only n memory units that need to be programmed, but also memory units that do not need to be programmed located within the address range. Obviously, when there are multiple programming pressure operations, the size of these programming ranges can be different. Moreover, except that the number of memory units that need to be programmed in the last programming range may be less than n, the number of memory units that need to be programmed in the remaining programming ranges is n.

[0044] The following is in conjunction with the appendix Figures 3 to 9 The technical solutions proposed in this invention will be further described in detail below with specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0045] Please refer to Figure 3 An embodiment of the present invention provides a method for writing data to a memory, comprising:

[0046] Verification phase: Programming verification of the memory (e.g.) Figure 3 As shown in step S21), the programming verification result is written into the programming cache (e.g., Figure 3 (as shown in step S22);

[0047] Programming phase: Based on the results of programming verification, the area to be written is programmed and pressured by simultaneously performing programming and pressure operations on every n memory units that need to be programmed, so as to complete the entire data writing process of the memory. Here, n is greater than 1 and is an integer.

[0048] In one example, the steps for programming verification of the memory during the verification phase may include:

[0049] First, the user-input data to be written (i.e., the data to be written in this memory) is cached in the programming cache (e.g., ...). Figure 5 (as shown in step S20);

[0050] Next, perform programming verification (such as...) Figure 3 As shown in step S21, the programming buffer is read and the data stored in each memory cell in the area to be written is verified to be consistent with the corresponding data to be written read from the programming buffer.

[0051] Then, the verification result is written (or "updated" or "cached") to the programming cache (e.g., Figure 3(as shown in step S22). If they match, the storage unit does not need to be programmed and is a storage unit that does not need to be programmed; if they do not match, the storage unit needs to be programmed and is a storage unit that needs to be programmed.

[0052] During the programming phase, the programming verification results stored in the programming cache are read first (e.g., ... Figure 3 As shown in step S23), then based on the read programming verification result, determine whether the corresponding storage unit needs programming (e.g., Figure 3 As shown in step S24), the location of each memory cell that needs to be programmed is determined, as well as the number of memory cells that need to be programmed. Then, the memory's write area can be programmed and pressured simultaneously for every n memory cells that need to be programmed (e.g., ...). Figure 3 (as shown in step S25) to complete the entire write data process of the memory, where n is greater than 1 and is an integer.

[0053] In one example, step S24 can be performed simultaneously with step S25. That is, for every n memory cells that need to be programmed, programming pressure operations are immediately performed on these n memory cells simultaneously (or "together") to write the corresponding data to be written to these n memory cells. When the last address in the memory's write area is determined, even if the number of memory cells that need to be programmed is less than n, programming pressure operations are still performed on these memory cells that have a total number of less than n. When the last programming pressure operation is completed, the entire write operation of the memory is completed.

[0054] In another example, step S24 can be used to first determine all memory cells that need to be programmed in the area to be written, and then group these memory cells to be programmed according to their address order, with each group consisting of n cells (if there are any remaining cells, these remaining cells are grouped together). After grouping, programming and pressure operations are performed simultaneously (or "together") on all memory cells to be programmed in each group, thereby writing the corresponding data to be written into the memory cells to be programmed in that group. After the last programming and pressure operation is completed, the entire write operation of the memory is completed.

[0055] Obviously, Figure 3 The data writing method of the illustrated embodiment first completes the programming verification of all memory cells in the write area of ​​the memory before starting the first programming pressure operation (i.e., performing a programming pressure operation on the corresponding memory cells that need to be programmed in the write area). However, the technical solution of the present invention is not limited to this.

[0056] Please refer to Figure 4Another embodiment of the present invention also provides a method for writing data to a memory, which includes the following steps:

[0057] S21, each memory cell in the write area of ​​the memory is programmed and verified in sequence, that is, the data stored in the current memory cell is verified to be consistent with the data to be written expected by the user.

[0058] S22, write the programming verification results to the programming cache in real time (i.e., "update" or "cache");

[0059] S23, Read the latest programming verification result stored in the programming cache;

[0060] S24. Based on the read programming verification result, determine whether the corresponding storage unit needs to be programmed. Wherein, the stored data in the storage unit that needs to be programmed is inconsistent with the data to be written expected by the user.

[0061] S25, if so, then when n memory units that need to be programmed are identified, programming and pressurizing operations are performed on these n memory units together to write the corresponding data to be written into these n memory units that need to be programmed.

[0062] S26. If not, determine whether the address of the corresponding memory cell is the last address. If it is the last address, end the process. If it is not the last address, return to step S21 and continue with the programming verification of the next memory cell address.

[0063] thus, Figure 4 The technical solution of the embodiment shown can perform programming verification and programming pressure operation at the same time, thereby further shortening the memory write data time and improving the memory write data efficiency.

[0064] In one example, this can be achieved by updating and resetting the count. Figure 4 Step S25 in the illustrated embodiment. Please refer to... Figure 5 The method for writing data to the memory in this example specifically includes the following steps:

[0065] S20, write the data to be written (or "cache" it) into the programming cache;

[0066] S21, Perform programming verification on the current storage unit, that is, compare the corresponding data in the programming cache with the data already stored in the current storage unit to determine whether the two are consistent;

[0067] S22, write the programming verification result of the current storage unit to the programming cache in real time (i.e., "update to" or "cache to");

[0068] S23, Read the latest programming verification result stored in the programming cache;

[0069] S24, based on the read programming verification result, determine whether the current storage unit needs to be programmed, wherein the stored data in the storage unit that needs to be programmed is inconsistent with the data to be written expected by the user;

[0070] S251, if it is a memory cell that needs to be programmed, then the count (or "count value") is incremented by 1;

[0071] S252, determine whether the count (or "count value") of the memory cell that needs to be programmed has reached n;

[0072] If n is reached, then jump to S254 and record the end address of this round of counting.

[0073] If n is not reached, then execute S253 to determine whether it is the last address in the area to be written (i.e., whether the last memory unit that needs to be programmed has been counted). If yes, then execute S254. If no, then increment the address by 1 and return to step S21.

[0074] S255, determine if the count value is 0. If not, execute S256, perform programming pressure operation on all the counted (e.g., n in each round except the last round, and less than n in the last round) memory units that need to be programmed, so as to write the corresponding data to be written into these memory units that need to be programmed. If yes, end the current write operation of the memory.

[0075] S26. Determine whether the end address of the record is equal to the address of the last unit that needs to be programmed. If yes, end the current write data operation of the memory. If no, increment the address by 1 and return to step S21 to continue the programming verification of the next memory unit.

[0076] thus, Figure 5 The example shown can program and verify the memory cells in the write area of ​​the memory according to the address order of the memory cells, and can perform programming and pressure operation while verifying, thereby greatly improving the write data efficiency of the memory.

[0077] The effects of the memory writing method of the present invention will be further explained in detail below with specific application examples.

[0078] Please refer to Figure 6In a specific application example, all memory cells are located at the intersection of the word line (WL) and the bit line (BL). Along the direction from BL0 to BL255, the memory cells are sequentially: the first memory cell (located at the intersection of BL0 and WL126), the second memory cell (located at the intersection of BL1 and WL126), the third memory cell (located at the intersection of BL2 and WL126), the fourth memory cell (located at the intersection of BL3 and WL126), the fifth memory cell (located at the intersection of BL4 and WL126), the sixth memory cell (located at the intersection of BL5 and WL126), ..., the 256th memory cell (located at the intersection of BL255 and WL126). During the programming pressure operation, by applying pressure to different WL and BL lines, information can be written to the selected memory cells. Figure 6 In the diagram, solid black dots indicate that the data in the memory cell does not match the user's expected value and requires programming, while empty circles indicate that the data in the memory cell matches the user's expected value and does not require programming. The memory and its writable area in this application example are both... Figure 2 The example shown is where the area to be written is line WL126.

[0079] In this application example, n=4, meaning that a single programming and pressurizing operation can only program and pressurize 4 memory cells that need to be programmed simultaneously. This application example involves verifying the programming of each memory cell on row WL126 from the 1st to the 256th memory cell. The initial count is 0. Based on the programming verification results, the count is incremented by 1 for each memory cell that needs programming. After counting to 4, the count is reset to zero and restarted.

[0080] In this application example, when counting to the 5th memory cell (i.e., the intersection of BL4 and WL126), the count value is 4 for the first time. At this point, the programming range is determined to be P1. P1 contains 4 memory cells that need to be programmed (i.e., the 1st, 2nd, 4th, and 5th memory cells) and 1 memory cell that does not need to be programmed (i.e., the 3rd memory cell). Therefore, programming pressure operations are performed simultaneously on these 4 memory cells that need to be programmed in P1 (i.e., on the basis of pressure applied to WL126, BL0, BL1, BL3, and BL4 are also pressured simultaneously) to write the corresponding data into the 1st, 2nd, 4th, and 5th memory cells. After writing data within the P1 programming range, the count is reset to zero and restarted from the 6th memory cell. When the count reaches the 10th memory cell (located at the intersection of BL9 and WL126), the count is 4 for the second time. At this point, the programming range is determined to be P2. P2 contains 4 memory cells that need to be programmed (the 6th memory cell at the intersection of BL5 and WL126, the 7th memory cell at the intersection of BL6 and WL126, the 8th memory cell at the intersection of BL7 and WL126, and the 10th memory cell at the intersection of BL9 and WL126) and 1 memory cell that does not need to be programmed (the 9th memory cell at the intersection of BL8 and WL126). Thus, programming and pressure operations are simultaneously performed on these 4 memory cells that need to be programmed (i.e., while applying pressure to word line WL126, pressure is also applied to BL5, BL6, BL7, and BL9 simultaneously) to write the corresponding data into these 4 memory cells. After the data writing within the P2 programming range is completed, the count value is cleared to zero. If the 11th storage unit is a storage unit that needs to be programmed, the counting starts again from the 11th storage unit, and so on, until the programming and pressurization operations of each storage unit that needs to be programmed within the last programming range Pa on WL126 are completed.

[0081] As shown above, the solution in this application example requires a programming pressurization operations to complete the write data operation of line WL126. Moreover, except for the last programming pressurization operation, each subsequent programming pressurization operation is only executed after counting to 4 memory cells that need to be programmed. Therefore, the programming range of P1 to Pa may vary depending on the number of memory cells that do not need to be programmed within this range.

[0082] contrast Figure 6 and Figure 2 It can be seen that the programming range P1 is greater than the programming range Q1, and in this application example, the corresponding data to be written can be written to the 10th memory unit in the second programming pressurization operation. Figure 2The example shown demonstrates that the corresponding data to be written can only be written to the 10th memory cell in the third programming and pressurization operation, therefore 'a' will be less than 'm'. Thus, it can be seen that, under the same data input as existing technologies, the technical solution of this invention can effectively reduce the number of programming operations in memory write operations and improve memory write efficiency.

[0083] Please refer to Figure 7 In another specific application example, all memory cells are located at the intersection of word lines (WL) and bit lines (BL). Along the direction from BL0 to BL255, the memory cells in each row are sequentially named: the 1st memory cell (located at the intersection of BL0 and the corresponding WL), the 2nd memory cell (located at the intersection of BL1 and the corresponding WL), the 3rd memory cell (located at the intersection of BL2 and the corresponding WL), the 4th memory cell (located at the intersection of BL3 and the corresponding WL), the 5th memory cell (located at the intersection of BL4 and the corresponding WL), the 6th memory cell (located at the intersection of BL5 and the corresponding WL), ..., the 256th memory cell (located at the intersection of BL255 and the corresponding WL). During the programming pressure operation, by applying pressure to different WLs and BLs, information can be written to selected memory cells. Figure 7 In the diagram, a solid black dot indicates that the data in the memory cell does not match the user's expected value and requires programming, while an empty circle indicates that the data in the memory cell matches the user's expected value and does not require programming. The same applies to memory cells in rows WL2 and WL126 of this memory.

[0084] In this application example, if existing technology is used to write data to all memory cells on row WL126, the programming range selected for each programming operation is the same: the total number of memory cells to be programmed and the number of memory cells not to be programmed are both 8. The first programming pressure operation reads the programming buffers corresponding to the 8 memory cells in programming range Q1. After identification, it is found that there are 6 memory cells to be programmed within programming range Q1. Therefore, in subsequent programming pressure operations, in addition to pressure applying pressure to WL126, only BL0 to BL5 corresponding to these 6 memory cells are pressured simultaneously. After writing information to these 6 memory cells, the second programming pressure operation reads the programming buffers corresponding to the 8 memory cells in programming range Q2, and identifies and pressures the 8 memory cells in Q2. This process continues until all memory cells in the last programming range Qc of the memory's write area are identified and pressured. Therefore, the existing solution requires c programming pressure operations to complete the write operation on row WL126.

[0085] If the write data method of the memory of this invention is used to write data to WL2, then n=8, meaning that a single programming and pressurizing operation can only program and pressurize 8 memory cells that need to be programmed simultaneously. At this time, the programming verification, determination, and counting of memory cells that need to be programmed are performed along the direction from the 1st memory cell to the 256th memory cell in the WL2 row. The initial count value is 0. Based on the programming verification result, the count value is incremented by 1 for each memory cell that needs to be programmed. After counting to 8, the count value is reset to zero and the counting restarts. Specifically, when counting to the 10th storage unit (i.e., the storage unit at the intersection of BL9 and WL2), the count value is 8 for the first time. At this point, the programming range is determined as P1. P1 contains 8 storage units that need to be programmed (i.e., storage units 1 to 6, 9 and 10 on WL2) and 2 storage units that do not need to be programmed (i.e., storage units 7 to 8 on WL2). Therefore, programming pressure operations are performed simultaneously on these 8 storage units that need to be programmed in P1 (i.e., on the basis of pressure on WL2, pressure is further applied to BL0 to BL5 and BL8 to BL9 simultaneously) to write the corresponding data into the 8 storage units 1 to 6, 9 and 10 on the WL2 row. After writing data within the P1 programming range, the count is reset to zero, and counting restarts from the 11th memory cell on WL2 (located at the intersection of BL10 and WL2). The programming range is determined to be P2 only when the count reaches 8 for the second time. P2 also contains 8 memory cells that need to be programmed. Therefore, programming and pressure operations are simultaneously performed on these 8 memory cells within P2 to write the corresponding data to them. After writing data within the P2 programming range, the count is reset to zero, and this process continues until the programming and pressure operations on the memory cells requiring programming in the last programming range Pb are completed. Figure 7 The programming range Pb shown contains 8 memory units that need to be programmed and 3 memory units that do not need to be programmed, therefore Pb has a total of 11 memory units. As can be seen from the above, the solution of this invention requires b programming and pressurization operations to complete the write data operation of line WL126.

[0086] contrast Figure 7As can be seen from the data writing process on row W2 and W126 shown: (1) When applying the existing scheme, the size of each programming range is the same, and the total number of memory units that need to be programmed and those that do not need to be programmed in each programming range Q1 to Qc is 8. The number of memory units that need to be programmed in the programming range Q1 to Qc may be different. However, when applying the scheme of the present invention, except for the last programming pressurization operation, each programming pressurization operation must be performed after counting to 8 memory units that need to be programmed. Therefore, the programming range of P1 to Pb may be different due to the different number of memory units that do not need to be programmed in this range (i.e., the programming range is adjustable relative to the existing scheme). Moreover, except for the last programming range Pb, the number of memory units that need to be programmed in each programming range P1 to Pb-1 is equal, which is 8. (2) The programming range P1 is larger than the programming range Q1. The method of the present invention can write the corresponding data to be written to the 10th memory unit in the first programming pressurization operation, while the existing method can only write the corresponding data to be written to the 10th memory unit in the second programming pressurization operation. Therefore, b will be less than c. Therefore, under the same data input as existing solutions, the technical solution of the present invention can effectively reduce the number of programming operations in memory write operations and improve memory write efficiency.

[0087] Please refer to Figure 8 In another specific application example, all memory cells are located at the intersection of word lines (WL) and bit lines (BL). Along the direction from BL0 to BL255, the memory cells in each row are sequentially named: the 1st memory cell (located at the intersection of BL0 and the corresponding WL), the 2nd memory cell (located at the intersection of BL1 and the corresponding WL), the 3rd memory cell (located at the intersection of BL2 and the corresponding WL), the 4th memory cell (located at the intersection of BL3 and the corresponding WL), the 5th memory cell (located at the intersection of BL4 and the corresponding WL), the 6th memory cell (located at the intersection of BL5 and the corresponding WL), ..., the 256th memory cell (located at the intersection of BL255 and the corresponding WL). During the programming pressure operation, by applying pressure to different WLs and BLs, information can be written to the selected memory cells. Figure 8 In the diagram, solid black dots indicate that the data in the storage unit does not match the user's expected value and requires programming, while empty circles indicate that the data in the storage unit matches the user's expected value and does not require programming. In this application example, n=8, meaning that a single programming and pressurization operation can only program and pressurize 8 storage units that require programming simultaneously.

[0088] The memory performs two write operations. The first write operation targets row WL2, and the second write operation targets row WL3. The write process for row WL2 is similar to... Figure 7 The data writing process for line WL2 is the same, so it will not be described in detail here.

[0089] When writing data to WL3, the program verifies the programming of each memory cell in WL3 from the first memory cell to the 256th memory cell, determines which memory cells need to be programmed, and counts them. The initial count is 0. Based on the programming verification results, the count is incremented by 1 for each memory cell that needs to be programmed. After counting to 8, the count is reset to zero and the counting starts again. The counting process begins when the count reaches the 8th memory cell on row WL3 (the memory cell at the intersection of BL7 and WL3), resulting in a count of 8. At this point, the programming range is defined as P1', which contains only 8 memory cells requiring programming (i.e., the 1st to 8th memory cells on WL3). Therefore, programming pressure is applied simultaneously to these 8 memory cells in P1' (i.e., in addition to applying pressure to WL3, BL0 to BL7 are also simultaneously pressured) to write the corresponding data into the 1st to 8th memory cells on row WL3. After writing the data within the P1' programming range, the count is reset to zero. Since the 9th and 10th memory cells on row WL3 do not require programming, the counting restarts from the 11th memory cell on WL3 (located at the intersection of BL10 and WL3). The programming range is defined as P2' when the count reaches 8 for the second time. P2' also contains 8 memory cells. There are eight memory cells that need to be programmed, and the programming and pressure operations are performed simultaneously on these eight memory cells within programming range P2' to write the corresponding data into these eight memory cells. After the data writing within the programming range of P2' is completed, the count value is cleared to zero, and so on, until the programming and pressure operations of the memory cells that need to be programmed in the last programming range Pd' are completed. There are eight memory cells that need to be programmed in each programming range P1' to Pd-1', but only three memory cells that need to be programmed in programming range Pd'. This is because after programming verification reaches the last memory cell on line WL3 (i.e., the last address of line WL3), the count value can only count up to the last memory cell that needs to be programmed on line WL3 (located at the intersection of BL254 and WL3), so the count value cannot reach n in the last round. Obviously, in the last programming and pressure operation, only the three memory cells that need to be programmed in the last programming range Pd' need to be programmed and pressured together.

[0090] In other application examples, n can also be any other suitable value, which will not be elaborated here.

[0091] Based on the same inventive concept, one embodiment of the present invention also provides a system including a memory and a memory controller coupled thereto, wherein the memory controller writes data into the memory using the memory write data method described in any of the embodiments of the present invention described above.

[0092] The memory writing method and system of the present invention can, based on the results of programming verification, simultaneously perform programming and pressure operations on the write area of ​​the memory for every n memory cells that need to be programmed, thereby completing the entire write process of the memory. The size of each programming range is actually calculated according to the number of memory cells n that need to be programmed, excluding memory cells that do not need to be programmed. Therefore, during the memory write operation, the size of the single programming range can be increased to the maximum extent within a limited power consumption, making the programming range of the memory adjustable compared to the prior art. Thus, under the same data input as the prior art, the number of programming operations in the memory write operation can be effectively reduced, thereby improving the write efficiency of the memory.

[0093] Based on the same inventive concept, please refer to Figure 9 An embodiment of the present invention also provides a memory controller 3, which is coupled to a memory 4 and includes a programming verification module 31 and a programming pressure module 34. The programming verification module 31 is configured to perform programming verification on the memory 4 to determine the location and number of memory cells that need to be programmed in the write area of ​​the memory 4; the programming pressure module 34 is coupled to the programming verification module 31 and is configured to, based on the programming verification result of the programming verification module 31, simultaneously perform programming pressure operations on every n memory cells that need to be programmed to complete the entire write data process of the memory, where n is greater than 1 and is an integer.

[0094] Optionally, the memory controller 3 further includes a programming cache 30, which is configured to cache at least one of the data to be written in the memory 4 and the programming verification result of the programming verification module 31. The programming verification module 31 is coupled to the programming cache 30 and is further configured to: read the data cached in the programming cache 30 and verify whether the stored data in each memory cell in the write area of ​​the memory 4 is consistent with the corresponding write data read from the programming cache 30. If they are consistent, the memory cell does not need to be programmed; if they are inconsistent, the memory cell needs to be programmed. The programming cache 30 can be any suitable cache such as SRAM, or it can be a dedicated storage area in the memory 4; the present invention does not impose specific limitations on this.

[0095] Optionally, the memory controller 3 further includes a programming counter 32, which is coupled to the programming verification module 31 and the programming pressure module 34, and is configured to count the memory cells that need to be programmed in the write area of ​​the memory 4 according to the programming verification result of the programming verification module 31, and the count value does not exceed n, so that the count value is cleared when n is reached to prepare for the next round of counting. The programming pressure module 34 is further configured to simultaneously apply programming pressure to each memory cell that needs to be programmed corresponding to the current round count result of the programming counter 32, so as to write the corresponding data to be written into each memory cell that needs to be programmed corresponding to the current round count result of the programming counter 32.

[0096] Optionally, the memory controller 3 further includes a programming judgment module 33, which is coupled to the programming counter 32 and the programming pressure module 34, and is configured to: determine whether the current count value of the programming counter has reached n; if it has, then clear the count value of the programming counter 32 to end the current round of counting, and prepare for the next round of counting; if it has not reached n, then further determine whether the programming counter 32 has currently counted to the last memory cell that needs to be programmed in the write area of ​​the memory 4; if so, then end the current round of counting of the programming counter 32; if not, then allow the programming counter 32 to continue counting. Further optionally, the programming judgment module 33 can also be coupled to the programming buffer 30, and is configured to read the programming verification results in the programming buffer 30, and determine whether each memory cell in the write area of ​​the memory 4 needs to be programmed based on the programming verification results; and when it is determined that the current memory cell needs to be programmed, increment the count value of the programming counter 32 by 1.

[0097] It should be understood that, in the memory controller of this embodiment, the programming cache 30, programming verification module 31, programming counter 32, programming judgment module 33, and programming pressure module 34 can be implemented in one device, or any one of these modules can be split into multiple units, or at least part of the functions of one or more of these modules can be combined with at least part of the functions of other modules and implemented in one module or unit. Furthermore,

[0098] In the wafer defect classification system according to an embodiment of the present invention, at least one of the programming buffer 30, programming verification module 31, programming counter 32, programming judgment module 33, and programming pressure module 34 can be at least partially implemented as hardware circuits, such as field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), systems-on-a-chip, systems-on-a-substrate, systems-on-package, application-specific integrated circuits (ASICs), or can be implemented in hardware or firmware in any other reasonable manner of integrating or packaging circuits, or in a suitable combination of software, hardware, and firmware implementations. Alternatively, at least one of the programming buffer 30, programming verification module 31, programming counter 32, programming judgment module 33, and programming pressure module 34 can be at least partially implemented as computer program modules, which, when run by a computer, can execute the functions of the corresponding modules and can be upgraded via software.

[0099] Based on the same inventive concept, please continue to refer to Figure 9 An embodiment of the present invention also provides a system including a memory 4 and a memory controller 3 as described in the above embodiments. The memory controller 3 is coupled to the memory 4 and controls the read and write data operations of the memory 4.

[0100] In summary, the memory controller and system of the present invention, when performing memory write operations, can simultaneously perform programming and pressure operations on the memory's write area based on the results of programming verification, thereby completing the entire write process of the memory. This maximizes the size of a single programming range within a limited power consumption, making the memory's programming range adjustable compared to existing technologies. Consequently, with the same data input as existing technologies, the number of programming operations in memory write operations can be effectively reduced, improving memory write efficiency.

[0101] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for writing data to a memory, characterized in that, Includes the following steps: The memory is programmed and verified to determine the location and number of memory cells that need to be programmed in the write area of ​​the memory; Based on the results of the programming verification, the area to be written is programmed and pressured by simultaneously performing programming and pressure operations on every n memory cells that need to be programmed, so as to complete the entire data writing process of the memory. Here, n is greater than 1 and is an integer.

2. The method for writing data to a memory as described in claim 1, characterized in that, The steps for verifying the programming of the memory include: The data to be written in the memory is cached in the programming cache; The programming buffer is read, and it is verified whether the stored data in each storage unit in the write area is consistent with the corresponding write data read from the programming buffer. If they are consistent, the storage unit does not need to be programmed; if they are inconsistent, the storage unit is the storage unit that needs to be programmed.

3. The method for writing data to a memory as described in claim 1 or 2, characterized in that, The step of verifying the programming of the memory further includes: caching the result of the programming verification into the programming cache.

4. The method for writing data to a memory as described in claim 1, characterized in that, Programming and pressure application to the write area only begins after all memory cells in the write area have been programmed and verified; alternatively, programming and pressure application can be performed on the memory cells in the write area that have been identified as needing programming, while simultaneously verifying the programming of the corresponding memory cells in the write area.

5. The method for writing data to a memory as described in claim 4, characterized in that, The steps of programming and pressurizing the memory's writable region include: The memory cells that need to be programmed in the results of the programming verification are counted in address order; Determine whether the current count value has reached n, where n is the number of memory units that need to be programmed that can be programmed and pressurized simultaneously in one operation; If the target is reached, then the programming pressure operation is performed simultaneously on the n memory units that need to be programmed in this round of counting, so as to write the corresponding data to be written into the n memory units that need to be programmed, and then the count value is cleared to prepare for the start of the next round of counting. If not, determine whether the current count has reached the last memory cell that needs to be programmed in the write area. If yes, stop counting and simultaneously perform programming pressure operation on all memory cells that need to be programmed in this round of counting to write the corresponding data to be written into each memory cell that needs to be programmed in this round of counting. If not, continue counting in this round.

6. The method for writing data to a memory as described in claim 5, characterized in that, The step of programming and pressurizing the memory to be written area further includes: whenever the count value of the current round reaches n or the last memory cell to be programmed in the memory to be written area is counted, the address of the last memory cell to be programmed in the current round is recorded, and it is further determined whether the recorded address is the address of the last memory cell to be programmed in the memory to be written area. If so, the entire data writing process of the memory is ended after the programming and pressurizing operation of the current round is completed.

7. A memory controller, characterized in that, include: The programming verification module is configured to perform programming verification on the memory to determine the location and number of memory cells that need to be programmed in the write area of ​​the memory; The programming pressure module is coupled to the programming verification module and is configured to program and pressure the area to be written by simultaneously performing programming pressure operations on every n memory units that need to be programmed, based on the programming verification results of the programming verification module, so as to complete the entire data writing process of the memory. Here, n is greater than 1 and is an integer.

8. The memory controller as claimed in claim 7, characterized in that, It also includes a programming cache, which is configured to cache the data to be written in the memory; the programming verification module is coupled to the programming cache and is further configured to: read the programming cache and verify whether the stored data in each storage unit in the area to be written is consistent with the corresponding data to be written read from the programming cache; if they are consistent, the storage unit does not need to be programmed; if they are inconsistent, the storage unit is the storage unit that needs to be programmed.

9. The memory controller as claimed in claim 8, characterized in that, The programming verification module is further configured to cache the result of the programming verification in the programming cache.

10. The memory controller as claimed in any one of claims 7-9, characterized in that, It also includes a programming counter, which is coupled to the programming verification module and the programming pressure module, and is configured to count the memory cells that need to be programmed in the area to be written according to the programming verification result of the programming verification module, and the count value does not exceed n, so that the count value is cleared when n is counted to start the next round of counting; The programming pressure module is configured to simultaneously program and pressure each of the memory units that need to be programmed corresponding to the current count result of the programming counter, so as to write the corresponding data to be written into each of the memory units that need to be programmed corresponding to the current count result of the programming counter.

11. The memory controller as claimed in claim 10, characterized in that, It also includes a programming judgment module, which is coupled to the programming counter and the programming pressure module, and is configured to: Determine whether the current count value of the programming counter has reached n. If it has, clear the count value of the programming counter to end the current round of counting and start the next round of counting. If it has not reached n, further determine whether the programming counter has counted to the last memory unit that needs to be programmed in the area to be written. If it has, end the current round of counting of the programming counter. If not, let the programming counter continue counting.

12. A system, characterized in that, The system includes a memory and a coupled memory controller, wherein the memory controller writes data into the memory using the memory write method as described in any one of claims 1-6; Alternatively, the system may include a memory and a memory controller as described in any one of claims 7-11, the memory controller being coupled to the memory and controlling read and write operations of the memory.

Images