A gate drive circuit with adjustable pull-in and pull-off current capability

Abstract

This invention relates to the field of gate drive circuit technology and discloses a gate drive circuit with adjustable pull-in / pull current capability, including a first-stage level shift circuit, a second-stage level shift circuit, a signal shaping and enhancement circuit, and a configurable push-pull output circuit. The first-stage level shift circuit generates a clamping voltage rail to limit the signal swing; the second-stage level shift circuit converts the ground potential logic signal into a high-voltage floating signal; the signal shaping and enhancement circuit performs waveform shaping and power amplification on the signal. The configurable push-pull output circuit includes multiple parallel push-pull drive branches, divided into normally-operated basic drive branches and optional drive branches controlled by digital signals. This invention dynamically adjusts the total equivalent channel width of the output stage transistor by changing the number of parallel branches in operation, providing a large current to reduce losses when driving large loads and limiting the current to suppress electromagnetic interference when driving small loads, thus achieving flexible adaptation of drive characteristics to load requirements.

Description

Technical Field

[0001] This invention relates to the field of gate drive circuit technology, specifically to a gate drive circuit with adjustable pull-in / sink current capability. Background Technology

[0002] The gate drive circuit, as a key interface unit in power electronic conversion systems, mainly connects the low-voltage microcontroller or digital signal processor to the high-voltage power semiconductor device. Its core function is to receive low-power logic pulse signals from the control unit and, through internal level conversion and power amplification, provide a drive signal with sufficient amplitude and current capability to the gate of the power device to rapidly charge and discharge the gate input capacitor, thereby precisely controlling the switching of the power device between the on and off states.

[0003] In existing technologies, gate drive circuits commonly employ a push-pull output stage structure based on complementary metal-oxide-semiconductor (CMOS) technology. This involves connecting P-type and N-type field-effect transistors in series to handle current up and down, respectively. During integrated circuit design and manufacturing, the physical dimensions of the output stage transistors, particularly the channel width to channel length ratio, are typically fixed based on predetermined typical application scenarios. This results in the output impedance of the drive circuit and its maximum peak pull-in / pull-out current becoming immutable values ​​after chip packaging.

[0004] However, this drive circuit architecture with fixed output characteristics struggles to meet the system performance requirements under different load characteristics. Since the gate charge of power semiconductor devices varies significantly depending on their power rating and manufacturing process, when the drive circuit is applied to a large capacitor load, the fixed drive current is often insufficient to support fast switching, leading to a prolonged Miller plateau duration and significantly increased switching losses. Conversely, when applied to a small capacitor load, an excessively large drive current margin can cause extremely high voltage and current change rates, resulting in severe parasitic oscillations and overshoot in the gate voltage, thereby deteriorating the system's electromagnetic compatibility performance. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a gate drive circuit with adjustable pull-in current capability, thus solving the problem.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a gate drive circuit with adjustable pull-in / pull current capability, wherein the gate drive circuit is connected between the high-side supply voltage BST and the switching node voltage SH, and is configured to drive the high-side power transistor. The gate drive circuit mainly includes a first-stage level shift circuit, a second-stage level shift circuit, a signal shaping and enhancement circuit, and a configurable push-pull output circuit.

[0007] The first-stage level shifting circuit connects the high-side supply voltage BST and the switching node voltage SH. This circuit is configured to generate two floating reference voltage rails: an upper clamping voltage VPCLAMP and a lower clamping voltage VNCLAMP. The upper clamping voltage VPCLAMP is lower than the high-side supply voltage BST by a first preset voltage value, and the lower clamping voltage VNCLAMP is higher than the switching node voltage SH by a second preset voltage value. This first-stage level shifting circuit establishes a safe voltage operating range, preventing gate-source overvoltage breakdown in subsequent circuitry.

[0008] The signal input of the second-stage level shift circuit is connected to the external control signal input IN. The second-stage level shift circuit is configured to transmit signals from the low-voltage logic domain to the high-voltage floating logic domain, converting a low-voltage pulse-width modulated signal based on ground potential into a high-voltage drive signal that floats based on the switching node voltage SH. During this process, the second-stage level shift circuit uses the upper clamping voltage VPCLAMP and the lower clamping voltage VNCLAMP to limit the voltage swing of the internal control node.

[0009] The signal shaping and enhancement circuit is connected to the signal output terminal of the second-stage level shifting circuit. The signal shaping and enhancement circuit is configured to perform waveform shaping and progressively amplify the driving capability of the high-voltage drive signal, and output a first drive control signal and a second drive control signal. The signal shaping and enhancement circuit employs a progressively amplified buffer stage structure to match the output impedance of the preceding stage circuit and drive the input capacitor of the following stage circuit.

[0010] A configurable push-pull output circuit is connected between the output of the signal shaping and enhancement circuit and the gate of the high-side power transistor. The configurable push-pull output circuit includes multiple parallel push-pull drive branches, each including at least one basic drive branch and one optional drive branch. The basic drive branch is configured in a normally-on operating mode, continuously switching in response to the first drive control signal and the second drive control signal. The optional drive branch is configured in a controlled operating mode controlled by a digital selection signal SEL. The configurable push-pull output circuit controls the enabled or disabled state of the optional drive branch through logic gates, thereby changing the number of parallel push-pull drive branches participating in the operation.

[0011] In a specific implementation, the output current capability of the gate drive circuit depends on the physical characteristics of the output stage field-effect transistor. Based on the saturation current characteristics of the metal-oxide-semiconductor field-effect transistor, the drive current... With the channel width of the transistor and channel length The ratios are related, and the relationship is expressed as:

[0012]

[0013] In the formula, For carrier mobility, The capacitance per unit area of ​​the gate oxide layer. Gate-source voltage, Threshold voltage, The total equivalent channel width of all transistors in operation in the configurable push-pull output circuit.

[0014] By controlling the number of selectable drive branches connected to the circuit using the digital selection signal SEL, the total equivalent channel width in the above formula is substantially changed. When the number of the accessible optional drive branches increases, Increase the drive current provided by the gate drive circuit. Increase; when the number of the available drive branches decreases. The drive current provided by the gate drive circuit is reduced. Decrease.

[0015] A second aspect of the present invention provides a method for adjusting the driving capability based on the gate driving circuit.

[0016] The method includes: generating a clamping voltage rail adapted to high-side drive through a first-stage level shifting circuit; converting a low-voltage control signal into a high-voltage drive signal through a second-stage level shifting circuit; and amplifying the signal through a signal shaping and enhancement circuit.

[0017] The core of this method lies in the configuration of the output stage: receiving the digital selection signal SEL, and controlling the on / off state of the selectable drive branch in the configurable push-pull output circuit according to the logic state of the digital selection signal SEL.

[0018] When driving a large capacitive load, the control logic responds to a valid digital selection signal SEL and enables the optional drive branch. The optional drive branch operates in parallel with the basic drive branch, superimposing the output current to improve the charging and discharging speed of the load capacitor and reduce the switching losses of the high-side power transistor.

[0019] When driving a small capacitive load, the control logic responds to the invalid digital selection signal SEL, disabling the optional drive branch and placing it in a high-impedance state. At this time, only the basic drive branch operates, limiting the peak output current to reduce the rate of voltage and current change during switching, suppressing electromagnetic interference and voltage overshoot.

[0020] Furthermore, this method also involves transmission delay matching during the signal shaping and enhancement stage. By adjusting the delay times of the high-side signal transmission path and the low-side signal transmission path, the transmission delays of the upper-side drive signal and the lower-side drive signal are made consistent, thereby maintaining the preset dead time in the input signal and preventing the power transistor from shoot-through short-circuiting.

[0021] This invention provides a gate drive circuit with adjustable pull-in / sink current capability. It has the following advantages: 1. This invention utilizes digital logic to control the activation status of multiple parallel push-pull branches in the output stage, enabling a step-wise adjustment of the total equivalent channel width of the field-effect transistor. When driving large capacitive loads, the circuit engages more branches to output larger currents, significantly reducing switching losses. When driving small capacitive loads, the circuit retains only the basic branches to limit the rate of current change, effectively suppressing voltage overshoot and electromagnetic interference. This dynamic reconfiguration mechanism at the hardware level solves the technical challenge of traditional fixed-parameter drive circuits simultaneously achieving high switching speed and electromagnetic compatibility performance, enabling precise adaptation to loads of different power levels.

[0022] 2. This invention constructs a floating low-voltage operating range between the high-voltage power supply terminal and the switching node terminal by setting up a two-stage level shifting architecture combined with voltage clamping technology. The first-stage circuit uses voltage regulators to generate a reference voltage rail that follows the floating potential, strictly limiting the voltage swing of the internal control signal. This design ensures that the low-voltage transistors used for signal transmission always withstand a safe gate-source voltage, avoiding gate oxide layer breakdown caused by overvoltage stress in high-voltage floating environments. Thus, without using expensive high-voltage withstand devices, the circuit's withstand voltage reliability in high-voltage applications is significantly improved.

[0023] 3. This invention optimizes the waveform steepness and timing accuracy of internal control signals by integrating a progressively amplified signal shaping unit and transmission delay matching logic. Employing an inverter chain structure with increasing physical dimensions, it achieves impedance transformation from high-impedance logic input to low-impedance power output, ensuring rapid drive of subsequent parallel branches. Simultaneously, delay calibration of the high-side and low-side signal paths eliminates dead-time deviations caused by transmission path differences, preventing shoot-through short circuits in the power transistor bridge arms and ensuring the timing safety of the power electronic system under high-frequency switching operations. Attached Figure Description

[0024] Figure 1 Schematic diagram of a gate drive circuit with adjustable pull-in current; Figure 2 This is a schematic diagram of the first-stage level shifting circuit; Figure 3 This is a schematic diagram of the second-stage level shifting circuit. Detailed Implementation

[0025] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Please see the appendix Figure 1 -Appendix Figure 3 This invention provides a gate drive circuit with adjustable pull-in / pull-out current capability, used to drive a high-side power transistor, typically an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). The gate drive circuit is connected between the high-side supply voltage BST and the switching node voltage SH. The gate drive circuit includes a first-stage level shift circuit, a second-stage level shift circuit, a signal shaping and enhancement circuit, and a configurable push-pull output circuit.

[0027] The first-stage level shifting circuit connects the high-side supply voltage BST terminal and the switching node voltage SH terminal. This circuit is configured to generate the clamping voltage rails required for internal control. The first-stage level shifting circuit outputs an upper clamping voltage VPCLAMP and a lower clamping voltage VNCLAMP. The upper clamping voltage VPCLAMP is set to be lower than the high-side supply voltage BST by a first preset voltage value. The lower clamping voltage VNCLAMP is set to be higher than the switching node voltage SH by a second preset voltage value. In one specific embodiment, both the first and second preset voltage values ​​are 5V, meaning the upper clamping voltage VPCLAMP equals BST minus 5V, and the lower clamping voltage VNCLAMP equals SH plus 5V. The upper clamping voltage VPCLAMP and the lower clamping voltage VNCLAMP serve as the power and ground rails for the internal high-voltage side control signals, providing a safe voltage operating range for subsequent level shifting operations and preventing gate-source overvoltage breakdown of internal devices.

[0028] The signal input terminal of the second-stage level shifter circuit is connected to the external control signal input terminal IN, and the signal output terminal of the second-stage level shifter circuit is connected to the input terminal of the signal shaping and enhancement circuit. The external control signal input terminal IN receives a low-voltage pulse width modulation (PWM) signal. The second-stage level shifter circuit is configured to convert the low-voltage PWM signal based on ground potential into a high-voltage drive signal based on the floating switching node voltage SH.

[0029] Specifically, the second-stage level shifting circuit responds to the level transition of the low-voltage PWM signal, controls the on and off of the internal high-voltage transistor, thereby changing the potential state of the output node. The second-stage level shifting circuit uses the upper clamping voltage VPCLAMP and the lower clamping voltage VNCLAMP to limit the voltage swing of the internal control node, ensuring that the high-voltage drive signal transitions within the preset voltage range.

[0030] The signal shaping and enhancement circuit is connected between the second-stage level shift circuit and the configurable push-pull output circuit. The signal shaping and enhancement circuit includes a multi-stage cascaded inverter chain. This chain is configured to shape and amplify the high-voltage drive signal. The signal shaping and enhancement circuit outputs a first drive control signal to control the conduction of the current-source transistor and a second drive control signal to control the conduction of the current-sink transistor. For the specific circuit structure of the inverter chain, those skilled in the art can implement it using a CMOS inverter structure. CMOS inverter structures are well-known in the art and will not be described in detail here.

[0031] The configurable push-pull output circuit is the final output stage of the gate drive circuit. The output of the configurable push-pull output circuit is connected to the gate of the high-side power transistor. The configurable push-pull output circuit includes multiple push-pull drive branches connected in parallel. Each of the multiple parallel push-pull drive branches includes at least one basic drive branch and one or more optional drive branches. The outputs of all push-pull drive branches are connected to the same node to drive the high-side power transistor. The basic drive branch is configured to be normally on, continuously responding to the first drive control signal and the second drive control signal. The optional drive branches are connected to a configuration signal input, which receives a digital selection signal SEL. The digital selection signal SEL determines the enabled or disabled state of the optional drive branch through a control logic gate circuit.

[0032] When the digital selection signal SEL is valid, the selectable drive branch and the basic drive branch switch simultaneously, providing charging and discharging current to the gate of the high-side power transistor. When the digital selection signal SEL is invalid, the selectable drive branch is in a high-impedance state or a cutoff state, and only the basic drive branch provides charging and discharging current to the gate of the high-side power transistor.

[0033] The configurable push-pull output circuit adjusts the total current drive capability of the output stage by changing the number of branches operating in parallel. The current drive capability of the gate drive circuit depends on the width-to-length ratio of the output stage MOSFET. The current formula for the MOSFET in the saturation region is as follows:

[0034] In the formula, This represents the drain-source current, i.e., the drive current; Indicates carrier mobility; This represents the capacitance per unit area of ​​the gate oxide layer; Indicates the channel width of the MOSFET; Indicates the channel length of the MOSFET; Indicates the gate-source voltage; This represents the threshold voltage.

[0035] With a fixed semiconductor manufacturing process, carrier mobility Gate oxide layer capacitance per unit area Length of the trench and threshold voltage All are constant values. Drive current. With the width of the trench They are directly proportional. In the mode where multiple push-pull drive branches operate in parallel, the total equivalent channel width of the configurable push-pull output circuit is equal to the sum of the channel widths of the MOS transistors in all enabled push-pull drive branches.

[0036] By controlling the access of selectable drive branches via the digital selection signal SEL, the total equivalent channel width of the configurable push-pull output circuit is substantially altered. Increasing the number of selectable drive branches increases the total equivalent channel width, thereby improving the charging and discharging speed of the gate capacitor of the high-side power transistor by the gate drive circuit, making it suitable for high-load applications. Conversely, decreasing the number of selectable drive branches decreases the total equivalent channel width, limiting the peak charging and discharging current and reducing electromagnetic interference (EMI) and voltage overshoot during switching, making it suitable for low-load applications. This method of changing the output stage's equivalent channel width based on digital signal control achieves dynamic matching between drive capability and load characteristics.

[0037] Following the description of the overall architecture above, the first-stage level shifter circuit in the gate drive circuit functions as the one that constructs the reference voltage rail. The first-stage level shifter circuit is connected between the high-side supply voltage BST and the switching node voltage SH. Utilizing the reverse breakdown characteristic or forward conduction voltage drop characteristic of the voltage regulator, the first-stage level shifter circuit generates two logic level reference points floating above the switching node voltage SH.

[0038] The first-stage level shifting circuit includes an upper clamping voltage generation circuit. This circuit is connected to the high-side supply voltage BST. The upper clamping voltage generation circuit is configured to output an upper clamping voltage VPCLAMP. It includes a first clamping diode D3 and a first biasing element. The first clamping diode D3 is configured as a Zener diode. The cathode of the first clamping diode D3 is connected to the high-side supply voltage BST. The anode of the first clamping diode D3 is connected to the upper clamping voltage output terminal. This upper clamping voltage output terminal is the node where the upper clamping voltage VPCLAMP is output. The first biasing element is connected between the upper clamping voltage output terminal and the switching node voltage SH, or connected to ground. This first biasing element provides the bias current required for reverse breakdown of the first clamping diode D3, establishing a stable potential for the upper clamping voltage VPCLAMP.

[0039] The breakdown voltage of the first clamping diode D3 is set to a first specific voltage value. In this embodiment, the first specific voltage value is selected as 5V. The potential of the upper clamping voltage VPCLAMP is equal to the potential of the high-side supply voltage BST minus the breakdown voltage of the first clamping diode D3. That is:

[0040] The upper clamping voltage VPCLAMP serves as the low-level reference voltage for the current-source transistor MP in subsequent logic circuits. When the gate potential of the current-source transistor MP is pulled low to the upper clamping voltage VPCLAMP, the gate-source voltage of the current-source transistor MP... When the negative turn-on threshold is reached, such as -5V, the pull-out current transistor MP enters the conduction state.

[0041] The first-stage level shifting circuit also includes a lower clamping voltage generation circuit. The lower clamping voltage generation circuit is connected to the switching node voltage SH. The lower clamping voltage generation circuit is configured to output a lower clamping voltage VNCLAMP. The lower clamping voltage generation circuit includes a second clamping diode D2 and a second biasing element. The second clamping diode D2 is configured as a Zener diode. The anode of the second clamping diode D2 is connected to the switching node voltage SH. The cathode of the second clamping diode D2 is connected to the lower clamping voltage output terminal. The lower clamping voltage output terminal is the node that outputs the lower clamping voltage VNCLAMP. The second biasing element is connected between the high-side supply voltage BST and the lower clamping voltage output terminal. The second biasing element is configured to draw current from the high-side supply voltage BST to the cathode of the second clamping diode D2, maintaining the second clamping diode D2 in a reverse breakdown state.

[0042] The breakdown voltage of the second clamping diode D2 is set to a second specific voltage value. In this embodiment, the second specific voltage value is selected as 5V. The potential of the lower clamping voltage VNCLAMP is equal to the potential of the switching node voltage SH plus the breakdown voltage of the second clamping diode D2. That is:

[0043] The lower clamping voltage VNCLAMP serves as the high-level reference voltage for the current sink transistor MN in subsequent logic circuits. When the gate potential of the current sink transistor MN is pulled high to the lower clamping voltage VNCLAMP, the gate-source voltage of the current sink transistor MN... When the positive turn-on threshold is reached, such as +5V, the sinking current tube MN enters the conduction state.

[0044] Regarding the first clamping diode D3 and the second clamping diode D2 described in the specification, in addition to the implementation using Zener diodes, those skilled in the art can also use a series-connected forward-conducting diode group, a MOSFET configured as a diode connection, or a low-dropout linear regulator (LDO) structure to achieve the voltage clamping function. Any circuit structure that can maintain a constant voltage difference between the upper clamping voltage VPCLAMP and the high-side supply voltage BST, or between the lower clamping voltage VNCLAMP and the switching node voltage SH, falls within the technical scope of the voltage clamping unit covered by the claims of this invention.

[0045] Through the cooperation of the upper and lower clamping voltage generation circuits, the first-stage level shifting circuit defines a clear signal swing range for the subsequent second-stage level shifting circuit. Specifically, the first-stage level shifting circuit ensures that the signal controlling the subsequent current-pull transistor swings only between the high-side supply voltage BST and the upper clamping voltage VPCLAMP, while simultaneously ensuring that the signal controlling the subsequent current-sink transistor swings only between the lower clamping voltage VNCLAMP and the switching node voltage SH. This rail-separated clamping design avoids excessive control signal amplitude that could cause breakdown damage to the gate oxide layer of the transistors in the subsequent push-pull output stage, ensuring circuit reliability under high-voltage driving conditions.

[0046] The second-stage level shifter circuit is connected between the external control signal input terminal IN and the signal shaping and enhancement circuit. The second-stage level shifter circuit is configured to realize signal transmission from the low-voltage logic domain to the high-voltage floating logic domain. The second-stage level shifter circuit uses the upper clamping voltage VPCLAMP and the lower clamping voltage VNCLAMP generated by the first-stage level shifter circuit to define the voltage swing of the internal control signal on the high-voltage side.

[0047] The second-stage level shifter circuit includes a logic control circuit, a high-voltage transmission unit, and a high-side latch output unit. The logic control circuit receives an externally input pulse-width modulation signal IN and generates a pair of complementary logic control signals to control the first high-voltage transistor M13 and the second high-voltage transistor M19 in the high-voltage transmission unit. Both the first high-voltage transistor M13 and the second high-voltage transistor M19 are high-voltage-resistant N-type laterally diffused metal-oxide-semiconductor (LDMOS) devices, whose drains can withstand the high voltage difference between the high-side supply voltage BST and ground potential.

[0048] The high-side latch output unit is connected between the high-side supply voltage BST and the upper clamping voltage VPCLAMP. The high-side latch output unit includes a first load element, a second load element, and a push-pull buffer stage consisting of a fourth transistor M24 and a fifth transistor M26.

[0049] When the externally input pulse width modulation signal IN transitions from low to high, the first high-voltage transistor M13 receives the high-level signal and enters the conducting state. The conduction of the first high-voltage transistor M13 generates a pull-down current flowing from the high-side supply voltage BST. This pull-down current flows through the first load element, generating a voltage drop at the gate of the fourth transistor M24, pulling the gate potential of the fourth transistor M24 down to near the upper clamping voltage VPCLAMP.

[0050] The fourth transistor, M24, is a P-type field-effect transistor, with its source connected to the high-side supply voltage BST. When its gate potential is pulled low, the fourth transistor M24 satisfies the turn-on condition. The circuit is then turned on. Simultaneously, this low-level signal acts on the gate of the fifth transistor M26, causing the N-type fifth transistor M26 to turn off. At this time, the output terminal OUT of the second-stage level shift circuit is pulled up to the high-side supply voltage BST through the conducting fourth transistor M24.

[0051] When the externally input pulse width modulation signal IN transitions from high to low, the logic control circuit drives the second high-voltage transistor M19 to turn on. Similarly, the pull-down current generated by the second high-voltage transistor M19 flows through the second load element, changing the state of the internal latch node. For example, through a cross-coupling structure or reset transistor M20, this restores the gate potential of the fourth transistor M24 to the high-side supply voltage BST, thereby turning off the fourth transistor M24. Simultaneously, the gate of the fifth transistor M26 is driven high and turns on. At this time, the output terminal OUT of the second-stage level shift circuit is pulled down to the upper clamping voltage VPCLAMP through the turned-on fifth transistor M26.

[0052] Through the above process, the second-stage level shifting circuit converts the ground-based PWM signal into a high-voltage drive signal that oscillates between the high-side supply voltage BST and the upper clamping voltage VPCLAMP. This high-voltage drive signal is then input to a signal shaping and enhancement circuit to drive the current-source transistor MP in the configurable push-pull output circuit.

[0053] It should be noted that, for the lower drive signal controlling the current sinking transistor MN, the second-stage level shift circuit contains another set of high-voltage transmission branches with a symmetrical structure. This branch converts the input signal into a signal that oscillates between the switching node voltage SH and the lower clamping voltage VNCLAMP. Its working principle is the same as the generation process of the upper drive signal described above, and will not be repeated here.

[0054] The signal shaping and enhancement circuit is connected between the signal output of the second-stage level shift circuit and the configurable push-pull output circuit. The signal shaping and enhancement circuit is configured to receive the high-voltage drive signal from the second-stage level shift circuit, perform waveform shaping and progressive amplification of the high-voltage drive signal, and output a steep-edge internal gate control signal.

[0055] The signal shaping and enhancement circuit includes a high-side signal shaping branch for driving the high-side power transistors and a low-side signal shaping branch for driving the low-side power transistors. The operating voltage rail of the high-side signal shaping branch is connected to the high-side supply voltage BST and the upper clamping voltage VPCLAMP. The operating voltage rail of the low-side signal shaping branch is connected to the lower clamping voltage VNCLAMP and the switching node voltage SH.

[0056] Both the high-side signal shaping branch and the low-side signal shaping branch employ a multi-stage cascaded inverter chain structure. In a specific embodiment, the multi-stage cascaded inverter chain includes an even number of inverter units connected in series to ensure that the output signal of the signal shaping and enhancement circuit maintains a non-in-phase logic relationship with the input signal. Each stage of the multi-stage cascaded inverter chain consists of a P-type metal-oxide-semiconductor field-effect transistor (PMOS) and an N-type metal-oxide-semiconductor field-effect transistor (NMOS) connected in series.

[0057] To achieve a progressively increased drive current capability, the physical dimensions of the transistors in a multi-stage cascaded inverter chain increase progressively along the signal propagation direction. Specifically, the channel width of the transistor in the Nth stage inverter unit is defined as... The channel width of the transistor in the (N+1)th stage inverter unit is ,but Set to be greater than In a preferred embodiment, and The ratio is set between 2 and 4.

[0058] With the above-described size configuration, the first-stage inverter unit has the smallest transistor channel width and the smallest input gate capacitance, thus exhibiting high input impedance characteristics to match the limited output drive capability of the second-stage level shifter circuit and reduce signal transmission delay. The final-stage inverter unit has the largest transistor channel width and the largest transient output current capability, thus exhibiting low output impedance characteristics to quickly drive the parasitic capacitances of multiple parallel branches in the subsequent configurable push-pull output circuit.

[0059] In addition, the signal shaping and enhancement circuit is equipped with a transmission delay matching unit. This unit adjusts the number of inverter stages or transistor sizes in the high-side and low-side signal shaping branches to ensure consistent signal transmission delay times for both the high-side and low-side drive paths. This transmission delay matching design aims to maintain the preset dead time of external control signals, preventing shoot-through short circuits in the high-side and low-side power transistors due to inconsistent transmission delays.

[0060] The output of the signal shaping and enhancement circuit is connected to the gate input of the basic drive branch and the optional drive branch in the configurable push-pull output circuit, respectively.

[0061] A configurable push-pull output circuit is connected between the output of the signal shaping and enhancement circuit and the gate of the high-side power transistor. As the final power execution stage of the gate drive circuit, the configurable push-pull output circuit is configured to dynamically adjust the gate drive current of the high-side power transistor according to external digital control commands. The power input of the configurable push-pull output circuit is connected to the high-side supply voltage BST, and the ground reference terminal of the configurable push-pull output circuit is connected to the switching node voltage SH.

[0062] The configurable push-pull output circuit includes multiple push-pull drive branches connected in parallel. Specifically, each of the multiple parallel push-pull drive branches includes one basic drive branch and at least one optional drive branch. In this embodiment, the number of optional drive branches is set to two: a first optional drive branch and a second optional drive branch. The outputs of the basic drive branch, the first optional drive branch, and the second optional drive branch are connected to the same drive output node HO. The drive output node HO is connected to the gate of an external high-side power transistor.

[0063] The basic drive branch is configured for constant-on operation. It includes a basic source transistor (MP0) and a basic sink transistor (MN0). MP0 is a P-type field-effect transistor (FET), and MN0 is an N-type FET. The source of MP0 is connected to the high-side supply voltage BST, and its drain is connected to the drive output node HO. MP0's gate directly receives the high-side drive signal from the signal shaping and enhancement circuit. MN0's source is connected to the switching node voltage SH, and its drain is connected to the drive output node HO. MN0's gate directly receives the low-side drive signal from the signal shaping and enhancement circuit. During circuit operation, the basic drive branch continuously follows the changes in the high-side and low-side drive signals, performing pull-up or pull-down operations on the drive output node HO.

[0064] The first and second optional drive branches are configured in a controlled operating mode. The first optional drive branch includes a first gating logic unit, a first current-source transistor MP1, and a first current-sinking transistor MN1. To accommodate the floating voltage domain of the high-side drive circuit, the first gating logic unit is connected to a control signal level shifter. The control signal level shifter is configured to convert the ground-potential-based digital selection signal SEL into an internal selection signal that floats based on the switching node voltage SH.

[0065] The first strobing logic unit consists of logic gates whose power supply is connected to the high-side supply voltage BST. The first strobing logic unit has a signal input terminal and an enable control terminal. The signal input terminal is connected to the output of the signal shaping and enhancement circuit. The enable control terminal receives the first bit signal SEL after level shifting. <0> .

[0066] When the first signal SEL <0> When the active level is high, the first gating logic unit performs a transmission operation on the input signal, transmitting the high-side drive signal to the gate of the first current-source transistor MP1 and the low-side drive signal to the gate of the first current-sink transistor MN1. At this time, the first selectable drive branch participates in driving the output node HO.

[0067] When the first signal SEL <0> When the signal level is invalid, such as low, the first gating logic unit performs a level clamping operation. The first gating logic unit outputs a high level to clamp the gate potential of the first current-source transistor MP1 to the high-side supply voltage BST, causing MP1 to turn off. Simultaneously, the first gating logic unit outputs a low level to clamp the gate potential of the first current-sinking transistor MN1 to the switching node voltage SH, causing MN1 to turn off. At this time, the first selectable drive branch presents a high-impedance state and does not output current to the drive output node HO. The internal structure and working principle of the second selectable drive branch are the same as the first selectable drive branch. The second selectable drive branch is controlled by the second bit signal SEL in the digital selection signal SEL. <1> control.

[0068] The configurable push-pull output circuit achieves equivalent output impedance adjustment through the above parallel structure. The total output current capability of the gate drive circuit depends on the sum of the channel widths of all operating current-source transistors and current-sink transistors. The total current-source capability is defined as follows: As shown in the formula below:

[0069] Define the total sinking current capacity As shown in the formula below:

[0070] In the two formulas above, Indicates hole mobility; Indicates electron mobility; Indicates the gate oxide capacitance; Indicates the transistor channel length; These represent the source-gate voltage and the gate-source voltage, respectively. These represent the absolute values ​​of the threshold voltages for P-type and N-type transistors, respectively.

[0071] This represents the total equivalent channel width of the P-type transistor involved in the operation. This represents the total equivalent channel width of the N-type transistors involved in the operation. The calculation logic is as follows:

[0072]

[0073] in, These are the physical channel widths of the basic current-source transistor, the first current-source transistor, and the second current-source transistor, respectively. These are the physical channel widths of the base current sinking transistor, the first current sinking transistor, and the second current sinking transistor, respectively. This is a state coefficient; it takes a value of 1 when the corresponding digital selection signal SEL is valid and a value of 0 when it is invalid. By changing... The value can be adjusted in steps by a configurable push-pull output circuit. The size, and thus change For example, when driving large capacitive loads, such as high-power IGBT modules, the following settings are used: At this point, the total equivalent channel width is at its maximum, providing the maximum peak drive current to ensure a sufficiently fast switching speed. When driving small capacitive loads, such as low-power MOSFETs, the setting... At this time, only the basic drive branch is working, the total equivalent channel width is minimized, the peak value of the drive current is limited, and thus the gate voltage overshoot and electromagnetic interference oscillation are suppressed.

[0074] Based on the aforementioned hardware architecture of the configurable push-pull output circuit, the gate drive circuit can execute adaptation strategies for different load characteristics. The load adaptation strategy adjusts the equivalent internal resistance of the gate drive circuit output stage by setting the encoding state of the digital selection signal SEL, thereby controlling the magnitude of the drive current and optimizing the rate of voltage and current change during the switching process.

[0075] In specific application scenarios, the gate input impedance of the external high-side power transistor primarily exhibits a capacitive load. When the externally connected high-side power transistor is a high-power insulated-gate bipolar transistor (IGBT) or a large-size power MOSFET, it has a large gate input capacitance and a large total gate charge Qg. In such high-load scenarios, insufficient drive current can lead to a prolonged Miller plateau duration for the high-side power transistor, increasing switching losses.

[0076] For high-load scenarios, the digital selection signal SEL is configured to be in an all-on state, for example, the first signal SEL. <0> Second bit signal SEL <1> All are set to active level. At this time, the basic drive branch, the first optional drive branch, and the second optional drive branch are all in the working state. The total equivalent channel width of the configurable push-pull output circuit reaches its maximum value. According to the aforementioned current formula, the maximized total equivalent channel width provides the maximum peak source and sink current. The large peak current can quickly charge and discharge the large gate input capacitor, shortening the turn-on delay time and turn-off delay time of the high-side power transistor.

[0077] Conversely, when the externally connected high-side power transistor is a low-power MOSFET, it has a small gate input capacitance. In such low-load scenarios, excessive drive current can lead to an excessively rapid gate voltage rise rate. Excessive coupling through parasitic inductance can cause voltage overshoot and oscillations in the circuit, thereby triggering electromagnetic interference (EMI) and even causing the gate-source voltage to exceed the breakdown threshold.

[0078] For low-load scenarios, the digital selection signal SEL is configured in the base state, such as the first signal SEL. <0> Second bit signal SEL <1> Both are set to an invalid level. At this time, the first and second optional drive branches are disabled and exhibit a high-impedance cutoff state, with only the basic drive branch driving the output node HO. The total equivalent channel width of the configurable push-pull output circuit is minimized. This minimized total equivalent channel width limits the charge / discharge rate of the gate capacitance, resulting in a smooth rise or fall of the gate voltage. This controlled drive strength effectively suppresses voltage overshoot and oscillation, optimizing the electromagnetic compatibility (EMC) performance of the gate drive circuit.

[0079] For medium-load scenarios between high and low loads, the digital selection signal SEL is configured to an intermediate state, for example, only the first signal SEL is selected. <0> Set to active level. At this point, the configurable push-pull output circuit provides a moderate drive current. This stepped configuration offers finer drive capability selection than traditional fixed drive circuits, achieving a balance between drive speed and electromagnetic interference suppression performance.

[0080] The beneficial effects of this invention are demonstrated in the above-described dynamic configuration process. Compared with traditional fixed drive capability circuits, the gate drive circuit proposed in this embodiment effectively constructs a voltage source with variable output internal resistance by digitally adjusting the number of parallel output stage MOS transistors.

[0081] From the perspective of time constant, the equivalent time constant of the gate drive circuit Approximately equal to the output internal resistance of the drive circuit With load capacitance The product of, i.e. In traditional technologies, A fixed time constant results in With load capacitance The linear increase in resistance leads to a slower switching speed. This invention, however, alters the output internal resistance of the drive circuit by adjusting the number of parallel branches. When the load capacitance When the value increases, it can be reduced by adding parallel branches. When the load capacitance When decreasing, increase by reducing parallel branches. This reverse regulation mechanism enables the gate drive circuit to maintain relatively consistent signal response characteristics across a wide range of load variations.

[0082] Furthermore, the architecture based on inverter chains and multiple parallel branches adopted in this embodiment avoids the loop stability problems caused by the introduction of complex analog feedback loops in traditional analog regulation schemes. The digital selection signal SEL directly controls the on / off state of the physical branches, featuring fast response speed, simple control logic, and strong anti-interference capability. This hardware-level reconfigurability allows the same gate driver chip to be widely used in various power electronic systems of different power levels, such as motor drives, power converters, and inverters, reducing system hardware costs and design complexity.

[0083] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A gate drive circuit with adjustable pull-in / sink current capability, characterized in that, The circuit includes a gate drive circuit connected between the high-side supply voltage BST and the switching node voltage SH. The gate drive circuit includes: The first-stage level shifting circuit is connected to the high-side power supply voltage BST and the switching node voltage SH. The first-stage level shifting circuit is configured to generate an upper clamping voltage VPCLAMP and a lower clamping voltage VNCLAMP. The second-stage level shifting circuit has its signal input terminal connected to the external control signal input terminal IN. The second-stage level shifting circuit is configured to convert a low-voltage pulse width modulation signal based on ground potential into a high-voltage drive signal based on the voltage SH of the switching node. A signal shaping and enhancement circuit, wherein the input terminal of the signal shaping and enhancement circuit is connected to the signal output terminal of the second-stage level shifting circuit, and the signal shaping and enhancement circuit is configured to perform waveform shaping and progressive amplification of the driving capability of the high-voltage driving signal, and output a first driving control signal and a second driving control signal. A configurable push-pull output circuit is connected between the output terminal of the signal shaping and enhancement circuit and the gate of the high-side power transistor. The configurable push-pull output circuit includes multiple push-pull drive branches connected in parallel, and the multiple push-pull drive branches connected in parallel include at least one basic drive branch and one optional drive branch. The basic drive branch is configured to operate in a normally-on mode, the optional drive branch is configured to operate in a controlled mode controlled by the digital selection signal SEL, and the configurable push-pull output circuit adjusts the output current capability of the gate drive circuit by adjusting the enabled or disabled state of the optional drive branch.

2. The gate drive circuit with adjustable pull-in current capability according to claim 1, characterized in that, The first-stage level shifting circuit includes an upper clamping voltage generation circuit and a lower clamping voltage generation circuit: The upper clamping voltage generation circuit includes a first clamping diode D3 and a first biasing element. The first clamping diode D3 is connected between the output node of the high-side supply voltage BST and the upper clamping voltage VPCLAMP. The first biasing element is configured to provide a reverse breakdown current to maintain the upper clamping voltage VPCLAMP below the high-side supply voltage BST by a first preset voltage value. The lower clamping voltage generation circuit includes a second clamping diode D2 and a second biasing element. The second clamping diode D2 is connected between the output node of the switching node voltage SH and the lower clamping voltage VNCLAMP. The second biasing element is configured to provide a reverse breakdown current to maintain the lower clamping voltage VNCLAMP above the switching node voltage SH by a second preset voltage value.

3. The gate drive circuit with adjustable pull-in current capability according to claim 1, characterized in that, The second-stage level shifting circuit includes a logic control circuit, a high-voltage transmission unit, and a high-side latch output unit; The logic control circuit is configured to receive the signal from the external control signal input terminal IN and drive the high-voltage transmission unit. The high-voltage transmission unit includes a high-voltage resistant N-type laterally diffused metal-oxide-semiconductor device, and the high-voltage transmission unit is configured to convert the logic state on the low-voltage side into a pull-down current flowing through the high-side latch output unit. The high-side latch output unit is connected between the high-side supply voltage BST and the upper clamping voltage VPCLAMP. The high-side latch output unit is configured to generate the high-voltage drive signal that oscillates between the high-side supply voltage BST and the upper clamping voltage VPCLAMP in response to the pull-down current at the signal output terminal of the second-stage level shift circuit.

4. The gate drive circuit with adjustable pull-in current capability according to claim 1, characterized in that, The signal shaping and enhancement circuit includes a high-side signal shaping branch and a low-side signal shaping branch; Both the high-side signal shaping branch and the low-side signal shaping branch include multi-stage cascaded inverter chains, and the inverter units in the multi-stage cascaded inverter chains are composed of P-type metal-oxide-semiconductor field-effect transistors and N-type metal-oxide-semiconductor field-effect transistors connected in series. Along the signal transmission direction, the channel width of the transistor in the later stage inverter unit of the multi-stage cascaded inverter chain is greater than the channel width of the transistor in the previous stage inverter unit, and the signal shaping and enhancement circuit exhibits high input impedance characteristics and low output impedance characteristics.

5. A gate drive circuit with adjustable pull-in current capability according to claim 4, characterized in that, The signal shaping and enhancement circuit also includes a transmission delay matching unit; The transmission delay matching unit is configured to adjust the signal transmission delay time in the high-side signal shaping branch and the low-side signal shaping branch, so that the transmission delay of the high-side signal shaping branch is consistent with the transmission delay of the low-side signal shaping branch, so as to maintain the preset dead time in the low-voltage pulse width modulation signal.

6. The gate drive circuit with adjustable pull-in current capability according to claim 1, characterized in that, The basic drive branch includes a basic current-pull transistor MP0 and a basic current-sink transistor MN0. The source of the basic current-source transistor MP0 is connected to the high-side power supply voltage BST, and the gate of the basic current-source transistor MP0 receives the first drive control signal. The source of the basic current sinking transistor MN0 is connected to the switching node voltage SH, and the gate of the basic current sinking transistor MN0 receives the second drive control signal. The drain of the basic current-pull transistor MP0 and the drain of the basic current-sink transistor MN0 are connected to the same drive output node HO.

7. A gate drive circuit with adjustable pull-in / sink current capability according to claim 6, characterized in that, The optional drive branch includes a first gating logic unit, a first current-pull transistor MP1, and a first current-sinking transistor MN1; The signal input terminal of the first gating logic unit is connected to the output of the signal shaping and enhancement circuit, and the enable control terminal of the first gating logic unit is connected to the digital selection signal SEL. The source of the first current-source transistor MP1 is connected to the high-side power supply voltage BST, and the gate of the first current-source transistor MP1 is connected to the first output terminal of the first gating logic unit. The source of the first current sinking transistor MN1 is connected to the switching node voltage SH, and the gate of the first current sinking transistor MN1 is connected to the second output terminal of the first gating logic unit. The drain of the first current-pull transistor MP1 and the drain of the first current-sink transistor MN1 are connected to the drive output node HO.

8. A gate drive circuit with adjustable pull-in / sink current capability according to claim 7, characterized in that, The optional drive branch also includes a control signal level shifter; The control signal level shifter is configured to convert the ground potential-based digital selection signal SEL into an internal selection signal that floats based on the switching node voltage SH, and transmit the internal selection signal to the enable control terminal of the first gating logic unit.

9. A gate drive circuit with adjustable pull-in / sink current capability according to claim 7, characterized in that, The first gating logic unit is configured to execute the following control logic: When the digital selection signal SEL is active, the first gating logic unit transmits the first drive control signal to the gate of the first current-pull transistor MP1 and transmits the second drive control signal to the gate of the first current-sink transistor MN1. When the digital selection signal SEL is invalid, the first gating logic unit clamps the gate potential of the first current-source transistor MP1 to the high-side supply voltage BST to turn off the first current-source transistor MP1, and clamps the gate potential of the first current-source transistor MN1 to the switching node voltage SH to turn off the first current-source transistor MN1, so that the optional drive branch presents a high-impedance cutoff state.

10. A gate drive circuit with adjustable pull-in / sink current capability according to claim 1, characterized in that, The total equivalent channel width of the configurable push-pull output circuit is equal to the sum of the channel widths of all transistors in the basic drive branch and the optional drive branch in the enabled state. When the digital selection signal SEL controls more of the optional drive branches to be in the enabled state, the total equivalent channel width increases, thereby increasing the peak output current of the configurable push-pull output circuit to adapt to large capacitor loads; When the digital selection signal SEL controls fewer of the optional drive branches to be in the enabled state, the total equivalent channel width is reduced, thereby limiting the peak output current of the configurable push-pull output circuit to accommodate small capacitive loads.

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