A silicon-germanium based NPN / PNP longitudinal phototriode array structure and method of fabrication thereof

Abstract

This invention belongs to the field of semiconductor optoelectronic devices, and relates to a silicon-germanium-based NPN / PNP vertical phototransistor array structure and its manufacturing method. The structure includes a substrate layer and phototransistor units. The substrate layer is an N+ type silicon substrate, serving as the supporting substrate for the common collector region and the common conductive path. The phototransistor units include multiple NPN and PNP type phototransistor units. Both the NPN and PNP type phototransistor units include an emitter region and a silicon-based phototransistor array. 1‑x Ge x Base region and collector region, Si 1‑x Ge x The thickness of the base region is 50~300nm, 0

Description

Technical Field

[0001] This application relates to the field of semiconductor optoelectronic device technology, specifically to a silicon-germanium based NPN / PNP vertical phototransistor array structure and its manufacturing method. Background Technology

[0002] Optoelectronic tweezers (OET) are a technique that utilizes the photoelectric effect to generate a non-uniform electric field in a liquid medium, thereby enabling the capture, movement, and sorting of dielectric particles, cells, and other targets. Compared to traditional mechanical optical tweezers, OET offers advantages such as lower cost, high throughput and parallel manipulation of large numbers of targets, and seamless integration with microfluidic chips, making it a promising candidate for applications in life sciences fields such as single-cell analysis, liquid biopsy, and drug screening.

[0003] In an OET system, the photoelectric conversion layer is the core component that determines the device performance. When light of a specific wavelength (usually near-infrared light, λ=700~900nm) irradiates the photoelectric conversion layer, photogenerated carriers undergo directional separation under the influence of the built-in electric field of the pn junction or heterojunction. This results in a non-uniform electric field distribution near the interface between the liquid medium and the photoelectric layer, driving the dielectric particles to generate dielectric electrophoresis (DEP) force. The spatial distribution characteristics of this non-uniform electric field directly determine the localization degree and control precision of the DEP force field.

[0004] Currently, the mainstream OET (Optical Transistor) photoelectric conversion layer in the industry uses a pure silicon (Si) material system, mainly based on silicon-based photodiodes or phototransistor structures. The advantages of the pure silicon approach are: mature silicon material processes, low cost, and compatibility with existing CMOS integrated circuit manufacturing processes. However, the pure silicon approach has inherent technical bottlenecks when dealing with the "highly conductive liquid phase physiological environment": The band gap of pure silicon is 1.12 eV. Its absorption coefficient decreases significantly for near-infrared photons with wavelengths exceeding 800 nm. Near the 850 nm wavelength commonly used in OET, the absorption coefficient of pure silicon is approximately 200 cm⁻¹. -1 This means that the single absorption rate of a 1μm thick silicon layer for 850nm photons is less than 20%, which limits the amount of photogenerated carriers and results in insufficient equivalent photocurrent gain.

[0005] In traditional silicon phototransistor design, the conventional approach to improving current gain β is to increase the base thickness (1–3 μm) and reduce the base doping concentration. However, a thicker base means a longer carrier transit time and a larger junction capacitance, which typically limits the device's -3dB bandwidth to below 1 MHz, failing to meet the requirements of high-throughput OET chips for rapid optical pattern updates (frame rate ≥ 30 fps). Conversely, if the pure silicon base is thinned to improve response speed, the light absorption efficiency further deteriorates, and the β value drops sharply to less than 50 times, failing to overcome the bypass effect of the high-conductivity liquid phase medium.

[0006] When the OET chip operates in a high-conductivity liquid environment such as physiological saline (dielectric conductivity σ≥1mS / cm, comparable to the equivalent photoconductivity of the photoelectric layer), the non-uniform electric field generated by illumination is partially "short-circuited" by the liquid medium, and the equivalent control force field decays to the point where it cannot effectively drive the target cells. This "bypass effect" makes the effective control force field strength of the pure silicon solution significantly lower than the actual control requirements under clinical physiological conductivity conditions, greatly limiting the leap of OET technology from the laboratory to clinical applications.

[0007] Most existing OET solutions are based on single-polarity (N-type or P-type) photoelectric conversion units, which can only generate single-polarity DEP force fields (positive DEP or negative DEP). The synchronous or sequential generation of positive and negative DEP force fields requires switching or timing control of external electrode structures, which increases system complexity and makes it impossible to achieve pixel-level localized bipolar DEP cooperative control.

[0008] In summary, the field of OET technology faces the unresolved technical problem of "high gain, high bandwidth, and bipolar synergistic control in a high-conductivity liquid environment," and a novel photoelectric conversion structure is urgently needed to overcome this bottleneck. Summary of the Invention

[0009] On one hand, this application provides a silicon-germanium-based NPN / PNP vertical phototransistor array structure, including a substrate layer and phototransistor units disposed above the substrate layer. The substrate is an N+ type silicon substrate, which serves as the supporting substrate for the common current collection area and the common conductive path. The phototransistor unit includes multiple NPN phototransistor units and PNP phototransistor units arranged in a horizontal array; Both the NPN phototransistor unit and the PNP phototransistor unit include an emitter region and a Si region. 1-x Ge x The base region and collector region, the Si 1-x Ge x The thickness of the base region is 50~300nm, 0 <x≤0.3; A deep trench isolation structure extending longitudinally into the interior of the substrate is provided between adjacent phototransistor units; The light-receiving surface of the phototransistor unit faces the liquid-phase control cavity, and there is no light-shielding metal layer covering the light-receiving surface.

[0010] In a preferred embodiment, the Si 1-x Ge x In the base region, x gradually changes from x1 on the collector side to x2 on the emitter side along the thickness direction, where x1>x2>0, forming a built-in quasi-electric field to assist the directional drift of charge carriers.

[0011] In a preferred embodiment, the Si 1-x Ge x The base region is a multilayer superlattice structure, consisting of several periodic layers, each of which comprises stacked silicon and Si layers. 1-x Ge x The number of periodic layers is 3 to 10, and the thickness of a single periodic layer is 10 to 50 nm.

[0012] In a preferred embodiment, the emitter region of the PNP phototransistor unit is a P+ emitter region, and the collector region is a selective P+ buried layer disposed within the N+ type silicon substrate; the emitter region, Si 1-x Ge x The base area and collector area are arranged from top to bottom.

[0013] Furthermore, the Si 1-x Ge x The base region doping concentration is 1×10 16 ~1×10 18 cm -3 The emission region and the Si 1-x Ge x The base regions are offset by narrowing the band gap to improve the emitter injection efficiency and increase the current gain.

[0014] In a preferred embodiment, the deep trench isolation structure is filled with an insulating medium, which is at least one of SiO2, Si3N4, and polyimide; the depth of the deep trench isolation structure is greater than the depth of the deepest doped region of the phototransistor unit, and the minimum pixel size of the phototransistor unit is 3×3μm.

[0015] In a preferred embodiment, the plurality of phototransistor units are arranged in any one of the following: a cross array, a striped array, or an asymmetric ratio, to simultaneously form a positive and a negative permittivity force field within the liquid phase manipulation cavity. Furthermore, in the asymmetric arrangement, the ratio of NPN phototransistor units to PNP phototransistor units is 1:8 to 8:1.

[0016] On the other hand, this application provides a method for manufacturing the structure described above, comprising the following steps: S1. Fabrication of buried layer: In the region corresponding to the PNP type unit in the N+ type silicon substrate, a P+ buried layer is formed by ion implantation; S2. Fabrication of the epitaxial layer: A silicon epitaxial layer and a Si layer are sequentially grown on the substrate surface by chemical vapor deposition. 1-x Ge x The base region epitaxial layer is constructed, and the thickness of the base region is controlled to be 50~300nm; S3. Prepare a deep trench isolation structure by etching a deep trench that penetrates the epitaxial layer and extends into the substrate layer, and fill the deep trench with an insulating medium. S4. Prepare the base region and emitter region by ion implantation in separate steps to form the base region and emitter region corresponding to NPN and PNP, respectively.

[0017] Further, in step S2, an N-type silicon epitaxial layer is epitaxially grown on the substrate surface using low-pressure chemical vapor deposition, and Si is grown in situ. 1-x Ge x After the base region epitaxial layer, the flow ratio of germane to silane in the growth gas source is adjusted in real time to make the Si 1-x Ge x The germanium composition in the epitaxial layer of the base region exhibits a gradient distribution.

[0018] Furthermore, it also includes S5, which involves thinning the back side of the substrate layer and sputtering a Ti / Au composite metal layer as a common current collector lead-out terminal; after the passivation protective layer is deposited on the front side of the epitaxial layer, it is assembled with the upper electrode plate with a transparent conductive layer to form the liquid phase manipulation cavity.

[0019] Compared with the prior art, the technical solution disclosed in this invention has the following beneficial effects: 1. Si 1-x Ge x Bandgap engineering significantly improves gain and near-infrared response: the Si 1-x Ge x By adjusting the germanium composition (0 < X ​​≤ 0.30), the base region bandgap is narrowed from 1.12 eV in pure Si to 0.88–1.10 eV, thereby increasing the near-infrared (900–1100 nm) absorption coefficient by 3–5 times. At the same time, the heterojunction forms a discontinuous valence band, which greatly improves the emission efficiency, resulting in a performance improvement of more than 1.5 times compared to existing pure silicon-based phototransistor solutions.

[0020] 2. Ultra-thin Si 1-x Gex The base region enables high-speed response: the Si 1-x Ge x The thickness of the base region is only 50-300nm, which is more than an order of magnitude smaller than that of the traditional pure silicon base region (1-3μm). The ultra-thin base region significantly shortens the minority carrier transit time, enabling the device to have an internal bandwidth of more than 10MHz and a response time of less than 0.5μs, which can meet the requirements of high-throughput single-cell rapid sorting.

[0021] 3. Monolithic bipolar integration, flexible functionality: By integrating NPN and PNP type SiS on the same chip... 1-x Ge x The phototransistor unit can generate positive dielectric electrophoresis (pDEP) and negative dielectric electrophoresis (nDEP) force fields respectively. By using various array arrangements such as cross arrays, stripe arrays, or asymmetric proportions, pDEP / nDEP functional partitions can be formed on the same chip, realizing the synchronous capture and sorting of different types of micro and nano particles. Compared with existing phototransistor array solutions that only contain a single polarity, the functional flexibility is significantly enhanced.

[0022] 4. High light response sensitivity with no light-shielding metal layer: The light-receiving surface of each phototransistor unit faces the liquid-phase control cavity and is not covered by a light-shielding metal layer. It adopts a virtual electrode working mode, and the incident light can directly irradiate Si. （1-x） Ge x The base region maximizes the efficiency of photogenerated carrier generation, enabling dielectrophoretic manipulation at lower optical power and reducing the risk of photodamage to biological samples such as cells.

[0023] 5. Pixel-level electrical isolation, minimum pixel size 3×3μm: The deep trench isolation structure extends longitudinally into the substrate layer, with a depth greater than the deepest doped region, achieving full dielectric physical isolation between adjacent pixels and completely eliminating electrical crosstalk between pixels (crosstalk < 0.5%); combined with the virtual electrode design, the minimum pixel size can reach 3×3μm, which can meet the fine manipulation requirements of nanoparticles and subcellular structures. Attached Figure Description

[0024] Exemplary embodiments of the present invention can be more fully understood by referring to the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain the present invention and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0025] Figure 1 A cross-sectional schematic diagram of the overall structure of a silicon-germanium-based NPN / PNP vertical phototransistor array structure provided by the present invention; Figure 2A cross-sectional schematic diagram of a partial structure of a silicon-germanium-based NPN / PNP vertical phototransistor array provided by the present invention shows the composition of each layer of the PNP and NPN type units; Figure 3 This is a top view of the transistor cross array structure in Embodiment 1 of the present invention; Figure 4 This is a schematic cross-sectional view of the upper electrode plate structure in Embodiment 1 of the present invention; Figure 5 This is a top view of the stripe array arrangement in Embodiment 2 of the present invention; Figure 6 This is a top view schematic diagram of an asymmetrical proportional arrangement in Embodiment 3 of the present invention; Figure 7 This is a top view schematic diagram of another asymmetrical proportional arrangement in Embodiment 3 of the present invention; Figure 8 This is a schematic diagram of the process flow for manufacturing a silicon-germanium-based NPN / PNP vertical phototransistor array structure according to Embodiment 4 of the present invention.

[0026] Figure Labels 1—Substrate; 11—P + Buried layer; 2-N - 31-PNP type epitaxial layer; 311-PNP type phototransistor unit; 312-PNP type Si 1-x Ge x Base region; 313—PNP collector region; 32—NPN type phototransistor unit; 321—NPN emitter region; 322—NPN type Si 1-x Ge x Base region; 323—NPN collector region; 4—liquid phase control cavity; 5—upper electrode structure; 51—transparent substrate; 52—transparent conductive layer; 6—back metal layer; 7—deep trench isolation structure. Detailed Implementation

[0027] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present application.

[0028] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this application are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them. It should also be understood that in the embodiments of this application, "multiple" can refer to two or more, and "at least one" can refer to one, two, or more. Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone.

[0029] In the description of this invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0031] In the description of this invention, it should be noted that, unless otherwise expressly specified and limited, the term "Si" is used interchangeably with "Si". 1-x Ge x "Base region": refers to the region based on Si 1-x Ge x The base region of the phototransistor is made of an alloy (0 < x ≤ 0.30), which has a narrower band gap than the pure silicon emission region, forming a heterojunction. Photons are efficiently absorbed in this region, generating photogenerated carriers. By using a gradient or uniform germanium composition, band gap engineering can be achieved to optimize the spectral response and carrier transit characteristics of the device.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "virtual electrode" refers to a region on the chip surface where, when a phototransistor unit is illuminated, the equivalent resistance of the device is significantly reduced due to the generation of photogenerated carriers, resulting in enhanced conductivity. This region functions as if a physical metal electrode were placed at that location, but in reality, there is no metal structure there; hence the term "virtual electrode." The position and shape of the virtual electrode can be programmed in real time using an illumination pattern, giving the chip a highly flexible controllability.

[0033] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "all-dielectric electrical decoupling" refers to the electrical independence between adjacent phototransistor units through a deep trench isolation structure, so that the working state (light / dark state) of one unit does not affect the electrical characteristics of adjacent units, thereby ensuring that each pixel can be independently programmed and controlled.

[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "positive dielectric electrophoresis (pDEP)" refers to the dielectric effect in which particles are attracted to and move towards regions of high electric field strength, which typically occurs when the polarizability of the particles is greater than that of the surrounding medium.

[0035] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "negative dielectrophoresis (nDEP)" refers to the dielectrophoretic effect in which particles are repelled and moved toward regions of low electric field strength, which typically occurs when the polarizability of the particles is less than that of the surrounding medium.

[0036] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "asymmetric ratio arrangement" refers to an arrangement in an array chip in which two or more units with different physical properties (such as generating dielectric forces in different directions) are arranged in a non-uniform manner in terms of spatial distribution weight and functional area division.

[0037] Furthermore, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use. Techniques, methods, and devices known to those skilled in the art will not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0038] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] Example 1: Cross-array arrangement of silicon-germanium based NPN / PNP vertical phototransistor array structure like Figure 1 , Figure 2 As shown, this embodiment provides a silicon-germanium-based NPN / PNP vertical phototransistor array structure for optoelectronic tweezers chips, which includes, from bottom to top: a substrate layer 1 (N+ type silicon substrate, containing a P+ buried layer 11), an N- type epitaxial layer 2, a phototransistor unit (composed of multiple PNP type phototransistor units 31 and NPN type phototransistor units 32), a liquid phase manipulation cavity 4, and an upper electrode structure 5; a back metal layer 6 is provided on the back side of the substrate layer 1.

[0041] Substrate 1 is an N+ type silicon substrate with a thickness of 500–700 μm and a resistivity of no more than 0.005 Ω·cm. Substrate 1 serves a dual purpose: firstly, it acts as a mechanical support substrate for the entire chip, providing sufficient structural rigidity; secondly, it serves as a common conductive path, with a Ti / Au composite metal layer 6 (Ti layer thickness approximately 20 nm, Au layer thickness approximately 200 nm) disposed on its back side, serving as a common collector region lead-out for applying a DC bias voltage to the chip. The N+ type heavily doped substrate has extremely low resistivity and can be considered a good conductor, ensuring that the collector regions of each phototransistor unit form a low-impedance common node, thereby establishing a basis for a uniform electric field distribution between the chip and the liquid phase manipulation cavity.

[0042] A selective P+ buried layer 11 with a thickness of about 1 to 2 μm and a doping concentration of about 1 × 10⁻⁶ is formed in the corresponding PNP region of the substrate layer 1. 19 cm -3 It serves as the collector region of the PNP type phototransistor unit 31.

[0043] The phototransistor unit is formed on the N-type epitaxial layer 2 and Si above the substrate layer 1. 1-x Ge x The base region epitaxial layer includes multiple PNP type phototransistor units 31 and NPN type phototransistor units 32 arranged in a horizontal array.

[0044] The PNP type phototransistor unit 31 includes, from top to bottom: PNP emitter region 311: P+ doped region, with a doping concentration of 1×10⁻⁶. 19 ~5×10 19 cm -3 The implantation depth is approximately 0.3 μm, formed by BF2+ ion implantation; PNP type Si 1-x Ge x Base region 312: Si 1-x Ge x An alloy (germanium content x=0.15), approximately 120 nm thick, with a doping concentration of 1×10⁻⁶. 16 ~1×10 17 cm -3 It is an N-type doped base region with a band gap of approximately 1.02 eV, which is about 0.10 eV narrower than that of pure silicon, significantly improving the absorption efficiency of near-infrared photons. PNP collector region 313: i.e., P+ buried layer 11, with a doping concentration of approximately 1×10⁻⁶. 19 cm -3 .

[0045] The NPN type phototransistor unit 32 includes, from top to bottom: NPN emitter region 321: N+ doped region, with a doping concentration of 1×10⁻⁶. 19 ~5×10 19 cm -3 The implantation depth is approximately 0.3 μm, formed by the implantation of phosphorus ions (P). NPN type Si 1-x Ge x Base region 322: Si 1-x Ge x An alloy (germanium content x=0.15), approximately 120 nm thick, with a doping concentration of 1×10⁻⁶. 16 ~1×10 17 cm -3 It is a P-type doped material, formed by B+ ion implantation; NPN collector region 323: directly utilizes N+ type silicon substrate layer 1, without the need for separate formation.

[0046] Each phototransistor unit's light-receiving surface (i.e., the upper surface of the emitting region) faces the liquid-phase manipulation cavity 4, and is not covered by a light-shielding metal layer. When light of a specific wavelength shines on the Si of the phototransistor... 1-x Ge x In the base region, due to Si 1-x Ge xThe base region has a narrower bandgap than pure silicon, resulting in a higher photon absorption coefficient and generating more photogenerated electron-hole pairs. These pairs separate under the influence of the built-in electric field, forming a photogenerated current that reduces the internal resistance of the device. This is equivalent to forming a localized "virtual electrode" on the chip surface, thereby generating a non-uniform alternating electric field within the liquid phase manipulation cavity 4. This drives the dielectrophoresis (DEP) force to manipulate the micro-nano particles within the cavity.

[0047] Due to Si 1-x Ge x The heterogeneous emitter junction forms a valence band discontinuity (for PNP type) or a conduction band discontinuity (for NPN type), which effectively blocks the reverse injection of majority carriers, enabling the current gain β to reach 200-300, which is 1.5-4 times higher than that of the pure silicon-based region (β=50-200).

[0048] like Figure 3 As shown, in this embodiment, the PNP type phototransistor unit 31 and the NPN type phototransistor unit 32 are arranged in a checkerboard pattern (cross array arrangement), and the polarity of any pixel is opposite to that of all its adjacent pixels. This arrangement can simultaneously form regularly alternating pDEP regions and nDEP regions on the chip surface, which is suitable for the synchronous capture and separation of mixed particle groups.

[0049] Each phototransistor unit has a lateral dimension (pixel size) of 10μm × 10μm and a pixel pitch of 1μm. The corresponding deep trench isolation structure 7 has a width of 1μm and an aspect ratio of 15:1 (depth approximately 15μm). The deep trench is filled with SiO2 insulating dielectric to achieve full dielectric physical isolation between adjacent units. The trench depth (15μm) is greater than the depth of the deepest doped region (approximately 5μm for the P+ buried layer), ensuring thorough electrical decoupling and crosstalk between adjacent pixels <0.5%.

[0050] refer to Figure 1 and Figure 4 The liquid-phase manipulation cavity 4 is formed by the upper surface of the phototransistor unit (covered by a surface passivation protective layer) and the inner surface of the upper electrode structure 5, with a height (cavity spacing) of 50 μm. It is supported and sealed by a SU-8 photoresist insulating gasket with a height of 50 μm. The cavity is filled with a suspension containing the micro-nano particles to be manipulated (such as cell suspension, nanoparticle solution, etc.).

[0051] The upper electrode structure 5 includes, from top to bottom: a transparent substrate 51, a borosilicate glass with a thickness of 0.5 mm and a light transmittance of more than 90%; and a transparent conductive layer 52, an ITO thin film sputtered on the inner surface of the transparent substrate 51 with a thickness of about 100 nm and a sheet resistance of no more than 20 Ω.

[0052] By applying an AC bias voltage of 10kHz to 1MHz (peak value 5 to 20V) between the transparent conductive layer 52 (upper electrode structure) and the back metal layer 6 (common current collector area), a uniform background alternating electric field is established in the liquid phase control cavity 4, which serves as the driving power source for dielectric electrophoresis control.

[0053] The core of the performance improvement of the phototransistor array structure described in this invention lies in the heterojunction bandgap engineering. In the Si of the NPN / PNP type phototransistor unit... 1-x Ge x In the base region, the introduction of the Ge component generates a valence band shift ΔE at the emitter junction interface. v Because it is significantly greater than the conduction band offset ΔE c This provides an extremely high barrier for reverse hole injection from the base region to the emitter region in PNP cells. According to the heterojunction current gain formula: β∝(Ne / Nb)×exp(ΔEg / kT), where ΔE... g For Si and Si 1-x Ge x The bandgap difference. This mechanism allows the invention to be applied even with a base region doping concentration of N. B Even at higher voltage levels (to reduce base resistance and ensure response speed), extremely high current gain β can still be achieved through exponential term compensation. This characteristic successfully breaks through the technical bottleneck of the mutual constraint between "gain and bandwidth" in traditional pure silicon transistors.

[0054] Working principle: When the chip is working, an AC bias voltage is first applied between the upper electrode structure 5 (ITO layer 52) and the back metal layer 6. In the absence of light, each phototransistor unit is in the off state, with high internal resistance and a uniform electric field distribution in the liquid phase cavity, without significant DEP force field generation. When a spatial light modulator (SLM) or digital micromirror device (DMD) projects a specific pattern of light (wavelength 600-1100nm) onto the chip surface, the phototransistor units Si emitting light are illuminated. 1-x Ge x Photogenerated carriers are generated in the base region, causing the equivalent device resistance to decrease rapidly (under illumination, the internal resistance can be reduced to less than 1 / 100 of that in the dark state). This forms a "bright virtual electrode" at the corresponding pixel location, significantly increasing the local electric field strength and gradient. This generates positive or negative dielectric electrophoresis (pDEP) forces (depending on the transistor polarity) on micro- and nano-particles within the liquid cavity, enabling particle capture, movement, or sorting manipulation. By dynamically changing the projected light pattern, real-time programmable manipulation of single or multiple particles can be achieved without the need for mechanical moving parts.

[0055] Example 2: Striped Array Arrangement Silicon-Germanium-Based NPN / PNP Vertical Phototransistor Array Structure The main difference between this embodiment and Embodiment 1 lies in the arrangement of the phototransistor units and the Si...1-x Ge x Base region parameters. For example... Figure 5 As shown, this embodiment uses a stripe array arrangement: Phototransistor units of the same polarity are connected along the X-direction (first direction) of the chip, forming a striped region; NPN and PNP striped regions are arranged alternately along the Y-direction (second direction) of the chip, with a stripe width of 20μm (containing 2 columns of pixel units) and a spacing (isolation groove) of 1.5μm; Si 1-x Ge x The germanium composition of the base region is x=0.20 (uniform composition), with a thickness of approximately 150 nm and a doping concentration of approximately 5 × 10⁻⁶. 16 cm -3 The deep trench isolation structure 7 has a width of 1.5μm and an aspect ratio of 12:1 (depth of approximately 18μm), and is filled with Si3N4 insulating medium; the liquid phase manipulation cavity has a height of 100μm; and the pixel lateral dimension is 20μm×20μm.

[0056] In this embodiment, Si 1-x Ge x The germanium content in the base region is increased to 20%, the band gap is further narrowed to approximately 0.97 eV, the near-infrared absorption coefficient is increased by approximately 30% compared to Example 1, and the current gain β reaches 250–350. The advantage of the stripe array arrangement is that it forms a wider pDEP / nDEP functional band along the X direction, which is suitable for applications that require guiding particle flow along a fixed direction (such as particle sorting channels). It can be combined with the flow channel structure in microfluidic chips to achieve continuous sorting of particles in flow.

[0057] Other technical features (substrate layer, phototransistor unit structural parameters, upper electrode structure, etc.) are the same as in Example 1, and will not be repeated here.

[0058] Example 3: Asymmetric Proportional Arrangement Silicon-Germanium Based NPN / PNP Vertical Phototransistor Array Structure The main difference between this embodiment and Embodiment 1 lies in the arrangement ratio of the phototransistor units and the Si... 1-x Ge x Base region parameters. For example... Figure 6 As shown, this embodiment employs an asymmetric ratio arrangement and a gradient germanium composition base region: Si 1-x Ge x The germanium composition x in the base region is gradually distributed along the thickness direction: x1=0.25 on the side near the collector region and x2=0.05 on the side near the emitter region, with a thickness of about 100nm. The gradually distributed composition forms a built-in quasi-electric field (about 40kV / cm), which accelerates the drift of minority carriers in the base region to the collector junction, further shortening the transit time to <0.3μs and the bandwidth to 15MHz. In this embodiment, the ratio of NPN phototransistor units 32 to PNP phototransistor units 31 in the chip array region is 8:1. The NPN phototransistor units 32 (generating pDEP force fields) are concentrated in the central region of the chip, forming the main capture area, which is suitable for the efficient capture of target particles (such as cells of a specific particle size). The PNP phototransistor units 31 (generating nDEP force fields) are distributed in the peripheral region of the chip, forming a repulsion boundary to prevent non-target particles from entering the capture area. The pixel lateral size is 3μm×3μm, the width of the deep trench isolation structure is 1μm, the aspect ratio is 20:1 (depth is about 20μm), and it is filled with polyimide (PI) insulating medium. The height of the liquid phase manipulation cavity is 30μm, which is suitable for the fine manipulation of single cell layers.

[0059] In another implementation, such as Figure 7 As shown, PNP phototransistor units 31 are concentrated in the central region of the chip array, forming a central repulsion region; while NPN phototransistor units 32 are distributed in the peripheral region. The ratio of NPN phototransistor units 32 to PNP phototransistor units 31 is 1:8. The central PNP region generates an nDEP force field, which can push away or capture non-target particles; the peripheral NPN region generates a pDEP force field, which attracts target particles and keeps them in the edge region of the chip, realizing the "outward sorting" of target particles.

[0060] In practical applications, the ratio of NPN phototransistor unit 32 to PNP phototransistor unit 31 can be flexibly set from 1:8 to 8:1 according to the target particle capture requirements.

[0061] The advantage of asymmetric ratio arrangement is that it can form functional partitions with different electric field intensities on the same chip, which is suitable for selective capture and enrichment of specific target particles in mixed samples, and improves the selectivity of manipulation.

[0062] Other technical features are the same as in Embodiment 1, and will not be repeated here.

[0063] Example 4: Manufacturing method of silicon-germanium based NPN / PNP vertical phototransistor array structure like Figure 8 As shown, this embodiment provides a method for manufacturing a silicon-germanium-based NPN / PNP vertical phototransistor array structure for optoelectronic tweezers chips. Taking the chip of Embodiment 1 (cross-array arrangement, 10μm×10μm pixels) as an example, the method includes the following steps: S1. Fabrication of the buried layer: An N+ type silicon substrate layer 1 (resistivity ≤ 0.005 Ω·cm, thickness approximately 600 μm, crystal orientation <100>) is provided. Heavy N+ doping ensures the formation of a low-impedance common collector node, providing a uniform electric field distribution for subsequent devices. A 50 nm SiO2 masking layer is grown by thermal oxidation, and PNP-type cell regions are defined by photolithography. B+ ion implantation is performed at an implantation energy of 150 keV and a dose of 5 × 10⁻⁶ ions. 15 cm -2 In a nitrogen-protected atmosphere, a push trap was formed at 1050°C for 30 minutes, resulting in a junction depth of approximately 1.5 μm and a peak concentration of approximately 1 × 10⁻⁶. 19 cm -3 P+ buried layer 11 (PNP collector region 313); remove the masking oxide layer to complete the preparation of P+ buried layer.

[0064] S2. Fabrication of the epitaxial layer: An N-type silicon epitaxial layer 2 (approximately 5 μm thick, with a doping concentration of approximately 1 × 10⁻⁶) is epitaxially grown on the surface of substrate layer 1 using low-pressure chemical vapor deposition (LPCVD). 16 cm -3 (Growth temperature approximately 1050℃); Continue in-situ growth of Si 1- x Ge x The epitaxial layer in the base region (germanium composition x=0.15, thickness approximately 120nm) was switched to a mixed gas source of SiH4 (100sccm) / GeH4 (15sccm) / H2 (20slm), the growth temperature was reduced to 620℃ (within the range of 550~700℃), the chamber pressure was 20Torr (within the range of 10~100Torr), and the growth rate was approximately 5nm / min (within the range of 1~10nm / min).

[0065] S3. Fabrication of deep trench isolation structure, (1) Photolithography to define deep trench pattern: A layer of SiO2 and Si3N4 with a thickness of 300-500nm is deposited on the surface of the epitaxial layer by plasma-enhanced chemical vapor deposition (PECVD) as a hard mask layer; a deep trench array pattern is defined on the surface of the hard mask layer by deep ultraviolet (DUV) photolithography, with a minimum linewidth of 1μm, and then the pattern is transferred to the hard mask layer by dry etching and the photoresist is stripped off; (2) Deep silicon etching: Using the hard mask layer as a baffle, a vertical high selectivity dry etching is performed by Bosch process of inductively coupled plasma reactive ion etching (ICP-RIE); the etching completely penetrates the upper Si layer. 1-x Ge x The base region epitaxial layer and the N-type silicon epitaxial layer extend longitudinally to 2-3 μm inside the N+ type silicon substrate layer. The total etching depth is controlled at about 810 μm. The aspect ratio of the deep trench is controlled between 8:1 and 10:1 to ensure that adjacent pixel units are physically and electrically decoupled by the entire dielectric. (3) Insulating dielectric filling: After etching, a SiO2 sidewall passivation layer with a thickness of 10-20 nm is grown in situ on the inner wall of the deep trench using rapid thermal oxidation (RTO) process to repair lattice damage caused by dry etching and suppress lateral leakage current; then, a SiO2 insulating dielectric is filled into the deep trench without voids using high-density plasma chemical vapor deposition (HDP-CVD) process; finally, the SiO2 insulating dielectric is thinned and stopped by chemical mechanical process. 1-x Ge x The epitaxial layer surface achieves global surface planarization.

[0066] S4. Fabrication of base region and emitter region, (1) PNP type unit: collector region is P+ buried layer 11 (already completed in S2); N-type background epitaxial layer is directly used as PNP type Si 1-x Ge x Base region 312; BF2+ ion implantation was performed (implantation energy 80 keV, dose 5 × 10⁻⁶). 15 cm -2 (2) NPN type unit: B+ ion implantation (implantation energy 80keV, dose 5×10) 12 cm -2 ) in Si 1- x Ge x NPN type Si is formed in the epitaxial layer 1-x Ge x Base region 322; P+ ion implantation (implantation energy 60 keV, dose 5 × 10⁻⁶) 15 cm -2 (3) Forming NPN emitter region 321; collector region directly utilizes N+ type silicon substrate layer 1; (3) Annealing activation: N2 protective atmosphere, annealing at 950℃ for 10min to activate implanted ions, repair lattice damage, annealing temperature controlled below 1000℃ to avoid Si 1-x Ge x Excessive diffusion of Ge atoms in the layer.

[0067] S5. Post - process, (1) Back - side electrode deposition: After the back - side of the substrate layer 1 is thinned to about 200μm and CMP processed, a Ti layer (20nm) and an Au layer (200nm) are deposited by electron - beam evaporation to form the back - side metal layer 6; (2) Surface passivation protection: A 100nm SiO2 passivation protection layer is deposited by PECVD process; (3) Upper - plate structure preparation: A 100nm ITO transparent conductive layer 52 with a sheet resistance of about 15Ω is magnetron - sputtered on the inner surface of the borosilicate glass substrate 51; (4) Cavity assembly bonding: SU - 8 insulating gaskets (height 50μm) are formed by positive - side photolithography on the front - side of the triode array chip, and the upper - plate structure 5 is aligned and bonded with the front - side of the chip to form a sealed liquid - phase manipulation cavity 4 with a height of 50μm; Inlet / outlet ports are introduced to complete the chip assembly.

[0068] Performance parameter comparison with the prior art: Performance indicators a-Si:H pure silicon phototransistor This invention is a PNP type This invention is an NPN type Built-in gain None (<1) 50～200× 200～500× 200～500× responsiveness <1A / W 5~10A / W ≥15A / W ≥15A / W Response time >1μs <1μs <0.5μs <0.5μs Internal bandwidth <1MHz ~5MHz >10MHz >10MHz Near-infrared response (900-1100nm) / cm⁻¹ <50 ~200 ~600 ~600 Minimum pixel size ~50μm ≥10μm ≥3μm ≥3μm Dark current / pixel High (nA~μA) <1nA <0.5nA <0.5nA High conductivity solution compatible No (>1 mS / cm) weak Yes (≤15mS / cm) Yes (≤15mS / cm) Front metal interconnect need need None (virtual electrode) None (virtual electrode) Pixel crosstalk High (no isolation) medium <0.5% (deep trench isolation) <0.5% (deep trench isolation) CMOS process compatible Difference good Good (SiGe BiCMOS) Good (SiGe BiCMOS) In summary, by introducing the Si 1-x Ge x base - region technology into the NPN / PNP phototransistor lateral array, combined with the deep - trench isolation structure, liquid - phase manipulation cavity, transparent upper - plate structure and back - side common collector region, the following core advantages are achieved: High gain and fast speed: The Si 1-x Ge x base - region β≥200, responsivity≥15A / W, bandwidth>10MHz, response time<0.5μs. Fundamentally, the "bypass - short - circuit effect" in the high - conductivity liquid - phase physiological environment is overcome. At the same time, by using the high infrared absorption rate of the ultra - thin Si 1-x Ge x base - region and the high emission efficiency of the heterojunction, the equivalent photoconductance generated under the same illumination is increased by more than one order of magnitude, making the impedance of the light - receiving pixel region much lower than the bypass impedance of the high - conductivity liquid - phase medium. Thus, the driving voltage is mainly concentrated on the inside of the liquid - phase manipulation cavity, realizing strong localization and high - precision dielectrophoresis manipulation in the high - conductivity physiological environment; Wide spectrum: By adjusting the Ge component 0 < x < 0.3 in the Si 1-x Ge x base - region, the bandgap of the base - region can be customized and narrowed to 0.88 - 1.10eV. The narrowing of the bandgap means that the device can absorb photons with lower energy (longer wavelength), directly stretching the spectral response boundary to 1100nm. The absorption coefficient in the near - infrared band is increased by 3 - 5 times compared with pure silicon, perfectly compatible with low - light - toxicity biological light sources.

[0069] High pixel density: Deep - trench isolation + virtual - electrode design, the minimum pixel is 3×3μm, reducing the electrical crosstalk between pixels to <0.5%, ensuring that in a highly dense pixel array, each point can be independently programmed and operated without interference; Flexible Functionality: The NPN / PNP bipolar integration provides a pDEP / nDEP bipolar force field. At the same time, by integrating these two polarities of phototubes on the same monolithic chip, it can overcome the limitations of traditional unipolar photoelectric tweezers that can only "attract" or "repel". Designed as a checkerboard cross array, striped channel array or asymmetric scale array, it can capture target cells (pDEP bright area) and push away impurities (nDEP dark area or specific polarity area) in different regions of the same chip, achieving pixel-level multifunctional dynamic bipolar sorting. Process compatibility: Si 1-x Ge x The base region is manufactured using a BiCMOS process, which is compatible with mature CMOS production lines and has the potential for large-scale production. This lays the most solid technical production line foundation for the commercialization of this high-performance optoelectronic tweezers chip from the laboratory to clinical high-throughput liquid biopsy and drug screening.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application.

Claims

1. A silicon-germanium based NPN / PNP vertical phototransistor array structure, comprising a substrate layer and phototransistor units disposed above the substrate layer, characterized in that: The substrate layer is N. + A silicon substrate is used as the supporting substrate for the common current collection area and the common conductive path. The phototransistor unit includes multiple NPN phototransistor units and PNP phototransistor units arranged in a horizontal array; Both the NPN phototransistor unit and the PNP phototransistor unit include an emitter region and a Si region. 1-x Ge x The base region and collector region, the Si 1-x Ge x The thickness of the base region is 50~300nm, 0 <x≤0.3; A deep trench isolation structure extending longitudinally into the interior of the substrate is provided between adjacent phototransistor units; The light-receiving surface of the phototransistor unit faces the liquid-phase control cavity, and there is no light-shielding metal layer covering the light-receiving surface.

2. The silicon-germanium based NPN / PNP vertical phototransistor array structure according to claim 1, characterized in that: The Si 1-x Ge x In the base region, x gradually changes from x1 on the collector side to x2 on the emitter side along the thickness direction, where x1>x2>0, forming a built-in quasi-electric field to assist the directional drift of charge carriers.

3. The silicon-germanium based NPN / PNP vertical phototransistor array structure according to claim 1, characterized in that: The Si 1-x Ge x The base region is a multilayer superlattice structure, consisting of several periodic layers, each of which comprises stacked silicon and Si layers. 1- x Ge x The number of periodic layers is 3 to 10, and the thickness of a single periodic layer is 10 to 50 nm.

4. The silicon-germanium based NPN / PNP vertical phototransistor array structure according to claim 1, characterized in that: The emitter region of a PNP phototransistor is P + The transmitting region and the collector region are located in the N + Selective P in type silicon substrate layer + Buried layer; emitter region, Si 1-x Ge x The base area and collector area are arranged from top to bottom.

5. The silicon-germanium based NPN / PNP vertical phototransistor array structure according to claim 1, characterized in that: The Si 1-x Ge x The base region doping concentration is 1×10 16 ~1×10 18 cm -3 The emission region and the Si 1-x Ge x The base regions are offset by narrowing the band gap to improve the emitter injection efficiency and increase the current gain.

6. The silicon-germanium based NPN / PNP vertical phototransistor array structure according to claim 1, characterized in that: The deep trench isolation structure is filled with an insulating medium, namely SiO2 and Si3N. 4、 At least one of polyimide; the depth of the deep trench isolation structure is greater than the depth of the deepest doped region of the phototransistor unit, and the minimum pixel size of the phototransistor unit is 3×3μm.

7. The silicon-germanium based NPN / PNP vertical phototransistor array structure according to claim 1, characterized in that: The multiple phototransistor units are arranged in any one of the following: cross array, stripe array, or asymmetric ratio, to simultaneously form a positive and negative permittivity force field within the liquid phase control cavity. In the asymmetric ratio arrangement, the ratio of NPN type phototransistor units to PNP type phototransistor units is 1:8 to 8:

1.

8. A method for manufacturing a silicon-germanium-based NPN / PNP vertical phototransistor array structure as described in any one of claims 1-7, characterized in that, Includes the following steps: S1. Prepare the buried layer, in N + In the region corresponding to the PNP type cell within the silicon substrate, P-type cells are formed using ion implantation. + Buried layer; S2. Fabrication of the epitaxial layer: A silicon epitaxial layer and a Si layer are sequentially grown on the substrate surface by chemical vapor deposition. 1-x Ge x The base region epitaxial layer is constructed, and the thickness of the base region is controlled to be 50~300nm; S3. Prepare a deep trench isolation structure by etching a deep trench that penetrates the epitaxial layer and extends into the substrate layer, and fill the deep trench with an insulating medium. S4. Prepare the base region and emitter region by ion implantation in separate steps to form the base region and emitter region corresponding to NPN and PNP, respectively.

9. The manufacturing method according to claim 8, characterized in that: In step S2, low-pressure chemical vapor deposition is used to epitaxially grow an N-type silicon epitaxial layer on the substrate surface, and Si is grown in situ. 1-x Ge x In the base region epitaxial layer, the flow ratio of germane to silane in the growth gas source is adjusted in real time to make the Si... 1-x Ge x The germanium composition in the epitaxial layer of the base region exhibits a gradient distribution.

10. The manufacturing method according to claim 8, characterized in that: It also includes S5, which involves thinning the back side of the substrate layer and sputtering a Ti / Au composite metal layer as a common current collector lead-out terminal; after the passivation protective layer is deposited on the front side of the epitaxial layer, it is assembled with the upper electrode plate with a transparent conductive layer to form the liquid phase manipulation cavity.

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