Display device

Abstract

A display device according to one embodiment of the present application includes: a substrate; a panel insulating layer disposed on the substrate and including a plurality of insulating layers; touch pads disposed on the panel insulating layer; a protective layer configured to be spaced apart from the touch pads on the panel insulating layer and including an organic material; and an over-etched region disposed between the touch pads and the protective layer, wherein at least a portion of the panel insulating layer is recessed in the over-etched region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0196886, filed on December 26, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This application relates to a display device. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices are being utilized.

[0005] Among display devices, OLED displays, being self-emissive, offer advantages such as wider viewing angles and higher contrast ratios. Furthermore, because they do not require a separate backlight, they are lighter, thinner, and consume less power than LCD devices. In addition, OLED displays can be driven with low voltage, have fast response times, and, most importantly, are inexpensive to manufacture. Summary of the Invention

[0006] This application aims to provide a display device that can minimize the penetration path of moisture, humidity, etc., along its penetration pads.

[0007] This application also aims to provide a display device that can minimize the moisture penetration path of the solder pads and suppress or prevent silver (Ag) residue defects.

[0008] This application also aims to provide a display device that can more smoothly deposit the bonding lines of the pads.

[0009] The purpose of this application is not limited to the above-mentioned purposes, and other technical purposes can be deduced from the following embodiments.

[0010] According to one embodiment of this application, a display device is provided, the display device comprising: a substrate; a panel insulating layer disposed on the substrate and including a plurality of insulating layers; touch pads disposed on the panel insulating layer; a protective layer configured to be spaced apart from the touch pads on the panel insulating layer and comprising an organic material; and an over-etched region disposed between the touch pads and the protective layer, wherein at least a portion of the panel insulating layer is recessed in the over-etched region.

[0011] According to another embodiment of this application, a display device is provided, the display device comprising: a substrate; a panel insulating layer disposed on the substrate and including a plurality of insulating layers; pads disposed on the panel insulating layer; connecting lines electrically connected to the pads; and an over-etched region, at least a portion of the panel insulating layer being recessed in the over-etched region, wherein the over-etched region overlaps with the connecting lines.

[0012] The detailed description and accompanying drawings include details of other embodiments.

[0013] According to the embodiments of this application, the moisture penetration path of water, humidity, etc., along its penetration pads can be minimized.

[0014] According to the embodiments of this application, the moisture penetration path of the pads can be minimized and silver (Ag) residue defects can be suppressed or prevented.

[0015] According to the embodiments of this application, the connection lines of the pads can be deposited more smoothly.

[0016] According to the embodiments of this application, the reliability of the display panel can be improved, thereby increasing the lifespan of the display device and reducing power consumption.

[0017] However, the effects that can be obtained from this application are not limited to those described above, and those skilled in the art to which this application pertains will be able to clearly understand other effects not mentioned based on the following description. Attached Figure Description

[0018] Figure 1 This is a plan view of a display device according to one embodiment.

[0019] Figure 2 It shows the basis Figure 1 A cross-sectional view of the curved state of the display panel.

[0020] Figure 3 It is along Figure 1 The cross-sectional view taken by line A-A' in the diagram.

[0021] Figure 4 yes Figure 3 A detailed cross-sectional view of the light-emitting part.

[0022] Figure 5 It is a detailed cross-sectional view of the light-emitting part based on the modified example.

[0023] Figure 6 It is based on Figure 3 A cross-sectional view of the touch area.

[0024] Figure 7 yes Figure 1A magnified view of region Q1 in the image.

[0025] Figure 8 It is along Figure 7 The cross-sectional view taken by line B-B' in the diagram.

[0026] Figure 9 It is along Figure 7 The cross-sectional view taken by line C-C' in the diagram.

[0027] Figures 10 to 12 This is a view showing the manufacturing method of each process operation of the display device according to this embodiment.

[0028] Figure 13 This is a plan view of a display panel according to another embodiment.

[0029] Figure 14 This is a cross-sectional view of a display device according to another embodiment.

[0030] Figure 15 This is a cross-sectional view of a display device according to yet another embodiment.

[0031] Figure 16 This is a cross-sectional view of a display device according to yet another embodiment.

[0032] Explanation of reference numerals in the attached figures

[0033] 10: Display devices

[0034] 100: Display panel

[0035] 101: Substrate

[0036] 120, 130: Thin-film transistors

[0037] 111: First protective layer

[0038] 112: Second protective layer

[0039] 150: Light-emitting part

[0040] 151: First electrode

[0041] 152: Organic layer

[0042] 153: Second electrode

[0043] PA1: First pad area

[0044] PA2: Second pad area

[0045] TPD: Touch Pad

[0046] TSL: Touch Sensing Cable

[0047] OE: Over-etched area

[0048] GR: Groove. Detailed Implementation

[0049] In the following description, embodiments will be illustrated with reference to the accompanying drawings. In this application, when a first component (or region, layer, portion, etc.) is described as being "on," "connected," or "bonded" to a second component, it means that the first component may be directly connected / bonded to the second component, or a third component may be disposed between them.

[0050] The same reference numerals denote the same parts. Furthermore, in the drawings, the thickness, scale, and dimensions of parts are exaggerated for effective description of the technical content. The term "and / or" includes all one or more combinations that can be defined by the associated configuration.

[0051] Various components may be described using terms such as first and second, but the components are not limited by the terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the implementation, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. Unless the context clearly indicates otherwise, the singular form includes the plural form.

[0052] Terms such as "below," "on the lower side," "above," and "on the lower side" are used to describe the relationships between the components illustrated in the accompanying drawings. These terms are relative concepts and are described relative to the direction indicated by the markings in the drawings.

[0053] It should be understood that terms such as “comprising” or “having” are intended to specify the presence of features, quantities, steps, operations, components, parts or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0054] Figure 1 This is a plan view of a display device according to one embodiment.

[0055] Reference Figure 1 According to one embodiment, the display device 10 may include a display panel 100. The display panel 100 may include a display area DA comprising a plurality of pixels PX and a non-display area NDA surrounding the display area DA. The flat surface shape of the display area DA may be rectangular. However, embodiments of this application are not limited to this, and the flat surface shape of the display area DA may be square, circular, elliptical, or other polygonal shapes. For example, the display area DA may have a rounded corner rectangular shape, but is not limited to this, and may also have an angled corner rectangular shape.

[0056] In the implementation, the first direction DR1 and the second direction DR2 are different directions and intersect each other, for example, perpendicular directions in a plan view. Figure 1 In this embodiment, the first direction DR1 may be substantially the same as the extension direction of the short side of the display panel 100, and the second direction DR2 may be substantially the same as the extension direction of the long side of the display panel 100. However, the directions described in the embodiment should be understood as relative directions, and the embodiment is not limited to the described directions.

[0057] The display area DA may include a short side extending in the first direction DR1 and a long side extending in the second direction DR2. The non-display area NDA may surround the display area DA. The non-display area NDA may be located on one side and the other side of the display area DA in the first direction DR1, and on one side and the other side of the display area DA in the second direction DR2.

[0058] The display panel 100 may further include a sensor non-display area NDA_S and sensor holes SH1 and SH2 surrounded by the sensor non-display area NDA_S. In a plan view, sensor holes SH1 and SH2 may be surrounded by the display area NDA_S. For example, sensor holes SH1 and SH2 may be as follows: Figure 1 The two sensor holes are shown, but the embodiments of this application are not limited to this. For example, the sensor hole can be set to a single sensor hole. The two sensor holes SH1 and SH2 can each include a sensor hole in which an infrared sensor is disposed and a sensor hole in which a camera sensor is disposed, but the embodiments of this application are not limited to this. The sensor non-display area NDA_S can be disposed between the sensor holes SH1 and SH2 and the display area DA. The sensor non-display area NDA_S can completely surround the sensor holes SH1 and SH2. Pixel PX may not be set in the sensor non-display area NDA_S.

[0059] Gate drive units (GIPs) can be provided in non-display areas NDA located on one side and the other side of the first direction DR1 of the display area DA. A low-potential voltage line VSSL can be provided outside the gate drive unit GIP in the non-display area NDA. For example, as... Figure 1 As shown, the low-potential voltage line VSSL can extend from the printed circuit board FPCB, through the sub-region SR and the curved region BR, and can be located outside the gate drive unit GIP in the non-display region NDA, and is configured to surround the display region DA.

[0060] Located on the other side of the second direction DR2 of the display area DA (e.g., Figure 1The non-display area NDA at the lower side of the display area DA can extend further from the central portion of the other side toward the other side of the display area DA in the second direction DR2. The width of the non-display area NDA in the first direction DR1 extending further from the central portion of the other side toward the other side of the display area DA in the second direction DR2 can be smaller than the width of the non-display area NDA in the first direction DR1 adjacent to the other side of the display area DA in the second direction DR2.

[0061] The display device 10 may include a main region MR, a sub-region SR, and a curved region BR between the main region MR and the sub-region SR. The main region MR may be formed by the display region DA and the non-display regions NDA surrounding the four sides of the display region DA, and the curved region BR and the sub-region SR may be formed by the portion extending from the central portion of the other side toward the other side in a second direction DR2 toward the display region DA.

[0062] The curved region BR can be located between the sub-region SR and the main region MR. The sub-region SR may include a first pad region PA1 and a second pad region PA2 located at the other end of the sub-region SR in the second direction DR2.

[0063] The display device 10 may further include a data driver unit (DIC) and a printed circuit board (FPCB). The data driver unit (DIC) may be disposed in a first pad area PA1, and the printed circuit board (FPCB) may be attached to a second pad area PA2. Multiple pads connected to the data driver unit (DIC) and the printed circuit board (FPCB) may be disposed in each of the first pad area PA1 and the second pad area PA2.

[0064] The data driving unit DIC can be configured as, for example, a driver chip (IC), but is not limited thereto. In one embodiment, a case is described in which the data driving unit DIC is set by a chip-on-plastic method in which the data driving unit DIC is directly mounted on the display panel 100; however, embodiments of this application are not limited thereto, and the data driving unit DIC can be set by a chip-on-glass method or a chip-on-film method.

[0065] According to one embodiment, the display panel 100 may further include a crack sensing pattern CSP surrounding a low-potential voltage line VSSL. The crack sensing pattern CSP may be configured to completely surround the display area DA, such as... Figure 1 As shown in the diagram. For example, the crack sensing pattern CSP can be disposed outside the low-potential voltage line VSSL. However, embodiments of this application are not limited to this, and a portion of the crack sensing pattern CSP may not be disposed in the non-display area NDA on the other side of the second direction DR2 of the display area DA.

[0066] Figure 2It shows the basis Figure 1 A cross-sectional view of the curved state of the display panel.

[0067] Reference Figure 2 According to one embodiment, the curved region BR of the display panel 100 of the display device 10 can be bent in the thickness direction (or the third direction DR3). Therefore, the main region MR and the sub-region SR can overlap each other in the thickness direction. The display panel 100 can be bent such that the lower surface of the main region MR faces the upper surface of the sub-region SR. A printed circuit board FPCB can be attached to the end of the sub-region SR.

[0068] Figure 3 It is along Figure 1 The cross-sectional view taken by line A-A' in the diagram.

[0069] Reference Figure 3 The display panel has 100 pixels per square meter (see PX). Figure 1 The pixel PX1 may include multiple sub-pixels PX1, PX2, and PX3. The first sub-pixel PX1 may be a red sub-pixel, the second sub-pixel PX2 may be a green sub-pixel, and the third sub-pixel PX3 may be a blue sub-pixel; however, the embodiments of this application are not limited to this. In some embodiments, the pixel PX further includes a fourth sub-pixel, and the fourth sub-pixel may be a white sub-pixel; however, the embodiments of this application are not limited to this. In some embodiments, the pixel may include one red sub-pixel, two green sub-pixels, and one blue sub-pixel; however, the embodiments of this application are not limited to this. For example, the multiple sub-pixels PX1, PX2, and PX3 may be arranged in a stripe pattern on the first direction DR1, but are not limited to this, and may also be arranged in a pentile pattern.

[0070] The display panel 100 may include a substrate 101, a first thin-film transistor 120, a second thin-film transistor 130, a light-emitting portion 150, a package portion 170, a touch portion 180, a color filter insulating layer 114, a black matrix BM, color filters 191, 192, and 193, and a planarization layer OC. The display panel 100 may include at least one panel insulating layer and at least one touch insulating layer between the substrate 101 and the light-emitting portion 150. The at least one panel insulating layer may include at least one of a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a 3-1 insulating layer 105-1, a 3-2 insulating layer 105-2, a fourth insulating layer 106, a fifth insulating layer 108, a sixth insulating layer 109, a first protective layer 111, and a second protective layer 112, and the at least one touch insulating layer may include at least one of a touch buffer layer 181, a first touch insulating layer 183, and a second touch insulating layer 184.

[0071] The substrate 101 may include one or more plastic materials. For example, the substrate 101 may be a multi-substrate comprising a variety of plastic materials such as polyimide. For example, the substrate 101 may include a first substrate portion 101a and a second substrate portion 101b, each comprising a plastic material, and a third substrate portion 101c comprising an inorganic insulating material between the first substrate portion 101a and the second substrate portion 101b, but the embodiments of this application are not limited thereto.

[0072] A buffer layer 102 may be provided on the substrate 101. The buffer layer 102 can minimize or delay the diffusion of moisture or oxygen through the substrate 101. The buffer layer 102 can be formed by alternatingly stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once, but the embodiments of this application are not limited to this.

[0073] A first light-shielding layer 126 may be provided on the buffer layer 102. The first light-shielding layer 126 can prevent light from passing through the first semiconductor layer 123 of the first thin-film transistor 120. For example, the first semiconductor layer 123 may be configured to overlap with the first light-shielding layer 126. The first light-shielding layer 126 may be formed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but the embodiments of this application are not limited thereto.

[0074] A first insulating layer 103 may be provided on the buffer layer 102 and the first light-shielding layer 126. The first insulating layer 103 prevents short circuits between components of the first thin-film transistor 120 and the first light-shielding layer 126. The first insulating layer 103 may be formed of the same material as the buffer layer 102, but embodiments of this application are not limited thereto. For example, the first insulating layer 103 may be formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but embodiments of this application are not limited thereto.

[0075] A first thin-film transistor 120 may be disposed on the first insulating layer 103. The first thin-film transistor 120 may include a first source electrode 121, a first gate electrode 122, a first semiconductor layer 123, and a first drain electrode 124.

[0076] A first semiconductor layer 123 may be disposed on the first insulating layer 103. The first semiconductor layer 123 may include metal oxide semiconductors such as indium gallium zinc oxide (IGZO) and silicon-based semiconductor materials such as amorphous silicon and polycrystalline silicon, but the embodiments of this application are not limited thereto. The first semiconductor layer 123 may include a channel region, a source region, and a drain region.

[0077] Because polycrystalline semiconductor layers have higher mobility than amorphous semiconductor layers and oxide semiconductor layers, power consumption can be lower and reliability can be excellent. Therefore, driving transistors can be formed from polycrystalline semiconductor layers.

[0078] A second insulating layer 104 may be disposed on the first semiconductor layer 123. The second insulating layer 104 may be formed of the same material as the first insulating layer 103 and may prevent short circuits between the first semiconductor layer 123 and other components of the first thin-film transistor 120.

[0079] A first gate electrode 122 may be disposed on the second insulating layer 104. The first gate electrode 122 may be disposed on the second insulating layer 104 to overlap with the channel region of the first semiconductor layer 123. The first gate electrode 122 may be formed of a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or compounds thereof, but embodiments of this application are not limited thereto. The first gate electrode 122 may be disposed together with the gate line.

[0080] A third insulating layer 105-1, 105-2 may be formed on the first gate electrode 122. The third insulating layer 105-1, 105-2 can be formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once, but embodiments of this application are not limited thereto. For example, insulating layer 105-1 may include silicon oxide (SiOx), and insulating layer 105-2 may include silicon nitride (SiNx), but embodiments of this application are not limited thereto.

[0081] A first source electrode 121 and a first drain electrode 124 may be disposed on the third insulating layers 105-1 and 105-2.

[0082] The first source electrode 121 and the first drain electrode 124 can be electrically connected to the first semiconductor layer 123 through contact holes. The first source electrode 121 and the first drain electrode 124 may comprise metallic materials. For example, the first source electrode 121 and the first drain electrode 124 may be formed from a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, but the embodiments of this application are not limited thereto.

[0083] The first source electrode 121 and the first drain electrode 124 may be disposed together with the data line. For example, the data line may be made of the same material as the first source electrode 121 and the first drain electrode 124 and may be formed coplanarly with them, but the embodiments of this application are not limited thereto.

[0084] The storage electrode 140 may be spaced apart from the first thin-film transistor 120. The storage electrode 140 may include a first storage electrode 141 and a second storage electrode 142.

[0085] The first storage electrode 141 may be formed of the same material as the first gate electrode 122 and disposed on the same layer as the first gate electrode 122, but the embodiments of this application are not limited thereto.

[0086] The second storage electrode 142 may be disposed on the first storage electrode 141. The second storage electrode 142 may be disposed on the third insulating layers 105-1 and 105-2, and the third insulating layers 105-1 and 105-2 between the first storage electrode 141 and the second storage electrode 142 may be used as a dielectric to generate capacitance. The second storage electrode 142 may be formed of the same material as the first storage electrode 141, but the embodiments of this application are not limited thereto.

[0087] The second thin-film transistor 130 may be configured to be spaced apart from the first thin-film transistor 120 and the storage electrode 140. The second thin-film transistor 130 may include a second source electrode 131, a second gate electrode 132, a second semiconductor layer 133, and a second drain electrode 134.

[0088] The second light-shielding layer 136 can be disposed on the same layer as the second storage electrode 142.

[0089] Similar to the first light-shielding layer 126, the second light-shielding layer 136 prevents light from traveling to the second semiconductor layer 133, thereby extending the lifetime of the second thin-film transistor 130. For example, the second semiconductor layer 133 may be configured to overlap with the second light-shielding layer 136.

[0090] A fourth insulating layer 106 may be provided on the second light-shielding layer 136. The fourth insulating layer 106 may be formed of the same material as the first insulating layer 103, the second insulating layer 104 or the third insulating layers 105-1, 105-2, but the embodiments of this application are not limited thereto.

[0091] A second semiconductor layer 133 may be disposed on the fourth insulating layer 106. The second semiconductor layer 133 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0092] The second semiconductor layer 133 may include metal oxide semiconductors such as indium gallium zinc oxide (IGZO) and silicon-based semiconductor materials such as amorphous silicon and polycrystalline silicon, but the embodiments of this application are not limited thereto.

[0093] A fifth insulating layer 108 may be disposed on the second semiconductor layer 133. The fifth insulating layer 108 may be formed of the same material as the first insulating layer 103, the second insulating layer 104, the third insulating layer 105-1, 105-2 or the fourth insulating layer 106, but the embodiments of this application are not limited thereto.

[0094] A second gate electrode 132 may be disposed on the fifth insulating layer 108.

[0095] The second gate electrode 132 may be formed of the same material as the first gate electrode 122. For example, the second gate electrode 132 may be formed of a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd) or compounds thereof, but the embodiments of this application are not limited thereto.

[0096] A sixth insulating layer 109 may be provided on the second gate electrode 132. The sixth insulating layer 109 may be formed of the same material as the first insulating layer 103, the second insulating layer 104, the third insulating layers 105-1, 105-2, the fourth insulating layer 106, or the fifth insulating layer 108, but the embodiments of this application are not limited thereto.

[0097] A first source electrode 121, a first drain electrode 124, a second source electrode 131, and a second drain electrode 134 may be disposed on the sixth insulating layer 109.

[0098] The second source electrode 131 and the second drain electrode 134 may be formed of the same material as the first source electrode 121 and the first drain electrode 124 and disposed in the same layer as the first source electrode 121 and the first drain electrode 124, but the embodiments of this application are not limited thereto. For example, the second source electrode 131 and the second drain electrode 134 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but the embodiments of this application are not limited thereto. For example, the second source electrode 131 may be electrically connected to the second storage electrode 142. The second source electrode 131 may pass through the sixth insulating layer 109, the fifth insulating layer 108 and the fourth insulating layer 106 and may be electrically connected to the second storage electrode 142.

[0099] The first thin-film transistor 120 can be a driving transistor, and the second thin-film transistor 130 can be a switching transistor, but the embodiments of this application are not limited thereto.

[0100] A first protective layer 111 may be provided on the first source electrode 121 and the first drain electrode 124.

[0101] The first protective layer 111 can planarize the upper part of the first thin-film transistor 120 and protect the first thin-film transistor 120. The first protective layer 111 can be formed of an organic material. For example, the first protective layer 111 can be formed of an organic material including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, but the embodiments of this application are not limited thereto.

[0102] A second protective layer 112 may be provided on the first protective layer 111. The second protective layer 112 may include the same material as the first protective layer 111, but the embodiments of this application are not limited thereto.

[0103] In some embodiments, a third protective layer may be further provided on the upper surface of the second protective layer 112, but the embodiments of this application are not limited thereto.

[0104] A connecting electrode 145 may be provided between the first protective layer 111 and the second protective layer 112.

[0105] The connecting electrode 145 can electrically connect the first thin-film transistor 120 to the light-emitting part 150. The connecting electrode 145 can be formed of the same material as the first source electrode 121 and the first drain electrode 124, but the embodiments of this application are not limited thereto.

[0106] The connecting electrode 145 may be formed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but the embodiments of this application are not limited thereto.

[0107] A light-emitting part 150 may be provided on the second protective layer 112. The light-emitting part 150 may include a first electrode 151, an organic layer 152, and a second electrode 153. The first electrode 151 may be used as an anode, and the second electrode 153 may be used as a cathode.

[0108] A first electrode 151 may be disposed on the second protective layer 112. The first electrode 151 may be electrically connected to the first thin-film transistor 120 through a contact hole formed in the second protective layer 112. The first electrode 151 may be a reflective electrode for reflecting light, but the embodiments of this application are not limited thereto. The first electrode 151 may comprise a metallic material with high reflectivity, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), or an APC alloy, and may be formed by a single layer or multiple layers, but the embodiments of this application are not limited thereto.

[0109] An organic layer 152 may be disposed on the first electrode 151. The organic layer 152 may include one or more light-emitting structures (or light-emitting elements or components) stacked on the first electrode 151 in a sequence or reverse order of hole transport-related layers and electron transport-related layers. For example, the hole transport-related layer may include a hole transport layer, a hole injection layer, an electron blocking layer, a p-type charge generation layer, etc., but the embodiments of this application are not limited thereto. For example, the electron transport-related layer may include an electron transport layer, an electron injection layer, a hole blocking layer, an n-type charge generation layer, etc., but the embodiments of this application are not limited thereto. The organic layer 152 may be an organic light-emitting layer, an inorganic light-emitting layer, a quantum dot light-emitting layer, a micro light-emitting diode, a miniature light-emitting diode, etc., but the embodiments of this application are not limited thereto. For example, the organic layer 152 of the display panel 100 according to one embodiment of this application may include an organic light-emitting layer. The organic layer 152 may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer. The organic layer 152 may be a white light-emitting layer, but the embodiments of this application are not limited thereto. The specific structure of the organic layer 152 according to one embodiment will be described below.

[0110] Figure 4 yes Figure 3 A detailed cross-sectional view of the light-emitting part.

[0111] Reference Figure 4 The light-emitting part 150 may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3.

[0112] The thickness of the light-emitting portion 150 in each sub-pixel PX1, PX2 or PX3 may be different, but the embodiments of this application are not limited to this, and the thickness of the light-emitting portion 150 in each sub-pixel PX1, PX2 or PX3 may be the same.

[0113] The organic layer 152 may include a first organic layer 152a disposed in the first sub-pixel PX1, a second organic layer 152b disposed in the second sub-pixel PX2, and a third organic layer 152c disposed in the third sub-pixel PX3. The light-emitting layers EML1, EML2, and EML3 of the organic layers 152a, 152b, and 152c may be physically separated, but the lower and upper layers of the light-emitting layers EML1, EML2, and EML3 may be integrally formed across the sub-pixels PX1, PX2, and PX3. The thickness of each light-emitting layer EML1, EML2, or EML3 may be different. For example, the thickness of the first light-emitting layer EML1 may be the largest, the thickness of the second light-emitting layer EML2 may be the second largest, and the thickness of the third light-emitting layer EML3 may be the smallest, but the embodiments of this application are not limited to this.

[0114] A hole injection layer HIL can be disposed on the first electrode 151. The hole injection layer HIL can be located between the first electrode 151 and the light-emitting layers EML1, EML2, and EML3. The hole injection layer HIL can be disposed integrally across sub-pixels PX1, PX2, and PX3, but is not limited thereto.

[0115] A hole transport layer (HTL) can be set on the hole injection layer (HIL). The hole transport layer (HTL) can be located between the hole injection layer (HIL) and the light emission layers (EML1, EML2, EML3). The hole transport layer (HTL) can be set as a single unit across sub-pixels (PX1, PX2, PX3), but is not limited to this.

[0116] Light-emitting layers EML1, EML2, and EML3 can be set on the hole transport layer HTL. The first light-emitting layer EML1 can be set in the first sub-pixel PX1, the second light-emitting layer EML2 can be set in the second sub-pixel PX2, and the third light-emitting layer EML3 can be set in the third sub-pixel PX3.

[0117] The thickness of each light-emitting layer EML1, EML2, or EML3 may vary, but is not limited to this.

[0118] Each of the first luminescent layer EML1, the second luminescent layer EML2, and the third luminescent layer EML3 may include a material capable of emitting light in the visible light range by receiving and recombinizing holes and electrons.

[0119] An electron blocking layer (EBL) can be set on each emissive layer (EML1, EML2, or EML3). The electron blocking layer (EBL) can be set uniformly across sub-pixels (PX1, PX2, and PX3).

[0120] An electron transport layer (ETL) can be set on the electron blocking layer (EBL). The ETL can be set up uniformly across sub-pixels PX1, PX2, and PX3, but is not limited to this.

[0121] A second electrode 153 can be set on the electron transport layer ETL.

[0122] Figure 5 It is a detailed cross-sectional view of the light-emitting part based on the modified example.

[0123] Reference Figure 4 and Figure 5 The organic layer 152_1 may include a first organic layer 152a_1 disposed in the first sub-pixel PX1, a second organic layer 152b_1 disposed in the second sub-pixel PX2, and a third organic layer 152c_1 disposed in the third sub-pixel PX3.

[0124] like Figure 4 and Figure 5The illustration shows an example where the light-emitting layer of organic layers 152, 152_1 is formed as one or two stacks for each sub-pixel PX1, PX2 or PX3. However, the embodiments of this application are not limited to this, and the light-emitting layer may be formed as three or more stacks.

[0125] The luminescent layers of each organic layer 152a_1, 152b_1, or 152c_1 can be physically separated, but the lower and upper layers of the luminescent layers can be integrated across sub-pixels PX1, PX2, and PX3. The thickness of each luminescent layer can be different.

[0126] A hole injection layer HIL, a first hole transport layer HTL1, light-emitting layers EML1a, EML2a, EML3a, a hole blocking layer HBL, a first electron transport layer ETL1, a common charge layer CGL, a second hole transport layer HTL2, light-emitting layers EML1b, EML2b, EML3b, an electron blocking layer EBL, and a second electron transport layer ETL2 can be sequentially disposed on the first electrode 151.

[0127] The hole blocking layer HBL can be set up as a single unit across sub-pixels PX1, PX2, and PX3.

[0128] A common charge layer CGL may be disposed between the first electron transport layer ETL1 and the second hole transport layer HTL2. The common charge layer CGL may include a conductive material, but the embodiments of this application are not limited thereto.

[0129] and Figure 4 The descriptions of the hole injection layer (HIL), hole transport layer (HTL), luminescent layers (EML1, EML2, EML3), electron transport layer (ETL), and electron blocking layer (EBL) are largely the same and can be applied to... Figure 5 The structure consists of a hole injection layer HIL, a first hole transport layer HTL1, light-emitting layers EML1a, EML2a, EML3a, a first electron transport layer ETL1, a second hole transport layer HTL2, light-emitting layers EML1b, EML2b, EML3b, an electron blocking layer EBL, and a second electron transport layer ETL2.

[0130] A second electrode 153 may be disposed on the second electron transport layer ETL2.

[0131] Return to reference Figure 3 A second electrode 153 may be disposed on the organic layer 152. The second electrode 153 may be a transparent electrode that transmits light, but the embodiments of this application are not limited thereto. For example, the second electrode 153 may comprise a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a metal that transmits visible light, but the embodiments of this application are not limited thereto.

[0132] The embankment 154 may be configured to expose the first electrode 151. The embankment 154 may define the openings (or light-emitting regions EA1, EA2, EA3) of sub-pixels PX1, PX2, and PX3, and may be configured to cover the edge portion (or outer periphery) of the first electrode 151. That is, the first sub-pixel PX1 may include a first light-emitting region EA1 and a first non-light-emitting region NEA1 surrounding the first light-emitting region EA1, the second sub-pixel PX2 may include a second light-emitting region EA2 and a second non-light-emitting region NEA2 surrounding the second light-emitting region EA2, and the third sub-pixel PX3 may include a third light-emitting region EA3 and a third non-light-emitting region NEA3 surrounding the third light-emitting region EA3. That is, each non-light-emitting region NEA1, NEA2, or NEA3 may correspond to the boundary between adjacent sub-pixels PX1, PX2, and PX3.

[0133] The dam portion 154 may include a black base material. For example, the dam portion 154 may be formed of a material containing black pigment or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, photosensitive polymer, etc., but the embodiments of this application are not limited thereto. When the dam portion 154 is formed of a material containing black pigment or black dye, the dam portion 154 may be an opaque dam portion. When the dam portion 154 is formed of a material containing black pigment or black dye, it can block external light or light reflected from the outside, thereby preventing the brightness of the display device from decreasing.

[0134] A blocking section RAS can be further installed on the embankment 154. For example... Figure 3 As shown, the blocking portion RAS can be disposed at all boundaries NEA1, NEA2, and NEA3 between sub-pixels PX1, PX2, and PX3, but the embodiments of this application are not limited to this. The blocking portion RAS can be directly disposed on the upper surface of the dam 154, but the embodiments of this application are not limited to this. The blocking portion RAS can be used to separate the organic layer 152 from the boundaries of adjacent sub-pixels PX1, PX2, and PX3. In some embodiments, the blocking portion RAS can be omitted, and a groove structure recessed from the surface of the dam 154 can be applied.

[0135] Spacers 155 may be further provided on the embankment 154. Spacers 155 may be formed of the same material as the embankment 154, but embodiments of this application are not limited to this. For example, spacers 155 may be a transparent embankment, but are not limited to this, and spacers 155 may be formed of the same material as the embankment 154. For example, spacers 155 may be provided on at least one of the boundaries of the first to third sub-pixels PX1, PX2, PX3, but embodiments of this application are not limited to this. The embankment 154 and spacers 155 may be formed of the same material and simultaneously formed through a halftone mask, but embodiments of this application are not limited to this.

[0136] An organic layer 152 may be provided on the first electrode 151, the embankment 154, and the spacer 155. A second electrode 153 may be provided on the organic layer 152.

[0137] An encapsulation portion 170 may be provided on the second electrode 153. The encapsulation portion 170 may include one or more insulating layers. For example, the encapsulation portion 170 may include a first encapsulation layer 171, a second encapsulation layer 172 disposed on the first encapsulation layer 171, and a third encapsulation layer 173 disposed on the second encapsulation layer 172. The encapsulation portion 170 may include one or more inorganic insulating material layers and one or more organic material layers. For example, the first encapsulation layer 171 and the third encapsulation layer 173 may include inorganic insulating materials, and the second encapsulation layer 172 may include organic materials, but the embodiments of this application are not limited thereto.

[0138] A touch portion 180 may be provided on the encapsulation portion 170. The touch portion 180 may include a touch buffer layer 181, a first touch conductive layer, a first touch insulating layer 183, a second touch insulating layer 184, and a second touch conductive layer. In some embodiments, one or more touch organic layers may be further provided on the second touch conductive layer, but the embodiments of this application are not limited thereto.

[0139] Figure 6 It is based on Figure 3 A cross-sectional view of the touch area.

[0140] Reference Figure 3 and Figure 6 A touch buffer layer 181 may be provided on the encapsulation portion 170. For example, the touch buffer layer 181 may be provided on the third encapsulation layer 173. The touch buffer layer 181 may be formed of the same material as the buffer layer 102, but the embodiments of this application are not limited thereto.

[0141] A first touch conductive layer may be disposed on the touch buffer layer 181. The first touch conductive layer may include a bridging electrode 182. The bridging electrode 182 and sensor electrode 185, which will be described below, may be disposed at each boundary between adjacent sub-pixels PX1, PX2, and PX3. For example, the bridging electrode 182 and sensor electrode 185 may be disposed in non-light-emitting areas NEA1, NEA2, and NEA3. The bridging electrode 182 and sensor electrode 185 may overlap with the black matrix BM, which will be described below, in the thickness direction. The black matrix BM may cover the bridging electrode 182 and sensor electrode 185. Therefore, the bridging electrode 182 and sensor electrode 185 may be prevented from being externally visible.

[0142] A first touch insulating layer 183 and a second touch insulating layer 184 may be disposed on the first touch conductive layer. The first touch insulating layer 183 and the second touch insulating layer 184 disposed on the first touch insulating layer 183 can prevent short circuits between the first touch conductive layer and the second touch conductive layer. The first touch insulating layer 183 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof, but the embodiments of this application are not limited thereto. The second touch insulating layer 184 may include an organic insulating material, but the embodiments of this application are not limited thereto, and the second touch insulating layer 184 may include the same material as the first touch insulating layer 183.

[0143] A second touch conductive layer may be disposed on the second touch insulating layer 184. The second touch conductive layer may include a first sensor electrode 185a and a second sensor electrode 185b. The sensor electrode 185a may be disposed in a first direction DR1 (see...). Figure 1 The first sensor electrode 185a extends on the first sensor electrode DR1 and in the second direction DR2 (see) which is different from the first direction DR1. Figure 1 The second sensor electrode 185b extends on the surface.

[0144] The bridging electrode 182 can be electrically connected to the first sensor electrode 185a through contact holes formed in the first touch insulating layer 183 and the second touch insulating layer 184. For example, the first sensor electrode 185a and the bridging electrode 182 can be connected in a first direction DR1 (see...). Figure 1 Extending upwards.

[0145] The sensor electrode 185 and the bridging electrode 182 may comprise metallic materials. For example, the sensor electrode 185 and the bridging electrode 182 may be formed of titanium (Ti), nickel (Ni), aluminum (Al), or alloys thereof, and may be formed of a three-layer structure such as titanium (Ti) / aluminum (Al) / titanium (Ti), but embodiments of this application are not limited thereto.

[0146] Return to reference Figure 3 A color filter insulating layer 114 may be disposed on the second touch conductive layer. The color filter insulating layer 114 may be formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but the embodiments of this application are not limited thereto.

[0147] A black matrix BM can be formed on the color filter insulating layer 114. The black matrix BM may include a black base material. For example, the black matrix BM may include a light-shielding material or a light-absorbing material. For example, the black matrix BM may be formed from a material including black pigments, black dyes, etc. The black matrix BM may cover the bridging electrode 182 and the sensor electrode 185. Therefore, the bridging electrode 182 and the sensor electrode 185 can be prevented from being seen from the outside. For example, the width of the black matrix BM may be smaller than the width of the embankment 154.

[0148] For example, the distance between the boundary between the luminous regions EA1, EA2, EA3 and the non-luminous regions NEA1, NEA2, NEA3 and the end of the black matrix BM can be longer than the distance between the boundary between the luminous regions EA1, EA2, EA3 and the non-luminous regions NEA1, NEA2, NEA3 and the end of the embankment 154. The end of the embankment 154 can coincide with the boundary between the luminous regions EA1, EA2, EA3 and the non-luminous regions NEA1, NEA2, NEA3, but this embodiment is not limited to this. In a display panel 100 according to one embodiment, since the embankment 154 may include a black base material and the distance between the boundaries of the light-emitting regions EA1, EA2, EA3 and the non-light-emitting regions NEA1, NEA2, NEA3 and the ends of the black matrix BM is longer than the distance between the boundaries of the light-emitting regions EA1, EA2, EA3 and the non-light-emitting regions NEA1, NEA2, NEA3 and the ends of the embankment 154, light emitted from the light-emitting regions EA1, EA2, EA3 can be emitted upward at a viewing angle that widens the distance between the boundaries of the light-emitting regions EA1, EA2, EA3 and the non-light-emitting regions NEA1, NEA2, NEA3 and the ends of the black matrix BM. Therefore, brightness reduction based on viewing angle can be prevented. However, when the distance between the boundaries of the light-emitting regions EA1, EA2, EA3 and the non-light-emitting regions NEA1, NEA2, NEA3 and the ends of the black matrix BM is longer than the distance between the boundaries of the light-emitting regions EA1, EA2, EA3 and the ends of the dam 154, and the dam 154 is formed only of transparent material, light incident from the outside is reflected by the dam 154, resulting in visible ring spots. However, in the display panel 100 according to one embodiment, externally incident light can be absorbed or blocked by the dam 154, which includes a black base material, thereby preventing the generation of ring spots.

[0149] Color filters 191, 192, and 193 can be set on the black matrix BM. Color filters 191, 192, and 193 can be respectively set on the first to third sub-pixels PX1, PX2, and PX3, and can block specific colors of light emitted from the light-emitting areas EA1, EA2, and EA3 of the sub-pixels PX1, PX2, and PX3. The first color filter 191 can be set to block light of colors other than red (R) light. In this case, the first color filter 191 can be set as a red color filter. The second color filter 192 can be set to block light of colors other than green (G) light. In this case, the second color filter 192 can be set as a green color filter. The third color filter 193, set in the third sub-pixel PX3, can be set to block light of colors other than blue (B) light. In this case, the third color filter 193 can be set as a blue color filter. However, the embodiments of this application are not limited to this.

[0150] For example, each color filter 191, 192, or 193 may be in direct contact with the side and top surfaces of the black matrix BM. For example, each color filter 191, 192, or 193 may be spaced apart from the boundaries of adjacent sub-pixels PX1, PX2, and PX3, but the embodiments of this application are not limited thereto, and the color filters 191, 192, and 193 may overlap each other in the thickness direction.

[0151] A planarization layer OC can be provided on color filters 191, 192, and 193. The planarization layer OC can be used to flatten the steps formed by color filters 191, 192, and 193. For example, the planarization layer OC may include an organic insulating material.

[0152] Figure 7 yes Figure 1 A magnified view of region Q1 in the image. Figure 8 It is along Figure 7 The cross-sectional view taken by line B-B' in the diagram. Figure 9 It is along Figure 7 The cross-sectional view taken by line C-C' in the diagram.

[0153] For ease of description, Figure 7 A display panel 100 is shown, which omits the data drive unit (DIC) and the printed circuit board (FPCB).

[0154] Reference Figure 1 and Figures 7 to 9 The display device 10 may include multiple pads P (IPD, OPD, VSSP, VDDP, TPD, PD) and multiple connection lines L (ICL, OCL, VSSL, VDDL, TSL).

[0155] The first pad area PA1 may include input pads IPD and output pads OPD. Each of the input pads IPD and output pads OPD may be configured as multiple pads.

[0156] Each of the multiple input pads IPD and multiple output pads OPD can be repeatedly set on the first direction DR1. The output pads OPD can be set on one side of the first pad area PA1 on the second direction DR2, and the input pads IPD can be set on the other side of the first pad area PA1 on the second direction DR2.

[0157] The input pad IPD and output pad OPD are electrically connected to the data driver unit DIC contacts mounted on the first pad area PA1. The input pad IPD is electrically connected to the input bump contacts of the data driver unit DIC. The output pad OPD is electrically connected to the output bump contacts of the data driver unit DIC.

[0158] The input pads (IPD) can receive various signals and voltages from the outside and transmit them to the data driver unit (DIC). The output pads (OPD) can supply various signals and voltages processed and output by the data driver unit (DIC) to the outside.

[0159] The second pad area PA2 may include a low-potential voltage pad VSSP, a high-potential voltage pad VDDP, a touch pad TPD, and a signal pad PD. The display panel 100 can be electrically connected to the printed circuit board FPCB through the second pad area PA2.

[0160] Low-potential voltage pads (VSSP), high-potential voltage pads (VDDP), touch pads (TPD), and signal pads (PD) can be disposed on the sixth insulating layer 109 and formed as multiple layers. These multiple layers may include the same material as the first drain electrode 124, the second source electrode 131, and the second drain electrode 134, or may include the same material as the connection electrode 145.

[0161] For example, the touch pad TPD can be disposed on the sixth insulating layer 109 and can be composed of a first touch pad layer TPD1 and a second touch pad layer TPD2 disposed on the first touch pad layer TPD1. The first touch pad layer TPD1 can be disposed on the same layer as the first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134, and can include the same material as the first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134, and can be formed by the same process as the first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134. The second touch pad layer TPD2 can include the same material as the connection electrode 145 and can be formed by the same process as the connection electrode 145.

[0162] The input pad IPD can be disposed on the sixth insulating layer 109, and can be composed of a first input pad layer IPD1, a second input pad layer IPD2 disposed on the first input pad layer IPD1, and a third input pad layer IPD3 disposed on the second input pad layer IPD2. The first input pad layer IPD1 can be disposed on the same layer as the first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134, and can include the same material as the first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134, and can be formed by the same process as the first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134. The second input pad layer IPD2 can include the same material as the connection electrode 145 and can be formed by the same process as the connection electrode 145. The third input pad layer IPD3 may include the same material as the sensor electrode 185 of the touch portion 180 and may be formed by the same process as the sensor electrode 185 of the touch portion 180.

[0163] The second input pad layer IPD2 and the third input pad layer IPD3 are in direct contact with each other. In some areas, a touch buffer layer 181 and a first touch insulating layer 183 may be provided between the second input pad layer IPD2 and the third input pad layer IPD3, but the embodiments of this application are not limited to this.

[0164] The output pads (OPDs) can be disposed on the sixth insulating layer 109 and can be composed of a first output pad layer (OPD1), a second output pad layer (OPD2) disposed on the first output pad layer (OPD1), and a third output pad layer (OPD3) disposed on the second output pad layer (OPD2). The first output pad layer (OPD1) can be disposed on the same layer as the first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134. It can include the same material as the first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134, and can be formed using the same process as the first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134. The second output pad layer (OPD2) can include the same material as the connection electrode 145 and can be formed using the same process as the connection electrode 145. The third output pad layer OPD3 may include the same material as the sensor electrode 185 of the touch portion 180 and may be formed by the same process as the sensor electrode 185 of the touch portion 180.

[0165] The second output pad layer OPD2 and the third output pad layer OPD3 are in direct contact with each other. In some areas, a touch buffer layer 181 and a first touch insulating layer 183 may be provided between the second output pad layer OPD2 and the third output pad layer OPD3, but the embodiments of this application are not limited to this.

[0166] The second protective layer 112 may also be disposed within the sub-region SR. In the sub-region SR, the second protective layer 112 may expose the first pad region PA1 and the second pad region PA2. In the sub-region SR, the second protective layer 112 may expose the pads IPD and OPD disposed in the first pad region PA1, and the pads VSSP, VDDP, TPD, and PD disposed in the second pad region PA2.

[0167] In the sub-region SR, the second protective layer 112 can be configured to be spaced apart from the pads IPD, OPD, VSSP, VDDP, TPD, and PD. In the sub-region SR, the second protective layer 112 can expose all areas of the pads IPD, OPD, VSSP, VDDP, TPD, and PD.

[0168] Because the second protective layer 112 is spaced apart from the pads IPD, OPD, VSSP, VDDP, TPD, and PD, it can block moisture and other substances from penetrating along the penetration paths of the pads IPD, OPD, VSSP, VDDP, TPD, and PD. Therefore, it can suppress or prevent moisture and other substances from penetrating the pads IPD, OPD, VSSP, VDDP, TPD, and PD, and minimize the bulging of organic films, etc. Furthermore, it can improve the reliability of the display panel 100, thereby increasing the lifespan of the display device 10 and reducing power consumption.

[0169] In the first pad region PA1, the second protective layer 112 can expose both the input pad IPD and the output pad OPD, and can be disposed between the input pad IPD and the output pad OPD. The second protective layer 112 disposed on the first pad region PA1 can be formed in an island shape and configured to be spaced apart from another second protective layer 112. However, embodiments of this application are not limited to this, and the second protective layer 112 disposed on the first pad region PA1 can be omitted.

[0170] The display device 10 may include an input connection line ICL, an output connection line OCL, a low-potential voltage line VSSL, a high-potential voltage line VDDL, and a touch sensing line TSL disposed on the display panel 100.

[0171] The input connection line ICL can be positioned between the signal pad PD and the input pad IPD, and can electrically connect the signal pad PD to the input pad IPD. One side of the input connection line ICL can be electrically connected to the signal pad PD, and the other side can be electrically connected to the input pad IPD.

[0172] The input connection line ICL can be integrally formed with the input pad IPD, but is not limited thereto. The input connection line ICL can be formed by a first input connection line layer ICL1 and a second input connection line layer ICL2 disposed on the first input connection line layer ICL1. The first input connection line layer ICL1 is integrally formed with the first input pad layer IPD1, and the second input connection line layer ICL2 is integrally formed with the second input pad layer IPD2.

[0173] The output connection line OCL can be electrically connected to the output pad OPD. One side of the output connection line OCL can be electrically connected to the output pad OPD, and the other side can be electrically connected to one of the following: a data line, a gate line, etc.

[0174] The output connection line (OCL) can be integrally formed with the output pad (OPD), but is not limited to this. The output connection line (OCL) can be formed by a first output connection line layer (OCL1) and a second output connection line layer (OCL2) disposed on the first output connection line layer (OCL1). The first output connection line layer (OCL1) can be integrally formed with the first output pad layer (OPD1). The second output connection line layer (OCL2) can be integrally formed with the second output pad layer (OPD2).

[0175] Figure 7 The diagram shows that the signal pad PD is separated from the low-potential voltage pad VSSP, the high-potential voltage pad VDDP, and the touch pad TPD, and the low-potential voltage line VSSL, the high-potential voltage line VDDL, and the touch sensing line TSL are set independently of the first pad area PA1, but the embodiments of this application are not limited thereto.

[0176] For example, at least one of the low-potential voltage pad VSSP, high-potential voltage pad VDDP, and touch pad TPD can be one of the signal pads PD. That is to say, Figure 7 The low-potential voltage pad VSSP, high-potential voltage pad VDDP, and touch pad TPD are shown to be configured separately from the data drive unit DIC via separate lines VSSL, VDDL, and TSL. However, at least one of the low-potential voltage pad VSSP, high-potential voltage pad VDDP, and touch pad TPD can be electrically connected to the input pad IPD via the input connection line ICL.

[0177] The low-potential voltage line VSSL can be electrically connected to the low-potential voltage pad VSSP. The low-potential voltage line VSSL and the low-potential voltage pad VSSP can be integrally formed, but are not limited to this, and can make contact with each other through contact holes or the like.

[0178] The high-potential voltage line VDDL can be electrically connected to the high-potential voltage pad VDDP. The high-potential voltage line VDDL and the high-potential voltage pad VDDP can be integrally formed, but are not limited to this, and can make contact with each other through contact holes or the like.

[0179] The touch sensing line (TSL) can be electrically connected to the touch pad (TPD). The touch sensing line (TSL) may include the same material as the sensor electrode 185 of the touch unit 180. The touch sensing line (TSL) can be formed using the same process as the sensor electrode 185 of the touch unit 180.

[0180] The touch sensing line TSL can be physically contacted and electrically connected to the touch pad TPD exposed through the second protective layer 112, the touch buffer layer 181, and the first touch insulating layer 183. The touch sensing line TSL may have one side electrically connected to the touch pad TPD and the other side electrically connected to the sensor electrode 185 of the touch portion 180.

[0181] The display device 10 may include an over-etched region OE on a substrate 101 disposed in a sub-region SR. The over-etched region OE may be disposed in a non-display region NDA. The over-etched region OE may be disposed on one side of the touch pad TPD in a second direction DR2. The over-etched region OE may be disposed between the touch pad TPD and the display region DA. The over-etched region OE may be disposed between the curved region BR and the touch pad TPD. The over-etched region OE may be disposed between a second protective layer 112 disposed in the sub-region SR and the touch pad TPD.

[0182] In the over-etched area OE, at least a portion of panel insulating layers 102, 103, 104, 105-1, 105-2, 106, 107, 108, and 109 are provided between the substrate 101 and the touch pad TPD. The over-etched area OE may include a recess GR defined by at least one of the panel insulating layers 102, 103, 104, 105-1, 105-2, 106, 107, 108, and 109. For example, in the over-etched area OE, the sixth insulating layer 109 among the panel insulating layers 102, 103, 104, 105-1, 105-2, 106, 107, 108, and 109 may be recessed to expose the fifth insulating layer 108 beneath it. The recess GR defined by the sixth insulating layer 109 and the fifth insulating layer 108 may be provided in the over-etched area OE.

[0183] In the groove GR, the touch buffer layer 181 may be in direct contact with the fifth insulating layer 108, but is not limited thereto.

[0184] In the over-etched area OE, the panel insulating layer disposed between the substrate 101 and the touch pad TPD can have a smaller thickness than in the rest of the area.

[0185] In the over-etched area (OE), the panel insulating layer disposed between the substrate 101 and the touch pad (TPD) may have a lower height than the rest of the area. Here, the height of the panel insulating layer may refer to the height of the top surface of the panel insulating layer from the substrate 101.

[0186] The over-etched region OE may overlap with the touch sensing line TSL in the thickness direction (third direction DR3). The touch sensing line TSL may extend across the over-etched region OE, but is not limited thereto. In addition, at least one groove GR may be formed. For example, one or more grooves GR may be formed along a touch sensing line TSL. That is, one or more grooves GR may overlap with a touch sensing line TSL in the thickness direction (third direction DR3).

[0187] Over-etched areas (OE) can be formed during the process of etching the second protective layer 112 surrounding the pads IPD, OPD, VSSP, VDDP, TPD, and PD.

[0188] The manufacturing method of this application will be described below. For the components included in the manufacturing method, those referenced... Figures 1 to 9 For those contents that are substantially the same, give the same figure labels, and the repeated contents may be omitted or briefly described.

[0189] Figures 10 to 12 This is a view showing the manufacturing method of each process operation of the display device according to this embodiment. Figures 10 to 12 A cross-section of the second pad region PA2 of subregion SR is shown.

[0190] First, refer to Figure 3 and Figure 10 During the process of applying the second protective layer 112, the second protective layer 112 may also be disposed in the sub-region SR. The second protective layer 112 disposed in the sub-region SR may cover one side surface on the second direction DR2 of the touch pad TPD. However, the embodiments of this application are not limited to this, and the second protective layer 112 may cover pads IPD, OPD, VSSP, VDDP, TPD, PD (see Figure 7 A side surface on the second direction DR2.

[0191] Due to the pads IPD, OPD, VSSP, VDDP, TPD, PD (see...) Figure 7One side surface of the second direction DR2 is covered by the second protective layer 112, so that the etchant used for patterning the first electrode 151 can be suppressed or prevented from contacting the pads IPD, OPD, VSSP, VDDP, TPD, PD (see Figure 7 ) contact. In particular, when pads IPD, OPD, VSSP, VDDP, TPD, PD (see Figure 7 When aluminum (Al) is included, it can suppress or prevent Ag residue defects that may occur when the pads come into contact with silver (Ag) included in the etchant used to pattern the first electrode 151, and further suppress or prevent the bulging of the second protective layer 112.

[0192] The second protective layer 112 may define an opening OP that exposes the panel insulation layer beneath it. The opening OP may expose the sixth insulation layer 109. The opening OP may be formed by patterning during the application of the second protective layer 112. Thus, the sidewalls defining the opening OP may be formed with a gently tapered shape.

[0193] Further reference Figure 11 A photoresist PR can be formed, which covers the second protective layer 112 on one side of the second direction DR2 of the opening OP and exposes the second protective layer 112 on the other side of the second direction DR2, and covers the pads IPD, OPD, VSSP, VDDP, TPD, and PD (see...). Figure 7 ).

[0194] Photoresist PR can be patterned to expose a second protective layer 112 covering the pads IPD, OPD, VSSP, VDDP, TPD, and PD (see...). Figure 7 And exposes a portion of the sixth insulating layer 109 through the opening OP between the touch pad TPD and the second protective layer 112.

[0195] exist Figure 11 In the middle, the exposed areas not covered by the second protective layer 112 and the photoresist PR can correspond to Figure 7 The over-etched area OE.

[0196] Further reference Figure 12 It can etch areas exposed by photoresist PR. Due to the coverage of pads IPD, OPD, VSSP, VDDP, TPD, PD (see...) Figure 7 The second protective layer 112 is removed, so the pads IPD, OPD, VSSP, VDDP, TPD, PD (see...) Figure 7 It can be set to be spaced apart from the second protective layer 112. Therefore, it can block moisture and other substances from penetrating along the penetration paths of its pads IPD, OPD, VSSP, VDDP, TPD, and PD.

[0197] Furthermore, in the area exposed by the photoresist PR, at least a portion of the panel insulating layers 102, 103, 104, 105-1, 105-2, 106, 107, 108, and 109 disposed between the substrate 101 and the touch pad TPD can be etched in the thickness direction (third direction DR3). Figure 12 In this process, the sixth insulating layer 109 exposed by the photoresist PR can be etched to form the over-etched region OE and the groove GR exposed by the fifth insulating layer 108.

[0198] When the opening OP of the second protective layer 112 is not formed and the same etching is performed using photoresist PR, dry etching is performed, and after etching, the side surface of the second protective layer 112 is formed into a cone shape with a large angle to the sixth insulating layer 109. That is, the side surface of the second protective layer 112 can have a very steep slope.

[0199] When the side surface of the second protective layer 112 has a steep slope, the touch sensing line TSL (see Figure 8 It may not extend smoothly due to step coverage and may break during the deposition process.

[0200] In other words, by pre-forming openings (OPs) during the patterning process of the second protective layer 112, the side surfaces of the second protective layer 112 have gentle slopes, enabling the smooth deposition of touch sensing lines (TSLs) (see...). Figure 8 ).

[0201] During the manufacturing process, over-etched areas (OE) and grooves (GR) can be formed to block moisture penetration along the penetration paths of the pads (IPD, OPD, VSSP, VDDP, TPD, PD), and the touch sensing line (TSL) can be smoothly deposited (see...). Figure 8 ).

[0202] Here, the photoresist PR can be used to form sensor holes SH1, SH2 (see...). Figure 1 The photoresist PR is used. That is, the process of removing the second protective layer 112 covering the pads IPD, OPD, VSSP, VDDP, TPD, and PD (see...). Figure 7 The process of forming the over-etched area OE and the groove GR can be achieved by forming the sensor holes SH1 and SH2 (see...). Figure 1 The same process is used to perform the process.

[0203] Therefore, since no separate process is required, the increase in process time, cost, etc. can be minimized.

[0204] Other embodiments of this application will be described below. For the components included in these other embodiments, references will be made. Figures 1 to 12 For those contents that are substantially the same, give the same figure labels, and the repeated contents may be omitted or briefly described.

[0205] Figure 13 This is a plan view of a display panel according to another embodiment. Figure 13 This is an enlarged view of the sub-area SR of the display panel 100.

[0206] Reference Figure 13 According to this embodiment, the over-etched region OE_1 of the display device 10_1 may overlap with both the touch sensing line TSL and the input connection line ICL. The over-etched region OE_1 may extend in the first direction DR1 and intersect with both the touch sensing line TSL and the input connection line ICL.

[0207] In this case, the implementation of this application is not limited to this. The input connection line ICL may include the same material as the sensor electrode 185 of the touch portion 180 and may be formed by the same process as the sensor electrode 185 of the touch portion 180.

[0208] Figure 13 The over-etched region OE_1 is shown to overlap with the touch sensing line TSL and the input connection line ICL, but embodiments of this application are not limited thereto. For example, the over-etched region OE_1 may further extend in the first direction DR1 to overlap with the low-potential voltage line VSSL and the high-potential voltage line VDDL.

[0209] Figure 13 The over-etched region OE_1 is shown to be integrally formed, but the embodiments of this application are not limited thereto. For example, the over-etched region OE_1 may be configured as multiple over-etched regions, and the multiple over-etched regions OE_1 may be separate. In this case, the multiple over-etched regions OE_1 may be configured to overlap with at least one of the multiple touch sensing lines TSL and the multiple input connection lines ICL.

[0210] For example, each of the multiple over-etched regions OE_1 can overlap with a touch sensing line TSL or an input connection line ICL.

[0211] In this case, since the second protective layer 112 is set to be spaced apart from the pads IPD, OPD, VSSP, VDDP, TPD, and PD, it can block moisture and other moisture from penetrating along the penetration path of the pads IPD, OPD, VSSP, VDDP, TPD, and PD, and smoothly deposit the touch sensing line TSL.

[0212] Figure 14 This is a cross-sectional view of a display device according to yet another embodiment.

[0213] Reference Figure 14 According to this embodiment, the over-etched region OE_2 of the display device 10_2 may be recessed in the thickness direction (third direction DR3), but the fifth insulating layer 108 may not be exposed.

[0214] Specifically, in the over-etched region OE_2, the sixth insulating layer 109 may be recessed in the thickness direction (third direction DR3), but the fifth insulating layer 108 may not be exposed. The side and bottom surfaces of the groove GR may be entirely defined by the sixth insulating layer 109.

[0215] The lower surface of the groove GR may have a different roughness than the upper surface of the sixth insulating layer 109 outside the over-etched region OE_2. The lower surface of the groove GR may have a higher roughness than the upper surface of the sixth insulating layer 109 outside the over-etched region OE_2, but is not limited to this.

[0216] In this case, since the second protective layer 112 is set to be spaced apart from the pads IPD, OPD, VSSP, VDDP, TPD, and PD, it can block moisture and other moisture from penetrating along the penetration path of the pads IPD, OPD, VSSP, VDDP, TPD, and PD, and smoothly deposit the touch sensing line TSL.

[0217] Figure 15 This is a cross-sectional view of a display device according to yet another embodiment.

[0218] Reference Figure 15 In the over-etched region OE_3 of the display device 10_3 according to this embodiment, the sixth insulating layer 109 and the fifth insulating layer 108 may also be recessed.

[0219] In the over-etched region OE_3, the sixth insulating layer 109 can penetrate in the thickness direction, and a portion of the fifth insulating layer 108 can be recessed. Therefore, the groove GR can be defined by the sixth insulating layer 109 and the fifth insulating layer 108. The lower surface of the groove GR can be defined by the fifth insulating layer 108, and the side surfaces of the groove GR can be defined by the sixth insulating layer 109 and the fifth insulating layer 108.

[0220] In this case, since the second protective layer 112 is set to be spaced apart from the pads IPD, OPD, VSSP, VDDP, TPD, and PD, it can block moisture and other moisture from penetrating along the penetration path of the pads IPD, OPD, VSSP, VDDP, TPD, and PD, and smoothly deposit the touch sensing line TSL.

[0221] Figure 16 This is a cross-sectional view of a display device according to yet another embodiment.

[0222] Reference Figure 16The display device 10_4 according to this embodiment further includes a photoresist residue PRD. The photoresist residue PRD can be... Figure 11 The residue remaining after the photoresist PR was not completely removed.

[0223] Photoresist residue (PRD) can be disposed between the second protective layer 112 and the over-etched area OE. Photoresist residue (PRD) can also be disposed between the sixth insulating layer 109 and the touch buffer layer 181.

[0224] In this case, since the second protective layer 112 is set to be spaced apart from the pads IPD, OPD, VSSP, VDDP, TPD, and PD, it can block moisture and other moisture from penetrating along the penetration path of the pads IPD, OPD, VSSP, VDDP, TPD, and PD, and smoothly deposit the touch sensing line TSL.

[0225] The display device according to various embodiments of this application can be described as follows.

[0226] According to an embodiment of this application, a display device is provided, the display device comprising: a substrate; a panel insulating layer disposed on the substrate and including a plurality of insulating layers; touch pads disposed on the panel insulating layer; a protective layer configured to be spaced apart from the touch pads on the panel insulating layer and comprising an organic material; and an over-etched region disposed between the touch pads and the protective layer, wherein at least a portion of the panel insulating layer is recessed in the over-etched region.

[0227] According to various embodiments of this application, the display device may further include a main region, a sub-region, and a curved region disposed between the main region and the sub-region, wherein the main region includes a display area; and wherein the touch pads, the protective layer, and the over-etched area may be disposed in the sub-region.

[0228] According to various embodiments of this application, the display device may further include a non-display area disposed around the display area, wherein the touch pads, the protective layer, and the over-etched area may be disposed in the non-display area.

[0229] According to various embodiments of this application, the display device may further include a touch sensing line electrically connected to the touch pad, wherein the touch sensing line may overlap with the over-etched area.

[0230] According to various embodiments of this application, the display device may further include: a first pad region, the first pad region including a plurality of input pads and a plurality of output pads; a second pad region, the second pad region including the touch pad and a plurality of signal pads; and a plurality of input connection lines, the plurality of input connection lines electrically connecting the plurality of input pads to the plurality of signal pads, wherein the plurality of input connection lines may overlap with the over-etched region.

[0231] According to various embodiments of this application, the touch sensing line may extend to be spaced apart from the first pad area.

[0232] According to various embodiments of this application, the display device may further include: a light-emitting portion disposed on the protective layer; and a touch portion disposed on the light-emitting portion, wherein the touch portion may include a sensor electrode and a bridging electrode connecting the sensor electrode, and the touch sensing line may include the same material as the sensor electrode.

[0233] According to various embodiments of this application, the display device may further include a second pad area and a printed circuit board mounted on the second pad area, wherein the touch pad is disposed in the second pad area.

[0234] According to various embodiments of this application, the display device may further include a first pad region and a data driving unit mounted on the first pad region, wherein the first pad region includes an input pad and an output pad.

[0235] According to various embodiments of this application, the protective layer may be disposed in an island shape between the input pad and the output pad.

[0236] According to various embodiments of this application, the protective layer can expose the entire area of ​​the touch pad.

[0237] According to various embodiments of this application, the panel insulating layer may include a first insulating layer and a second insulating layer disposed on the first insulating layer, and in the over-etched region, the second insulating layer may penetrate in the thickness direction to expose the first insulating layer.

[0238] According to various embodiments of this application, a portion of the upper part of the first insulating layer exposed by the second insulating layer may be recessed.

[0239] According to various embodiments of this application, the panel insulating layer may include a first insulating layer and a second insulating layer disposed on the first insulating layer, and in the over-etched area, the second insulating layer may cover the first insulating layer.

[0240] According to various embodiments of this application, the panel insulating layer may further include photoresist residue disposed on the panel insulating layer, wherein the photoresist residue may be disposed between the protective layer and the over-etched area.

[0241] According to various embodiments of this application, the upper surface of the second insulating layer in the over-etched region may have a different roughness than the upper surface of the second insulating layer outside the over-etched region.

[0242] According to various embodiments of this application, the side surface of the protective layer may have a gentle slope, and the touch sensing line may extend on the side surface of the protective layer.

[0243] According to an embodiment of this application, a display device is provided, the display device comprising: a substrate; a panel insulating layer disposed on the substrate and including a plurality of insulating layers; pads disposed on the panel insulating layer; connecting lines electrically connected to the pads; and an over-etched region, at least a portion of the panel insulating layer being recessed in the over-etched region, wherein the over-etched region may overlap with the connecting lines.

[0244] According to various embodiments of this application, the pad may be a touch pad, and the connection line may be a touch sensing line electrically connected to the touch pad.

[0245] According to various embodiments of this application, the display device may further include a protective layer disposed on the panel insulating layer, wherein the over-etched area may be disposed between the pads and the protective layer.

[0246] According to various embodiments of this application, the display device may further include a main region, a sub-region, and a curved region disposed between the main region and the sub-region, the main region including a display area, wherein the pads, the protective layer, and the over-etched area may be disposed in the sub-region.

[0247] According to various embodiments of this application, the protective layer can expose the entire area of ​​the pad.

[0248] Although embodiments have been described above with reference to the accompanying drawings, those skilled in the art will understand that the above-described technical configurations can be implemented in other specific forms without altering their technical spirit or essential characteristics. Therefore, it should be understood that the above-described embodiments are illustrative rather than restrictive in all respects. Furthermore, the scope of the embodiments is determined by the appended claims rather than the detailed description. Moreover, the meaning and scope of the claims, as well as all changes or modifications derived from their equivalents, should be interpreted as being included within the scope of the embodiments.

Claims

1. A display device, comprising: substrate; A panel insulating layer, wherein the panel insulating layer is disposed on the substrate and includes a plurality of insulating layers; Touch pads are disposed on the panel insulating layer; A protective layer, the protective layer being spaced apart from the touch pads on the panel insulating layer and comprising an organic material; as well as An over-etched area is provided between the touch pad and the protective layer, and at least a portion of the panel insulating layer is recessed in the over-etched area.

2. The display device according to claim 1, further comprising a main region, a sub-region, and a curved region disposed between the main region and the sub-region, wherein the main region includes a display area; The touch pads, the protective layer, and the over-etched area are located in the sub-region.

3. The display device according to claim 2, further comprising a non-display area disposed around the display area. The touch pads, the protective layer, and the over-etched area are located in the non-display area.

4. The display device of claim 1, further comprising a touch sensing line electrically connected to the touch pad, The touch sensing line overlaps with the over-etched area.

5. The display device according to claim 4, further comprising: A first pad area, the first pad area including multiple input pads and multiple output pads; A second pad area, the second pad area including the touch pad and a plurality of signal pads; and Multiple input connection lines electrically connect the multiple input pads to the multiple signal pads. The multiple input connection lines overlap with the over-etched area.

6. The display device of claim 5, wherein the touch sensing line extends to be spaced apart from the first pad area.

7. The display device according to claim 4, further comprising: The light-emitting part is disposed on the protective layer; and a touch portion provided on the light-emitting part, The touch portion includes sensor electrodes and bridging electrodes connected to the sensor electrodes, and The touch sensing line comprises the same material as the sensor electrodes.

8. The display device according to claim 1, further comprising a second pad area and a printed circuit board mounted on the second pad area, wherein the touch pad is disposed in the second pad area.

9. The display device according to claim 8, further comprising a first pad region and a data driving unit mounted on the first pad region, the first pad region comprising an input pad and an output pad.

10. The display device of claim 9, wherein the protective layer is disposed in an island shape between the input pad and the output pad.

11. The display device of claim 1, wherein the protective layer exposes the entire area of ​​the touch pad.

12. The display device according to claim 1, wherein the panel insulating layer comprises a first insulating layer and a second insulating layer disposed on the first insulating layer, and In the over-etched region, the second insulating layer penetrates in the thickness direction to expose the first insulating layer.

13. The display device of claim 12, wherein a portion of the upper portion of the first insulating layer exposed through the second insulating layer is recessed.

14. The display device according to claim 1, wherein the panel insulating layer comprises a first insulating layer and a second insulating layer disposed on the first insulating layer, and In the over-etched area, the second insulating layer covers the first insulating layer.

15. The display device according to claim 1, further comprising photoresist residue disposed on the insulating layer of the panel. The photoresist residue is disposed between the protective layer and the over-etched area.

16. The display device of claim 14, wherein the upper surface of the second insulating layer in the over-etched region has a different roughness than the upper surface of the second insulating layer outside the over-etched region.

17. The display device of claim 4, wherein the side surface of the protective layer has a gentle slope, and The touch sensing line extends on the side surface of the protective layer.

18. A display device, comprising: substrate; A panel insulating layer, wherein the panel insulating layer is disposed on the substrate and includes a plurality of insulating layers; solder pads are disposed on the panel insulating layer; Connecting wires, the connecting wires being electrically connected to the pads; and In the over-etched area, at least a portion of the panel insulating layer is recessed in the over-etched area. The over-etched area overlaps with the connecting line.

19. The display device of claim 18, wherein the pad is a touch pad and the connection line is a touch sensing line electrically connected to the touch pad.

20. The display device according to claim 19, further comprising a protective layer disposed on the panel insulating layer, The over-etched area is located between the pad and the protective layer.

21. The display device according to claim 20, further comprising a main region, a sub-region, and a curved region disposed between the main region and the sub-region, wherein the main region includes a display area. The pads, the protective layer, and the over-etched area are located in the sub-region.

22. The display device of claim 21, wherein the protective layer exposes the entire area of ​​the pads.

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