Display device and electronic device

Abstract

This invention discloses a display device and an electronic device. The display device includes: a first electrode defining a plurality of first openings; a plurality of first light-emitting elements, each in the plurality of first openings and configured to emit light of a first color; a second electrode defining a plurality of second openings; a plurality of second light-emitting elements, each in the plurality of second openings and configured to emit light of a second color; a third electrode defining a plurality of third openings; and a plurality of third light-emitting elements, each in the plurality of third openings and configured to emit light of a third color, wherein the first electrode, the second electrode, and the third electrode are separated from each other and electrically disconnected.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0195910, filed on December 24, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to display devices and electronic devices. Background Technology

[0003] Recently, with the increasing interest in information display, research and development of display devices are ongoing. Summary of the Invention

[0004] This disclosure provides a display device and an electronic device capable of independently providing a cathode voltage for each pixel.

[0005] A display device according to an embodiment of the present disclosure includes: a first electrode defining a plurality of first openings; a plurality of first light-emitting elements, each in the plurality of first openings and configured to emit light of a first color; a second electrode defining a plurality of second openings; a plurality of second light-emitting elements, each in the plurality of second openings and configured to emit light of a second color; a third electrode defining a plurality of third openings; and a plurality of third light-emitting elements, each in the plurality of third openings and configured to emit light of a third color, wherein the first electrode, the second electrode, and the third electrode are separated from each other and electrically disconnected.

[0006] A plurality of first light-emitting elements may be configured to receive a first voltage through a first electrode, wherein a plurality of second light-emitting elements are configured to receive a second voltage through a second electrode, and wherein a plurality of third light-emitting elements are configured to receive a third voltage through a third electrode.

[0007] In a planar diagram, there may be no electrodes between the first electrode and the second electrode, or between the second electrode and the third electrode.

[0008] In the plan view, the first electrode, the second electrode, and the third electrode can be arranged sequentially along a first direction and extend in a second direction intersecting the first direction, wherein a plurality of first openings, a plurality of second openings, and a plurality of third openings are arranged along the second direction, and wherein, in the plan view, the first electrode surrounds only a plurality of first light-emitting elements, the second electrode surrounds only a plurality of second light-emitting elements, and the third electrode surrounds only a plurality of third light-emitting elements.

[0009] In the plan view, the first electrode, the second electrode, and the third electrode can be arranged sequentially and repeatedly along the first direction and extend in the second direction intersecting the first direction, wherein a plurality of first openings, a plurality of second openings, and a plurality of third openings are arranged along the second direction.

[0010] The first light-emitting element, the second light-emitting element, and the third light-emitting element may each include an anode electrode, a light-emitting layer above the anode electrode, and a cathode electrode above the light-emitting layer, wherein the first electrode contacts the cathode electrode of the first light-emitting element, the second electrode contacts the cathode electrode of the second light-emitting element, and the third electrode contacts the cathode electrode of the third light-emitting element. The display device further includes: an encapsulation layer located above the cathode electrode at the first, second, and third openings; an organic layer located above the encapsulation layer and covering it; and a pixel defining layer located above the anode electrode and defining a plurality of openings corresponding to the first, second, and third openings, wherein the organic layer fills between the first, second, and third electrodes and contacts the pixel defining layer between the first, second, and third electrodes.

[0011] Multiple first light-emitting elements can correspond one-to-one with multiple first openings, wherein multiple second light-emitting elements correspond one-to-one with multiple second openings, and wherein multiple third light-emitting elements correspond one-to-one with multiple third openings.

[0012] The first light-emitting element, the second light-emitting element, and the third light-emitting element may each include an organic light-emitting diode.

[0013] A display device according to an embodiment of the present disclosure includes: a first electrode defining a plurality of first openings; a plurality of first light-emitting elements respectively in the plurality of first openings and configured to emit light of a first color; a second electrode defining a plurality of second openings and a plurality of third openings and electrically separated from the first electrode; a plurality of second light-emitting elements respectively in the plurality of second openings and configured to emit light of a second color; and a plurality of third light-emitting elements respectively in the plurality of third openings and configured to emit light of a third color.

[0014] Multiple first light-emitting elements can emit blue light, multiple second light-emitting elements emit red light, and multiple third light-emitting elements emit green light.

[0015] In the plan view, the first electrode and the second electrode may be spaced apart from each other in a first direction and extend in a second direction intersecting the first direction, wherein a plurality of first openings, a plurality of second openings and a plurality of third openings are arranged along the second direction.

[0016] The first electrode and the second electrode may be arranged alternately and repeatedly along a first direction, wherein the first electrode is connected to another first electrode at one end, and wherein the second electrode is connected to another second electrode at the other end.

[0017] Multiple second openings and multiple third openings can be arranged alternately along the second direction.

[0018] The first light-emitting element, the second light-emitting element, and the third light-emitting element may each include an anode electrode, a light-emitting layer above the anode electrode, and a cathode electrode above the light-emitting layer, wherein the first electrode contacts the cathode electrode of the first light-emitting element, wherein the second electrode contacts the cathode electrodes of the second and third light-emitting elements, and wherein the display device further includes: a pixel defining layer above the anode electrode and defining a plurality of openings corresponding to the first opening, the second opening, and the third opening; an encapsulation layer above the cathode electrode at the first opening, the second opening, and the third opening; and an organic layer above the encapsulation layer and covering the encapsulation layer, wherein the organic layer fills between the first electrode and the second electrode and contacts the pixel defining layer between the first electrode and the second electrode.

[0019] An electronic device according to an embodiment of the present disclosure includes: a processor configured to provide image data; and a display device configured to display an image based on the image data, and includes: a first electrode defining a plurality of first openings; a plurality of first light-emitting elements respectively in the plurality of first openings and configured to emit light of a first color; a second electrode defining a plurality of second openings and electrically separated from the first electrode; and a plurality of second light-emitting elements respectively in the plurality of second openings and configured to emit light of a second color.

[0020] The first light-emitting element and the second light-emitting element may each include an anode electrode, a light-emitting layer above the anode electrode, and a cathode electrode above the light-emitting layer, wherein the first electrode contacts the cathode electrode of the first light-emitting element, wherein the second electrode contacts the cathode electrode of the second light-emitting element, and wherein the display device further includes: a pixel defining layer above the anode electrode and defining a plurality of openings corresponding to the first opening and the second opening; an encapsulation layer above the cathode electrode at the first opening and the second opening; and an organic layer above the encapsulation layer, covering the encapsulation layer, filling between the first electrode and the second electrode, and contacting the pixel defining layer between the first electrode and the second electrode.

[0021] The display device may further include: a third electrode defining a plurality of third openings and electrically separated from the first electrode and the second electrode; and a plurality of third light-emitting elements, each in the plurality of third openings and configured to emit light of a third color, wherein, in a plan view, the first electrode, the second electrode and the third electrode are arranged sequentially along a first direction and extend in a second direction intersecting the first direction, and wherein the plurality of first openings, the plurality of second openings and the plurality of third openings are arranged along the second direction.

[0022] The display device may further include: a plurality of third light-emitting elements, each in a plurality of third openings defined in a second electrode, and configured to emit green light, wherein a plurality of first light-emitting elements emit blue light, and wherein a plurality of second light-emitting elements emit red light.

[0023] The display device may further include: a plurality of third light-emitting elements, each in a plurality of third openings defined in a second electrode, and configured to emit light of a third color, wherein, in a plan view, the first electrode and the second electrode are spaced apart from each other in a first direction and arranged alternately and repeatedly, and extend in a second direction intersecting the first direction, wherein the plurality of first openings, the plurality of second openings and the plurality of third openings are arranged along the second direction, wherein the first electrode is connected at one end to another first electrode, and wherein the second electrode is connected at the other end to another second electrode.

[0024] The display device may further include: a plurality of third light-emitting elements, each in a plurality of third openings defined in a second electrode, and configured to emit light of a third color, wherein, in a plan view, the first electrode and the second electrode are spaced apart from each other in a first direction and extend in a second direction intersecting the first direction, and wherein the plurality of first openings, the plurality of second openings and the plurality of third openings are arranged along the second direction, and the plurality of second openings and the plurality of third openings are arranged alternately along the second direction.

[0025] In the display device and electronic device according to embodiments of the present disclosure, a first electrode (or first partition wall) surrounding a first light-emitting element and a second electrode (or second partition wall) surrounding a second light-emitting element (e.g., in a plan view) are separated from each other, and different voltages (or cathode voltages) can be supplied to the first light-emitting element and the second light-emitting element. Accordingly, power consumption can be reduced or improved.

[0026] The aspects of the embodiments disclosed herein are not limited to those described or shown above, and many more aspects of the disclosure will be described in detail below. Attached Figure Description

[0027] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0028] Figure 2 The illustration includes Figure 1 A block diagram of one or more embodiments of subpixels in a display device.

[0029] Figure 3 It is a diagram. Figure 2 Circuit diagram of one or more embodiments of the sub-pixel.

[0030] Figure 4 The illustration includes Figure 1 A plan view of one or more embodiments of a display unit in a display device.

[0031] Figure 5 and Figure 6 It is a diagram. Figure 4 A plan view of one or more embodiments of a display panel.

[0032] Figure 7 The diagram is along Figure 5 A cross-sectional view of one or more embodiments of the display panel along line A-A'.

[0033] Figure 8 The diagram is along Figure 5 A cross-sectional view of one or more embodiments of the display panel with line B-B'.

[0034] Figure 9 yes Figure 8 A magnified view of region AA.

[0035] Figure 10 The diagram is along Figure 5 A cross-sectional view of one or more embodiments of the display panel with line C-C'.

[0036] Figure 11 and Figure 12 It is a diagram. Figure 4 A plan view of one or more other embodiments of the display panel.

[0037] Figure 13 The diagram is along Figure 11 A cross-sectional view of one or more embodiments of the display panel with line D-D'.

[0038] Figure 14 The diagram is along Figure 11 A cross-sectional view of one or more embodiments of the display panel with line E-E'.

[0039] Figures 15A to 15D It is a diagram. Figure 4 A plan view of one or more other embodiments of the display panel.

[0040] Figure 15E and Figure 15F The diagram is along Figure 15C A cross-sectional view of one or more embodiments of the display panel with line K-K'.

[0041] Figures 16A to 16I It is a diagram. Figure 4 A plan view of one or more other embodiments of the display panel.

[0042] Figures 17 to 24 This is a cross-sectional view of the process operation of a method for manufacturing a display device according to one or more embodiments.

[0043] Figure 25 It is a block diagram of an electronic device according to one or more embodiments.

[0044] Figure 26 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0045] Aspects of some embodiments of this disclosure and their implementation methods can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Accordingly, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or unnecessary for a person of ordinary skill in the art to fully understand aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore their repeated description may be omitted.

[0046] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments illustrated herein. The terms "can," "may," or "may not" are used in the description of embodiments to correspond to one or more embodiments of this disclosure.

[0047] Those skilled in the art will understand that, when considered in its entirety, various suitable features of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically associated with each other in a variety of suitable ways, and that the various embodiments may be implemented independently of each other or in any suitable combination with one another, unless otherwise stated or implied.

[0048] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, this disclosure is not limited to the dimensions and thicknesses of elements shown in the drawings arbitrarily for ease of description. Additionally, the use of crosshairs and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scale, commonalities between illustrated elements, and / or any other characteristics, properties, or characteristics of the elements.

[0049] Various embodiments are described herein with reference to cross-sectional diagrams, which are schematic illustrations of the structures of the embodiments and / or intermediates. Therefore, variations in the shape of the diagrams are expected, for example, due to manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of the illustrated elements, layers, or regions, but rather include deviations in shape due to, for example, manufacturing processes.

[0050] For example, the injection zone illustrated as rectangular typically has arcuate or curved features at its edges and / or a gradient of injectant concentration, rather than a binary change from the injection zone to the non-injection zone. Similarly, the burial zone formed by injection can result in some injection in the zone between the burial zone and the surface through which the injection occurs.

[0051] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “above,” “higher,” “upper side,” and “side” (e.g., as in “sidewall”) are used herein to describe the relationship between one element or feature and another element(s) as shown in the accompanying figures. It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “below” other elements or features will then be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both upper and lower orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged “on” a second part, this indicates that the first part is arranged above or below the second part based on the direction of gravity, and not limited to its upper side.

[0052] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting the portion of the object from the side. The terms "overlapping" or "overlapping" mean that the first object may be above, below, or to the side of the second object, and vice versa. Additionally, the term "overlapping" can include stacking, facing, extending over, covering, or partially covering, or any other suitable term that will be understood and appreciated by one of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separated from," "set to one side," or "offset from," and any other suitable equivalent that will be understood and appreciated by one of ordinary skill in the art. The term "facing" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can be understood as indirectly opposite each other, although still facing each other.

[0053] It will be understood that when a component, layer, area, or part (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as "formed on," "on," "connected to," or "(operably, functionally, or communicatively) coupled to" another component, layer, area, or part," it can be directly formed on, directly connected to, or directly coupled to that other component, layer, area, or part, or indirectly formed on, indirectly connected to, or indirectly coupled to that other component, layer, area, or part, such that one or more intervening components, layers, areas, or parts may exist. Furthermore, this can be collectively referred to as direct or indirect connection or coupling, and integral or non-integral connection or coupling. For example, when a layer, area, or component is referred to as "electrically connected" or "electrically coupled" to another layer, area, or component, it can be directly electrically connected or coupled to that other layer, area, or component, or there may be one or more intervening layers, areas, or components. One or more intervening components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Accordingly, "connection" is not limited to the connections illustrated in the drawings or detailed description, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression "connection" indicates an electrical connection, and "direct connection / direct coupling" or "directly on" means that a component is directly connected or directly coupled to another component or directly on another component, without any intervening components.

[0054] Furthermore, in this specification, when a portion of a layer, film, region, or plate is formed on another portion, the forming direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, or plate is formed "below" another portion, this includes not only the case where the portion is "directly" "below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing the relationship between components, such as "between" and "directly between," or "adjacent to" and "directly adjacent to," can be interpreted in a similar way. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or layers.

[0055] For the purposes of this disclosure, expressions such as “at least one of,” “any one of,” or “one or more of” modify the entire list of elements when placed after the list of elements, but do not modify any individual element in the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of two or more of only X, only Y, only Z, X, Y, and Z, such as, for example, XYZ, XY, YZ, and XZ or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or,” and the term “and / or” includes any and all combinations of one or more of the items in the relevant list. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases modify the entire list of elements when placed before / after the list of elements, but do not modify any individual element in the list. Unless otherwise specified, when “C to D” is stated, it means above C and below D.

[0056] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or superiority, and are used only to distinguish one element, component, area, layer, or section from another. Therefore, the first element, component, area, layer, or section described below may be referred to as the second element, component, area, layer, or section without departing from the spirit and scope of this disclosure. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or sets of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively mean “first category (or first set),” “second category (or second set),” etc.

[0057] In the example, the x, y, and / or z directions are not limited to directions corresponding to the three axes of a Cartesian coordinate system and can be interpreted broadly. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first, second, and / or third directions.

[0058] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, the singular form “a” is also intended to include the plural form, and the plural form is also intended to include the singular form, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “having,” and “including” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0059] When one or more embodiments can be implemented differently, a particular process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0060] As used herein, the terms “substantially,” “approximately,” “approximately,” and similar terms are used as terms of approximation rather than terms of degree and are intended to take into account the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of ±5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” or “approximately” as used herein includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, “approximately” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, the word “may” is used when describing embodiments of this disclosure to refer to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that would be tolerated by one of ordinary skill in the art. Other expressions may also be expressions from which “substantially” has been omitted.

[0061] In some embodiments, well-known structures and arrangements may be described and illustrated in the accompanying drawings in relation to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, storage elements, wire connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware may be programmed and controlled by software to perform the various functions discussed herein, optionally driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and processors performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, in some embodiments, blocks, units, and / or modules may be physically divided into two or more interacting individual blocks, units, and / or modules without departing from the scope of this disclosure. Additionally, in some embodiments, blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules without departing from the scope of this disclosure.

[0062] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant technology and / or this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0063] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0064] refer to Figure 1 The display device 100 may include a display unit 110 (or a display panel), a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0065] The display unit 110 includes a sub-pixel SP. The sub-pixel SP can be connected to the gate driver 120 via the first gate line GL1 to the m-th gate line GLm, where m is a positive integer. The sub-pixel SP can be connected to the data driver 130 via the first data line DL1 to the n-th data line DLn, where n is a positive integer.

[0066] Each of the subpixels SP may include at least one light-emitting element configured to generate light. Each of the subpixels SP can generate light of a corresponding color such as red, green, blue, cyan, magenta, or yellow. Two or more subpixels in the subpixel SP can constitute a pixel PXL. For example, as Figure 1 As shown, three sub-pixels can form pixel PXL.

[0067] The gate driver 120 is connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. The gate driver 120 can output gate signals to the first gate lines GL1 to m-th gate lines GLm in response to a gate control signal GCS. In one or more embodiments, the gate control signal GCS may include a start signal indicating the start of each frame and a horizontal synchronization signal for timing-synchronizing the output of gate signals with the applied data signals, etc.

[0068] In one or more embodiments, first light emission control lines EL1 to m-th light emission control lines ELm connected to the sub-pixels SP in the row direction may be further provided. In this case, the gate driver 120 may include a light emission control driver configured to control the first light emission control lines EL1 to m-th light emission control lines ELm, and the light emission control driver may operate according to the control of the controller 150.

[0069] The gate driver 120 may be located on one side of the display unit 110. However, the embodiments are not limited to this. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be located on one side of the display unit 110 and on the opposite side of the display unit 110. Therefore, the gate driver 120 may be located around the display unit 110 in various forms.

[0070] Data driver 130 is connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 receives image data DATA and data control signal DCS from controller 150. Data driver 130 operates in response to data control signal DCS. In one or more embodiments, data control signal DCS may include source start pulse, source shift clock, and source output enable signal, etc.

[0071] The data driver 130 can use a voltage supplied from the voltage generator 140 to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data lines DLn. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, a data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Accordingly, the corresponding sub-pixel SP can generate light corresponding to the data signal, and the image is displayed on the display unit 110.

[0072] In one or more embodiments, the gate driver 120 and the data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0073] Voltage generator 140 can operate in response to a voltage control signal VCS provided from controller 150. Voltage generator 140 is configured to generate a voltage and provide the generated voltage to components of display device 100. For example, voltage generator 140 can be configured to generate a voltage by receiving an input voltage from outside display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0074] Voltage generator 140 can generate a first power voltage VDD and a second power voltage VSS, and the first power voltage VDD and the second power voltage VSS can be provided to sub-pixels SP. The first power voltage VDD can have a relatively high voltage level, and the second power voltage VSS can have a lower voltage level than the first power voltage VDD. In one or more other embodiments, the first power voltage VDD or the second power voltage VSS can be provided by an external device of display device 100.

[0075] Voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage applied to sub-pixel SP. For example, in a sensing operation for sensing the electrical characteristics of the transistor and / or light-emitting element of sub-pixel SP, a reference voltage can be applied to the first data line DL1 to the nth data line DLn, and voltage generator 140 can generate the reference voltage.

[0076] The controller 150 controls various operations of the display device 100. The controller 150 receives input image data IMG and control signal CTRL from the outside. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0077] The controller 150 can convert input image data IMG into a format suitable for display device 100 or display unit 110, and can output image data DATA. In one or more embodiments, the controller 150 can output image data DATA by arranging the input image data IMG into sub-pixels SP in rows.

[0078] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted in a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 can be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 can be functionally distinct components within the driver integrated circuit (DIC). In one or more other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 can be provided as a component separate from the driver integrated circuit (DIC).

[0079] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense the ambient temperature and generate temperature data TEP indicating the sensed temperature. In one or more embodiments, the temperature sensor 160 may be disposed adjacent to the display unit 110 and / or the driver integrated circuit DIC.

[0080] The controller 150 can control various operations of the display device 100 in response to temperature data TEP. In one or more embodiments, the controller 150 can adjust the brightness of the image output from the display unit 110 in response to the temperature data TEP. For example, the controller 150 can adjust the data signal and the first power voltage VDD and the second power voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0081] Figure 2 The illustration includes Figure 1 A block diagram of one or more embodiments of subpixels in a display device. Figure 2 In Figure 1 In the sub-pixels SP, the sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0082] refer to Figure 2 Subpixel SPij may include subpixel circuit PXC and light-emitting element LD.

[0083] The light-emitting element (LD) is connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN is the transmission... Figure 1 The first power voltage node VDD, and the second power voltage node VSSN are the transmission nodes. Figure 1 The node of the second power voltage VSS (or cathode voltage).

[0084] The anode electrode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via the sub-pixel circuit PXC, and the cathode electrode CE of the light-emitting element LD can be coupled to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit PXC.

[0085] The sub-pixel circuit PXC can be connected to Figure 1 Among the first gate line GL1 to the m-th gate line GLm, the i-th gate line GLi, Figure 1 The first light emission control line EL1 to the m-th light emission control line ELm, including the i-th light emission control line ELi and Figure 1 The j-th data line DLj is one of the first data lines DL1 to the nth data line DLn. The sub-pixel circuit PXC is configured to control the light-emitting element LD according to the signals received through these signal lines.

[0086] The sub-pixel circuit PXC can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In one or more embodiments, as Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit PXC can operate in response to gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. Therefore, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit PXC can operate in response to gate signals received via the corresponding sub-gate lines.

[0087] The sub-pixel circuit PXC can operate in response to an emission control signal received via the i-th emission control line ELi. In one or more embodiments, the i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit PXC can operate in response to an emission control signal received via the corresponding sub-emission control line.

[0088] The sub-pixel circuit PXC can receive a data signal via the j-th data line DLj. The sub-pixel circuit PXC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. In response to a light emission control signal received via the i-th light emission control line ELi, the sub-pixel circuit PXC can control the current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN based on the stored voltage. Accordingly, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0089] Figure 3 It is a diagram. Figure 2 Circuit diagram of one or more embodiments of the sub-pixel.

[0090] refer to Figure 3 Subpixel SPij may include subpixel circuit PXC and light-emitting element LD.

[0091] The sub-pixel circuit PXC can be connected to the i-th gate line GLi', the i-th light emission control line ELi', and the j-th data line DLj. Figure 2 Compared to the i-th gate line GLi, the i-th gate line GLi' can further include a third sub-gate line SGL3. With Figure 2 Compared to the i-th light emission control line ELi, the i-th light emission control line ELi' may include a first sub-light emission control line SEL1 and a second sub-light emission control line SEL2.

[0092] The sub-pixel circuit PXC may include a first transistor T1 to a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0093] The first transistor T1 is connected between the first power voltage node VDDN and the first node N1. The gate (or gate electrode) of the first transistor T1 is connected to the second node N2, so that the first transistor T1 can be turned on according to the voltage level of the second node N2. The first transistor T1 can be referred to as the driving transistor.

[0094] The second transistor T2 is connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 is connected to the first sub-gate line SGL1, so that the second transistor T2 can be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 can be referred to as a switching transistor.

[0095] The third transistor T3 is connected between the first node N1 and the second node N2. The gate of the third transistor T3 is connected to the second subgate line SGL2, so that the third transistor T3 can be turned on in response to the gate signal of the second subgate line SGL2.

[0096] The fourth transistor T4 is connected between the first node N1 and the anode electrode AE ​​of the light-emitting element LD. The gate of the fourth transistor T4 is connected to the second sub-light-emitting control line SEL2, so that the fourth transistor T4 can be turned on in response to the light-emitting control signal of the second sub-light-emitting control line SEL2.

[0097] The fifth transistor T5 is connected between the anode electrode AE ​​of the light-emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN is configured to transmit the initialization voltage. In one or more embodiments, the initialization voltage can be supplied by… Figure 1 The voltage is provided by voltage generator 140. In one or more other embodiments, the initialization voltage may be provided by an external device of display device 100. The gate of the fifth transistor T5 is connected to the third subgate line SGL3, such that the fifth transistor T5 can be turned on in response to the gate signal of the third subgate line SGL3.

[0098] The sixth transistor T6 is connected between the first power voltage node VDDN and the first transistor T1. The gate of the sixth transistor T6 is connected to the first sub-light emission control line SEL1, so that the sixth transistor T6 can be turned on in response to the light emission control signal of the first sub-light emission control line SEL1.

[0099] The first capacitor C1 is connected between the second transistor T2 and the second node N2. The second capacitor C2 is connected between the first power voltage node VDDN and the second node N2.

[0100] Therefore, the sub-pixel circuit PXC may include first transistors T1 to sixth transistors T6, a first capacitor C1, and a second capacitor C2. However, the embodiments are not limited thereto. The sub-pixel circuit PXC can be implemented as any of various forms of circuits including multiple transistors and one or more capacitors. For example, the sub-pixel circuit PXC may include two transistors and one capacitor. Depending on the embodiment of the sub-pixel circuit PXC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-light emission control lines included in the i-th light emission control line ELi' can be varied.

[0101] The first transistor T1 through the sixth transistor T6 can be P-type transistors. Each of the first transistor T1 through the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). However, the embodiments are not limited thereto. For example, at least one of the first transistor T1 through the sixth transistor T6 can be replaced by an N-type transistor.

[0102] In one or more embodiments, the first transistor T1 to the sixth transistor T6 may include amorphous silicon semiconductor, monocrystalline silicon, polycrystalline silicon semiconductor, or oxide semiconductor, etc.

[0103] The light-emitting element (LD) may include an anode electrode AE, a cathode electrode CE, and a light-emitting layer. The light-emitting layer may be located between the anode electrode AE ​​and the cathode electrode CE. After the data signal transmitted via the j-th data line DLj is reflected in the voltage of the second node N2, the fourth transistor T4 and the sixth transistor T6 can be turned on when the light-emitting control signals of the first sub-light-emitting control line SEL1 and the second sub-light-emitting control line SEL2 are enabled to a low level. The first transistor T1 can be turned on according to the voltage of the second node N2, and therefore current can flow from the first power voltage node VDDN to the second power voltage node VSSN. The light-emitting element LD emits light according to the amount of current flowing through it.

[0104] Figure 4 The illustration includes Figure 1 A plan view of one or more embodiments of a display unit in a display device.

[0105] refer to Figure 4 ,for Figure 1 The display panel DP of one or more embodiments of the display unit 110 may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA (e.g., in a plan view) is located around the display area DA.

[0106] The display panel (DP) can include the base layer (BSL), subpixels (SP), and pads (PD).

[0107] When the display panel (DP) is used as a display for head-mounted displays (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, or augmented reality (AR) devices, the display panel (DP) can be placed very close to the user's eyes. In this case, subpixels (SPs) with relatively high integration are required. To improve the integration of the subpixel SPs, the substrate layer (BSL) can be provided as a silicon substrate. The subpixel SPs and / or the display panel (DP) can be formed on the substrate layer (BSL) which is a silicon substrate, but are not limited to this.

[0108] Subpixels SP are located in the display area DA and on the substrate layer BSL. Subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments are not limited to this. For example, subpixels SP can be arranged in a sawtooth shape along the first direction DR1 and the second direction DR2. For example, subpixels SP can be arranged in a pentiline shape. ® Pentyl arrangement ® (This is a registered trademark of Samsung Display Co., Ltd., Republic of Korea). The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction. Two or more subpixels in subpixel SP can constitute a pixel PXL.

[0109] The components used to control subpixels SP can be located in the non-display area NDA, on the base layer BSL. For example, such as Figure 1 The wiring connecting the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn to the sub-pixel SP can be located in the non-display area NDA.

[0110] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 may be integrated into the non-display area NDA of the display panel DP. In one or more embodiments, Figure 1 The gate driver 120 can be mounted on the display panel DP and can be located in the non-display area NDA. In one or more other embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In one or more embodiments, the temperature sensor 160 can be located in the non-display area NDA to sense the temperature of the display panel DP.

[0111] The pad PD is located in the non-display area NDA, on the base layer BSL. The pad PD can be electrically connected to the sub-pixel SP via wiring. For example, the pad PD can be connected via... Figure 1 The first data line DL1 to the nth data line DLn are connected to the sub-pixel SP.

[0112] The pads PD can bond the display panel DP to the display device 100 (see...). Figure 1 Other components. In one or more embodiments, the voltages and signals required for the operation of components included in the display panel DP can be transmitted from the pads PD via... Figure 1 The driver integrated circuit (DIC) is provided. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit (DIC) via the pad PD. For example, a first power voltage VDD and a second power voltage VSS can be received from the driver integrated circuit (DIC) via the pad PD. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via the pad PD.

[0113] In one or more embodiments, the display area DA can have various shapes. The display area DA can have a closed loop shape including straight edges and / or curved edges. For example, the display area DA can have shapes such as polygons, circles, semicircles, and ellipses.

[0114] In one or more embodiments, the display panel DP may have a flat display surface. In one or more other embodiments, the display panel DP may have a display surface that is at least partially curved. In one or more embodiments, the display panel DP may be bendable, foldable, or rollable. In this case, the display panel DP and / or the substrate layer BSL may comprise a material with flexible properties.

[0115] Figure 5 and Figure 6 It is a diagram. Figure 4 A plan view of one or more embodiments of a display panel. Figure 5 In the image, first sub-pixels SP1 to third sub-pixels SP3 and first partition walls SW1 to third partition walls SW3 are shown in a portion of the display panel DP, and... Figure 6 The image shows the first partition wall SW1 to the third partition wall SW3 in the display panel DP.

[0116] refer to Figure 5 The first partition wall SW1 (or the first electrode) includes a first partition wall opening OPS1 (or a first opening), and the first light-emitting element LD1 of the first sub-pixel SP1 may be located in each of the first partition wall openings OPS1. The first light-emitting element LD1 may be located in each of the first partition wall openings OPS1, and the first light-emitting element LD1 may correspond to the first partition wall opening OPS1 (e.g., a one-to-one correspondence). For example, the first partition wall SW1 may extend in a second direction DR2, and the first partition wall openings OPS1 may be arranged along the second direction DR2. In a plan view, the first partition wall SW1 may surround only the first light-emitting element LD1. The first light-emitting element LD1 may emit light of a first color (e.g., blue). The cathode electrode of the first light-emitting element LD1 may be electrically connected to the first partition wall SW1 (see...). Figure 7 and Figure 8 Voltage (e.g., applied to) Figure 2 and Figure 3 The second power voltage node VSSN Figure 1 The second electrical voltage (VSS) can be applied to the cathode electrode of the first light-emitting element LD1 through the first partition wall SW1.

[0117] The second partition wall SW2 (or the second electrode) includes a second partition wall opening OPS2 (or a second opening), and the second light-emitting element LD2 of the second sub-pixel SP2 may be located in each of the second partition wall openings OPS2. The second light-emitting element LD2 may be located in each of the second partition wall openings OPS2, and the second light-emitting element LD2 may correspond one-to-one with the second partition wall opening OPS2. For example, the second partition wall SW2 may be spaced apart from the first partition wall SW1 in the first direction DR1, and may be separated from or electrically insulated (or disconnected) from the first partition wall SW1. No electrode may be located between the first partition wall SW1 and the second partition wall SW2, but this disclosure is not limited thereto. The second partition wall SW2 may extend in the second direction DR2, and the second partition wall opening OPS2 may be arranged along the second direction DR2. In a plan view, the second partition wall SW2 may surround the second light-emitting element LD2. The second light-emitting element LD2 may emit light of a second color (e.g., red). The cathode electrode of the second light-emitting element LD2 may be electrically connected to the second partition wall SW2 (see...). Figure 7 and Figure 8 Voltage can be applied to the cathode electrode of the second light-emitting element LD2 through the second partition wall SW2.

[0118] The third partition wall SW3 (or the third electrode) includes a third partition wall opening OPS3 (or a third opening), and the third light-emitting element LD3 of the third sub-pixel SP3 may be located in each of the third partition wall openings OPS3. A third light-emitting element LD3 may be located in each of the third partition wall openings OPS3, and the third light-emitting element LD3 may correspond one-to-one with a third partition wall opening OPS3. For example, the third partition wall SW3 may be spaced apart from the second partition wall SW2 in the first direction DR1, and may be separated from or electrically insulated from the second partition wall SW2 (and the first partition wall SW1). No electrode may be located between the second partition wall SW2 and the third partition wall SW3, but this disclosure is not limited thereto. The third partition wall SW3 extends in the second direction DR2, and the third partition wall opening OPS3 may be arranged along the second direction DR2. In a plan view, the third partition wall SW3 may surround the third light-emitting element LD3. The third light-emitting element LD3 may emit light of a third color (e.g., green). The cathode electrode of the third light-emitting element LD3 may be electrically connected to the third partition wall SW3 (see...). Figure 7 and Figure 8 Voltage can be applied to the cathode electrode of the third light-emitting element LD3 through the third partition wall SW3.

[0119] like Figure 6 As shown, the first partition wall SW1, the second partition wall SW2 and the third partition wall SW3 can be arranged alternately and repeatedly along the first direction DR1.

[0120] Corresponding to the arrangement of the first light-emitting elements LD1 to the third light-emitting elements LD3, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be arranged sequentially along the first direction DR1. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be arranged repeatedly along the second direction DR2. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can constitute a pixel PXL.

[0121] The first sub-pixel SP1 may include a first light-emitting region EMA1. The first light-emitting region EMA1 may be a region emitting light from the first light-emitting element LD1 (or light-emitting layer) of the first sub-pixel SP1, and may correspond to the first partition wall opening OPS1 of the first partition wall SW1. The second sub-pixel SP2 may include a second light-emitting region EMA2. The second light-emitting region EMA2 may be a region emitting light from the second light-emitting element LD2 of the second sub-pixel SP2, and may correspond to the second partition wall opening OPS2 of the second partition wall SW2. The third sub-pixel SP3 may include a third light-emitting region EMA3. The third light-emitting region EMA3 may be a region emitting light from the third light-emitting element LD3 of the third sub-pixel SP3, and may correspond to the third partition wall opening OPS3 of the third partition wall SW3. The periphery of the first light-emitting region EMA1 to the third light-emitting region EMA3 may be a non-light-emitting region NEA.

[0122] In one or more embodiments, different voltages (or voltages with different voltage levels) may be applied to the first partition wall SW1, the second partition wall SW2, and the third partition wall SW3. Each of the voltages may be applied to... Figure 2 and Figure 3 The second power voltage node VSSN Figure 1 The second electrical voltage VSS. For reference, the driving voltages for the first light-emitting element LD1 to the third light-emitting element LD3 to emit light can be different from each other. For example, the driving voltage of the first light-emitting element LD1 can be approximately 3.5V, the driving voltage of the second light-emitting element LD2 can be approximately 3.8V, and the driving voltage of the third light-emitting element LD3 can be approximately 3.9V. Depending on the driving voltages of the first light-emitting element LD1 to the third light-emitting element LD3, the voltages applied to the first partition wall SW1 to the third partition wall SW3 can be different from each other. However, this disclosure is not limited thereto. For example, the voltage applied to the second partition wall SW2 can be different from the voltage applied to the first partition wall SW1, and the voltage applied to the third partition wall SW3 can be the same as the voltage applied to the second partition wall SW2.

[0123] As described above, the first partition wall SW1 to the third partition wall SW3 can be separated from each other, and different voltages can be supplied to the first light-emitting element LD1 to the third light-emitting element LD3 through the first partition wall SW1 to the third partition wall SW3. The voltage can be supplied to the first light-emitting element LD1 to the third light-emitting element LD3 in a more optimized manner, thereby reducing or improving power consumption.

[0124] Figure 7 The diagram is along Figure 5 A cross-sectional view of one or more embodiments of the display panel along line A-A'. Figure 8 The diagram is along Figure 5 A cross-sectional view of one or more embodiments of the display panel with line B-B'. Figure 9 yes Figure 8 A magnified view of region AA. Figure 10 The diagram is along Figure 5 A cross-sectional view of one or more embodiments of the display panel with line C-C'. Figure 7 and Figure 10 The structure from the basement layer BSL to the partition wall SW is shown, and Figure 8 The structure above the partition wall SW is further shown.

[0125] refer to Figures 5 to 10 The substrate layer (BSL) may include a glass substrate. In one or more embodiments, the substrate layer (BSL) may include a polyimide (PI) substrate. In one or more embodiments, the substrate layer (BSL) may include a silicon wafer substrate formed using semiconductor processes. The substrate layer (BSL) may include, but is not limited to, semiconductor materials suitable for forming circuit elements.

[0126] The pixel circuit layer (PCL) is located on the substrate layer (BSL) (as used herein, "located on" can mean "above"). The substrate layer (BSL) and / or the pixel circuit layer (PCL) may include an insulating layer and conductive patterns located between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may form sub-pixel circuits (PXCs). Sub-pixel circuits (PXCs) may be included in corresponding sub-pixels (SPs). For example, sub-pixel circuits (PXCs) may include a first sub-pixel circuit (PXC1) for a first sub-pixel (SP1), a second sub-pixel circuit (PXC2) for a second sub-pixel (SP2), and a third sub-pixel circuit (PXC3) for a third sub-pixel (SP3).

[0127] Each of the first sub-pixel circuits PXC1 to the third sub-pixel circuits PXC3 may include a plurality of transistors and one or more capacitors. Each transistor may include a semiconductor portion comprising a source region, a drain region, and a channel region, and a gate electrode superimposed on the semiconductor portion. In one or more embodiments, when the substrate layer BSL is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other on a third direction DR3 with an insulating layer interposed therebetween. In one or more embodiments, when the substrate layer BSL is provided as a silicon substrate, the semiconductor portion is included in the substrate layer BSL, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL, but is not limited thereto.

[0128] The anode electrode AE ​​can be located on the pixel circuit layer PCL. The anode electrode AE ​​can contact the sub-pixel circuits PXC of the pixel circuit layer PCL. The anode electrode AE ​​can include an opaque conductive material capable of reflecting light, but the embodiments are not limited thereto.

[0129] The first anode electrode AE1 can be located in the first sub-pixel SP1. The first anode electrode AE1 can be electrically connected to the first sub-pixel circuit PXC1. The second anode electrode AE2 can be located in the second sub-pixel SP2. The second anode electrode AE2 can be electrically connected to the second sub-pixel circuit PXC2. The third anode electrode AE3 can be located in the third sub-pixel SP3. The third anode electrode AE3 can be electrically connected to the third sub-pixel circuit PXC3.

[0130] The pixel-defining layer (PDL) is located on the anode electrode (AE). The PDL may include light-emitting openings (OPP) that expose a portion of each of the anode electrodes (AE) (see [link to PDL]). Figure 9 The light-emitting regions corresponding to the first sub-pixels SP1 to SP3 respectively can be defined by the light-emitting openings OPP of the pixel-defining layer PDL. Alternatively, it can be understood that the light-emitting regions corresponding to the first sub-pixels SP1 to SP3 respectively are defined by the anode electrode AE.

[0131] In one or more embodiments, the pixel defining layer (PDL) may include an inorganic material. For example, the pixel defining layer (PDL) may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x In one or more other embodiments, the pixel-defining layer (PDL) may include an organic material. However, the material of the pixel-defining layer (PDL) is not limited thereto.

[0132] The separator wall SW can be located on the pixel definition layer (PDL). The separator wall SW can be located at or between the boundaries of the first sub-pixel SP1 and the third sub-pixel SP3. The separator wall SW can include a first separator wall SW1, a second separator wall SW2, and a third separator wall SW3. The first separator wall SW1, the second separator wall SW2, and the third separator wall SW3 can be spaced apart from each other or separated from each other relative to the boundaries between the first sub-pixel SP1 and the third sub-pixel SP3. The separator walls SW are not separated between sub-pixels SP that emit light of the same color. For example, as... Figure 10 As shown, the first separator wall SW1 is not separated between the first sub-pixels SP1.

[0133] The separator wall SW may include a separator wall opening OPS that overlaps with the light-emitting opening OPP of the pixel-defining layer PDL on the third-direction DR3. The first separator wall SW1 may include a first separator wall opening OPS1, the second separator wall SW2 may include a second separator wall opening OPS2, and the third separator wall SW3 may include a third separator wall opening OPS3. The separator wall opening OPS of the separator wall SW may expose the anode electrode AE ​​together with the light-emitting opening OPP of the pixel-defining layer PDL.

[0134] The separator wall SW can include a first sub-separator wall SW_S1 and a second sub-separator wall SW_S2. The first sub-separator wall SW_S1 can be located on the pixel confinement layer (PDL). The first sub-separator wall SW_S1 can be directly located on the pixel confinement layer (PDL). The second sub-separator wall SW_S2 can be located on the first sub-separator wall SW_S1. The second sub-separator wall SW_S2 can be directly located on the first sub-separator wall SW_S1.

[0135] In the cross-sectional view, the partition wall SW can have an undercut shape. For example, the width of the second sub-partition wall SW_S2 can be greater than the width of the first sub-partition wall SW_S1. For example, the second sub-partition wall SW_S2 can protrude from the first sub-partition wall SW_S1 in a planar direction defined by the first direction DR1 and the second direction DR2. For example, as... Figure 9 As shown, the second sub-separator wall SW_S2 may form a tip protruding from the first sub-separator wall SW_S1. The thickness of the second sub-separator wall SW_S2 on the third-direction DR3 may be less than the thickness of the first sub-separator wall SW_S1 on the third-direction DR3, but is not limited thereto. In one or more embodiments, the second sub-separator wall SW_S2 may have robust characteristics to the etching environment compared to the first sub-separator wall SW_S1. For example, the first sub-separator wall SW_S1 may include aluminum (Al) and the second sub-separator wall SW_S2 may include titanium (Ti), but is not limited thereto. The tip of the second sub-separator wall SW_S2 may be used to separate the light-emitting layer EM and / or the cathode electrode CE, as will be described later.

[0136] In one or more embodiments, the first sub-separator wall SW_S1 and / or the second sub-separator wall SW_S2 may include a conductive material. In one or more embodiments, the first sub-separator wall SW_S1 and the second sub-separator wall SW_S2 may include different conductive materials. The first sub-separator wall SW_S1 and the second sub-separator wall SW_S2 may be electrically connected to the cathode electrode CE to transmit the second electrical voltage VSS to the cathode electrode CE.

[0137] The emitting layer EM can be located on the anode electrode AE. The emitting layer EM can be located in the emitting aperture OPP of the pixel limiting layer PDL and the partition wall aperture OPS of the partition wall SW. The emitting layer EM can be located on the anode electrode AE ​​exposed by the emitting aperture OPP and the partition wall aperture OPS.

[0138] The light-emitting layer (EM) may include an intermediate layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes, etc.

[0139] The light-emitting layer EM may include a first light-emitting layer EM1 of the first sub-pixel SP1, a second light-emitting layer EM2 of the second sub-pixel SP2, and / or a third light-emitting layer EM3 of the third sub-pixel SP3. The first light-emitting layer EM1 to the third light-emitting layer EM3 may emit different colors of light. For example, the first light-emitting layer EM1 may emit blue light, the second light-emitting layer EM2 may emit red light, and the third light-emitting layer EM3 may emit green light, but this disclosure is not limited to this.

[0140] The first light-emitting layer EM1 can be located in the light-emitting opening OPP of the pixel-limiting layer PDL of the first sub-pixel SP1 and the first partition wall opening OPS1 of the first partition wall SW1. The second light-emitting layer EM2 can be located in the light-emitting opening OPP of the pixel-limiting layer PDL of the second sub-pixel SP2 and the second partition wall opening OPS2 of the second partition wall SW2. The third light-emitting layer EM3 can be located in the light-emitting opening OPP of the pixel-limiting layer PDL of the third sub-pixel SP3 and the third partition wall opening OPS3 of the third partition wall SW3.

[0141] In one or more embodiments, the pixel defining layer PDL (or the edge of the pixel defining layer PDL) may be spaced apart from the top surface of the anode electrode AE ​​on a third-direction DR3, and the light-emitting layer EM may be filled between the pixel defining layer PDL and the anode electrode AE. For example, as Figure 9 As shown, the edge of the pixel-defining layer PDL can be spaced apart from the upper surface of the first anode electrode AE1 on the third-direction DR3. (See reference later.) Figure 17As described, a sacrificial layer (or protective layer) may be located between the anode electrode AE ​​and the pixel defining layer PDL to reduce or prevent damage to the anode electrode AE ​​during etching of the pixel defining layer PDL and / or the spacer wall SW, etc. When the sacrificial layer is removed during the formation of the light-emitting opening OPP of the pixel defining layer PDL, the pixel defining layer PDL may be spaced apart from the upper surface of the anode electrode AE ​​on the third-direction DR3.

[0142] The cathode electrode CE may be located on the light-emitting layer EM. The cathode electrode CE may be located in the partition wall opening OPS of the partition wall SW. The cathode electrode CE may be a thin metal layer with a thickness sufficient to transmit light emitted from the light-emitting layer EM. The cathode electrode CE may be formed of a metallic material or a transparent conductive material to have a relatively thin thickness. In one or more embodiments, the cathode electrode CE may include at least one of various transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In one or more other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited to these.

[0143] The cathode electrode CE may include a first cathode electrode CE1 of a first sub-pixel SP1, a second cathode electrode CE2 of a second sub-pixel SP2, and / or a third cathode electrode CE3 of a third sub-pixel SP3. The first cathode electrode CE1 may be located on a first light-emitting layer EM1. The second cathode electrode CE2 may be located on a second light-emitting layer EM2. The third cathode electrode CE3 may be located on a third light-emitting layer EM3. The first cathode electrode CE1 may be located in the first partition wall opening OPS1 of the first partition wall SW1 and may contact the first partition wall SW1. The second cathode electrode CE2 may be located in the second partition wall opening OPS2 of the second partition wall SW2 and may contact the second partition wall SW2. The third cathode electrode CE3 may be located in the third partition wall opening OPS3 of the third partition wall SW3 and may contact the third partition wall SW3.

[0144] When holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transported to the intermediate layer of the luminescent layer EM to form excitons, light can be generated when the excitons transition from the excited state to the ground state. The brightness of the light can be determined by the amount of current flowing through the intermediate layer. The wavelength range of the generated light can be determined by the structure of the intermediate layer.

[0145] The first anode electrode AE1, the first light-emitting layer EM1, and the first cathode electrode CE1 can constitute the first light-emitting element LD1 (see...). Figure 5 The second anode electrode AE2, the second light-emitting layer EM2, and the second cathode electrode CE2 can constitute the second light-emitting element LD2 (see...). Figure 5 The third anode electrode AE3, the third light-emitting layer EM3, and the third cathode electrode CE3 can constitute the third light-emitting element LD3 (see...). Figure 5 Each of the first light-emitting element LD1 to the third light-emitting element LD3 can be an organic light-emitting diode.

[0146] The encapsulation layer TFE is located on the cathode electrode CE and the separator wall SW. The encapsulation layer TFE may cover the underlying layer, which includes the first light-emitting elements LD1 to the third light-emitting elements LD3. The encapsulation layer TFE may be configured to reduce or prevent the permeation of oxygen and / or moisture into the first light-emitting elements LD1 to the third light-emitting elements LD3. In one or more embodiments, the encapsulation layer TFE may comprise an inorganic film or an organic film. For example, the inorganic film may comprise silicon nitride (SiN). x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y For example, organic films can include organic materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). However, the materials of the organic and inorganic films of the encapsulation layer TFE are not limited to these.

[0147] The encapsulation layer TFE may include a first encapsulation layer TFE1 for the first sub-pixel SP1, a second encapsulation layer TFE2 for the second sub-pixel SP2, and a third encapsulation layer TFE3 for the third sub-pixel SP3. The first encapsulation layer TFE1 may be located on the first cathode electrode CE1. The second encapsulation layer TFE2 may be located on the second cathode electrode CE2. The third encapsulation layer TFE3 may be located on the third cathode electrode CE3.

[0148] The first encapsulation layer TFE1 can be located in the first partition wall opening OPS1 of the first partition wall SW1. The second encapsulation layer TFE2 can be located in the second partition wall opening OPS2 of the second partition wall SW2. The third encapsulation layer TFE3 can be located in the third partition wall opening OPS3 of the third partition wall SW3.

[0149] In one or more embodiments, the first encapsulation layer TFE1 to the third encapsulation layer TFE3 may be partially located on the partition wall SW (or the second sub-partition wall SW_S2). The edge of each of the first encapsulation layer TFE1 to the third encapsulation layer TFE3 may be spaced apart from the partition wall SW (or the second sub-partition wall SW_S2). For example, the edge of each of the first encapsulation layer TFE1 to the third encapsulation layer TFE3 may be spaced apart from the upper surface of the partition wall SW (or the second sub-partition wall SW_S2) on a third-direction DR3. Figure 9As shown, the edge of the first encapsulation layer TFE1 may be spaced apart from the upper surface of the second sub-separator wall SW_S2 on the third direction DR3. If external stress is applied or if panel strain such as bending of the display panel DP occurs, the stress may be concentrated in the area where the edge of the encapsulation layer TFE is spaced apart from the lower layer, making it possible for cracks to appear in the encapsulation layer TFE, and thus, the encapsulation function may be lost. Accordingly, in the display device, the area where the edge of the encapsulation layer TFE is spaced apart from the lower layer is filled with an organic layer OL, thereby reducing or preventing the occurrence of cracks in the encapsulation layer TFE.

[0150] The organic layer OL can be located on and cover the encapsulation layer TFE. The organic layer OL can fill the space between the edge of the encapsulation layer TFE and the partition wall SW (or the second sub-partition wall SW_S2). In one or more embodiments, the organic layer OL can completely fill the space between the edge of the encapsulation layer TFE and the partition wall SW (or the second sub-partition wall SW_S2). Figure 9 As shown, the organic layer OL can completely fill the space between the edge of the first encapsulation layer TFE1 and the second sub-separator wall SW_S2. Correspondingly, there may be no space, cavity, or gap between the edge of the encapsulation layer TFE and the separator wall SW (or the second sub-separator wall SW_S2), but this is not a limitation. Because the organic layer OL is filled between the edge of the encapsulation layer TFE and the separator wall SW, it is possible to reduce or prevent the possibility of cracks appearing in the encapsulation layer TFE even if the edge of the encapsulation layer TFE is spaced apart from the separator wall SW.

[0151] The organic layer OL can also be filled between the first separator SW1 and the third separator SW3. The organic layer OL can contact the pixel-defining layer PDL between the first separator SW1 and the third separator SW3.

[0152] The organic layer OL can be formed from a photosensitive resin composition. The organic layer OL can be formed from a transparent photosensitive resin composition, allowing light emitted from the light-emitting layer EM to be transmitted. The organic layer OL can be formed from a low-temperature curable photosensitive resin composition to reduce or prevent damage to the light-emitting layer EM during the formation of the organic layer OL. For example, the organic layer OL can be formed from a photosensitive resin composition capable of curing at a low temperature of approximately 70°C to approximately 100°C, but is not necessarily limited to this.

[0153] The upper encapsulation layer UE may further be located on the organic layer OL. The upper encapsulation layer UE may be configured to cover the lower layer to reduce or prevent the permeation of oxygen and / or moisture into the lower layer. The upper encapsulation layer UE may include a first upper inorganic layer UI1 (or a first upper encapsulation layer), an upper organic layer UO (or a second upper encapsulation layer), and / or a second upper inorganic layer UI2 (or a third upper encapsulation layer) stacked sequentially. However, this disclosure is not limited thereto. In one or more embodiments, at least some of the first upper inorganic layer UI1, the upper organic layer UO, and the second upper inorganic layer UI2 may be omitted.

[0154] The first upper inorganic layer UI1 and the second upper inorganic layer UI2 may each include, but are not limited to, silicon nitride (SiN). x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y The upper organic layer UO may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene (BCB), etc., but is not limited to these.

[0155] Figure 11 and Figure 12 It is a diagram. Figure 4 A plan view of one or more other embodiments of the display panel. Figure 11 In the diagram, the first sub-pixels SP1 to SP3, as well as the first partition wall SW1 and the second partition wall SW2_1, are illustrated in a portion of the display panel DP_1, and... Figure 12 In the diagram, the first partition wall SW1 and the second partition wall SW2_1 are shown in the display panel DP_1.

[0156] refer to Figure 5 , Figure 6 , Figure 11 and Figure 12 Except for the second partition wall SW2_1, Figure 11 and Figure 12 Implementation examples and Figure 5 and Figure 6 The embodiments are substantially the same or similar, and therefore redundant descriptions will be omitted. Figure 11 The second partition wall SW2_1 can be connected with it Figure 5 The second partition wall SW2 and the third partition wall SW3 are integrally formed partition walls that are similar.

[0157] The second partition wall SW2_1 may further include a third partition wall opening OPS3 (or a third opening). The third light-emitting element LD3 of the third sub-pixel SP3 may be located in each of the third partition wall openings OPS3. The third partition wall opening OPS3 may be spaced apart from the second partition wall opening OPS2 in the first direction DR1, but is not limited thereto. In a plan view, the second partition wall SW2_1 may surround the second light-emitting element LD2 and the third light-emitting element LD3. The second light-emitting element LD2 may emit light of a second color (e.g., red), and the third light-emitting element LD3 may emit light of a third color (e.g., green). The first light-emitting element LD1 may emit light of a first color (e.g., blue).

[0158] The cathode electrode of the third light-emitting element LD3 can be electrically connected to the second partition wall SW2_1 (see...). Figure 13 and Figure 14 Voltage can be applied to the cathode electrode of the third light-emitting element LD3 through the second partition wall SW2_1.

[0159] like Figure 12 As shown, the first partition wall SW1 and the second partition wall SW2_1 can be alternately and repeatedly arranged along the first direction DR1. The first partition wall SW1 can be connected to another first partition wall SW1 at one end of the display panel DP_1 in the second direction DR2 (e.g., the upper area). Similarly, the second partition wall SW2_1 can be connected to another second partition wall SW2_1 at the other end of the display panel DP_1 in the second direction DR2 (e.g., the lower area).

[0160] In one or more embodiments, different voltages can be applied to the first partition wall SW1 and the second partition wall SW2_1. Each of the voltages can be applied to... Figure 2 and Figure 3 The second power voltage node VSSN Figure 1 The second electrical voltage VSS.

[0161] As described above, the first partition wall SW1 and the second partition wall SW2_1 are separated from each other, and different voltages can be supplied to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 through the first partition wall SW1 and the second partition wall SW2_1, respectively.

[0162] Figure 13 The diagram is along Figure 11 A cross-sectional view of one or more embodiments of the display panel with line D-D'. Figure 14 The diagram is along Figure 11 A cross-sectional view of one or more embodiments of the display panel along line E-E'. Figure 13The structure from the basement layer BSL to the partition wall SW_1 is shown in the figure, and... Figure 14 The structure above the partition wall SW_1 is further shown in the figure.

[0163] refer to Figure 7 , Figure 8 and Figures 11 to 14 Except for the second partition wall SW2_1, Figure 13 and Figure 14 Implementation examples and Figure 7 and Figure 8 The embodiments are substantially the same or similar, and therefore redundant descriptions will be omitted.

[0164] The separator wall SW_1 can be located on the pixel definition layer (PDL). The separator wall SW_1 can be located at or between the boundary of the first sub-pixel SP1 and the third sub-pixel SP3. The separator wall SW_1 includes a first separator wall SW1 and a second separator wall SW2_1, and the first separator wall SW1 and the second separator wall SW2_1 can be spaced apart from each other or separated from each other relative to the boundary between the first sub-pixel SP1 and the second sub-pixel SP2. The second separator wall SW2_1 (or separator wall SW_1) is not separated between the second sub-pixel SP2 and the third sub-pixel SP3.

[0165] The separator SW_1 may include a separator opening OPS that overlaps with the light-emitting opening OPP of the pixel-defining layer PDL on the third-direction DR3. The first separator SW1 may include a first separator opening OPS1, and the second separator SW2_1 may include a second separator opening OPS2 and a third separator opening OPS3. The separator opening OPS of the separator SW_1 may expose the anode electrode AE ​​together with the light-emitting opening OPP of the pixel-defining layer PDL.

[0166] The first light-emitting layer EM1 can be located in the light-emitting opening OPP of the pixel-limiting layer PDL of the first sub-pixel SP1 and the first partition wall opening OPS1 of the first partition wall SW1. The second light-emitting layer EM2 can be located in the light-emitting opening OPP of the pixel-limiting layer PDL of the second sub-pixel SP2 and the second partition wall opening OPS2 of the second partition wall SW2_1. The third light-emitting layer EM3 can be located in the light-emitting opening OPP of the pixel-limiting layer PDL of the third sub-pixel SP3 and the third partition wall opening OPS3 of the second partition wall SW2_1.

[0167] The first cathode electrode CE1 can be located in the first partition wall opening OPS1 of the first partition wall SW1 and can contact the first partition wall SW1. The second cathode electrode CE2 can be located in the second partition wall opening OPS2 of the second partition wall SW2_1 and can contact the second partition wall SW2_1. The third cathode electrode CE3 can be located in the third partition wall opening OPS3 of the second partition wall SW2_1 and can contact the second partition wall SW2_1.

[0168] Figures 15A to 15D It is a diagram. Figure 4 A plan view of one or more other embodiments of the display panel. Figure 15E and Figure 15F The diagram is along Figure 15C A cross-sectional view of one or more embodiments of the display panel with line K-K'.

[0169] First, refer to Figure 11 , Figure 12 and Figure 15A Except for the arrangement of the second partition wall opening OPS2_1 and the third partition wall opening OPS3_1, corresponding to Figure 15A One or more embodiments may be associated with the corresponding Figure 11 and Figure 12 One or more embodiments are substantially the same or similar. Additionally, the cross-sectional view along line F-F' is... Figure 7 The cross-sectional views are essentially the same or similar, and each of the cross-sectional views along line G-G' and along line H-H' can be compared with... Figure 10 The cross-sectional views are basically the same or similar. Therefore, redundant descriptions will be omitted.

[0170] The first partition wall SW1 includes a first partition wall opening OPS1, and the first light-emitting element LD1 of the first sub-pixel SP1 can be located in each of the first partition wall openings OPS1. The second partition wall SW2_1 can include a second partition wall opening OPS2_1 and a third partition wall opening OPS3_1, and the second light-emitting element LD2 of the second sub-pixel SP2 can be located in each of the second partition wall openings OPS2_1, and the third light-emitting element LD3 of the third sub-pixel SP3 can be located in each of the third partition wall openings OPS3_1.

[0171] The first partition wall SW1 and the second partition wall SW2_1 can be separated from each other, and different voltages can be supplied to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 through the first partition wall SW1 and the second partition wall SW2_1.

[0172] For reference Figure 12The first partition wall SW1 and the second partition wall SW2_1 can be arranged alternately and repeatedly along the first direction DR1. The first partition wall SW1 can be connected to another first partition wall SW1 at one end of the display panel DP_1 in the second direction DR2. Similarly, the second partition wall SW2_1 can be connected to another second partition wall SW2_1 at the other end of the display panel DP_1 in the second direction DR2.

[0173] The first partition wall opening OPS1 of the first partition wall SW1 can be arranged along the second direction DR2. The second partition wall opening OPS2_1 and the third partition wall opening OPS3_1 of the second partition wall SW2_1 can also be arranged along the second direction DR2. For example... Figure 15A As shown, the second partition wall opening OPS2_1 and the third partition wall opening OPS3_1 can be arranged alternately and repeatedly along the second direction DR2.

[0174] Corresponding to the arrangement of the second partition wall opening OPS2_1 and the third partition wall opening OPS3_1, the second sub-pixel SP2 and the third sub-pixel SP3 can be arranged on the second direction DR2. The first sub-pixel SP1 can be located on the first direction DR1 relative to each of the second sub-pixel SP2 and the third sub-pixel SP3.

[0175] The second sub-pixel SP2 and the third sub-pixel SP3 may have a smaller area than the first sub-pixel SP1. Correspondingly, the second light-emitting region EMA2_1 and the third light-emitting region EMA3_1 may have a smaller area than the first light-emitting region EMA1. However, the embodiments are not limited to this.

[0176] refer to Figure 15A and Figure 15B Except for the second partition wall SW2 and the third partition wall SW3, corresponding to Figure 15B One or more embodiments may be with Figure 15A The embodiments are essentially the same or similar. Additionally, the cross-sectional view along line J-J' can be compared with... Figure 7 The cross-sectional views are basically the same or similar. Therefore, redundant descriptions will be omitted.

[0177] The second partition wall SW2 may include a second partition wall opening OPS2, and the second light-emitting element LD2 of the second sub-pixel SP2 may be located in each of the second partition wall openings OPS2. The third partition wall SW3 may include a third partition wall opening OPS3, and the third light-emitting element LD3 of the third sub-pixel SP3 may be located in each of the third partition wall openings OPS3.

[0178] The first partition wall SW1, the second partition wall SW2, and the third partition wall SW3 are separated from each other, and different voltages can be supplied to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 through the first partition wall SW1, the second partition wall SW2, and / or the third partition wall SW3.

[0179] The second partition wall SW2 may include portions or main patterns that each surround the second light-emitting element LD2, and the main patterns of the second partition wall SW2 may be interconnected by a second connecting portion CNP2 (or a second connecting pattern) extending in the second direction DR2.

[0180] Similarly, the third partition wall SW3 may include portions or main patterns that each surround the third light-emitting element LD3, and the main patterns of the third partition wall SW3 may be interconnected by a third connecting portion CNP3 (or a third connecting pattern) extending in the second direction DR2.

[0181] Corresponding to the arrangement of the second partition wall opening OPS2 and the third partition wall opening OPS3, the main patterns of the second partition wall SW2 and the third partition wall SW3 can be alternately and repeatedly set along the second direction DR2.

[0182] The second connecting portion CNP2 and the third connecting portion CNP3 can be formed with the second partition wall SW2 and the third partition wall SW3 through the same process, but are not limited thereto.

[0183] In one or more embodiments, the second connecting portion CNP2 and the third connecting portion CNP3 may be located in different layers from the main patterns of the second partition wall SW2 and the third partition wall SW3.

[0184] For example, such as Figure 15C As shown, the main patterns of the second partition wall SW2 and the third partition wall SW3 can be physically separated from each other. The second connecting portion CNP2 extends in the second direction DR2 and can overlap with the main pattern of the second partition wall SW2.

[0185] For example, such as Figure 15E As shown, the second connection portion CNP2 can be a connection electrode CNE that overlaps with the second partition wall SW2 (or main pattern). The connection electrode CNE can be located in the same layer as the anode electrode AE ​​using the same process. The second partition wall SW2 (or main pattern) can be electrically connected to the connection electrode CNE through contact holes CNTs passing through the pixel defining layer PDL. The connection electrode CNE can also be applied to the third connection portion CNP3.

[0186] For example, such as Figure 15FAs shown, the second connection portion CNP2 can be a connection line CNL overlapping the second partition wall SW2 (or the main pattern). The connection line CNL can be located below the connection electrode CNE, or it can be included in the pixel circuit layer PCL. The second partition wall SW2 (or the main pattern) can be electrically connected to the connection line CNL via the connection electrode CNE. In one or more embodiments, the connection electrode CNE can be omitted, and the second partition wall SW2 (or the main pattern) can be directly connected to the connection line CNL.

[0187] In one or more embodiments, similar to the second connecting portion CNP2 and the third connecting portion CNP3, the first partition wall SW1 may also include the first connecting portion CNP1.

[0188] For example, such as Figure 15D As shown, the first partition wall SW1 includes a portion or main pattern surrounding the first light-emitting element LD1, and the main pattern of the first partition wall SW1 can be connected by a first connecting portion CNP1 (or a first connecting pattern) extending in the second direction DR2. Figure 15E Connection electrode CNE or Figure 15F The connecting line CNL can be applied to the first connecting part CNP1.

[0189] Figures 15A to 15D The arrangement of subpixels shown is merely an example, and embodiments are not limited thereto. Each pixel includes two or more subpixels that can be arranged in various ways, and each of the subpixels can have various shapes, as can each of the light-emitting regions. For example, a first partition wall SW1 can be arranged to connect subpixels emitting light of a first color, and a second partition wall SW2 can be arranged to connect subpixels emitting light of a second color without connecting the first partition wall SW1. (Refer to...) Figures 16A to 16I Describe the arrangement of partition walls SW1 to SW3 according to various arrangements of sub-pixels.

[0190] Figures 16A to 16I It is a diagram. Figure 4 A plan view of one or more other embodiments of the display panel. Because reference has been made to... Figures 5 to 15F The relationship between partition walls SW1 to SW3, partition wall openings OPS1 to OPS3, and light-emitting elements LD1 to LD3 is described, so redundant descriptions will be omitted, and the shape of partition walls SW1 to SW3 will be mainly described.

[0191] refer to Figure 16A The first sub-pixel SP1, the third sub-pixel SP3, the second sub-pixel SP2, and the third sub-pixel SP3 can be repeatedly arranged in a row ROW along the first direction DR1. For example, sub-pixels SP1 to SP3 can be arranged in a pentiline pattern. ®Pentyl arrangement ® (This is a registered trademark of Samsung Display Co., Ltd. of the Republic of Korea). The first sub-pixel SP1, the second sub-pixel SP2, and the two third sub-pixels SP3 can constitute a pixel PXL (or unit pixel).

[0192] Since only one type of light-emitting element is arranged in a column, the first partition wall SW1, the second partition wall SW2 and the third partition wall SW3 extend in the second direction DR2 and can be arranged sequentially and repeatedly along the first direction DR1.

[0193] refer to Figures 16B to 16D Subpixels SP1 to SP3 can be Diamond Pixel ® (Diamond Pixel) ® (This is a registered trademark of Samsung Display Co., Ltd. of the Republic of Korea). The first light-emitting element LD1 and the second light-emitting element LD2 can be arranged alternately in a column.

[0194] In one or more embodiments, such as Figure 16B As shown, the first partition wall SW1 may generally extend in the second direction DR2, may surround the first light-emitting element LD1 in odd-numbered rows (or even-numbered rows), and may have a curved shape to bypass the second light-emitting element LD2 (or the main pattern of the second partition wall SW2) in even-numbered columns (or odd-numbered columns). Similarly, the second partition wall SW2 generally extends in the second direction DR2 and surrounds the second light-emitting element LD2, and may have a curved shape to bypass the first light-emitting element LD1 (or the main pattern of the first partition wall SW1).

[0195] In one or more embodiments, such as Figure 16CAs shown, each of the first partition wall SW1 and the second partition wall SW2 can extend in a zigzag shape. For example, with respect to a column that includes a first light-emitting element LD1, the first partition wall SW1 can extend in a first inclined direction from the first light-emitting element LD1 in the first row and second column toward the first light-emitting element LD1 in the second row and first column, in a second inclined direction from the first light-emitting element LD1 in the second row and first column toward the first light-emitting element LD1 in the third row and second column, and in a first inclined direction from the first light-emitting element LD1 in the third row and second column toward the first light-emitting element LD1 in the fourth row and first column. Similar to the first partition wall SW1, the second partition wall SW2 can also extend alternately in the first and second inclined directions. The third partition wall SW3 can also extend in a zigzag shape, but is not limited to this. For example, the third partition wall SW3 can extend in the first direction DR1 to surround two third light-emitting elements LD3 in a row ROW, and can extend in the second direction DR2 toward the third light-emitting element LD3 in another row ROW. That is, the third partition wall SW3 can extend alternately in the first direction DR1 and the second direction DR2.

[0196] In one or more embodiments, such as Figure 16D As shown, each of the partition walls SW1 to SW3 can generally extend in the inclined direction.

[0197] refer to Figure 16E and Figure 16F The first light-emitting element LD1 can have a rhomboid or diamond-shaped planar shape, and the second light-emitting element LD2 and the third light-emitting element LD3 can have a triangular planar shape. In a row ROW, the second light-emitting element LD2 and the third light-emitting element LD3 can be arranged along the second direction DR2, and the first light-emitting element LD1 and the second light-emitting element LD2 and the third light-emitting element LD3 can be repeatedly arranged along the first direction DR1.

[0198] like Figure 16E As shown, each of the partition walls SW1 to SW3 can generally extend in the second direction DR2. Because the first light-emitting element LD1 and the second light-emitting element LD2 are arranged alternately in a row, the second partition wall SW2 can have a curved shape to surround the second light-emitting element LD2 while bypassing the third light-emitting element LD3 (or the third partition wall SW3). The third partition wall SW3 can have the same or similar shape as the second partition wall SW2.

[0199] like Figure 16F As shown, each of the partition walls SW1 to SW3 can generally extend in the first direction DR1.

[0200] refer to Figures 16G to 16I Each of the light-emitting elements LD1 to LD3 can have a hexagonal or circular planar shape. The light-emitting elements LD1 to LD3 can be arranged in a honeycomb shape.

[0201] like Figure 16G As shown, the first partition wall SW1, the second partition wall SW2 and the third partition wall SW3 extend in the second direction DR2 and can be arranged sequentially and repeatedly along the first direction DR1.

[0202] like Figure 16H As shown, each of the partition walls SW1 to SW3 can extend in a zigzag shape. For example, with respect to a column that includes a second light-emitting element LD2, the second partition wall SW2 can extend in a first inclined direction from the second light-emitting element LD2 in the first row and second column toward the second light-emitting element LD2 in the second row and first column, in a second inclined direction from the second light-emitting element LD2 in the second row and first column toward the second light-emitting element LD2 in the third row and second column, and in a first inclined direction from the second light-emitting element LD2 in the third row and second column toward the second light-emitting element LD2 in the fourth row and first column. Similar to the second partition wall SW2, each of the first partition wall SW1 and the third partition wall SW3 can extend alternately in the first and second inclined directions.

[0203] like Figure 16I As shown, each of the partition walls SW1 to SW3 can generally extend in the inclined direction.

[0204] Figures 16A to 16I The widths of each of the partition walls SW1 to SW3 and the distances between them shown are merely examples. Within the range where the partition walls SW1 to SW3 are separated from each other, the widths of the partition walls SW1 to SW3 and the distances between them can be adjusted in various ways. For example, to keep the distance between the partition walls SW1 to SW3 constant, the width of each of the partition walls SW1 to SW3 and the distance between them can be set, or the size of the main pattern (e.g., the portion surrounding the light-emitting element) and the width of the connecting portions (e.g., the portions connecting the main patterns) of the partition walls SW1 to SW3 can be set. Figure 15E Connection electrode CNE or Figure 15F The CNL connector can be applied to this connection section.

[0205] Figures 17 to 24 This is a cross-sectional view of the process operation of a method for manufacturing a display device according to one or more embodiments. Figures 17 to 24 It is used for manufacturing Figure 8The diagram shows cross-sectional views of each operation of the display panel manufacturing process, and redundant descriptions will be omitted for ease of description.

[0206] refer to Figure 17 A substrate layer (BSL) can be provided. A pixel circuit layer (PCL) can be formed on the substrate layer (BSL), and an anode electrode (AE) can be formed on the pixel circuit layer (PCL).

[0207] In one or more embodiments, a sacrificial layer (or protective layer) PS may be located on the anode electrode AE. The sacrificial layer PS can reduce or prevent damage to the anode electrode AE ​​during the etching of the pixel defining layer PDL and / or the separator wall SW. The sacrificial layer PS may include a first sacrificial layer PS1 formed on a first anode electrode AE1, a second sacrificial layer PS2 formed on a second anode electrode AE2, and a third sacrificial layer PS3 formed on a third anode electrode AE3.

[0208] The pixel-defining layer (PDL) can be formed on the anode electrode (AE) and / or the sacrificial layer (PS). The pixel-defining layer (PDL) can be formed entirely within the first sub-pixel (SP1) to the third sub-pixel (SP3).

[0209] The first sub-separator wall SW_S1 (or the first metal layer) can be formed on the pixel definition layer PDL. The first sub-separator wall SW_S1 can be completely formed in the first sub-pixel SP1 to the third sub-pixel SP3.

[0210] The second sub-separator wall SW_S2 (or the second metal layer) can be formed on the first sub-separator wall SW_S1. The second sub-separator wall SW_S2 can be completely formed in the first sub-pixel SP1 to the third sub-pixel SP3.

[0211] refer to Figure 18 The first partition wall SW1 to the third partition wall SW3 and the partition wall opening OPS can be formed by initial etching (or dry etching) of the first sub-partition wall SW_S1 and the second sub-partition wall SW_S2. The first partition wall SW1 can be formed in the first sub-pixel SP1, and the first partition wall opening OPS1 can be formed in the first partition wall SW1. The first partition wall opening OPS1 can overlap with the first anode electrode AE1. The second partition wall SW2 can be formed in the second sub-pixel SP2, and the second partition wall opening OPS2 can be formed in the second partition wall SW2. The third partition wall SW3 can be formed in the third sub-pixel SP3, and the third partition wall opening OPS3 can be formed in the third partition wall SW3.

[0212] refer to Figure 19The tip of the second sub-separator wall SW_S2 can be formed by secondary etching (or wet etching) of the separator wall SW. In one or more embodiments, the secondary etching process can be performed in an environment where the etch selectivity between the first sub-separator wall SW_S1 and the second sub-separator wall SW_S2 is relatively high. For example, the first sub-separator wall SW_S1 can be selectively etched because the etch rate of the first sub-separator wall SW_S1 to the etch solution is greater than the etch rate of the second sub-separator wall SW_S2. Accordingly, the width of the second sub-separator wall SW_S2 can be formed to be greater than the width of the first sub-separator wall SW_S1, and the second sub-separator wall SW_S2 can form a tip protruding from the first sub-separator wall SW_S1. For example, the separator wall SW to which secondary etching has been performed can have an undercut shape in a cross-sectional view.

[0213] refer to Figure 20 The pixel-defining layer (PDL) can be etched to form first light-emitting openings OPP1 to third light-emitting openings OPP3. First light-emitting openings OPP1 to third light-emitting openings OPP3 can be formed by etching the pixel-defining layer (PDL) exposed by the first partition wall openings OPS1 to third partition wall openings OPS3. First light-emitting opening OPP1 can overlap with first partition wall opening OPS1 on third-direction DR3. Second light-emitting opening OPP2 can overlap with second partition wall opening OPS2 on third-direction DR3. Third light-emitting opening OPP3 can overlap with third partition wall opening OPS3 on third-direction DR3.

[0214] The first light-emitting opening OPP1 to the third light-emitting opening OPP3 can expose the anode electrode AE. The sacrificial layer PS can be removed during the operation of forming the first light-emitting opening OPP1 to the third light-emitting opening OPP3, but is not limited to this.

[0215] refer to Figure 21 The first light-emitting layer EM1, the first cathode electrode CE1, and the first encapsulation layer TFE1 can be formed on the first anode electrode AE1.

[0216] The first light-emitting layer EM1 can be completely formed in the first sub-pixels SP1 to SP3. The first light-emitting layer EM1 can be separated by the tip structure of the separator wall SW. Accordingly, a region of the first light-emitting layer EM1 can be formed in the first light-emitting opening OPP1 and / or the first separator wall opening OPS1. This region of the first light-emitting layer EM1 can be formed on the first anode electrode AE1 exposed by the first light-emitting opening OPP1 and / or the first separator wall opening OPS1. Another region of the first light-emitting layer EM1 can be located in the second sub-pixels SP2 and SP3, but can be removed in subsequent processes.

[0217] The first cathode electrode CE1 can be formed on the first light-emitting layer EM1. The first cathode electrode CE1 can be completely formed in the first sub-pixels SP1 to SP3. The first cathode electrode CE1 can be separated by the tip structure of the separator wall SW. Accordingly, one region of the first cathode electrode CE1 can be formed in the opening OPS1 of the first separator wall. The other region of the first cathode electrode CE1 can be located in the second sub-pixel SP2 and the third sub-pixel SP3, but can be removed in a subsequent process.

[0218] The first encapsulation layer TFE1 may be formed on the first cathode electrode CE1. The first encapsulation layer TFE1 may be formed in the first partition wall opening OPS1. In one or more embodiments, the first encapsulation layer TFE1 may be formed entirely in the first sub-pixels SP1 to the third sub-pixels SP3.

[0219] refer to Figure 22 The first encapsulation layer TFE1 can be etched. For example, the portion of the first encapsulation layer TFE1 other than that formed on the first partition wall SW1 can be etched and removed. In the process of etching the first encapsulation layer TFE1, layers formed in areas other than the opening OPS1 of the first partition wall (e.g., another area of ​​the first light-emitting layer EM1 and / or another area of ​​the first cathode electrode CE1) can be removed together. Accordingly, a space can be formed between the edge of the first encapsulation layer TFE1 and the first partition wall SW1 (or the second sub-partition wall SW_S2).

[0220] refer to Figure 23 The second light-emitting layer EM2, the second cathode electrode CE2, and the second encapsulation layer TFE2 can be formed on the second anode electrode AE2.

[0221] The process and reference for forming the second light-emitting layer EM2, the second cathode electrode CE2, and the second encapsulation layer TFE2 Figure 21 and Figure 22 The processes for forming the first light-emitting layer EM1, the first cathode electrode CE1, and the first encapsulation layer TFE1 are substantially the same or similar, and therefore, redundant descriptions will be omitted.

[0222] refer to Figure 24 The third light-emitting layer EM3, the third cathode electrode CE3, and the third encapsulation layer TFE3 can be formed on the third anode electrode AE3.

[0223] The process and reference for forming the third light-emitting layer EM3, the third cathode electrode CE3, and the third encapsulation layer TFE3 Figure 21 and Figure 22 The processes for forming the first light-emitting layer EM1, the first cathode electrode CE1, and the first encapsulation layer TFE1 are substantially the same or similar, and therefore, redundant descriptions will be omitted.

[0224] Subsequently, an organic layer (OL) and an upper encapsulation layer (UE) can be formed to complete the process. Figure 8 The display panel.

[0225] The display device according to one or more embodiments is applicable to various types of electronic devices. In one or more embodiments, the electronic device includes the above-described display device, and may further include other modules or devices with additional functions in addition to the display device.

[0226] Figure 25 This is a block diagram of an electronic device according to one or more embodiments. Reference Figure 25 The electronic device 10 according to one or more embodiments may include a display module 11 (or display device), a processor 12, a memory 13, and a power module 14.

[0227] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0228] The memory 13 can store data and / or information used to operate the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11. The display module 11 can process the provided signals and output image information on the display screen.

[0229] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module. The power conversion module converts the power supplied by the power module and generates power for operating the electronic device 10.

[0230] At least one of the aforementioned components of the electronic device 10 may be included in the display device according to the embodiment described above. Additionally, in terms of function, some individual modules included in a single module may be included in the display device, while other individual modules may be provided separately from the display device. For example, the display module 11 may be included in the display device, while the processor 12, memory 13, and power module 14 may not be included in the display device but are provided separately in the electronic device 10.

[0231] Figure 26 These are schematic diagrams of electronic devices according to various embodiments.

[0232] refer to Figure 26Various types of electronic devices in embodiments of the application display device may include electronic devices for displaying images, such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d or desktop monitors 10_1e; wearable electronic devices including display modules, such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b or smartwatches 10_2c; or automotive electronic devices including display modules, such as interior mirror displays or central information displays (CIDs) located in the instrument cluster, central dashboard and / or instrument panel of a vehicle 10_3.

[0233] Accordingly, the spirit of this disclosure should not be limited to the described embodiments, and the claims and all equivalent or related modifications thereof are within the scope of the spirit of this disclosure.

Claims

1. A display device, comprising: The first electrode defines multiple first openings; A plurality of first light-emitting elements are respectively located in the plurality of first openings and configured to emit light of a first color; The second electrode defines multiple second openings; A plurality of second light-emitting elements are respectively located in the plurality of second openings and configured to emit light of a second color; The third electrode defines multiple third openings; as well as Multiple third light-emitting elements are respectively located in the multiple third openings and configured to emit light of a third color. The first electrode, the second electrode, and the third electrode are separated from each other and electrically disconnected.

2. The display device according to claim 1, wherein, The plurality of first light-emitting elements are configured to receive a first voltage through the first electrode. The plurality of second light-emitting elements are configured to receive a second voltage through the second electrode, and The plurality of third light-emitting elements are configured to receive a third voltage through the third electrode.

3. The display device according to claim 1, wherein, In the plan view, there is no electrode between the first electrode and the second electrode or between the second electrode and the third electrode.

4. The display device according to claim 1, wherein, In the plan view, the first electrode, the second electrode, and the third electrode are arranged sequentially along a first direction and extend in a second direction intersecting the first direction. The plurality of first openings, the plurality of second openings, and the plurality of third openings are arranged along the second direction, and In the plan view, the first electrode surrounds only the plurality of first light-emitting elements, the second electrode surrounds only the plurality of second light-emitting elements, and the third electrode surrounds only the plurality of third light-emitting elements.

5. The display device according to claim 1, wherein, In the plan view, the first electrode, the second electrode, and the third electrode are arranged sequentially and repeatedly along a first direction, and extend in a second direction intersecting the first direction. The plurality of first openings, the plurality of second openings, and the plurality of third openings are arranged along the second direction.

6. The display device according to claim 1, wherein, The first light-emitting element, the second light-emitting element, and the third light-emitting element each include an anode electrode, a light-emitting layer above the anode electrode, and a cathode electrode above the light-emitting layer. Wherein, the first electrode contacts the cathode electrode of the first light-emitting element. The second electrode is in contact with the cathode electrode of the second light-emitting element. The third electrode is in contact with the cathode electrode of the third light-emitting element. The display device further includes: An encapsulation layer is located above the cathode electrode at the first opening, the second opening, and the third opening; An organic layer, above and covering the encapsulation layer; and A pixel defining layer, above the anode electrode, defines a plurality of openings corresponding to the first opening, the second opening, and the third opening, and The organic layer is filled between the first electrode, the second electrode and the third electrode, and contacts the pixel defining layer between the first electrode, the second electrode and the third electrode.

7. The display device according to claim 1, wherein, The plurality of first light-emitting elements correspond one-to-one with the plurality of first openings. Wherein, the plurality of second light-emitting elements correspond one-to-one with the plurality of second openings, and The plurality of third light-emitting elements correspond one-to-one with the plurality of third openings.

8. The display device according to any one of claims 1-7, wherein, The first light-emitting element, the second light-emitting element, and the third light-emitting element each include an organic light-emitting diode.

9. A display device, comprising: The first electrode defines multiple first openings; A plurality of first light-emitting elements are respectively located in the plurality of first openings and configured to emit light of a first color; The second electrode defines a plurality of second openings and a plurality of third openings, and is electrically isolated from the first electrode; A plurality of second light-emitting elements are respectively located in the plurality of second openings and configured to emit light of a second color; as well as Multiple third light-emitting elements are respectively located in the multiple third openings and configured to emit light of a third color.

10. The display device according to claim 9, wherein, The plurality of first light-emitting elements emit blue light. Among them, the plurality of second light-emitting elements emit red light, and Among them, the plurality of third light-emitting elements emit green light.

11. The display device according to claim 9, wherein, In the plan view, the first electrode and the second electrode are spaced apart from each other in a first direction and extend in a second direction intersecting the first direction. The plurality of first openings, the plurality of second openings, and the plurality of third openings are arranged along the second direction.

12. The display device according to claim 11, wherein, The first electrode and the second electrode are arranged alternately and repeatedly along the first direction. Wherein, the first electrode is connected at one end to another first electrode, and The second electrode is connected to another second electrode at the other end.

13. The display device according to claim 11, wherein, The plurality of second openings and the plurality of third openings are arranged alternately along the second direction.

14. The display device according to claim 9, wherein, The first light-emitting element, the second light-emitting element, and the third light-emitting element each include an anode electrode, a light-emitting layer above the anode electrode, and a cathode electrode above the light-emitting layer. Wherein, the first electrode contacts the cathode electrode of the first light-emitting element. Wherein, the second electrode contacts the cathode electrode of the second light-emitting element and the third light-emitting element, and The display device further includes: A pixel defining layer is provided above the anode electrode and defines a plurality of openings corresponding to the first opening, the second opening and the third opening; An encapsulation layer is provided above the cathode electrode at the first opening, the second opening, and the third opening; and An organic layer, above and covering the encapsulation layer, and The organic layer fills the space between the first electrode and the second electrode and contacts the pixel defining layer between the first electrode and the second electrode.

15. An electronic device comprising: The processor is configured to provide image data; as well as A display device configured to display an image based on the image data, and includes: The first electrode defines multiple first openings; A plurality of first light-emitting elements are respectively located in the plurality of first openings and configured to emit light of a first color; The second electrode defines a plurality of second openings and is electrically isolated from the first electrode; and Multiple second light-emitting elements are respectively located in the multiple second openings and configured to emit light of a second color.

16. The electronic device according to claim 15, wherein, The first light-emitting element and the second light-emitting element each include an anode electrode, a light-emitting layer above the anode electrode, and a cathode electrode above the light-emitting layer. Wherein, the first electrode contacts the cathode electrode of the first light-emitting element. Wherein, the second electrode contacts the cathode electrode of the second light-emitting element, and The display device further includes: A pixel defining layer is provided above the anode electrode and defines a plurality of openings corresponding to the first opening and the second opening; An encapsulation layer is provided above the cathode electrode at the first and second openings; and An organic layer, above the encapsulation layer, covers the encapsulation layer, fills the space between the first electrode and the second electrode, and contacts the pixel defining layer between the first electrode and the second electrode.

17. The electronic device according to claim 15, wherein, The display device further includes: A third electrode, defining a plurality of third openings and electrically isolated from the first and second electrodes; and Multiple third light-emitting elements are respectively located in the multiple third openings and configured to emit light of a third color. In the plan view, the first electrode, the second electrode, and the third electrode are arranged sequentially along a first direction and extend in a second direction intersecting the first direction. The plurality of first openings, the plurality of second openings, and the plurality of third openings are arranged along the second direction.

18. The electronic device according to claim 15, wherein, The display device further includes: Multiple third light-emitting elements are respectively located in multiple third openings defined in the second electrode, and are configured to emit green light. Among them, the plurality of first light-emitting elements emit blue light, and Among them, the plurality of second light-emitting elements emit red light.

19. The electronic device according to claim 15, wherein, The display device further includes: Multiple third light-emitting elements are respectively located in multiple third openings defined in the second electrode, and are configured to emit light of a third color. In the plan view, the first electrode and the second electrode are spaced apart from each other and arranged alternately and repeatedly in a first direction, and extend in a second direction intersecting the first direction. The plurality of first openings, the plurality of second openings, and the plurality of third openings are arranged along the second direction. Wherein, the first electrode is connected at one end to another first electrode, and The second electrode is connected to another second electrode at the other end.

20. The electronic device according to claim 15, wherein, The display device further includes: Multiple third light-emitting elements are respectively located in multiple third openings defined in the second electrode, and are configured to emit light of a third color. In the plan view, the first electrode and the second electrode are spaced apart from each other in a first direction and extend in a second direction intersecting the first direction. The plurality of first openings, the plurality of second openings, and the plurality of third openings are arranged along the second direction, and the plurality of second openings and the plurality of third openings are arranged alternately along the second direction.

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