Display device, method of manufacturing display device, and electronic device

Abstract

A display device, a method of manufacturing the display device, and an electronic device are provided. The display device includes: a substrate; a planarization layer above the substrate; a first pixel electrode above the planarization layer; an emission layer above the first pixel electrode; a counter electrode above the emission layer; and a pixel defining layer between the emission layer and the counter electrode, defining a first pixel opening overlapping the first pixel electrode.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0197378, filed on December 26, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device including an emitting layer having a substantially uniform thickness that improves emission efficiency, a method of manufacturing a display device, and an electronic device. Background Technology

[0003] To support various functions, electronic devices include display devices capable of providing visual information such as images or videos to users. Such display devices have display elements such as organic light-emitting diodes (OLEDs) and thin-film transistors formed on a substrate, and operate by allowing the display elements to emit light. For example, the display element may include an emission layer between pixel electrodes and counter electrodes. When the thickness of the emission layer of the display element is non-uniform, the electric field applied to the emission layer is non-uniform, and therefore, the emission area decreases, and correspondingly, the emission efficiency decreases. Summary of the Invention

[0004] In display devices based on related technologies, the thickness of the emission layer is uneven because the emission layer is formed in the opening defined in the pixel defining layer, which reduces emission efficiency.

[0005] One or more embodiments include a display device comprising an emissive layer having a substantially uniform thickness that improves emission efficiency, a method of manufacturing the display device, and an electronic device. However, these are merely examples, and the scope of this disclosure is not limited thereto.

[0006] Additional aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0007] According to one or more embodiments, a display device includes: a substrate; a planarization layer over the substrate; a first pixel electrode over the planarization layer; an emission layer over the first pixel electrode; a counter electrode over the emission layer; and a pixel defining layer between the emission layer and the counter electrode, defining a first pixel opening overlapping the first pixel electrode.

[0008] A portion of the emission layer may be located between the portion of the pixel-defining layer that defines the first pixel opening and a portion of the first pixel electrode, wherein another portion of the emission layer is located between the portion of the counter electrode that overlaps with the first pixel opening and another portion of the first pixel electrode.

[0009] The display device may further include: a second pixel electrode, above the planarization layer and spaced apart from the first pixel electrode; and a third pixel electrode, above the planarization layer, opposite to the second pixel electrode and between the second pixel electrode and the third pixel electrode, wherein the emission layer overlaps with the first pixel electrode, the second pixel electrode and the third pixel electrode, and wherein the pixel defining layer further defines a second pixel opening overlapping with the second pixel electrode and a third pixel opening overlapping with the third pixel electrode.

[0010] The emitter layer can be located between the first pixel electrode and the second pixel electrode, and between the first pixel electrode and the third pixel electrode.

[0011] The display device may further include: an encapsulation layer above the counter electrode, and including at least one inorganic layer and at least one organic layer; a light-shielding wall portion above the encapsulation layer, and defining a first color conversion opening overlapping a first pixel opening, a second color conversion opening overlapping a second pixel opening, and a light-transmitting opening overlapping a third pixel opening; a first color conversion layer in the first color conversion opening; a second color conversion layer in the second color conversion opening; and a light-transmitting layer in the light-transmitting opening.

[0012] The display device may further include: an encapsulation layer above the counter electrode, and including at least one inorganic layer and at least one organic layer; a light-shielding wall portion above the encapsulation layer, and defining a first color conversion opening overlapping a first pixel opening, a second color conversion opening overlapping a second pixel opening, and a third color conversion opening overlapping a third pixel opening; a first color filter layer in the first color conversion opening; a second color filter layer in the second color conversion opening; and a third color filter layer in the third color conversion opening.

[0013] The display device may further include: a planarization auxiliary layer, which is above the planarization layer between the first pixel electrode and the second pixel electrode and between the first pixel electrode and the third pixel electrode, directly contacts the planarization layer, and directly contacts the portions of the emission layer between the first pixel electrode and the second pixel electrode and between the first pixel electrode and the third pixel electrode.

[0014] The upper surfaces of the planarization auxiliary layer, the first pixel electrode, the second pixel electrode, and the third pixel electrode can be substantially coplanar.

[0015] The planarization auxiliary layer may include the same material as the planarization layer.

[0016] The display device may further include: a second pixel electrode, above the planarization layer and spaced apart from the first pixel electrode; and a third pixel electrode, above the planarization layer and opposite to the second pixel electrode, with the first pixel electrode between the second pixel electrode and the third pixel electrode, wherein the emission layer includes a first emission layer between the first pixel electrode and the counter electrode, a second emission layer between the second pixel electrode and the counter electrode, and a third emission layer between the third pixel electrode and the counter electrode, the first emission layer, the second emission layer and the third emission layer being spaced apart from each other, and wherein the pixel defining layer further defines a second pixel opening overlapping the second pixel electrode and a third pixel opening overlapping the third pixel electrode.

[0017] The portions of the pixel-defined layer between the first and second emission layers and between the first and third emission layers can directly contact the planarization layer.

[0018] The display device may further include: a planarization auxiliary layer, which is above the planarization layer between the first pixel electrode and the second pixel electrode and between the first pixel electrode and the third pixel electrode, directly contacts the planarization layer, and directly contacts the portions of the pixel defining layer between the first pixel electrode and the second pixel electrode and between the first pixel electrode and the third pixel electrode.

[0019] The upper surfaces of the planarization auxiliary layer, the first pixel electrode, the second pixel electrode, and the third pixel electrode can be substantially coplanar.

[0020] The planarization auxiliary layer may include the same material as the planarization layer.

[0021] According to one or more embodiments, a method of manufacturing a display device includes: placing a first pixel electrode over a planarization layer over a substrate; placing an emission layer over the first pixel electrode; placing a pixel defining layer over the emission layer and defining a first pixel opening overlapping the first pixel electrode; and placing a counter electrode over the pixel defining layer.

[0022] A portion of the emission layer may be located between the portion of the pixel-defining layer that defines the first pixel opening and a portion of the first pixel electrode, wherein another portion of the emission layer is located between the portion of the counter electrode that overlaps with the first pixel opening and another portion of the first pixel electrode.

[0023] The method may further include: placing a second pixel electrode and a third pixel electrode above a planarization layer, the second pixel electrode being spaced apart from a first pixel electrode, the third pixel electrode being opposite to the second pixel electrode and the first pixel electrode being between the second and third pixel electrodes; covering the first pixel electrode, the second pixel electrode, and the third pixel electrode with a preliminary planarization auxiliary layer; and removing a portion of the preliminary planarization auxiliary layer to form a planarization auxiliary layer having an upper surface substantially coplanar with the upper surfaces of the first pixel electrode, the second pixel electrode, and the third pixel electrode, wherein the emission layer is integral across the first pixel electrode, the second pixel electrode, and the third pixel electrode, wherein the placement of the pixel defining layer includes coating a pixel defining layer forming material between the central portions of the first pixel electrode and the central portions of the second pixel electrode and between the central portions of the first pixel electrode and the central portions of the third pixel electrode and performing heat treatment on the pixel defining layer forming material, and wherein the formation of the planarization auxiliary layer is performed between the placement of the first pixel electrode and the placement of the emission layer.

[0024] The method may further include: placing a second pixel electrode and a third pixel electrode above a planarization layer, the second pixel electrode being spaced apart from the first pixel electrode, the third pixel electrode being opposite to the second pixel electrode and the first pixel electrode being located between the second pixel electrode and the third pixel electrode, wherein placing the emission layer includes: placing a preliminary emission layer integrally across the first pixel electrode, the second pixel electrode and the third pixel electrode, and removing the portion of the preliminary emission layer above the planarization layer between the first pixel electrode and the second pixel electrode and between the first pixel electrode and the third pixel electrode, and wherein placing the pixel defining layer includes coating a pixel defining layer forming material between the central portion of the first pixel electrode and the central portion of the second pixel electrode and between the central portion of the first pixel electrode and the central portion of the third pixel electrode and performing heat treatment on the pixel defining layer forming material.

[0025] The method may further include: between the placement of the first pixel electrode and the placement of the emitter layer, by covering the first pixel electrode, the second pixel electrode and the third pixel electrode with a preliminary planarization auxiliary layer and removing a portion of the preliminary planarization auxiliary layer, to place a planarization auxiliary layer having an upper surface substantially coplanar with the upper surfaces of the first pixel electrode, the second pixel electrode and the third pixel electrode.

[0026] According to one or more embodiments, an electronic device includes: a display device; and a housing that accommodates the display device and forms the appearance of the electronic device, wherein the display device includes: a substrate; a planarization layer over the substrate; a first pixel electrode over the planarization layer; an emission layer over the first pixel electrode; a counter electrode over the emission layer; and a pixel defining layer between the emission layer and the counter electrode, and defining a first pixel opening overlapping the first pixel electrode.

[0027] Other aspects beyond those described above will become apparent from the following detailed description, the claims, and the accompanying drawings used to implement this disclosure. Attached Figure Description

[0028] The above and other aspects of specific embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 This is a schematic diagram illustrating a perspective view of an electronic device according to one or more embodiments;

[0030] Figure 2 This is a schematic diagram illustrating a plan view of a display device according to one or more embodiments;

[0031] Figure 3 Is included Figure 2 Equivalent circuit diagram of pixel circuits in a display device;

[0032] Figure 4 It is a schematic map showing Figure 2 An enlarged plan view of area A of the display device;

[0033] Figure 5 This is a schematic map showing the section intercepted along line I-I'. Figure 4 A cross-sectional view of the display device;

[0034] Figure 6 It is a schematic map showing Figure 5 An enlarged cross-sectional view of area B of the display device;

[0035] Figure 7 This is a diagram used to describe a first color conversion layer, a second color conversion layer, and a light-transmitting layer included in a display device according to one or more embodiments;

[0036] Figure 8 This is a schematic diagram illustrating a cross-sectional view of a display device according to one or more embodiments;

[0037] Figure 9 This is a schematic diagram illustrating a cross-sectional view of a display device according to one or more embodiments;

[0038] Figure 10 This is a schematic diagram illustrating a cross-sectional view of a display device according to one or more embodiments;

[0039] Figures 11 to 15 It is a schematic map showing the manufacturing process. Figure 5 A cross-sectional view of a portion of the manufacturing process of a display device;

[0040] Figures 16 to 18 It is a schematic cross-sectional view for describing a method of manufacturing a display device according to one or more embodiments;

[0041] Figures 19 to 21 It is a schematic cross-sectional view for describing a method of manufacturing a display device according to one or more embodiments;

[0042] Figures 22 to 24 This is a schematic cross-sectional view used to describe a method of manufacturing a display device according to one or more embodiments; and Figure 25 This is a schematic diagram illustrating a cross-sectional view of a display device according to one or more embodiments. Detailed Implementation

[0043] Various aspects of some embodiments of this disclosure and their implementation methods can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be comprehensive and complete, and will fully convey various aspects of this disclosure to those skilled in the art. Accordingly, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments or are not essential for a full understanding of the aspects of this disclosure by those skilled in the art may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, repeated descriptions may be omitted.

[0044] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments illustrated herein. The terms "can," "may," or "may not" are used in the described embodiments to correspond to one or more embodiments of this disclosure.

[0045] Those skilled in the art will understand that, in view of the overall content of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in whole or in part, or combined with each other, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable way.

[0046] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, this disclosure is not limited to the dimensions and thicknesses of elements in the drawings, which are arbitrarily depicted for ease of description. Additionally, the use of crosshairs and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities among the illustrated elements, or any other characteristics, properties, etc.

[0047] Various embodiments are described herein with reference to cross-sectional diagrams as schematic illustrations of examples and / or intermediate structures. Therefore, variations in the shapes of the diagrams as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments based on the concepts of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the illustrated shapes of elements, layers, or regions, but rather include deviations in shape resulting from, for example, manufacturing processes.

[0048] For example, an injection zone illustrated as rectangular typically has circular or curved features at its edges and / or a gradient of injectant concentration, rather than a binary change from the injection zone to the non-injection zone. Similarly, an embedded zone formed by injection can result in some injection in the zone between the embedded zone and the surface through which the injection occurs.

[0049] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “below,” “below,” “above,” “above,” “higher,” “upper,” and “side” (e.g., “side” in “sidewall”) may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “below” other elements or features will be oriented “above” that other element or feature. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this indicates that the first part is arranged on the upper or lower side of the second part, and not limited to its upper side based on the direction of gravity.

[0050] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above. In other words, the expression "in a plan view," as used herein, can mean "when viewed from a perspective perpendicular to the substrate 100 (see [reference]..."). Figure 5 When viewed from the side, the phrase "in a schematic cross-sectional view" means when viewed from the side as a schematic cross-section taken by cutting the object portion perpendicularly. The terms "overlapping with" or "overlapping" mean that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlapping" may include stacking, facing, extending over, covering, or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" may include meanings such as "separated from," "set on one side," or "offset from," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The term "facing" may mean that the first object may be directly or indirectly opposite the second object. Where a third object is located between the first and second objects, although the first and second objects still face each other, the first and second objects may be understood as being indirectly opposite each other.

[0051] It will be understood that when a component, layer, area, or part (e.g., device, equipment, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "(operably, functionally, or communicatively) coupled to" another component, layer, area, or part), it can be directly formed on, directly connected to, or coupled to that other component, layer, area, or part, or indirectly formed on, indirectly connected to, or coupled to that other component, layer, area, or part, such that one or more intervening components, layers, areas, or parts may exist. Furthermore, this can collectively mean direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when a layer, area, or component is referred to as "electrically connected" or "electrically coupled" to another layer, area, or component, it can be directly electrically connected or coupled to that other layer, area, or component, or there can be one or more intervening layers, areas, or components. One or more intervening components can include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Accordingly, the connection is not limited to the connections illustrated in the accompanying drawings or described in the detailed description, and may also include other types of connections. In the described embodiments, unless explicitly described as a direct connection, the expression for connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or directly coupled to another component or directly on another component, without any intervening components.

[0052] Furthermore, in this specification, when a portion of a layer, film, region, or plate is formed on another portion, the forming direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, or plate is formed "below" another portion, this includes not only the case where the portion is "directly" "below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing the relationship between components can be interpreted, such as "between," "immediately between," or "adjacent to," and "directly adjacent to." It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or layers.

[0053] For the purposes of this disclosure, expressions such as “at least one of…”, “any one of…”, or “one or more of…”, when following a list of elements, modify the entire list of elements without modifying any individual element of the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the items in the relevant list. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of…”, “a plurality of…”, “one of…”, and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements without modifying any individual element of the list. Unless otherwise stated, when “C to D” is stated, it means above C and below D.

[0054] It will be understood that although the terms “first,” “second,” “third,” etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms do not correspond to a particular order, position, or superiority, and are used only to distinguish one element, component, area, region, layer, segment, or part from another. Therefore, the first element, component, area, layer, or part described below may be referred to as a second element, component, area, layer, or part without departing from the spirit and scope of this disclosure. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or sets of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0055] In the example, the x-axis, y-axis, and / or z-axis directions are not limited to directions corresponding to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first, second, and / or third directions.

[0056] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular form "a" and its variations are intended to include the plural form as well, and the plural form is intended to include the singular form as well. It will be further understood that, when used in this specification, the terms "comprising," "having," and "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0057] When one or more embodiments can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described sequence.

[0058] As used herein, the terms “substantially,” “approximately,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to describe the inherent deviations of measured or calculated values ​​that will be recognized by those skilled in the art. For example, “substantially” can include a range of + / - 5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” or “approximately” as used herein includes the stated value and means within an acceptable range of deviation for that particular quantity as determined by those skilled in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that is tolerable to those skilled in the art. Other expressions may also be derived from those that omit “substantially.”

[0059] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0060] Figure 1 This is a schematic diagram showing a perspective view of an electronic device 2 according to one or more embodiments. Figure 2 This is a schematic diagram showing a plan view of a display device 1 according to one or more embodiments.

[0061] like Figure 1 and Figure 2 As shown, the display device 1 displays moving or still images, and can display images on the electronic device 2 or perform data input or output.

[0062] exist Figure 1In this embodiment, according to one or more embodiments, the display device 1 is used for a mobile phone. However, other embodiments are not limited thereto. For example, the display device 1 can be used not only for portable electronic devices such as mobile communication terminals (e.g., mobile phones and smartphones), tablet PCs, laptop PCs, e-books, portable multimedia players (PMPs), navigation devices, or ultra-mobile PCs (UMPCs), but also as a display screen for various electronic devices such as televisions, monitors, billboards, or Internet of Things (IoT) devices.

[0063] Additionally, in one or more embodiments, the display device 1 can be used for electronic devices such as wearable devices (e.g., smartwatches, phone watches, glasses displays, or head-mounted displays (HMDs)). In one or more embodiments, the display device 1 can be used as a display for various electronic devices, such as a vehicle's dashboard, instrument panel, or central information display (CID) arranged on the center dashboard, an interior rearview mirror display replacing the vehicle's side mirrors, or a display arranged on the rear surface of the front seats for rear-seat entertainment.

[0064] In one or more embodiments, the display device 1 may be housed within a casing 3 of the electronic device 2. The casing 3 may protect internal components such as the display device 1 and may serve as a cover forming the exterior of the electronic device 2. Furthermore, the display device 1 may be connected to an electronic module of the electronic device 2 and may operate based on the electronic device 2. The display device 1 is described primarily below.

[0065] like Figure 2 As shown, the display device 1 may include a display area DA in which a plurality of pixels PX are arranged and a peripheral area PA located outside the display area DA. For example, the peripheral area PA may (e.g., in a plan view) completely surround the display area DA. This can be understood as the substrate 100 included in the display device 1 (see... Figure 5 It has a display area DA and a peripheral area PA.

[0066] Each of the pixels PX in the display device 1 is an area that can emit light of a specific color, and the display device 1 can use the light emitted from the pixel PX to provide an image. For example, each of the pixels PX can emit red light, green light, or blue light.

[0067] like Figure 2 As shown, the display area DA can have a polygonal shape such as a quadrilateral. For example, the display area DA can have a square shape, a rectangular shape whose horizontal length is greater than its vertical length, or a rectangular shape whose horizontal length is less than its vertical length. In some embodiments, the display area DA can have various shapes such as an ellipse or a circle.

[0068] The peripheral area PA can be a non-display area where no pixels PX are disposed. Drivers or similar devices for supplying electrical signals or power to the pixels PX can be disposed in the peripheral area PA. In one or more embodiments, one or more pads, to which various electronic components or printed circuit boards can be electrically connected, can be disposed in the peripheral area PA. The pads can be spaced apart from each other in the peripheral area PA and can be electrically connected to printed circuit boards or integrated circuit components.

[0069] Figure 3 This is an equivalent circuit diagram of the pixel circuit PC included in the display device 1 according to one or more embodiments. The pixel circuit PC can be electrically connected to a display element, and one display element can correspond to one pixel PX. Figure 3 In the image, organic light-emitting diodes (OLEDs) are shown as display elements.

[0070] The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The second transistor T2, acting as a switching transistor, may be connected to a scan line SL and a data line DL. The second transistor T2 can be turned on according to a switching signal received from the scan line SL to transmit a data signal received from the data line DL to the first transistor T1. The storage capacitor Cst may have one end electrically connected to the second transistor T2 and the other end electrically connected to the drive voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the second transistor T2 and the drive power supply voltage ELVDD supplied to the drive voltage line PL.

[0071] The first transistor T1, acting as the driving transistor, can be connected to the driving voltage line PL and the storage capacitor Cst. The first transistor T1 can control the magnitude of the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) in response to the value of the voltage stored in the storage capacitor Cst. The OLED can emit light with a certain brightness according to the driving current. The counter electrode of the OLED can receive the common power supply voltage ELVSS.

[0072] Figure 3 In this embodiment, the pixel circuit PC includes two transistors and one storage capacitor. However, other embodiments are not limited to this. For example, the number of transistors and the number of storage capacitors can be modified in various ways depending on the design of the pixel circuit PC.

[0073] Figure 4 It is a schematic map showing Figure 2 An enlarged plan view of area A of display device 1. For convenience, Figure 4 A plan view of the pixel defining layer 119 is shown. However, for ease of description, pixel electrodes disposed below the pixel defining layer 119 are also shown.

[0074] As described above, multiple pixels PX can be arranged in the display area DA. Each of the pixels PX can emit red, green, or blue light. A display element such as an organic light-emitting diode (OLED) can correspond to each of the pixels PX. For example, multiple display elements included in display device 1 can correspond to corresponding pixels PX of display device 1, and each of the multiple display elements can emit light. In this document, when a display element corresponds to a pixel or a pixel corresponds to a display element, it means that a pixel refers to the emitting area of ​​a display element.

[0075] like Figure 4 As shown, a pixel PX can be a first pixel PX1 that emits green light, a second pixel PX2 that emits red light, or a third pixel PX3 that emits blue light. In other words, multiple pixels PX can include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Green light is light in the wavelength range of approximately 495 nm to approximately 580 nm, red light is light in the wavelength range of approximately 580 nm to approximately 780 nm, and blue light is light in the wavelength range of approximately 400 nm to approximately 495 nm.

[0076] A stacked structure of pixel electrodes, an emitter layer, and a counter electrode can constitute a display element (e.g., an organic light-emitting diode). For example, multiple pixel electrodes can be arranged on the display area DA of substrate 100. In a plan view, the multiple pixel electrodes can be spaced apart from each other. For example, the first pixel electrode 211 and the second pixel electrode 212 can be spaced apart from each other in a first direction (e.g., the x-axis direction), and the third pixel electrode 213 can be located in the opposite direction to the second pixel electrode 212, with the first pixel electrode 211 between the third pixel electrode 213 and the second pixel electrode 212. The emitter layer 220 can be arranged on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 (as used herein, "arranged on" can mean "above").

[0077] A pixel defining layer 119 may be disposed over the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. For example, the pixel defining layer 119 may be disposed over the emitter layer 220. The pixel defining layer 119 may define a first pixel opening OP11, a second pixel opening OP12, and a third pixel opening OP13. In a plan view, the first pixel opening OP11 may overlap with the first pixel electrode 211. In a plan view, the second pixel opening OP12 may overlap with the second pixel electrode 212, and the third pixel opening OP13 may overlap with the third pixel electrode 213. Accordingly, the first pixel opening OP11 may expose the emitter layer 220 disposed on the central portion of the first pixel electrode 211. Similarly, the second pixel opening OP12 may expose the emitter layer 220 disposed on the central portion of the second pixel electrode 212. Furthermore, the third pixel opening OP13 may expose the emitter layer 220 disposed on the central portion of the third pixel electrode 213. In one or more embodiments, the electrode 230 (see...) Figure 5 It can be set on the emission layer 220.

[0078] Accordingly, a pixel opening in the pixel defining layer 119 can define an emission region of a display element. The emission region defined by the pixel opening can be defined as pixel PX. For example, the emission region defined by the first pixel opening OP11 can be defined as first pixel PX1. Similarly, the emission region defined by the second pixel opening OP12 can be defined as second pixel PX2. Furthermore, the emission region defined by the third pixel opening OP13 can be defined as third pixel PX3. Figure 4 In this embodiment, the first pixel opening OP11, the second pixel opening OP12, and the third pixel opening OP13 are substantially the same in size. However, other embodiments are not limited to this. The first pixel opening OP11, the second pixel opening OP12, and the third pixel opening OP13 may have different sizes.

[0079] exist Figure 4 The diagram illustrates a first pixel PX1, a second pixel PX2, and a third pixel PX3. However, other embodiments are not limited to this. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be repeated in a first direction (e.g., the x-axis direction) and / or a second direction (e.g., the y-axis direction). For example, based on... Figure 4 The second pixel PX2 can be arranged in the +x direction of the third pixel PX3, and the third pixel PX3 can be arranged in the -x direction of the second pixel PX2. Accordingly, the display elements corresponding to the first pixel PX1, the second pixel PX2, and the third pixel PX3, respectively, and the pixel circuits electrically connected to the respective display elements can also be repeatedly arranged in the first direction (e.g., the x-axis direction) or the second direction (e.g., the y-axis direction).

[0080] Figure 5 This is a schematic map showing the section intercepted along line I-I'. Figure 4 A cross-sectional view of the display device 1. (See figure.) Figure 5 As shown, the display device 1 may include a substrate 100.

[0081] The substrate 100 may comprise various materials having flexible or bendable properties. For example, the substrate 100 may comprise glass, metal, or polymer resin. Alternatively, the substrate 100 may comprise polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may be modified in various ways, such as by a multilayer structure comprising two layers each comprising the polymer resins described above, and a layer between the two layers comprising materials such as silicon dioxide (SiO₂). x Silicon nitride (SiN) x ) and / or silicon oxynitride (SiO) x N y The barrier layer of inorganic materials.

[0082] Multiple display elements and multiple pixel circuits electrically connected to these display elements can be arranged on the substrate 100. For example, a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3 can be arranged on the substrate 100. Each of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 can be electrically connected to a corresponding one of the first display element DPE1, the second display element DPE2, and the third display element DPE3.

[0083] Because the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 are structurally identical, the description will primarily focus on the first pixel circuit PC1. The first pixel circuit PC1 may include multiple transistors (TFTs) and a storage capacitor Cst. For ease of description, Figure 5 This shows that it can be used with the first transistor T1 (see...) Figure 3 (This corresponds to a transistor TFT.)

[0084] It can include, for example, SiO x SiN x and / or SiO x N y The inorganic material buffer layer 111 can be located between the transistor TFT and the substrate 100. The buffer layer 111 can improve the flatness of the upper surface of the substrate 100, or can prevent, reduce or minimize the penetration of impurities from the substrate 100 into the semiconductor layer Act of the transistor TFT.

[0085] like Figure 5 As shown, the transistor TFT may include a semiconductor layer Act, which may include amorphous silicon, polycrystalline silicon, organic semiconductor materials, or oxide semiconductor materials. Furthermore, the transistor TFT may include a gate electrode GE, a source electrode SE, and / or a drain electrode DE. The gate electrode GE may include various conductive materials and may have various layered structures (e.g., a molybdenum (Mo) layer and an aluminum (Al) layer). In some embodiments, the gate electrode GE may include titanium nitride (TiN). x The source electrode SE and drain electrode DE can include various conductive materials and can have various layered structures (e.g., Ti layer, Al layer and / or copper (Cu) layer).

[0086] To ensure insulation between the semiconductor layer Act and the gate electrode GE, materials such as SiO2 may be included. x SiN x and / or SiO x N y The inorganic gate insulating layer 113 can be placed between the semiconductor layer Act and the gate electrode GE. Figure 5 In this embodiment, the gate insulating layer 113 has a shape corresponding to the entire surface of the substrate 100 and a structure in which contact holes are defined in predetermined portions. However, other embodiments are not limited to this. For example, the gate insulating layer 113 may be patterned to have the same shape as the gate electrode GE.

[0087] Additionally, it can include SiO x SiN x and / or SiO x N y The first interlayer insulating layer 115 can be disposed on the gate electrode GE. The first interlayer insulating layer 115 can have one or more layers comprising the materials described above. Such an insulating layer comprising inorganic insulating materials can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). This also applies to the embodiments and modifications thereof described below.

[0088] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2, which overlap each other, and a first interlayer insulating layer 115 is placed between the first capacitor electrode CE1 and the second capacitor electrode CE2. The storage capacitor Cst may overlap with a transistor TFT. Regarding the above, Figure 5The diagram illustrates that the gate electrode GE of the transistor TFT is the first capacitor electrode CE1 of the storage capacitor Cst. However, other embodiments are not limited to this. For example, the storage capacitor Cst may not overlap with the transistor TFT. The second capacitor electrode CE2 of the storage capacitor Cst may comprise a conductive material such as Mo, Al, Cu, or Ti, and may have one or more layers comprising these materials.

[0089] It can include, for example, SiO x SiN x and / or SiO x N y The second interlayer insulating layer 117 of inorganic material can be disposed on the second capacitor electrode CE2 of the storage capacitor Cst. The second interlayer insulating layer 117 can have one or more layers including the materials described above.

[0090] The source electrode SE and drain electrode DE can be disposed on the second interlayer insulating layer 117. The source electrode SE and drain electrode DE can include materials with excellent conductivity. The source electrode SE and drain electrode DE can include conductive materials such as Mo, Al, Cu or Ti, and can have one or more layers including these materials. For example, the source electrode SE and drain electrode DE can have a Ti / Al / Ti multilayer structure.

[0091] However, other embodiments are not limited to this. For example, a transistor TFT may include only one of a source electrode SE and a drain electrode DE, or neither of them. For example, a transistor TFT may not have a drain electrode DE, another transistor TFT connected to this transistor TFT may not have a source electrode SE, and the semiconductor layers Act of the respective transistors may be connected to each other. This connection structure can produce the same effect as when this transistor TFT has a source electrode SE, the other transistor TFT has a drain electrode DE, and the source electrode SE of this transistor TFT is connected to the drain electrode DE of the other transistor TFT.

[0092] like Figure 5As shown, planarization layer 118 may cover the transistor TFT and the storage capacitor Cst. In other words, planarization layer 118 may be disposed on substrate 100. Planarization layer 118 may include organic insulating materials. For example, planarization layer 118 may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or combinations thereof. In one or more embodiments, a third interlayer insulating layer may be further disposed below planarization layer 118. The third interlayer insulating layer may include materials such as SiO2. x SiN x and / or SiO x N y Inorganic insulating materials.

[0093] Multiple display elements can be arranged on the planarization layer 118. For example, a first display element DPE1, a second display element DPE2, and a third display element DPE3 can be spaced apart from each other on the planarization layer 118. For example, the first display element DPE1 and the second display element DPE2 can be arranged on the planarization layer 118 and spaced apart from each other in a first direction (e.g., the x-axis direction), and the third display element DPE3 can be arranged on the planarization layer 118 and located on the opposite side of the second display element DPE2, with the first display element DPE1 between the third display element DPE3 and the second display element DPE2.

[0094] The first display element DPE1 may include a first pixel electrode 211, an emitter layer 220, and a counter electrode 230. The second display element DPE2 may include a second pixel electrode 212, an emitter layer 220, and a counter electrode 230. The third display element DPE3 may include a third pixel electrode 213, an emitter layer 220, and a counter electrode 230. In other words, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 provided in the first display element DPE1, the second display element DPE2, and the third display element DPE3, respectively, can be patterned. Each of the emitter layer 220 and the counter electrode 230 of the first display element DPE1, the second display element DPE2, and the third display element DPE3 may be integrally provided across the first display element DPE1, the second display element DPE2, and the third display element DPE3. In some embodiments, the emitter layer 220 and the counter electrode 230 of the first display element DPE1, the second display element DPE2, and the third display element DPE3 may be integrally provided across the entire surface of the substrate 100. The emission layer 220 can be arranged between the first pixel electrode 211, the second pixel electrode 212 and the third pixel electrode 213.

[0095] The first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 can be arranged on the planarization layer 118 and spaced apart from each other. For example, the first pixel electrode 211 and the second pixel electrode 212 can be spaced apart from each other in a first direction (e.g., the x-axis direction) and arranged on the planarization layer 118, and the third pixel electrode 213 can be arranged on the planarization layer 118 and located in the opposite direction to the second pixel electrode 212, with the first pixel electrode 211 located between the third pixel electrode 213 and the second pixel electrode 212 (e.g., the second pixel electrode 212 and the third pixel electrode 213 can be opposite to each other and the first pixel electrode 211 is between them).

[0096] The first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may include a light-transmitting conductive layer comprising a light-transmitting conductive oxide such as indium tin oxide (ITO), indium oxide (In2O3), or indium zinc oxide (IZO), and a reflective layer comprising a metal such as aluminum or silver (Ag). For example, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may have a three-layer structure of ITO / Ag / ITO.

[0097] like Figure 5As shown, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 can contact either the source electrode SE or the drain electrode DE, and can be electrically connected to the transistor TFT. For example, each of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 can contact either the source electrode SE or the drain electrode DE through a contact hole defined in the planarization layer 118.

[0098] The emitting layer 220 can be disposed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. In other words, the emitting layer 220 can be disposed across the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. For example, the emitting layer 220 can be provided as a single unit, or it can be provided as a single unit substantially across the entire surface of the substrate 100. Accordingly, the emitting layer 220 can be provided as a single unit across the first display element DPE1, the second display element DPE2, and the third display element DPE3. In other words, the emitting layer 220 can be provided as a single unit over the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213.

[0099] Accordingly, a portion of the emission layer 220 may be disposed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 (as used herein, the singular "part" and the plural "part" may be interchanged as needed for description). Some portions of the emission layer 220 may be disposed between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. Additionally, a portion of the emission layer 220 may be disposed between the second pixel electrode 212 and the third pixel electrode 213. For example, some portions of the emission layer 220 may be disposed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. In other words, the emission layer 220 may cover the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213.

[0100] Because the emitter layer 220 is integrally formed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213, the emitter layer 220 can have a substantially uniform thickness. For example, the portion of the emitter layer 220 disposed on the first pixel electrode 211 can have a substantially uniform thickness. Similarly, the portion of the emitter layer 220 disposed on the second pixel electrode 212 can have a substantially uniform thickness. Furthermore, the portion of the emitter layer 220 disposed on the third pixel electrode 213 can have a substantially uniform thickness.

[0101] Meanwhile, the thickness of the portion of the emitter layer 220 disposed on the first pixel electrode 211 can be greater than the thickness of the first pixel electrode 211. Similarly, the thickness of the portion of the emitter layer 220 disposed on the second pixel electrode 212 can be greater than the thickness of the second pixel electrode 212. Furthermore, the thickness of the portion of the emitter layer 220 disposed on the third pixel electrode 213 can be greater than the thickness of the third pixel electrode 213. For example, the thickness of each of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 can be approximately 100 nm, and the thickness of the portion of the emitter layer 220 disposed on the first pixel electrode 211, the second pixel electrode 212, or the third pixel electrode 213 can be from approximately 100 nm to approximately 500 nm.

[0102] The emitting layer 220 can emit red, green, or blue light. The emitting layer 220 may comprise organic materials, inorganic materials, or quantum dots. In some embodiments, the emitting layer 220 may comprise organic materials and quantum dots, or it may comprise inorganic materials and quantum dots. For example, the emitting layer 220 may comprise a polymer or a low-molecular-weight organic material capable of emitting light of a specific color (red, green, and blue). For example, the emitting layer 220 may comprise a polymer material based on polyphenylene acetylene (PPV) or polyfluorene. This emitting layer 220 can be formed using methods such as spin coating, slot coating, or inkjet printing. However, other embodiments are not limited thereto.

[0103] In one or more embodiments, a functional layer may be disposed below and / or above the emitter layer 220. The functional layer may include a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and / or an electron injection layer (EIL). This functional layer may be integrally provided across the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. Furthermore, similar to the emitter layer 220, the functional layer can be formed using methods such as spin coating, slot coating, or inkjet printing, and, as in the case of the emitter layer 220, substantially uniform film thickness achieved through this disclosure can be ensured.

[0104] The counter electrode 230 can be disposed on the emitter layer 220. The counter electrode 230 can be integrally provided across the entire surface of the substrate 100. Accordingly, the counter electrode 230 can be integrally provided across the first display element DPE1, the second display element DPE2, and the third display element DPE3. In other words, the counter electrode 230 can be integrally provided over the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. Accordingly, the counter electrode 230 can be disposed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. Furthermore, the emitter layer 220 can be disposed between the first pixel electrode 211 and the counter electrode 230, between the second pixel electrode 212 and the counter electrode 230, and between the third pixel electrode 213 and the counter electrode 230.

[0105] The counter electrode 230 may include a light-transmitting conductive layer comprising ITO, In2O3, or IZO, and may include a semi-transmitting film comprising a metal such as Al or Ag. For example, the counter electrode 230 may be a semi-transmitting film comprising magnesium (Mg) or silver.

[0106] Pixel defining layer 119 may be located between emitter layer 220 and counter electrode 230. As described above, pixel defining layer 119 may define a first pixel opening OP11, a second pixel opening OP12, and a third pixel opening OP13. When viewed from a direction perpendicular to substrate 100 (e.g., in a plan view), the first pixel opening OP11 may overlap with the first pixel electrode 211. When viewed from a direction perpendicular to substrate 100, the second pixel opening OP12 may overlap with the second pixel electrode 212, and the third pixel opening OP13 may overlap with the third pixel electrode 213.

[0107] Accordingly, it is shown schematically. Figure 5 Enlarged cross-sectional view of area B of display device 1 Figure 6 As shown, a portion of the emitting layer 220 may be disposed between the portion of the pixel defining layer 119 adjacent to the first pixel opening OP11 and a portion of the first pixel electrode 211, and another portion of the emitting layer 220 may be disposed between the portion of the counter electrode 230 overlapping with the first pixel opening OP11 and another portion of the first pixel electrode 211.

[0108] Similarly, a portion of the emitter layer 220 may be disposed between the portion of the pixel defining layer 119 adjacent to the second pixel opening OP12 and a portion of the second pixel electrode 212, and another portion of the emitter layer 220 may be disposed between the portion of the counter electrode 230 overlapping with the second pixel opening OP12 and another portion of the second pixel electrode 212. Furthermore, a portion of the emitter layer 220 may be disposed between the portion of the pixel defining layer 119 adjacent to the third pixel opening OP13 and a portion of the third pixel electrode 213, and another portion of the emitter layer 220 may be disposed between the portion of the counter electrode 230 overlapping with the third pixel opening OP13 and another portion of the third pixel electrode 213.

[0109] The pixel defining layer 119 defines a pixel by defining an opening corresponding to the pixel (e.g., an opening in the emitter layer 220 disposed on at least the central portion of the pixel electrode). Additionally, the pixel defining layer 119 can increase the distance between the edge of the pixel electrode and the counter electrode 230 on the pixel electrode. This reduces or prevents the possibility of damage to the display element at the edge of the pixel electrode (e.g., a short circuit caused by electric field concentration). Such a pixel defining layer 119 can comprise an organic material such as polyimide or HMDSO.

[0110] The encapsulation layer 300 can be disposed on the first display element DPE1, the second display element DPE2, and the third display element DPE3. For example, the encapsulation layer 300 can be disposed on the counter electrode 230. In other words, because the display elements DPE1, DPE2, and DPE3 may be damaged by moisture or oxygen from the outside, the encapsulation layer 300 can cover and protect the first display element DPE1, the second display element DPE2, and the third display element DPE3.

[0111] The encapsulation layer 300 may include at least one inorganic layer and at least one organic layer. For example, such as Figure 5 As shown, the encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330. For example, the encapsulation layer 300, which includes the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 330, and the organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330, may be disposed on the counter electrode 230.

[0112] The first inorganic encapsulation layer 310 may cover the counter electrode 230 and may include SiO2. x SiN x and / or SiO x N y .like Figure 5As shown, because the first inorganic encapsulation layer 310 can be formed along the structure below it, the upper surface of the first inorganic encapsulation layer 310 may not be flat. The organic encapsulation layer 320 may cover the first inorganic encapsulation layer 310, but unlike the first inorganic encapsulation layer 310, the upper surface of the organic encapsulation layer 320 may be approximately flat.

[0113] The organic encapsulation layer 320 may comprise one or more materials selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and HMDSO. The second inorganic encapsulation layer 330 may cover the organic encapsulation layer 320 and may include SiO₂. x SiN x and / or SiO x N y .

[0114] As described above, the encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330. Therefore, even if cracks appear in the encapsulation layer 300 due to this multi-layer structure, such cracks will not connect or extend between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320, or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330. Thus, the formation of external moisture or oxygen through its permeation into the display device 1 can be prevented, reduced, or minimized.

[0115] The light-shielding portion 410, the first color conversion layer 451, the second color conversion layer 452, and the light-transmitting layer 453 can be disposed on the encapsulation layer 300. The first color conversion layer 451, the second color conversion layer 452, and the light-transmitting layer 453 can transmit light emitted from the display element, or can convert light emitted from the display element into light of a corresponding color. The light transmitted by the first color conversion layer 451, the second color conversion layer 452, or the light-transmitting layer 453, or the light whose color has been converted by the first color conversion layer 451, the second color conversion layer 452, or the light-transmitting layer 453, can be one of green light, red light, and blue light. The first color conversion layer 451, the second color conversion layer 452, and the light-transmitting layer 453 can be spaced apart at a specific interval, and the light-shielding portion 410 can be located between the first color conversion layer 451, the second color conversion layer 452, and the light-transmitting layer 453. Therefore, the light-shielding wall portion 410 can reduce or prevent color mixing between the light converted or transmitted in the first color conversion layer 451, the second color conversion layer 452 and the light-transmitting layer 453.

[0116] The light-shielding portion 410 may define a first color conversion opening OP21, a second color conversion opening OP22, and a third color conversion opening OP23 (e.g., a light-transmitting opening). The first color conversion opening OP21 may overlap with the first pixel opening OP11, the second color conversion opening OP22 may overlap with the second pixel opening OP12, and the third color conversion opening / light-transmitting opening OP23 may overlap with the third pixel opening OP13. Thus, the first color conversion opening OP21 may correspond to the first display element DPE1, the second color conversion opening OP22 may correspond to the second display element DPE2, and the third color conversion opening / light-transmitting opening OP23 may correspond to the third display element DPE3.

[0117] The light-shielding wall portion 410 can be provided in various colors such as black, white, red, purple, or blue. The light-shielding wall portion 410 may include colored pigments or dyes. The light-shielding wall portion 410 may include a light-shielding material, and the light-shielding material may include an opaque inorganic insulating material comprising metal oxides such as titanium dioxide (TiO2), chromium oxide (Cr2O3), or molybdenum oxide (MoO3), or may include an opaque organic insulating material such as black resin. In another example, the light-shielding wall portion 410 may include an organic insulating material such as white resin.

[0118] A first color conversion layer 451 may be disposed in a first color conversion opening OP21, a second color conversion layer 452 may be disposed in a second color conversion opening OP22, and a light-transmitting layer 453 may be disposed in a third color conversion opening OP23 (e.g., a light-transmitting opening). The diagram illustrates the first color conversion layer 451, the second color conversion layer 452, and the light-transmitting layer 453 included in the display device 1. Figure 7 As shown, according to one or more embodiments, incident light Lib can be incident on the first color conversion layer 451, the second color conversion layer 452, and the light-transmitting layer 453. The incident light Lib can be light emitted by the first display element DPE1, the second display element DPE2, and the third display element DPE3. For example, the incident light Lib can be blue light having a wavelength range of approximately 400 nm to approximately 495 nm. The incident light Lib emitted from the display elements can be transmitted or converted into green, red, and blue light while passing through the first color conversion layer 451, the second color conversion layer 452, or the light-transmitting layer 453, enabling the display device 1 to generate a color image.

[0119] For example, the first color conversion layer 451 can convert blue incident light Lib into green light Lg. To this end, the first color conversion layer 451 may include a first photosensitive polymer 451a in which first quantum dots 451b are dispersed.

[0120] The first photosensitive polymer 451a may be a transparent organic material such as silicone or epoxy resin. The first quantum dot 451b may be excited by blue incident light Lib to isotropically emit green light Lg with a wavelength longer than that of blue light. The first quantum dot 451b may include group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV compounds, or combinations thereof.

[0121] The first scattering particles 451c can be further dispersed in the first photosensitive polymer 451a. The first scattering particles 451c can scatter the blue incident light Lib that is not absorbed by the first quantum dot 451b, so as to excite more first quantum dots 451b, thereby improving the color conversion efficiency of the first color conversion layer 451. The first scattering particles 451c can be, for example, TiO2 or metal particles.

[0122] The second color conversion layer 452 can convert blue incident light Lib into red light Lr. The second color conversion layer 452 may include a second photosensitive polymer 452a in which second quantum dots 452b are dispersed, and the second scattering particles 452c may be dispersed together with the second quantum dots 452b in the second photosensitive polymer 452a, thereby increasing the color conversion efficiency of the second color conversion layer 452.

[0123] The second photosensitive polymer 452a may comprise the same material as the first photosensitive polymer 451a, and the second scattering particle 452c may comprise the same material as the first scattering particle 451c. The second quantum dot 452b may comprise a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV compound, or a combination thereof. In other words, the second quantum dot 452b may comprise the same material as the first quantum dot 451b. However, the size of the second quantum dot 452b may be larger than the size of the first quantum dot 451b. Therefore, the second quantum dot 452b can be excited by blue incident light Lib and can isotropically emit red light Lr with a wavelength larger than that of green light Lg and larger than that of blue light Lb.

[0124] The light-transmitting layer 453 may include a third photosensitive polymer 453a in which third scattering particles 453c are dispersed. In other words, the light-transmitting layer 453 may omit the additional quantum dots that can be excited by blue incident light Lib. Similarly to the first photosensitive polymer 451a, the third photosensitive polymer 453a may include a light-transmitting organic material, and the third scattering particles 453c may include the same material as the first scattering particles 451c. Therefore, the blue incident light Lib incident on the light-transmitting layer 453 can pass through the light-transmitting layer 453 without color change, and thus, the light emitted through the light-transmitting layer 453 can be blue light Lb. However, the blue incident light Lib can be scattered by the third scattering particles 453c within the light-transmitting layer 453 and can be emitted to the outside. The light-transmitting layer 453 can transmit the blue incident light Lib incident on it without color change, thereby achieving higher light efficiency.

[0125] A capping layer 470 may be disposed on the first color conversion layer 451, the second color conversion layer 452, and the light-transmitting layer 453. Accordingly, the first color conversion layer 451, the second color conversion layer 452, and the light-transmitting layer 453 may be located between the encapsulation layer 300 and the capping layer 470. The capping layer 470 may cover the first color conversion layer 451, the second color conversion layer 452, and the light-transmitting layer 453. The capping layer 470 may include materials such as SiO2. x SiN x and / or SiO x N y Inorganic materials.

[0126] The quantum dots included in each of the first color conversion layer 451 and the second color conversion layer 452 comprise nanoparticles and, therefore, may degrade by reacting with moisture or oxygen. The encapsulation layer 300 and the capping layer 470 can cover the first color conversion layer 451 and the second color conversion layer 452 respectively below and above them, such that little to no moisture or oxygen permeates into the quantum dots in the first color conversion layer 451 and the second color conversion layer 452.

[0127] exist Figure 5 In this embodiment, the display element and color conversion layer of the display device 1 are formed on a single substrate. However, other embodiments are not limited to this. For example, the display element and encapsulation layer 300 may be formed on a lower substrate, and the color conversion layer and light-shielding wall portion 410 may be formed on an upper substrate. The lower substrate and the upper substrate may then be attached to each other to constitute the display device 1.

[0128] Figure 8 This is a schematic diagram showing a cross-sectional view of a display device 1 according to one or more embodiments. Figure 8The display device 1 and the above reference Figures 1 to 7 The described display device 1 is similar, and therefore, the following description focuses primarily on the aspects mentioned above. Figures 1 to 7 The differences are as described in display device 1. Figure 8 In, with Figures 1 to 7 The same reference numerals in the accompanying drawings denote the same components, and redundant descriptions are omitted.

[0129] In Figures 1 to 7 In the corresponding display device 1, some portions of the emitting layer 220 may be disposed between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. For example, some portions of the emitting layer 220 may be disposed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. Furthermore, in Figure 8 In the display device 1, some portions of the emitting layer 220 may be arranged between the first pixel electrode 211 and the second pixel electrode 212 and between the first pixel electrode 211 and the third pixel electrode 213.

[0130] In Figures 1 to 7 In the corresponding display device 1, the portions of the emitter layer 220 arranged between the first pixel electrode 211 and the second pixel electrode 212 and between the first pixel electrode 211 and the third pixel electrode 213 can directly contact the planarization layer 118.

[0131] However, as Figure 8 As shown, in the display device 1, the portions of the emitter layer 220 disposed between the first pixel electrode 211 and the second pixel electrode 212 and between the first pixel electrode 211 and the third pixel electrode 213 may not be in direct contact with the planarization layer 118 (for example, they may be spaced apart from the planarization layer 118).

[0132] For example, such as Figure 8 As shown, the display device 1 may include a planarization auxiliary layer 118A. The planarization auxiliary layer 118A may be disposed on the planarization layer 118 and may be located between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213, and may directly contact the planarization layer 118. In this case, the portions of the emitter layer 220 (e.g., in a plan view) disposed between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213, may directly contact the planarization auxiliary layer 118A. In other words, the planarization auxiliary layer 118A may be located (e.g., directly) between the planarization layer 118 and the emitter layer 220.

[0133] The upper surface of this planarization auxiliary layer 118A can form a flat surface (e.g., substantially coplanar with) the upper surfaces of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. In other words, the upper surfaces of the planarization auxiliary layer 118A, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 can form a flat surface (e.g., substantially coplanar). Therefore, the emitter layer 220, integrally formed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213, can have a substantially uniform thickness.

[0134] Meanwhile, the planarization auxiliary layer 118A may include the same material as the planarization layer 118. For example, the planarization auxiliary layer 118A may include an organic insulating material. For example, the planarization auxiliary layer 118A may include photoresist, BCB, polyimide, HMDSO, PMMA, polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or combinations thereof.

[0135] Figure 9 This is a schematic diagram showing a cross-sectional view of a display device 1 according to one or more embodiments. Figure 9 The display device 1 and the above reference Figures 1 to 7 The described display device 1 is similar, and therefore, the following description focuses primarily on the aspects mentioned above. Figures 1 to 7 The differences are as described in display device 1. Figure 9 In, with Figures 1 to 7 The same reference numerals in the accompanying drawings denote the same components, and redundant descriptions are omitted.

[0136] The above references Figures 1 to 7 In the described display device 1, some portions of the emissive layer 220 may be disposed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. Furthermore, in Figure 9 In the display device 1, some portions of the emitting layer 220 may be disposed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212 and between the first pixel electrode 211 and the third pixel electrode 213.

[0137] The above references Figures 1 to 7 In the described display device 1, the emission layer 220 can be integrally provided across the entire surface of the substrate 100.

[0138] However, as Figure 9 As shown, in display device 1, the emission layer 220 may be provided integrally without spanning the entire surface of the substrate 100. In other words, the emission layer 220 may be disposed only on a portion(s) of the planarization layer 118 disposed on the substrate 100. For example, the emission layer 220 may include multiple sub-emission layers. The multiple sub-emission layers may be disposed on the planarization layer 118 and may be spaced apart from each other.

[0139] For example, the emission layer 220 may include a first emission layer 221, a second emission layer 222, and a third emission layer 223. The first emission layer 221, the second emission layer 222, and the third emission layer 223 may be disposed on the planarization layer 118 and may be spaced apart from each other. The first emission layer 221 may be disposed between the first pixel electrode 211 and the counter electrode 230, the second emission layer 222 may be disposed between the second pixel electrode 212 and the counter electrode 230, and the third emission layer 223 may be disposed between the third pixel electrode 213 and the counter electrode 230.

[0140] In this configuration, the portions of the pixel defining layer 119 disposed between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213, can directly contact the planarization layer 118. For example, the portions of the pixel defining layer 119 disposed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213, can directly contact the planarization layer 118. Furthermore, in this configuration, a portion of the first emitting layer 221 can be disposed between the portion of the pixel defining layer 119 adjacent to the first pixel opening OP11 and a portion of the first pixel electrode 211, and another portion of the first emitting layer 221 can be disposed between the portion of the counter electrode 230 overlapping the first pixel opening OP11 and another portion of the first pixel electrode 211.

[0141] Similarly, a portion of the second emission layer 222 may be disposed between the portion of the pixel defining layer 119 adjacent to the second pixel opening OP12 and a portion of the second pixel electrode 212, and another portion of the second emission layer 222 may be disposed between the portion of the counter electrode 230 overlapping with the second pixel opening OP12 and another portion of the second pixel electrode 212. Furthermore, a portion of the third emission layer 223 may be disposed between the portion of the pixel defining layer 119 adjacent to the third pixel opening OP13 and a portion of the third pixel electrode 213, and another portion of the third emission layer 223 may be disposed between the portion of the counter electrode 230 overlapping with the third pixel opening OP13 and another portion of the third pixel electrode 213.

[0142] Generally, when any one layer is commonly provided across multiple display elements, leakage current can flow through that layer between the multiple display elements. In this case, the display quality of the display device may deteriorate, and for example, the color purity of the display device may decrease. However, in display device 1, the portions of the emitting layer 220 included in the first display element DPE1, the portions of the emitting layer 220 included in the second display element DPE2, and the portions of the emitting layer 220 included in the third display element DPE3 can be spaced apart from each other. In other words, these portions of the emitting layer 220 included in the first display element DPE1, the portions of the emitting layer 220 included in the second display element DPE2, and the portions of the emitting layer 220 included in the third display element DPE3 can be disconnected from each other. Therefore, the amount of leakage current flowing between the display elements through the emitting layer 220 can be reduced or eliminated. Therefore, the display quality of display device 1 is not degraded.

[0143] Figure 10 This is a schematic diagram showing a cross-sectional view of a display device 1 according to one or more embodiments. Figure 10 The display device 1 and the above reference Figure 8 The described display device 1 is similar, and therefore, the following description focuses primarily on the aspects mentioned above. Figure 8 The differences are as described in display device 1. Figure 10 In, with Figure 8 The same reference numerals in the accompanying drawings denote the same components, and redundant descriptions are omitted.

[0144] The above references Figure 8 In the described display device 1, the display device 1 may include a planarization auxiliary layer 118A. (Referring to the above references...) Figure 8 In the described display device 1, the upper surfaces of the planarization auxiliary layer 118A, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 can form flat surfaces, and the planarization auxiliary layer 118A can include the same material as the planarization layer 118. Furthermore, the display device 1 may include the planarization auxiliary layer 118A. Figure 10 In the display device 1, the upper surface of the planarization auxiliary layer 118A, the upper surface of the first pixel electrode 211, the upper surface of the second pixel electrode 212 and the upper surface of the third pixel electrode 213 can form a flat surface, and the planarization auxiliary layer 118A can include the same material as the planarization layer 118.

[0145] The above references Figure 8 In the described display device 1, the emission layer 220 can be integrally provided across the entire surface of the substrate 100.

[0146] However, as Figure 10 As shown, in display device 1, the emission layer 220 may be provided integrally without spanning the entire surface of the substrate 100. In other words, the emission layer 220 may be disposed only on a portion(s) of the planarization layer 118 disposed on the substrate 100. For example, the emission layer 220 may include multiple sub-emission layers. The multiple sub-emission layers may be disposed on the planarization layer 118 and may be spaced apart from each other.

[0147] For example, the emission layer 220 may include a first emission layer 221, a second emission layer 222, and a third emission layer 223. The first emission layer 221, the second emission layer 222, and the third emission layer 223 may be disposed on the planarization layer 118 and may be spaced apart from each other. The first emission layer 221 may be disposed between the first pixel electrode 211 and the counter electrode 230, the second emission layer 222 may be disposed between the second pixel electrode 212 and the counter electrode 230, and the third emission layer 223 may be disposed between the third pixel electrode 213 and the counter electrode 230.

[0148] In this configuration, the portions of the pixel defining layer 119 disposed between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213, can directly contact the planarization auxiliary layer 118A. For example, the portions of the pixel defining layer 119 disposed on (e.g., above) the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213, can directly contact the planarization auxiliary layer 118A. Furthermore, in this configuration, a portion of the first emitting layer 221 can be disposed between the portion of the pixel defining layer 119 adjacent to the first pixel opening OP11 and a portion of the first pixel electrode 211, and another portion of the first emitting layer 221 can be disposed between the portion of the counter electrode 230 overlapping the first pixel opening OP11 and another portion of the first pixel electrode 211.

[0149] Similarly, a portion of the second emission layer 222 may be disposed between the portion of the pixel defining layer 119 adjacent to the second pixel opening OP12 and a portion of the second pixel electrode 212, and another portion of the second emission layer 222 may be disposed between the portion of the counter electrode 230 overlapping with the second pixel opening OP12 and another portion of the second pixel electrode 212. Furthermore, a portion of the third emission layer 223 may be disposed between the portion of the pixel defining layer 119 adjacent to the third pixel opening OP13 and a portion of the third pixel electrode 213, and another portion of the third emission layer 223 may be disposed between the portion of the counter electrode 230 overlapping with the third pixel opening OP13 and another portion of the third pixel electrode 213.

[0150] References above Figure 9 Similarly, in the described display device 1, the portions of the emitter layer 220 included in the first display element DPE1, the portions of the emitter layer 220 included in the second display element DPE2, and the portions of the emitter layer 220 included in the third display element DPE3 can be disconnected from each other. Therefore, the amount of leakage current flowing between the display elements through the emitter layer 220 can be reduced or eliminated. Consequently, the display quality of the display device 1 is not degraded.

[0151] Figures 11 to 15 It is a schematic map showing the manufacturing process. Figure 5 A cross-sectional view of a portion of the manufacturing process of display device 1. For example, Figures 11 to 15 It is a schematic map showing the formation Figure 5 A cross-sectional view of the manufacturing process of the pixel electrode, emitter layer 220, pixel defining layer 119, and counter electrode 230 of the display device 1. For ease of description, in Figures 11 to 15 In the middle, based on the intercept along line I-I' Figure 4 A cross-section of the display device 1, describing its manufacturing process. Figure 5 This is part of the process of display device 1.

[0152] First, such as Figure 11As shown, a first pixel electrode 211 can be formed on the planarization layer 118. In addition, a second pixel electrode 212 and a third pixel electrode 213 can be formed on the planarization layer 118. For example, the second pixel electrode 212 can be formed on the planarization layer 118 to be spaced apart from the first pixel electrode 211 in a first direction (e.g., along the x-axis). The third pixel electrode 213 can be formed on the planarization layer 118 and can be located in the opposite direction to the second pixel electrode 212, with the first pixel electrode 211 between the third pixel electrode 213 and the second pixel electrode 212 (e.g., the second pixel electrode 212 and the third pixel electrode 213 can be opposite to each other with the first pixel electrode 211 between them). In other words, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 can be formed on the planarization layer 118.

[0153] Simultaneously, a planarization layer 118 can be formed on the substrate 100. Before the planarization layer 118 is formed on the substrate 100, a pixel circuit PC can be formed on the substrate 100. For example, a buffer layer 111 can be formed on the substrate 100, a semiconductor layer Act can be formed on the buffer layer 111, a gate insulating layer 113 can be formed on the semiconductor layer Act, and a gate electrode GE can be formed on the gate insulating layer 113. The gate electrode GE can be the first capacitor electrode CE1 of the storage capacitor Cst. Next, a first interlayer insulating layer 115 can be formed on the gate electrode GE, and a second capacitor electrode CE2 can be formed on the first interlayer insulating layer 115. Next, a second interlayer insulating layer 117 can be formed on the second capacitor electrode CE2. Next, a source electrode SE and a drain electrode DE can be formed on the second interlayer insulating layer 117, and a planarization layer 118 can be formed on the source electrode SE and the drain electrode DE. This formation of the planarization layer 118 and the pixel circuit PC can be performed by photolithography or the like, and a detailed description related to it is omitted.

[0154] Next, in one or more embodiments, contact holes may be defined in the planarization layer 118 such that each of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 can contact either the source electrode SE or the drain electrode DE, and then a preliminary pixel electrode layer may be formed on the planarization layer 118 to correspond to the entire surface of the substrate 100. The first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may be formed by patterning such a preliminary pixel electrode layer. In other words, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may be formed on the planarization layer 118 formed on the substrate 100.

[0155] The first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may include a light-transmitting conductive layer comprising a light-transmitting conductive oxide such as ITO, In2O3, or IZO, and a reflective layer comprising a metal such as Al or Ag. For example, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may have a three-layer structure of ITO / Ag / ITO.

[0156] Next, as Figure 12 As shown, the emission layer 220 can be formed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. For example, the emission layer 220 can be integrally formed across the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. For example, the emission layer 220 can be formed on the entire surface of the substrate 100. Accordingly, a portion of the emission layer 220 can be formed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213, and some portions of the emission layer 220 can also be formed between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. For example, some portions of the emission layer 220 can be formed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. In addition, a portion of the emission layer 220 can be formed between the second pixel electrode 212 and the third pixel electrode 213.

[0157] The emitter layer 220 may comprise a polymeric material based on PPV or polyfluorene. As described below, a pixel defining layer 119 is formed on the emitter layer 220, and therefore, the material included in the emitter layer 220 may not dissolve in the solvent included in the pixel defining layer forming material 119P. When a functional layer including a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), or an electron injection layer (EIL) is disposed on the emitter layer 220, similar to the material included in the emitter layer 220, the material included in the functional layer may not dissolve in the solvent included in the pixel defining layer forming material 119P.

[0158] Next, as Figure 13 and Figure 14 As shown, the pixel defining layer 119 can be formed on the emission layer 220. For example, as... Figure 13As shown, by using an inkjet printing method, the pixel defining layer forming material 119P can be coated between the central portions of the first pixel electrode 211 and the second pixel electrode 212, and between the central portions of the first pixel electrode 211 and the third pixel electrode 213. In other words, by using an inkjet printing method, the pixel defining layer forming material 119P can be coated onto the emitter layer 220 between the central portions of the first pixel electrode 211 and the second pixel electrode 212, and between the central portions of the first pixel electrode 211 and the third pixel electrode 213.

[0159] The pixel-defining layer forming material 119P can be a solution prepared by mixing an organic material, such as polyimide or HMDSO, with a solvent. The pixel-defining layer forming material 119P may include materials that can undergo a crosslinking reaction at a temperature lower than the temperature at which the material included in the emitter layer 220 deteriorates. For example, the pixel-defining layer forming material 119P can be made of UBE. TM UPIA-LB2001 manufactured by UPIA TM and UBE TM (It is a registered trademark of UBE Corporation of Japan), by TORAY TM Photoneece-LT (PHOTONEECE) manufactured TM and TORAY TM (It is a registered trademark of Toray Industries, Inc. of Japan) or by ZEON TM The manufactured ZEOCOAT-ZC100 (ZEOCOAT TM and ZEON TM It is a registered trademark of ZEON Corporation of Japan.

[0160] For example, an inkjet head IH including multiple nozzles can be used for inkjet printing. In other words, the multiple nozzles included in the inkjet head IH can be arranged on the emitter layer 220 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. By using the multiple nozzles of the inkjet head IH, a pixel defining layer forming material 119P can be coated onto the emitter layer 220 between the central portion of the first pixel electrode 211 and the central portion of the second pixel electrode 212, and between the central portion of the first pixel electrode 211 and the central portion of the third pixel electrode 213.

[0161] However, the multiple nozzles included in the inkjet head IH can even be arranged on the emitter layer 220 between the second pixel electrode 212 and the third pixel electrode 213, and the pixel defining layer forming material 119P can be coated between the central portion of the second pixel electrode 212 and the central portion of the third pixel electrode 213 using the multiple nozzles of the inkjet head IH. In other words, the pixel defining layer forming material 119P can be coated on the emitter layer 220 except for the portions of the emitter layer 220 that correspond to the first pixel opening OP11, the second pixel opening OP12, and the third pixel opening OP13, respectively. However, the method of coating the pixel defining layer forming material 119P disclosed herein is not limited to inkjet printing methods. For the method of coating the pixel defining layer forming material 119P disclosed herein, any method that optionally coats the pixel defining layer forming material 119P only at the location where the pixel defining layer 119 is formed can be used.

[0162] Next, as Figure 14 As shown, the pixel defining layer 119 can be formed by performing heat treatment on the pixel defining layer forming material 119P. For example, the pixel defining layer forming material 119P can be dried or heated. In some embodiments, the pixel defining layer forming material 119P can be dried at a first temperature to remove a portion of the solvent included in the pixel defining layer forming material 119P, and then the pixel defining layer forming material 119P can be heated to a second temperature above the first temperature. For example, the pixel defining layer forming material 119P can be dried at room temperature to remove a portion of the solvent included in the pixel defining layer forming material 119P, and then the pixel defining layer forming material 119P can be heat-treated by heating to about 100°C to about 200°C.

[0163] However, the heat treatment conditions for the pixel defining layer forming material 119P are not necessarily limited to this. Any heat treatment conditions typically performed after coating the organic film forming material to form the organic film can be used as the heat treatment conditions for the pixel defining layer forming material 119P. Therefore, a detailed description related to this is omitted. For example, when the pixel defining layer forming material 119P is from UBE... TM When using UPIA-LB2001, the pixel-defining layer forming material 119P can be dried at room temperature and then heated to approximately 150°C. When the pixel-defining layer forming material 119P is from TORAY... TM In Photoneece-LT, the pixel-defining layer forming material 119P can be dried at room temperature and then heated to approximately 170°C. When the pixel-defining layer forming material 119P is from ZEON... TMWhen using ZEOCOAT-ZC100, the pixel-defining layer forming material 119P can be dried at room temperature and then heated to approximately 180°C.

[0164] The pixel defining layer forming material 119P forming the pixel defining layer 119 is coated on the emitter layer 220 between the central portions of the first pixel electrode 211 and the second pixel electrode 212, between the central portions of the first pixel electrode 211 and the third pixel electrode 213, and between the central portions of the second pixel electrode 212 and the third pixel electrode 213. Therefore, the pixel defining layer 119 can define a first pixel opening OP11, a second pixel opening OP12, and a third pixel opening OP13. In a plan view, the first pixel opening OP11 can overlap with the first pixel electrode 211. Accordingly, a portion of the emitter layer 220 can be disposed between the portion of the pixel defining layer 119 adjacent to the first pixel opening OP11 and a portion of the first pixel electrode 211. Simultaneously, in a plan view, the second pixel opening OP12 can overlap with the second pixel electrode 212, and the third pixel opening OP13 can overlap with the third pixel electrode 213.

[0165] Generally, after coating the pixel defining layer forming material onto the entire surface of a substrate and performing heat treatment on the pixel defining layer forming material, pixel openings are formed by photolithography or the like, thereby forming a pixel defining layer. However, when an emitter layer is formed before forming the pixel defining layer, the emitter layer disposed under the pixel defining layer forming material may be damaged during the process of coating the pixel defining layer forming material onto the entire surface of the substrate and performing photolithography. However, in the method of manufacturing the display device 1, the pixel defining layer forming material 119P is only coated onto the emitter layer 220 except for the portions corresponding to the first pixel opening OP11, the second pixel opening OP12, and the third pixel opening OP13, and therefore, the photolithography process for defining the pixel openings in the pixel defining layer 119 can be omitted. Therefore, the emitter layer 220 is not damaged during the process of forming the pixel defining layer 119.

[0166] Next, as Figure 15 As shown, counter electrode 230 can be formed on pixel defining layer 119. Pixel defining layer 119 can be formed on emitter layer 220, and emitter layer 220 can be formed on first pixel electrode 211, second pixel electrode 212, and third pixel electrode 213. In other words, counter electrode 230 can be formed on first pixel electrode 211, second pixel electrode 212, and third pixel electrode 213.

[0167] For example, the counter electrode 230 can be integrally formed to correspond to the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. Therefore, the counter electrode 230 can completely overlap with the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. Because the first pixel opening OP11 overlaps with the first pixel electrode 211, a portion of the emitter layer 220 can be disposed between a portion of the counter electrode 230 and a portion of the first pixel electrode 211, these portions overlapping the first pixel opening OP11. Similarly, a portion of the emitter layer 220 can be disposed between a portion of the counter electrode 230 and a portion of the second pixel electrode 212, these portions overlapping the second pixel opening OP12. Furthermore, a portion of the emitter layer 220 can be disposed between a portion of the counter electrode 230 and a portion of the third pixel electrode 213, these portions overlapping the third pixel opening OP13.

[0168] The counter electrode 230 may include a transparent conductive layer comprising ITO, In2O3, or IZO, and may include a semi-transparent film comprising a metal such as Al or Ag. For example, the counter electrode 230 may be a semi-transparent film comprising magnesium (Mg) or silver (Ag).

[0169] Generally, an emitter layer is formed by coating an emitter layer forming material into a pixel opening defined in a pixel defining layer and then drying it. The emitter layer forming material is a solution prepared by mixing an organic material forming the emitter layer with a solvent. In this case, during the drying process of the emitter layer forming material, the solid components included in the emitter layer forming material (e.g., the organic material included in the emitter layer) move towards the edge of the pixel opening. Therefore, the thickness of the portion of the emitter layer adjacent to the pixel opening can be greater than the thickness of the portion of the emitter layer spaced apart from the pixel opening. In other words, the portion of the emitter layer formed on the pixel electrode may not have a substantially uniform thickness. In other words, when the emitter layer is formed by coating an emitter layer forming material into a pixel opening defined in a pixel defining layer and then drying it, a coffee ring effect occurs during the drying process of the emitter layer forming material.

[0170] However, in the method of manufacturing the display device 1, before forming the pixel defining layer 119, the emission layer 220 can be integrally formed across the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. Therefore, the portion of the emission layer 220 formed on the pixel electrodes has a substantially uniform thickness. For example, the portion of the emission layer 220 formed on the first pixel electrode 211 can have a substantially uniform thickness. Furthermore, the portions of the emission layer 220 formed on the second pixel electrode 212 and the portions of the emission layer 220 formed on the third pixel electrode 213 can also have substantially uniform thicknesses. Therefore, the emission efficiency of the display device 1 can be improved.

[0171] Figures 16 to 18 This is a schematic cross-sectional view used to describe a method of manufacturing a display device 1 according to one or more embodiments. For example, Figures 16 to 18 It is a schematic map showing the formation Figure 8 A cross-sectional view of the process of manufacturing the emitter layer 220 of the display device 1. The method for manufacturing the display device 1 is consistent with the reference. Figures 11 to 15 The following description corresponds to a modification of the method for manufacturing the display device 1 described herein, and therefore focuses on the method in conjunction with the reference. Figures 11 to 15 The difference lies in the method of manufacturing the described display device 1. Figures 16 to 18 In, with Figures 11 to 15 The same reference numerals in the accompanying drawings denote the same components, and redundant descriptions are omitted.

[0172] In this method of manufacturing display device 1, a first pixel electrode 211, a second pixel electrode 212, and a third pixel electrode 213 can be formed on a planarization layer 118, a pixel defining layer 119 can be formed on an emissive layer 220, and a counter electrode 230 can be formed on the pixel defining layer 119. This process can be compared with a reference... Figure 11 and Figures 13 to 15 The process for manufacturing the display device 1 described herein is the same, and therefore, redundant descriptions related to it are omitted. However, as Figures 16 to 18 As shown, in the method of manufacturing the display device 1, after the planarization auxiliary layer 118A is formed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212 and between the first pixel electrode 211 and the third pixel electrode 213, the emission layer 220 is formed.

[0173] First, such as Figure 16 As shown, the preliminary planarization auxiliary layer 118P can cover the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. In other words, the preliminary planarization auxiliary layer 118P can be integrally provided on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213.

[0174] Accordingly, a portion of the preliminary planarization auxiliary layer 118P can be disposed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. A portion of the preliminary planarization auxiliary layer 118P can be disposed between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. For example, a portion of the preliminary planarization auxiliary layer 118P can be disposed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. Additionally, a portion of the preliminary planarization auxiliary layer 118P can be disposed between the second pixel electrode 212 and the third pixel electrode 213. In other words, the preliminary planarization auxiliary layer 118P can cover the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213.

[0175] Simultaneously, the preliminary planarization auxiliary layer 118P may include the same material as the planarization layer 118. For example, the preliminary planarization auxiliary layer 118P may include an organic insulating material. For example, the preliminary planarization auxiliary layer 118P may include photoresist, BCB, polyimide, HMDSO, PMMA, polystyrene, polymer derivatives having phenolic groups, acryloyl polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or combinations thereof.

[0176] Next, as Figure 17 As shown, the planarization auxiliary layer 118A can be formed by removing a portion of the initial planarization auxiliary layer 118P. In other words, when referring to a direction perpendicular to the substrate 100 as a third direction (e.g., the z-axis direction), a portion of the initial planarization auxiliary layer 118P whose length from the initial planarization auxiliary layer 118P to the substrate 100 in the third direction (e.g., the z-axis direction) is greater than the length from the first pixel electrode 211 to the substrate 100 in the third direction (e.g., the z-axis direction). Therefore, the upper surface of the first pixel electrode 211 can be exposed, and the upper surface of the planarization auxiliary layer 118A can form a flat surface with the upper surface of the first pixel electrode 211. In addition, the upper surfaces of the second pixel electrode 212 and the third pixel electrode 213 can also be exposed, and the upper surface of the planarization auxiliary layer 118A can form a flat surface with the upper surfaces of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213.

[0177] In one or more embodiments, a portion of the initial planarization auxiliary layer 118P can be removed by a polishing process (e.g., chemical mechanical polishing (CMP) process). Therefore, the upper surface of the planarization auxiliary layer 118A can form a flat (e.g., substantially flat) surface (e.g., substantially coplanar with) the upper surfaces of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. In other words, the upper surface of the planarization auxiliary layer 118A can form a flat surface with the upper surfaces of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 without forming steps.

[0178] Next, as Figure 18 As shown, the emission layer 220 can be formed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. Because the upper surface of the planarization auxiliary layer 118A forms a flat surface with the upper surfaces of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213, the emission layer 220 formed on such a flat surface can have a more uniform thickness.

[0179] Figures 19 to 21 This is a schematic cross-sectional view used to describe a method of manufacturing a display device 1 according to one or more embodiments. For example, Figures 19 to 21 It is a schematic map showing the formation Figure 9 A cross-sectional view of the process of manufacturing the emitter layer 220 of the display device 1. The method for manufacturing the display device 1 is consistent with the reference. Figures 11 to 15 The following description corresponds to a modification of the method for manufacturing the display device 1 described herein, and therefore focuses on the method in conjunction with the reference. Figures 11 to 15 The difference lies in the method of manufacturing the described display device 1. Figures 19 to 21 In, with Figures 11 to 15 The same reference numerals in the accompanying drawings denote the same components, and redundant descriptions are omitted.

[0180] In this method of manufacturing display device 1, a first pixel electrode 211, a second pixel electrode 212, and a third pixel electrode 213 can be formed on a planarization layer 118, a pixel defining layer 119 can be formed on an emissive layer 220, and a counter electrode 230 can be formed on the pixel defining layer 119. This process is consistent with reference to... Figure 11 and Figures 13 to 15 The process of manufacturing the display device 1 described herein is substantially the same, and therefore, redundant descriptions related to it are omitted. However, as Figures 19 to 21As shown, in the method of manufacturing the display device 1, an emission layer 220 can be formed such that the portion of the emission layer 220 disposed on the first pixel electrode 211, the portion of the emission layer 220 disposed on the second pixel electrode 212, and the portion of the emission layer 220 disposed on the third pixel electrode 213 are disconnected from each other.

[0181] First, such as Figure 19 As shown, the preliminary emission layer 220P can be formed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. For example, the preliminary emission layer 220P can be integrally formed across the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. For example, the preliminary emission layer 220P can be formed on the entire surface of the substrate 100. Accordingly, a portion of the preliminary emission layer 220P can be formed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213, and a portion of the preliminary emission layer 220P can be formed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. In addition, a portion of the preliminary emission layer 220P can be formed on the planarization layer 118 between the second pixel electrode 212 and the third pixel electrode 213.

[0182] This initial emission layer 220P may include a polymer material based on PPV or polyfluorene.

[0183] Next, as Figure 20 As shown, a portion of the initial emitting layer 220P can be removed. For example, a laser irradiation portion (LAI) can be used to remove a portion of the initial emitting layer 220P. In other words, the laser irradiation portion (LAI) can irradiate the portion of the initial emitting layer 220P formed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. Additionally, the laser irradiation portion (LAI) can irradiate the portion of the initial emitting layer 220P formed on the planarization layer 118 between the second pixel electrode 212 and the third pixel electrode 213. However, the type of laser that can be used as the laser LA is not limited to this. Any laser that removes organic materials can be used as the laser LA for removing a portion of the initial emitting layer 220P.

[0184] Therefore, it is possible to form such as Figure 21The emission layer 220 is shown. In other words, portions of the initial emission layer 220P formed on the planarization layer 118 between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213, can be removed. Additionally, portions of the initial emission layer 220P formed on the planarization layer 118 between the second pixel electrode 212 and the third pixel electrode 213 can be removed. Therefore, the portions of the initial emission layer 220P disposed on the first pixel electrode 211, the portions of the initial emission layer 220P disposed on the second pixel electrode 212, and the portions of the initial emission layer 220P disposed on the third pixel electrode 213 can be disconnected from each other.

[0185] in other words, Figure 21 At least a portion of the first emission layer 221 may be the portion of the preliminary emission layer 220P formed on the first pixel electrode 211. Figure 21 At least a portion of the second emission layer 222 may be the portion of the initial emission layer 220P formed on the second pixel electrode 212, and Figure 21 At least a portion of the third emission layer 223 may be a portion of the initial emission layer 220P formed on the third pixel electrode 213. In other words, the emission layer 220 may include a first emission layer 221, a second emission layer 222, and a third emission layer 223, and the first emission layer 221, the second emission layer 222, and the third emission layer 223 may be arranged on the planarization layer 118 and spaced apart from each other.

[0186] Figures 22 to 24 This is a schematic cross-sectional view used to describe a method of manufacturing a display device 1 according to one or more embodiments. For example, Figures 22 to 24 It is a schematic map showing the formation Figure 10 A cross-sectional view of the process of manufacturing the emitter layer 220 of the display device 1. The method for manufacturing the display device 1 is consistent with the reference. Figures 16 to 18 The following description corresponds to a modification of the method for manufacturing the display device 1 described herein, and therefore focuses on the method in conjunction with the reference. Figures 16 to 18 The difference lies in the method of manufacturing the described display device 1. Figures 22 to 24 In, with Figures 16 to 18 The same reference numerals in the accompanying drawings denote the same components, and redundant descriptions are omitted.

[0187] In this method of manufacturing display device 1, a first pixel electrode 211, a second pixel electrode 212, and a third pixel electrode 213 can be formed on a planarization layer 118, a pixel defining layer 119 can be formed on an emissive layer 220, and a counter electrode 230 can be formed on the pixel defining layer 119. This process is consistent with reference to... Figure 11 and Figures 13 to 15The process of manufacturing the display device 1 described herein is substantially the same, and therefore, redundant descriptions related to it are omitted. However, in this method of manufacturing the display device 1, as... Figures 22 to 24 As shown, the emission layer 220 can be formed such that the portion of the emission layer 220 disposed on the first pixel electrode 211, the portion of the emission layer 220 disposed on the second pixel electrode 212, and the portion of the emission layer 220 disposed on the third pixel electrode 213 are disconnected from each other.

[0188] First, such as Figure 22 As shown, the preliminary emission layer 220P can be formed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. For example, the preliminary emission layer 220P can be integrally formed across the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. For example, the preliminary emission layer 220P can be formed on the entire surface of the substrate 100. Accordingly, a portion of the preliminary emission layer 220P can be formed on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213, and a portion of the preliminary emission layer 220P can be formed on the planarization auxiliary layer 118A between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. In addition, a portion of the preliminary emission layer 220P can be formed on the planarization auxiliary layer 118A between the second pixel electrode 212 and the third pixel electrode 213.

[0189] This initial emission layer 220P may include a polymer material based on PPV or polyfluorene.

[0190] Next, as Figure 23 As shown, a portion of the initial emitting layer 220P can be removed. For example, a laser irradiation portion LAI can be used to remove a portion of the initial emitting layer 220P. In other words, the laser irradiation portion LAI can irradiate the portion of the initial emitting layer 220P formed on the planarization auxiliary layer 118A between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213. Additionally, the laser irradiation portion LAI can irradiate the portion of the initial emitting layer 220P formed on the planarization auxiliary layer 118A between the second pixel electrode 212 and the third pixel electrode 213. However, the type of laser that can be used as the laser LA is not limited to this. Any laser that removes organic materials can be used as the laser LA for removing a portion of the initial emitting layer 220P.

[0191] Therefore, it is possible to form such as Figure 24The emission layer 220 is shown. In other words, portions of the initial emission layer 220P formed on the planarization auxiliary layer 118A between the first pixel electrode 211 and the second pixel electrode 212, and between the first pixel electrode 211 and the third pixel electrode 213, can be removed. Additionally, portions of the initial emission layer 220P formed on the planarization auxiliary layer 118A between the second pixel electrode 212 and the third pixel electrode 213 can be removed. Therefore, the portions of the initial emission layer 220P disposed on the first pixel electrode 211, the portions of the initial emission layer 220P disposed on the second pixel electrode 212, and the portions of the initial emission layer 220P disposed on the third pixel electrode 213 can be disconnected from each other.

[0192] in other words, Figure 24 At least a portion of the first emission layer 221 may be the portion of the preliminary emission layer 220P formed on the first pixel electrode 211. Figure 24 At least a portion of the second emission layer 222 may be the portion of the initial emission layer 220P formed on the second pixel electrode 212, and Figure 24 At least a portion of the third emission layer 223 may be a portion of the initial emission layer 220P formed on the third pixel electrode 213. In other words, the emission layer 220 may include a first emission layer 221, a second emission layer 222, and a third emission layer 223, and the first emission layer 221, the second emission layer 222, and the third emission layer 223 may be arranged on the planarization auxiliary layer 118A and spaced apart from each other.

[0193] exist Figure 5 In this embodiment, a first color conversion layer 451, a second color conversion layer 452, and a light-transmitting layer 453 are disposed on the encapsulation layer 300, enabling the display device 1 to generate a color image. However, other embodiments are not limited to this. For example, a color filter layer may be disposed on the encapsulation layer 300 to enable the display device 1 to generate a color image.

[0194] Figure 25 This is a schematic cross-sectional view of a display device 1 according to one or more embodiments. The display device 1 is related to the above references. Figures 1 to 7 The described display device 1 is similar, and therefore, the following description focuses primarily on the aspects mentioned above. Figures 1 to 7 The differences are as described in display device 1. Figure 25 In, with Figures 1 to 7 The same reference numerals in the accompanying drawings denote the same components, and redundant descriptions are omitted.

[0195] The above references Figures 1 to 7In the described display device 1, a light-shielding wall portion 410 can be disposed on the encapsulation layer 300, and the light-shielding wall portion 410 can define a first color conversion opening OP21, a second color conversion opening OP22, and a third color conversion opening OP23. Furthermore, in Figure 25 In the display device 1, the light-shielding wall portion 410 can be arranged on the encapsulation layer 300, and the light-shielding wall portion 410 can define the first color conversion opening OP21, the second color conversion opening OP22 and the third color conversion opening OP23.

[0196] The above references Figures 1 to 7 In the described display device 1, the first color conversion layer 451 can be arranged in the first color conversion opening OP21, the second color conversion layer 452 can be arranged in the second color conversion opening OP22, and the light-transmitting layer 453 can be arranged in the third color conversion opening OP23 (e.g., a light-transmitting opening).

[0197] However, as Figure 25 As shown, in the display device 1, the first color filter layer 461 can be arranged in the first color conversion opening OP21, the second color filter layer 462 can be arranged in the second color conversion opening OP22, and the third color filter layer 463 can be arranged in the third color conversion opening / light transmission opening OP23.

[0198] The first color filter layer 461, the second color filter layer 462, and the third color filter layer 463 can optionally transmit light of a corresponding color (e.g., a predetermined color). For example, the first color filter layer 461 can transmit green light, the second color filter layer 462 can transmit red light, and the third color filter layer 463 can transmit blue light.

[0199] For example, the first color filter layer 461 can be a green color filter. The first color filter layer 461 can transmit only light in the wavelength range of approximately 495 nm to approximately 580 nm. For this purpose, the first color filter layer 461 can include a green pigment or dye. The second color filter layer 462 can be a red color filter. The second color filter layer 462 can transmit only light in the wavelength range of approximately 580 nm to approximately 780 nm. For this purpose, the second color filter layer 462 can include a red pigment or dye. The third color filter layer 463 can be a blue color filter. The third color filter layer 463 can transmit only light in the wavelength range of approximately 450 nm to approximately 495 nm. For this purpose, the third color filter layer 463 can include a blue pigment or dye.

[0200] In this configuration, the light emitted by the first display element DPE1, the second display element DPE2, and the third display element DPE3 can be white light. Typically, the wavelength of white light is uniformly distributed across the visible light band, from approximately 450 nm to approximately 780 nm. In other words, only a portion of the light emitted by the first display element DPE1, belonging to the band from approximately 495 nm to approximately 580 nm, can pass through the first color filter layer 461. Similarly, only a portion of the light emitted by the second display element DPE2, belonging to the band from approximately 580 nm to approximately 780 nm, can pass through the second color filter layer 462, and only a portion of the light emitted by the third display element DPE3, belonging to the band from approximately 450 nm to approximately 495 nm, can pass through the third color filter layer 463. Therefore, the display device 1 can generate a color image by using the first color filter layer 461, the second color filter layer 462, and the third color filter layer 463.

[0201] According to one or more embodiments configured as described above, a display device, a method of manufacturing a display device, and an electronic device can be implemented including an emitting layer having a substantially uniform thickness that improves emission efficiency. However, the scope of this disclosure is not limited in this respect.

[0202] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be regarded as other similar features or aspects that may be used in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: substrate; A planarization layer is placed above the substrate; The first pixel electrode is located above the planarization layer; The emission layer is located above the first pixel electrode; Counter electrode, above the emission layer; as well as A pixel defining layer is provided between the emitter layer and the counter electrode, and defines a first pixel opening that overlaps with the first pixel electrode.

2. The display device according to claim 1, wherein, A portion of the emission layer lies between the portion of the pixel defining the first pixel opening and a portion of the first pixel electrode in the pixel defining layer. The other part of the emission layer is located between the portion of the counter electrode that overlaps with the opening of the first pixel and another part of the first pixel electrode.

3. The display device according to claim 1, further comprising: The second pixel electrode is located above the planarization layer and is spaced apart from the first pixel electrode. as well as The third pixel electrode is located above the planarization layer, opposite to the second pixel electrode, and the first pixel electrode is located between the second pixel electrode and the third pixel electrode. Wherein, the emitting layer overlaps with the first pixel electrode, the second pixel electrode, and the third pixel electrode, and The pixel defining layer further defines a second pixel opening that overlaps with the second pixel electrode and a third pixel opening that overlaps with the third pixel electrode.

4. The display device according to claim 3, wherein, Each part of the emission layer is located between the first pixel electrode and the second pixel electrode, and between the first pixel electrode and the third pixel electrode.

5. The display device according to claim 3, further comprising: An encapsulation layer is placed above the counter electrode and includes at least one inorganic layer and at least one organic layer. The light-shielding wall portion is located above the encapsulation layer and defines a first color conversion opening that overlaps with the first pixel opening, a second color conversion opening that overlaps with the second pixel opening, and a light-transmitting opening that overlaps with the third pixel opening; A first color conversion layer, located in the first color conversion opening; A second color conversion layer, located in the second color conversion opening; as well as A light-transmitting layer within the light-transmitting opening.

6. The display device according to claim 3, further comprising: An encapsulation layer is placed above the counter electrode and includes at least one inorganic layer and at least one organic layer. The light-shielding wall portion is located above the encapsulation layer and defines a first color conversion opening that overlaps with the first pixel opening, a second color conversion opening that overlaps with the second pixel opening, and a third color conversion opening that overlaps with the third pixel opening; A first color filter layer is located in the first color conversion opening; A second color filter layer is located in the second color conversion opening; as well as The third color filter layer is located in the third color conversion opening.

7. The display device according to claim 3, further comprising: A planarization auxiliary layer is located above the planarization layer between the first pixel electrode and the second pixel electrode, and between the first pixel electrode and the third pixel electrode, directly contacting the planarization layer and directly contacting the portions of the emission layer between the first pixel electrode and the second pixel electrode, and between the first pixel electrode and the third pixel electrode, respectively.

8. The display device according to claim 7, wherein, The upper surface of the planarization auxiliary layer, the upper surface of the first pixel electrode, the upper surface of the second pixel electrode, and the upper surface of the third pixel electrode are coplanar.

9. The display device according to claim 7, wherein, The planarization auxiliary layer comprises the same material as the planarization layer.

10. The display device according to claim 1, further comprising: The second pixel electrode is located above the planarization layer and is spaced apart from the first pixel electrode. as well as The third pixel electrode is located above the planarization layer and opposite to the second pixel electrode, with the first pixel electrode positioned between the second pixel electrode and the third pixel electrode. The emission layer includes a first emission layer between the first pixel electrode and the counter electrode, a second emission layer between the second pixel electrode and the counter electrode, and a third emission layer between the third pixel electrode and the counter electrode. The first emission layer, the second emission layer, and the third emission layer are spaced apart from each other. The pixel defining layer further defines a second pixel opening that overlaps with the second pixel electrode and a third pixel opening that overlaps with the third pixel electrode.

11. The display device according to claim 10, wherein, The pixel-defining layer directly contacts the planarization layer in portions between the first and second emission layers and between the first and third emission layers, respectively.

12. The display device according to claim 10, further comprising: A planarization auxiliary layer is located above the planarization layer between the first pixel electrode and the second pixel electrode, and between the first pixel electrode and the third pixel electrode, directly contacting the planarization layer and directly contacting the portions of the pixel defining layer between the first pixel electrode and the second pixel electrode, and between the first pixel electrode and the third pixel electrode, respectively.

13. The display device according to claim 12, wherein, The upper surface of the planarization auxiliary layer, the upper surface of the first pixel electrode, the upper surface of the second pixel electrode, and the upper surface of the third pixel electrode are coplanar.

14. The display device according to claim 12, wherein, The planarization auxiliary layer comprises the same material as the planarization layer.

15. A method of manufacturing a display device, the method comprising: The first pixel electrode is placed on top of the planarization layer above the substrate; The emission layer is placed above the first pixel electrode; A pixel defining layer is placed above the emitter layer and defines a first pixel opening that overlaps with the first pixel electrode; as well as The counter electrode is placed above the pixel defining layer.

16. The method according to claim 15, wherein, A portion of the emission layer lies between the portion of the pixel defining the first pixel opening and a portion of the first pixel electrode in the pixel defining layer. The other part of the emission layer is located between the portion of the counter electrode that overlaps with the opening of the first pixel and another part of the first pixel electrode.

17. The method of claim 15, further comprising: The second pixel electrode and the third pixel electrode are placed above the planarization layer, with the second pixel electrode spaced apart from the first pixel electrode, the third pixel electrode opposite to the second pixel electrode, and the first pixel electrode between the second pixel electrode and the third pixel electrode; The first pixel electrode, the second pixel electrode, and the third pixel electrode are covered with a preliminary planarization auxiliary layer; as well as A portion of the initial planarization auxiliary layer is removed to form a planarization auxiliary layer, the planarization auxiliary layer having an upper surface coplanar with the upper surfaces of the first pixel electrode, the second pixel electrode, and the third pixel electrode. The emission layer, spanning the first pixel electrode, the second pixel electrode, and the third pixel electrode, is a single unit. The placement of the pixel defining layer includes coating a pixel defining layer forming material between the central portions of the first pixel electrode and the second pixel electrode, and between the central portions of the first pixel electrode and the third pixel electrode, and performing heat treatment on the pixel defining layer forming material. The formation of the planarization auxiliary layer is performed between the placement of the first pixel electrode and the placement of the emission layer.

18. The method of claim 15, further comprising: The second pixel electrode and the third pixel electrode are placed above the planarization layer, with the second pixel electrode spaced apart from the first pixel electrode, the third pixel electrode opposite to the second pixel electrode, and the first pixel electrode located between the second pixel electrode and the third pixel electrode. The placement of the emission layer includes: placing a preliminary emission layer integrally across the first pixel electrode, the second pixel electrode, and the third pixel electrode, and removing the portion of the preliminary emission layer above the planarization layer between the first pixel electrode and the second pixel electrode, and between the first pixel electrode and the third pixel electrode. The placement of the pixel defining layer includes coating a pixel defining layer forming material between the central portion of the first pixel electrode and the central portion of the second pixel electrode, and between the central portion of the first pixel electrode and the central portion of the third pixel electrode, and performing heat treatment on the pixel defining layer forming material.

19. The method of claim 18, further comprising: Between the placement of the first pixel electrode and the placement of the emitter layer, a planarization auxiliary layer having an upper surface coplanar with the upper surfaces of the first pixel electrode, the second pixel electrode, and the third pixel electrode is placed by covering the first pixel electrode, the second pixel electrode, and the third pixel electrode with a preliminary planarization auxiliary layer and removing a portion of the preliminary planarization auxiliary layer.

20. An electronic device comprising: The display device according to any one of claims 1 to 14; as well as The casing houses the display device and forms the appearance of the electronic device.

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