Display device

Abstract

A display device includes: a substrate comprising a display area and a non-display area, the display area comprising a first display area and a second display area, the first display area comprising a first pixel area, the second display area comprising a second pixel area, the second pixel area comprising a first light-emitting area and a transmissive area; a first light-emitting diode comprising a first cathode in the first pixel area; a second light-emitting diode comprising a second cathode in the first light-emitting area; a cathode separation pattern between the first pixel area and the second pixel area; an anti-deposition pattern in the transmissive area; and a first low-potential voltage line and a second low-potential voltage line in the non-display area, wherein the first cathode and the second cathode are separated by the cathode separation pattern, and wherein the first cathode and the second cathode are respectively connected to the first low-potential voltage line and the second low-potential voltage line.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0195956, filed in Korea on December 24, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device capable of providing high brightness in a sensing pixel area. Background Technology

[0004] With the development of large-area display devices, the demand for flat panel display devices with smaller footprints is increasing. As a type of flat panel display device, the technologies of liquid crystal display devices, organic light-emitting display devices including organic light-emitting diodes (OLEDs), and inorganic light-emitting display devices including inorganic light-emitting diodes are developing rapidly.

[0005] For example, in organic light-emitting display devices, holes from the anode and electrons from the cathode recombine in the organic light-emitting layer to generate excitons, which then transition from an excited state to the ground state. As a result, light is emitted from the OLED. Summary of the Invention

[0006] This disclosure relates to a display device that substantially eliminates one or more problems associated with the limitations and drawbacks of related conventional technologies.

[0007] The purpose of this disclosure is to provide a display device capable of preventing brightness reduction in a sensing pixel area, which includes a light-emitting area and a transmissive area.

[0008] Additional features and advantages are set forth in the description which follows, and will be apparent from the description, or may become clear by practice of this disclosure. The purposes and other advantages of this disclosure are realized and obtained through the features described herein and in the accompanying drawings.

[0009] To achieve these and other advantages, according to the purposes of embodiments of this disclosure, as described herein, an aspect of this disclosure is a display device comprising: a substrate including a display area and a non-display area outside the display area, the display area including a first display area and a second display area, the first display area including a first pixel area, the second display area including a second pixel area, the second pixel area including a first light-emitting area and a transmissive area; a first light-emitting diode, the first light-emitting diode being in the first pixel area and including a first anode, a first light-emitting layer and a first cathode; a second light-emitting diode, the second light-emitting diode being in the first light-emitting area and including a second anode, a second light-emitting layer and a second cathode; a cathode separation pattern between the first pixel area and the second pixel area; an anti-deposition pattern in the transmissive area; a first low-potential voltage line in the non-display area; and a second low-potential voltage line in the non-display area, wherein the first cathode and the second cathode are separated by the cathode separation pattern, and wherein the first cathode is connected to the first low-potential voltage line and the second cathode is connected to the second low-potential voltage line.

[0010] It should be understood that the foregoing general description and the following detailed description are illustrative and exemplary, and are intended to further explain the claimed contents of this disclosure. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0012] Figure 1 This is a schematic plan view of a display device according to a first embodiment of the present disclosure.

[0013] Figure 2 This is a schematic circuit diagram of the pixel area of ​​a display device according to an embodiment of the present disclosure.

[0014] Figure 3 This is a schematic cross-sectional view of the pixel region of a display device according to a first embodiment of the present disclosure.

[0015] Figure 4 This is a schematic cross-sectional view of the light-emitting pixel region and the sensing pixel region of a display device according to a first embodiment of the present disclosure.

[0016] Figure 5This is a schematic cross-sectional view illustrating the connection between the light-emitting pixel region and the first low-potential voltage line, and the connection between the sensing pixel region and the second low-potential voltage line in a display device according to a first embodiment of the present disclosure.

[0017] Figure 6 This is a schematic cross-sectional view illustrating the light-emitting pixel region in a display device according to a first embodiment of the present disclosure, and the connection between the light-emitting pixel region and the first low-potential voltage line.

[0018] Figure 7 This is a schematic plan view of a display device according to a second embodiment of the present disclosure.

[0019] Figure 8 This is a schematic cross-sectional view illustrating the connection between the light-emitting pixel region and the first low-potential voltage line, and the connection between the sensing pixel region and the second low-potential voltage line in a display device according to a second embodiment of the present disclosure.

[0020] Figure 9 This is a schematic plan view of a display device according to a third embodiment of the present disclosure.

[0021] Figure 10 This is a schematic cross-sectional view illustrating the sensing pixel region in a display device according to a third embodiment of the present disclosure, and the connection between the sensing pixel region and the second low-potential voltage line. Detailed Implementation

[0022] Reference will now be made in detail to aspects of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations associated with this document will be omitted where such description would be deemed unnecessary to obscure the gist of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except that they must occur in a specific order. The same reference numerals consistently denote the same elements. The names of the corresponding elements used in the following description are chosen solely for ease of writing and may therefore differ from those used in actual products.

[0023] The advantages and features of this disclosure, and methods for implementing them, will become clear from the aspects described below with reference to the accompanying drawings. However, this disclosure is not limited to the aspects disclosed below, but can be implemented in various different forms, and these aspects are merely to make the disclosure complete. This disclosure is provided to fully inform those skilled in the art of the scope of this disclosure.

[0024] The shapes, dimensions, scales, angles, quantities, etc., disclosed in the accompanying drawings used to illustrate aspects of this disclosure are illustrative, and this disclosure is not limited to the matters illustrated. Throughout the application, the same reference numerals refer to the same parts. Furthermore, in describing this disclosure, detailed descriptions of related known technologies may be omitted if it is determined that such detailed descriptions unnecessarily obscure the subject matter of this disclosure. When terms such as "comprising," "having," or "constituting" are used in the application, additional parts may be added unless "only" is used. Furthermore, when parts are indicated in the singular, the plural is also included unless a specific description is provided.

[0025] The expression "at least one of a, b, and c" described throughout this application may include "a alone," "b alone," "c alone," "a and b," "a and c," "b and c," or "all of a, b, and c." The advantages and features of the invention, as well as methods of implementing them, will become apparent from the embodiments described in detail below with reference to the accompanying drawings.

[0026] When interpreting a component, it is interpreted as including a range of errors or tolerances, even though there is no explicit description of such a range of errors or tolerances.

[0027] When describing positional relationships, for example, when the positional relationship between two components is described as such as "above", "over", "below", or "next to", one or more other components may be placed between the two components, unless more restrictive terms such as "just" or "directly" are used.

[0028] When describing temporal relationships, such as when time sequence is described as "after", "following", "next", or "before", discontinuous situations may be included unless more restrictive terms such as "just", "immediately", or "directly" are used.

[0029] The area, length, or thickness of each component described in this application are shown for illustrative purposes, and the invention is not necessarily limited to the area, length, and thickness of the components shown.

[0030] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0031] The various aspects of this disclosure may be combined or integrated with each other, either partially or entirely, and may interoperate differently with each other and be technically driven, as will be fully understood by those skilled in the art. The aspects of this disclosure may be implemented independently of each other or may be implemented together in a mutually dependent relationship.

[0032] Unless otherwise specified, the transistors constituting the pixel circuits of this disclosure may include at least one of oxide thin-film transistors (Oxide TFTs), amorphous silicon TFTs (a-Si TFTs), and low-temperature polycrystalline silicon (LTPS) TFTs.

[0033] The following embodiments are described with reference to organic light-emitting display devices. However, the embodiments of this disclosure are not limited to organic light-emitting display devices. For example, the display device according to the embodiments of this disclosure may be an organic light-emitting display device using organic light-emitting materials or an inorganic light-emitting display device using inorganic light-emitting materials such as quantum dots. That is, the display device of this disclosure may be an organic light-emitting display device or an inorganic light-emitting display device.

[0034] The examples and preferred embodiments illustrated in the accompanying drawings will now be discussed in detail.

[0035] Figure 1 This is a schematic plan view of a display device according to a first embodiment of the present disclosure.

[0036] Reference Figure 1 The display device according to the first embodiment of the present disclosure includes a substrate 102 and a plurality of pixel regions P1, P2 and P3 arranged on the substrate 102.

[0037] A display area DA and a non-display area NDA outside the display area DA are defined on the substrate 102. The display area DA includes a first display area DA1 and a second display area DA2 outside the first display area DA1.

[0038] A first pixel region P1 is arranged in the first display area DA. (The first pixel region P1 is then arranged with...) Figure 2 The first light-emitting diode (LED) is D1. A plurality of first pixel regions P1 are arranged in the first display area DA1, and the plurality of first pixel regions P1 may include red pixel regions, green pixel regions and blue pixel regions.

[0039] A second pixel region P2 is arranged in the second display area DA2. (The second pixel region P2 is then arranged with...) Figure 2The second light-emitting diode (LED) is D2. The second pixel region P2 can be one of the red pixel region, green pixel region, and blue pixel region. Multiple second pixel regions P2 are arranged in the second display area DA2, and the multiple second pixel regions P1 can include red pixel regions, green pixel regions, and blue pixel regions.

[0040] The second pixel region P2 includes a light-emitting region EA and a transmissive region TA on one side of the light-emitting region EA, and the first pixel region P1 includes a light-emitting region but no transmissive region. For example, the area (e.g., planar area) of the light-emitting region of the first pixel region P1 may be approximately the same as the sum of the area of ​​the light-emitting region of the second pixel region P2 and the area of ​​the transmissive region of the second pixel region P2.

[0041] A cathode separation pattern 182 is provided between the first display area DA1 and the second display area DA2.

[0042] The first cathode of the first light-emitting diode D1 in the first display area DA1 and the second cathode of the second light-emitting diode D2 in the second display area DA2 are separated by a cathode separation pattern 182. That is, the cathodes of the plurality of first pixel areas P1 in the first display area DA1 are connected to each other, and the cathodes of the plurality of second pixel areas P2 in the second display area DA2 are connected to each other.

[0043] On the other hand, the first cathode in the first pixel region P1 and the second cathode in the second pixel region P2 are separated by the cathode separation pattern 182.

[0044] Furthermore, in the second pixel region P2, a second light-emitting diode D2 is provided in the light-emitting region EA, and an anti-deposition pattern 184 is provided in the transmission region TA. That is, in the second pixel region P2, a second cathode is provided in the light-emitting region EA, and an anti-deposition pattern 184 is provided in the transmission region TA, but there is no second cathode.

[0045] The cathode separation pattern 182 may extend in one direction, and the anti-deposition pattern 184 may extend (or protrude) from the cathode separation pattern 182 toward the second pixel region P2.

[0046] Therefore, the area of ​​the first light-emitting diode in the first pixel region P1 can be larger than the area of ​​the second light-emitting diode in the second pixel region P2.

[0047] The first pixel region P1 can be a pixel region that provides an image, and the second pixel region P2 can be a pixel region that provides a sensing function. For example, the first pixel region P1 can be referred to as a light-emitting pixel region, and the second pixel region P2 can be referred to as a sensing pixel region. A sensor can be positioned in the transmissive region.

[0048] A third pixel region P3 can be further arranged in the second display area DA2. (The third pixel region P3 is then arranged with...) Figure 2 The third light-emitting diode (LED) is D3.

[0049] The third pixel region P3 can be a light-emitting pixel region or a sensing pixel region. Multiple third pixel regions P3 can be arranged in the second display area DA2, and these multiple third pixel regions P3 may include red pixel regions, green pixel regions, and blue pixel regions. For ease of explanation, a display device having a third pixel region P3 as a light-emitting pixel region is shown.

[0050] Multiple light-emitting pixel regions are arranged in the first display area DA1, and multiple sensing pixel regions or multiple sensing pixel regions and multiple light-emitting pixel regions are arranged in the second display area DA2.

[0051] Figure 2 This is a schematic circuit diagram of the pixel area of ​​a display device according to an embodiment of the present disclosure.

[0052] like Figure 2 As shown, the display device includes ( Figure 1 The first pixel region P1 in the first display area DA1, and ( Figure 1 The second pixel region P2 and the third pixel region P3 in the second display area DA2.

[0053] The first pixel region P1 is a light-emitting pixel region, and the second pixel region P2 is a sensing pixel region. The third pixel region P3 is either a light-emitting pixel region or a sensing pixel region. Figure 3 In the second display area DA2, the third pixel region P3 is the light-emitting pixel region. That is, the light-emitting pixel region and the sensing pixel region are arranged in the second display area DA2.

[0054] The display device includes gate lines GL and data lines DL that intersect each other to define a first pixel region P1, a second pixel region P2, and a third pixel region P3. The first pixel region P1 and the third pixel region P3 include a light-emitting region EA, and the second pixel region P2 includes a light-emitting region EA and a transmissive region TA.

[0055] In the light-emitting region EA of each of the first to third pixel regions P1, P2 and P3, a first thin-film transistor (TFT) T1, a second TFT T2 and a storage capacitor Cst are arranged. In addition, a first light-emitting diode D1, a second light-emitting diode D2 and a third light-emitting diode D3 are respectively arranged in the first pixel region P1, the second pixel region P2 and the third pixel region P3.

[0056] The gate line GL extends along a first direction, and the data line DL extends along a second direction perpendicular to the first direction. Figure 2 In this embodiment, the first pixel region P1, the second pixel region P2, and the third pixel region P3 share a gate line GL. However, in other embodiments of this disclosure, the first pixel region P1, the second pixel region P2, and the third pixel region P3 may be connected to different gate lines GL.

[0057] In the first TFT T1, the gate electrode is connected to the gate line, and the source electrode is connected to the data line DL. In the second TFT T2, the gate electrode is connected to the drain electrode of the first TFT T1, and the source electrode is connected to the high potential voltage VDD.

[0058] In each of the first to third light-emitting diodes D1, D2, and D3, the anode is connected to the drain electrode of the second TFT T2. The cathode of each of the first light-emitting diode D1 and the third light-emitting diode D3 is connected to ( Figure 5 The first low-potential voltage line 192 is used to receive the first low-potential voltage, and the cathode of the second light-emitting diode D2 is connected to ( Figure 5 The second low potential voltage line 194 is used to receive the second low potential voltage.

[0059] The storage capacitor Cst is connected to the gate electrode and drain electrode of the second TFT T2.

[0060] In the display device disclosed herein, the first TFT T1 may be a switching TFT, and the second TFT T2 may be a driving TFT.

[0061] In a display device, when the gate signal applied through the gate line GL turns on the first TFT T1, the data signal of the data line DL is applied through the first TFT T1 to the gate electrode of the second TFT T2 and the electrode of the storage capacitor Cst.

[0062] When the data signal turns on the second TFT T2, a high-potential voltage current is supplied to each of the first LED D1, the second LED D2, and the third LED D3. Therefore, the first LED D1, the second LED D2, and the third LED D3 emit light.

[0063] Therefore, the current to the first LED D1, the second LED D2, and the third LED D3 is controlled to enable image display. Each of the first LED D1, the second LED D2, and the third LED D3 emits light through a current applied via a high potential voltage VDD applied through the second TFT T2.

[0064] The storage capacitor Cst is used to maintain the gate voltage of the driving TFT (second TFT T2) when the switching TFT (first TFT T1) is off. Therefore, even when the switching TFT is off, the level of the current applied to the OLEDD from the power line PL is maintained until the next frame.

[0065] Therefore, the display device can display the desired image.

[0066] Figure 3 This is a schematic cross-sectional view of the pixel region of a display device according to a first embodiment of the present disclosure, and Figure 4 This is a schematic cross-sectional view of the light-emitting pixel region and the sensing pixel region of a display device according to a first embodiment of the present disclosure. Figure 5 This is a schematic cross-sectional view illustrating the connection between the light-emitting pixel region and the first low-potential voltage line, and the connection between the sensing pixel region and the second low-potential voltage line in a display device according to a first embodiment of the present disclosure. Figure 6 This is a schematic cross-sectional view illustrating the light-emitting pixel region in a display device according to a first embodiment of the present disclosure, and the connection between the light-emitting pixel region and the first low-potential voltage line.

[0067] Figure 3 It is along Figure 1 The cross-sectional view taken by line I-I' in the middle, and Figure 4 It is along Figure 1 The cross-sectional view taken from line II-II' in the diagram. Figure 5 It is along Figure 1 The cross-sectional view taken from line III-III' in the middle, and Figure 6 It is along Figure 1 The cross-sectional view taken from line IV-IV' in the diagram.

[0068] Reference Figure 1 of Figures 3 to 6 According to a first embodiment of the present disclosure, a display device 100 includes: a substrate 102 including a display area DA and a non-display area NDA outside the display area DA; the display area DA includes a first display area DA1 and a second display area DA2; a first light-emitting diode D1 in the first display area DA1; a second light-emitting diode D2 in the second display area DA2; a cathode separation pattern 182 disposed between the first display area DA1 and the second display area DA2; an anti-deposition pattern 184 disposed in a portion of the second display area DA2; and a first low-potential voltage line 192 and a second low-potential voltage line 194 in the non-display area NDA.

[0069] A first pixel region P1, including a second light-emitting region, is arranged in a first display area DA1, and a second pixel region P2, including a first light-emitting region and a transmissive region TA, is arranged in a second display area DA2.

[0070] A first light-emitting diode (LED) D1 is disposed in a first pixel region P1, and the first LED D1 includes a first anode 158a, a first light-emitting layer 158b, and a first cathode 158c. A second LED D2 is disposed in a first light-emitting region of a second pixel region P2, and the second LED D2 includes a second anode 160a, a second light-emitting layer 160b, and a second cathode 160c.

[0071] The substrate 102 can be a glass substrate or a plastic substrate. For example, the substrate 102 can be one of a polyimide (PI) substrate, a polyethersulfone (PES) substrate, a polyethylene naphthalate (PEN) substrate, a polyethylene terephthalate (PET) substrate, and a polycarbonate (PC) substrate.

[0072] In an exemplary embodiment of this disclosure, the substrate 102 may have a three-layer structure including a first polyimide layer, a second polyimide layer, and an interlayer inorganic layer sandwiched between the first and second polyimide layers. The interlayer inorganic layer may be formed of an inorganic insulating material such as silicon oxide or silicon nitride.

[0073] A first light-shielding pattern 104 is formed on the substrate 102. Light passing through the substrate 104 can be blocked by the first light-shielding pattern 104. For example, the first light-shielding pattern 104 may be formed of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof, and may have a single-layer structure or a multi-layer structure.

[0074] A buffer layer formed of an inorganic insulating material, such as silicon oxide or silicon nitride, may be provided between the substrate 102 and the first light-shielding pattern 104.

[0075] A first buffer layer 106 covering the first light-shielding pattern 104 is disposed on the substrate 102. The first buffer layer 106 can block moisture and / or oxygen. For example, the first buffer layer 106 can be formed of an inorganic insulating material such as silicon oxide or silicon nitride, and has a single-layer structure or a multi-layer structure. When the first light-shielding pattern 104 is omitted, the first buffer layer 106 can be formed directly on the substrate 102 and in contact with the substrate 102.

[0076] A first semiconductor layer 110 corresponding to the first light-shielding pattern 104 is disposed on the first buffer layer 106. The first semiconductor layer 110 may include one of polycrystalline semiconductor material, amorphous semiconductor material, and oxide semiconductor material. When the first light-shielding pattern 104 and the first buffer layer 106 are omitted, the first semiconductor layer 110 may be directly disposed on the substrate 102.

[0077] In an exemplary embodiment of this disclosure, the first semiconductor layer 110 may be formed of a polycrystalline semiconductor material, such as polycrystalline silicon. The first semiconductor layer 110 may include a first channel region 110a, a first source region 110b on one side of the first channel region 110a, and a first drain region 110c on the other side of the first channel region 110a. Impurities may be doped into the first source region 110b and the drain region 110c.

[0078] A first gate insulating layer 112 covering the first semiconductor layer 110 is disposed on the first buffer layer 106. The first gate insulating layer 112 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, and may have a single-layer structure or a multi-layer structure.

[0079] A first gate electrode 114 corresponding to the first channel region 110a of the first semiconductor layer 110 is provided on the first gate insulating layer 112. In addition, a first capacitor electrode 116 spaced apart from the first gate electrode 114 is provided on the first gate insulating layer 112.

[0080] The first gate electrode 114 and the first capacitor electrode 116 may be disposed on the same layer and formed of the same material. For example, each of the first gate electrode 114 and the first capacitor electrode 116 may be formed of a metallic material such as Mo, Al, Cr, Au, Ti, Ni, Nd, Cu or alloys thereof, and may have a single-layer structure or a multi-layer structure.

[0081] A first interlayer insulating layer 118 is disposed on the first gate insulating layer 112, covering the first gate electrode 114 and the first capacitor electrode 116. The first interlayer insulating layer 118 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, and may have a single-layer structure or a multilayer structure.

[0082] A second capacitor electrode 130 corresponding to the first capacitor electrode 116 and a second light-shielding pattern 132 spaced apart from the second capacitor electrode 130 are provided on the first interlayer insulating layer 118.

[0083] The second capacitor electrode 130 and the second light-shielding pattern 132 may be disposed on the same layer and formed of the same material. For example, each of the second capacitor electrode 130 and the second light-shielding pattern 132 may be formed of a metallic material such as Mo, Al, Cr, Au, Ti, Ni, Nd, Cu or alloys thereof, and may have a single-layer structure or a multi-layer structure.

[0084] A second interlayer insulating layer 134 is disposed on the first interlayer insulating layer 118, covering the second capacitor electrode 130 and the second light-shielding pattern 132. The second interlayer insulating layer 134 can block external moisture and / or oxygen. For example, the second interlayer insulating layer 134 can be formed of an inorganic insulating material such as silicon oxide or silicon nitride, or an organic insulating material such as photoacrylic acid or benzocyclobutene (BCB), and has a single-layer structure or a multi-layer structure.

[0085] A second semiconductor layer 136 corresponding to the second light-shielding pattern 132 is formed on the second interlayer insulating layer 134. The second semiconductor layer 136 may include one of a polycrystalline semiconductor material, an amorphous semiconductor material, and an oxide semiconductor material.

[0086] In an exemplary embodiment of this disclosure, the second semiconductor layer 136 may be formed of an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO). The second semiconductor layer 136 may include a second channel region 136a, a second source region 136b on one side of the second channel region 136a, and a second drain region 136c on the other side of the second channel region 136a. Impurities may be doped into the second source region 136b and the drain region 136c.

[0087] A second gate insulating layer 138 covering the second semiconductor layer 136 is disposed on the second interlayer insulating layer 134. The second gate insulating layer 138 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, and may have a single-layer structure or a multilayer structure.

[0088] A second gate electrode 140 corresponding to the second channel region 136a of the second semiconductor layer 136 is provided on the second gate insulating layer 136. For example, the second gate electrode 140 may be formed of a metallic material such as Mo, Al, Cr, Au, Ti, Ni, Nd, Cu or alloys thereof, and may have a single-layer structure or a multi-layer structure.

[0089] A third interlayer insulating layer 142 covering the second gate electrode 140 is provided on the second gate insulating layer 138. The third interlayer insulating layer 142 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, and may have a single-layer structure or a multilayer structure.

[0090] A first source electrode 144a, a first drain electrode 144b, a second source electrode 146a, and a second drain electrode 146b are disposed on the third interlayer insulating layer 142.

[0091] The first source electrode 144a and the first drain electrode 144b are connected to the first source region 110b and the first drain region 110c, respectively, via contact holes passing through the third interlayer insulating layer 142, the second gate insulating layer 138, the second interlayer insulating layer 134, the first interlayer insulating layer 118, and the first gate insulating layer 112. The first source electrode 144a is connected to the first capacitor electrode 116 via a contact hole passing through the third interlayer insulating layer 142, the second gate insulating layer 138, the second interlayer insulating layer 134, and the first interlayer insulating layer 118.

[0092] The second source electrode 146a and the second drain electrode 146b are connected to the second source region 136b and the second drain region 136c, respectively, via contact holes passing through the third interlayer insulating layer 142 and the second gate insulating layer 138. The second source electrode 146a is connected to the second capacitor electrode 130 via contact holes passing through the third interlayer insulating layer 142, the second gate insulating layer 138, and the second interlayer insulating layer 134.

[0093] The first source electrode 144a and the first drain electrode 144b, as well as the second source electrode 146a and the second drain electrode 146b, may be disposed on the same layer and formed of the same material. For example, each of the first source electrode 144a and the first drain electrode 144b, as well as the second source electrode 146a and the second drain electrode 146b, may be formed of a metallic material such as Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof, and may have a single-layer structure or a multi-layer structure.

[0094] The first semiconductor layer 110, the first gate electrode 114, the first source electrode 144a, and the first drain electrode 144b constitute a first TFT T1, and the second semiconductor layer 136, the second gate electrode 140, the second source electrode 146a, and the second drain electrode 146b constitute a second TFT T2. For example, the first TFT T1 can be a switching TFT, and the second TFT can be a driving TFT. In addition, the first capacitor electrode 116 and the second capacitor electrode 130 constitute a storage capacitor.

[0095] The display device 100 of this disclosure includes a first TFT T1 and a second TFT T2. Each of the first semiconductor layer 110 of the first TFT T1 and the second semiconductor layer 136 of the second TFT T2 may include one of a polycrystalline semiconductor material, an amorphous semiconductor material, and an oxide semiconductor material, and at least one of the first semiconductor layer 110 of the first TFT T1 and the second semiconductor layer 136 of the second TFT T2 may include an oxide semiconductor material. In an exemplary embodiment of this disclosure, the first semiconductor layer 110 of the first TFT T1 may be formed of a polycrystalline semiconductor material, such as polycrystalline silicon, and the second semiconductor layer 136 of the second TFT T2 may be formed of an oxide semiconductor material.

[0096] exist Figure 3 In this configuration, a first gate electrode 114, a first source electrode 144a, and a first drain electrode 146a are disposed on the first semiconductor layer 110, and a second gate electrode 140, a second source electrode 146a, and a second drain electrode 146b are disposed on the second semiconductor layer 136. That is, each of the first TFT T1 and the second TFT T2 has a coplanar structure. Alternatively, in each of the first TFT T1 and the second TFT T2, the gate electrode may be disposed below the semiconductor layer, and the source electrode and drain electrode may be disposed above the semiconductor layer. That is, TFT T1 and T2 may have an anti-interleaved structure.

[0097] A third TFT (which may be a switching TFT) and a fourth TFT (which may be a driving TFT) are disposed in the second pixel region P2. For example, the third TFT may include a third semiconductor layer, a third gate electrode, a third source electrode, and a third drain electrode, and may have the same structure as the first TFT T1. The fourth TFT may include a fourth semiconductor layer, a fourth gate electrode, a fourth source electrode, and a fourth drain electrode, and may have the same structure as the second TFT T2.

[0098] In the third pixel region P3, which is the light-emitting pixel region, a first TFT T1, which is a switching TFT, and a second TFT T2, which is the same as the first pixel region P1, are set.

[0099] A planarization layer 150 is provided on the third interlayer insulating layer 142, covering the first source electrode 144a and the first drain electrode 144b, as well as the second source electrode 146a and the second drain electrode 146b. The planarization layer 150 may be formed of an organic insulating material such as photoacrylic acid or BCB.

[0100] The planarization layer 150 may include a first planarization layer 152 on the first source electrode 144a and the first drain electrode 144b, as well as a second source electrode 146a and the second drain electrode 146b, and a second planarization layer 154 on the first planarization layer 152.

[0101] A first connection electrode 148 corresponding to the second source electrode 146a is provided on the first planarization layer 152. The first connection electrode 148 can be connected to the second source electrode 146a through a contact hole in the first planarization layer 152.

[0102] A second connection electrode corresponding to the fourth source electrode is disposed on the first planarization layer 152. The second connection electrode can be connected to the fourth source electrode through contact holes in the first planarization layer 152.

[0103] Furthermore, a first low-potential voltage line 192 and a second low-potential voltage line 194 are provided on the first planarization layer 150a. The first low-potential voltage line 192 and the second low-potential voltage line 194 are provided in the non-display area NDA and are spaced apart from each other.

[0104] For example, each of the first connecting electrode 148, the second connecting electrode, the first low-potential voltage line 192, and the second low-potential voltage line 194 may be formed of a metallic material such as Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof, and may have a single-layer or multi-layer structure.

[0105] A second planarization layer 154 is disposed on the first planarization layer 152 to cover the first connection electrode 148, the second connection electrode, the first low-potential voltage line 192, and the second low-potential voltage line 194. The second planarization layer 154 includes a first connection contact hole exposing the first connection electrode 148, a second connection contact hole exposing the second connection electrode, a first contact hole CH1 and a third contact hole CH3 exposing the first low-potential voltage line 192, and a second contact hole CH2 exposing the second low-potential voltage line 194.

[0106] exist Figure 1 In this embodiment, the first contact hole CH1 and the third contact hole CH3, which expose the first low-potential voltage line 192, are spaced apart from each other. In embodiments of this disclosure, the first contact hole CH1 and the third contact hole CH3 may be integrated into one unit.

[0107] A first anode 158a and a second anode 160a are disposed on the second planarization layer 154. The first anode 158a corresponds to the first connection electrode 148 and is connected to the first connection electrode 148 through a first connection contact hole in the second planarization layer 154. The second anode 160a corresponds to the second connection electrode and is connected to the second connection electrode through a second connection contact hole in the second planarization layer 154.

[0108] A first anode 158a is formed in each first pixel region P1, and a second anode 160a is formed in each second pixel region P2. Each of the first anode 158a and the second anode 160a may include a transparent conductive oxide (TCO) layer formed of a conductive material having a relatively high work function (e.g., a transparent conductive oxide material). Each of the first anode 158a and the second anode 160a may further include a reflective layer. For example, the transparent conductive oxide material may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), tin oxide (SnO2), zinc oxide (ZnO), indium copper oxide (ICO), and aluminum zinc oxide (Al:ZnO, AZO), and the reflective layer may include at least one of silver (Ag); an alloy of Ag with one of palladium (Pd), Cu, In, and Nd; and an aluminum-palladium-copper alloy (APC).

[0109] In embodiments of this disclosure, each of the first anode 158a and the second anode 160a may have a double-layer structure of Ag / ITO or APC / ITO, or a triple-layer structure of ITO / Ag / ITO or ITO / APC / ITO.

[0110] A dam 156 is formed on a second planarization layer 154 at the boundary of the pixel region. The dam 156 covers the edge of each of the first anode 158a and the second anode 160a, and has openings to expose the center of each of the first anode 158a and the second anode 160a, respectively. The dam 156 may further include an opening corresponding to the transmission region TA of the second pixel region P2.

[0111] In the first pixel region P1 and the third pixel region P3, the first anode 158a and the third anode are exposed through the opening of the dam 156. In the light-emitting region EA of the second pixel region P2, the second anode 160a is exposed through the opening of the dam 156, and the second planarization layer 154 in the transmission region TA is exposed through the opening of the dam 156.

[0112] The dam 156 may extend into a portion of the non-display area NDA. The dam 156 may be formed of a transparent organic insulating material, such as photoacrylic acid, benzocyclobutene, or polyimide, to be transparent. In embodiments of this disclosure, the dam 156 may further include, for example, black light-absorbing particles to have light-absorbing properties.

[0113] In the non-display area NDA, the dam 156 is partially removed to expose the first contact hole CH1, the second contact hole CH2, and the third contact hole CH3. In other words, the dam 156 corresponding to the first low-potential voltage line 192 and the second planarization layer 154 are removed to form the first contact hole CH1 and the third contact hole CH3, and the dam 156 corresponding to the second low-potential voltage line 194 and the second planarization layer 154 are removed to form the second contact hole CH2.

[0114] exist Figure 6 In the third contact hole CH3, a portion of the embankment 156 and the second planarization layer 154 is disposed in the third contact hole CH3, such that the third contact hole CH3 is divided into two parts by this portion of the embankment 156 and the second planarization layer 154. Alternatively, the embankment 156 and the second planarization layer 154 in the third contact hole CH3 may be omitted, such that there is a single third contact hole CH3.

[0115] Spacers 159 are provided on the embankment 156. For example, spacers 159 may comprise organic insulating materials such as acrylic acid, benzocyclobutene (BCB), or polyimide, and may have a single-layer or multi-layer structure. Spacers 159 may be omitted.

[0116] A first light-emitting layer 158b is disposed on a first anode 158a, and a second light-emitting layer 160b is disposed on a second anode 160a. The first light-emitting layer 158b contacts the first anode 158a in an opening in the embankment 156, and the second light-emitting layer 160b contacts the second anode 160a in an opening in the embankment 156. An end of each of the first light-emitting layer 158b and the second light-emitting layer 160b may be disposed on the embankment 156.

[0117] For example, each of the first light-emitting layer 158b and the second light-emitting layer 160b may include an organic light-emitting material layer comprising a matrix and a dopant. Each of the first light-emitting layer 158b and the second light-emitting layer 160b may further include at least one of a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer to have a multilayer structure.

[0118] In embodiments of this disclosure, each of the first light-emitting layer 158b and the second light-emitting layer 160b may include an inorganic light-emitting material layer, which includes, for example, an inorganic light-emitting material such as quantum dots.

[0119] A cathode separation pattern 182 corresponding to the space between the first display area DA1 and the second display area DA2 is provided on the embankment 156, and an anti-deposition pattern 184 corresponding to the transmission area TA of the second pixel area P2 is provided on the second planarization layer 154.

[0120] The cathode separation pattern 182 extends into a portion of the non-display area NDA to be positioned between the first low-potential voltage line 192 and the second low-potential voltage line 194.

[0121] Each of the cathode separation pattern 182 and the anti-deposition pattern 184 includes a compound represented by Formula 1.

[0122] [Formula 1]

[0123]

[0124] In Formula 1, L1 and L2 are each independently selected from groups consisting of substituted or unsubstituted C6 to C30 arylene groups and substituted or unsubstituted C3 to C30 heteroarylene groups.

[0125] m and n are each independently 0 or 1, and

[0126] X1 to X6 are each independently selected from hydrogen and halogens.

[0127] In embodiments of this disclosure, the C6 to C30 aryl groups may be selected from the group consisting of: phenylene, biphenylene, terphenylene, naphthylene, anthraceneylene, pentanenylene, indenylene, indenoindenylene, heptalenylene, biphenylenylene, indacenylene, phenanthrenylene, and benzophenanthrenylene. Dibenzophenanthrenylene, azulenylene, pyrenylene, fluoranthenylene, triphenylenylene, chrysenylene, tetraphenylene, tetrasenylene, picenylene, pentaphenylene, pentacenylene, fluorenylene, indenofluorenylene, and spirofluorenylene.

[0128] In embodiments of this disclosure, the C3 to C30 heteroaryl groups may be composed of the group consisting of: pyrrolylene, pyridinylene, pyrimidinylene, pyrazinylene, pyridazinylene, triazinylene, tetrazinylene, imidazolylene, pyrazolylene, indolylene, isoindolylene, and indolylene. (indazolylene), indolizinylene, pyrrolizinylene, carbazolylene, benzocarbazolylene, dibenzocarbazolylene, indolocarbazolylene, indenocarbazolylene, benzofurocarbazolylene, benzothienocarbazolylene bazolylene), quinolinylene, isoquinolinylene, phthalazinylene, quinoxalinylene, cinnolinylene, quinazolinylene, quinozolinylene, quinolinylene, purinylene, phthalazinylene, quinoxalinylene benzoquinolinylene, benzoisoquinolinylene, benzoquinazolinylene, benzoquinoxalinylene, aridinylene, phenanthrolinylene, perimidinylene, phenanthridinylene, pteridinylene, cinnolinyleneNaphtharidinylene, furanylene, oxazinylene, oxazolylene, oxadiazolylene, triazolylene, dioxynylene, benzofuranyenel, dibenzofuranylene, thiopyranylene, xanthenylene, chromanylene, isochromanylene, thioazinylene, thiopheneylene henylene), benzothiophenylene, dibenzothiophenylene, difuropyrazinylene, benzofurodibenzofuranylene, benzothienobenzothiophenylene, benzothienodibenzothiophenylene, benzothienodibenzothiophenylene, benzothienobenzofuranylene, and benzothienodibenzofuranylene.

[0129] In embodiments of this disclosure, the substituents of the C6 to C30 aryl and C3 to C30 heteroaryl groups may be selected from the group consisting of substituted or unsubstituted C1 to C10 alkyl groups, substituted or unsubstituted C3 to C30 cycloalkyl groups, substituted or unsubstituted C6 to C30 aryl groups, and substituted or unsubstituted C3 to C30 heteroaryl groups.

[0130] Halogens can be selected from F, Cl, Br and I.

[0131] In embodiments of this disclosure, m and n can each be 0, and X1 to X6 can each be H or F.

[0132] In embodiments of this disclosure, m and n can each be 1, L1 and L2 can each be phenylene or thiophene, and X1 to X6 can each be H or F.

[0133] For example, the cathode separation pattern 182 and the anti-deposition pattern 184 each independently include a compound selected from Formula 2.

[0134] [Equation 2]

[0135]

[0136]

[0137] exist Figure 4 In the second planarization layer 154, an anti-deposition pattern 184 is provided corresponding to the transmission region TA of the second pixel region P2.

[0138] In embodiments of this disclosure, the second planarization layer 154 in the transmissive region TA of the second pixel region P2 can be removed, and an anti-deposition pattern 184 can be formed on the first planarization layer 152. In embodiments of this disclosure, the first planarization layer 152 and the second planarization layer 154 in the transmissive region TA of the second pixel region P2 can be removed, and an anti-deposition pattern 184 can be formed on the third interlayer insulating layer 142.

[0139] exist Figure 4 In this embodiment, the second light-emitting layer 160b is present in the light-emitting region EA but not in the transmission region TA. In embodiments of this disclosure, the second light-emitting layer 160b may exist in both the light-emitting region EA and the transmission region TA. In this case, an anti-deposition pattern 184 may be provided on the second light-emitting layer 160b in the transmission region TA.

[0140] The first cathode 158c and the second cathode 160c are formed by depositing conductive material on a substrate 102 including a first light-emitting layer 158b and a second light-emitting layer 160b, a cathode separation pattern 182, and an anti-deposition pattern 184. For example, the conductive material can be one of ITO, IZO, Al, Ag, Cu, Pb, Mg, Mo, Ti, and alloys thereof. Each of the first cathode 158c and the second cathode 160c can have a thin thickness to serve as a transparent or semi-transparent electrode.

[0141] The first cathode 158c is disposed on the entire surface of the first display area DA1. That is, the first cathodes 158c disposed in the plurality of first pixel areas P1 in the first display area DA1 are connected to each other, so that the entire surface of the first display area DA1 is covered by the first cathodes 158c.

[0142] Furthermore, the first cathode 158c extends into a portion of the non-display area NDA to contact the first low-potential voltage line 192 through the first contact hole CH1 and the third contact hole CH3. The portion of the first cathode 158c extending into the non-display area NDA may be referred to as the first cathode extension portion 158d.

[0143] The second cathode 160c is disposed in the second display area DA2. The second cathodes 160c disposed in the light-emitting areas EA of the plurality of second pixel areas P2 in the second display area DA2 are interconnected, such that the surface of the second display area DA2, except for the transmissive area TA, is covered by the second cathodes 160c. That is, in the second pixel area P2, the second cathode 160c exists in the light-emitting area EA but not in the transmissive area TA. As a result, the anti-deposition pattern 184 is not covered by the second cathode 160c and is exposed.

[0144] Furthermore, the second cathode 160c extends into a portion of the non-display area NDA to contact the second low-potential voltage line 194 through the second contact hole CH2. The portion of the second cathode 160c extending into the non-display area NDA may be referred to as the second cathode extension portion 160d.

[0145] The metal layers used to form the first cathode 158c and the second cathode 160c are patterned using a cathode separation pattern 182 and an anti-deposition pattern 184. Metal material is selectively deposited using the cathode separation pattern 182 and the anti-deposition pattern 184. That is, when metal material is deposited onto the entire surface of the display area DA using an aperture mask, metal material is not deposited in the areas where the cathode separation pattern 182 and the anti-deposition pattern 184 are presented, but is deposited in the areas where the cathode separation pattern 182 and the anti-deposition pattern 184 are not presented. As a result, the first cathode 158c and the second cathode 160c are formed.

[0146] In other words, the first cathode 158c in the first display area DA1 and the second cathode 160c in the second display area DA2 are separated by the cathode separation pattern 182, and metal deposition into the transmission area TA of the second pixel area P2 is prevented by the anti-deposition pattern 184. Since the compound (e.g., a material) represented by Formula 1 used for the anti-deposition pattern 184 is transparent, the transmittance in the transmission area TA can be maintained.

[0147] Since the first cathode 158c and the second cathode 160c are patterned by the cathode separation pattern 182, the side surface of each of the first cathode 158c and the second cathode 160c can contact the side surface of the cathode separation pattern 182. Furthermore, since the first cathode 158c and the second cathode 160c are patterned by the anti-deposition pattern 184, the side surface of each of the first cathode 158c and the second cathode 160c can contact the side surface of the anti-deposition pattern 184.

[0148] The first anode 158a, the first light-emitting layer 158b, and the first cathode 158c constitute the first light-emitting diode D1, and the second anode 160a, the second light-emitting layer 160b, and the second cathode 160c constitute the second light-emitting diode D2.

[0149] In the display device 100 of this disclosure, light from the first light-emitting layer 158b and the second light-emitting layer 160b passes through the first cathode 158c and the second cathode 160c, respectively, to display an image. That is, the display device 100 is a top-emitting display device.

[0150] The first cathode 158c in the first display area DA1 and the second cathode 160c in the second display area DA2 are separated by a cathode separation pattern 182. The first cathode 158c is electrically connected to the first low-potential voltage line 192 through the first cathode extension 158d, and the second cathode 160c is electrically connected to the second low-potential voltage line 194 through the second cathode extension 160d.

[0151] In embodiments of this disclosure, a first voltage can be applied to a first low-potential voltage line 192, and a second voltage less than the first voltage can be applied to a second low-potential voltage line 194. Therefore, the first voltage can be applied to the first cathode 158c via the first cathode extension 158d, and the second voltage less than the first voltage can be applied to the second cathode 160c via the second cathode extension 160d.

[0152] As described above, a light-emitting region is provided in the first pixel region P1, which is a light-emitting pixel region, but no transmission region is provided, and a light-emitting region EA and a transmission region are provided in the second pixel region P2, which is a sensing pixel region. As a result, the brightness of the light emitted from the second light-emitting diode D2 in the second pixel region P2 is lower than the brightness of the light emitted from the first light-emitting diode D1 in the first pixel region P1.

[0153] However, in the display device 100 of this disclosure, the first cathode 158c in the first display area DA1 including the first pixel area P1 and the second cathode 160c in the second display area DA2 including the second pixel area P2 are separated by a cathode separation pattern 182, and the first cathode 158c and the second cathode 160c are respectively connected to the first low-potential voltage line 192 and the second low-potential voltage line 194. A relatively low voltage is applied to the second cathode 160c of the second light-emitting diode D2 in the second pixel area P2, thereby increasing the brightness of the light from the second light-emitting diode D2. Therefore, it is possible to make the brightness of the first light-emitting diode D1 and the brightness of the second light-emitting diode D2 uniform, or to reduce the brightness difference between the first light-emitting diode D1 and the second light-emitting diode D2.

[0154] Reference Figure 1 and Figure 5 The first low potential voltage line 192 and the second low potential voltage line 194 are disposed in the non-display area NDA on one side of the display area DA, and the first cathode extension portion 158d and the second cathode extension portion 160d extend from the first cathode 158c and the second cathode 160c in the same direction.

[0155] In embodiments of this disclosure, the first low-potential voltage line 192 and the second low-potential voltage line 194 may be disposed in different regions of the non-display area NDA, and the first cathode extension portion 158d and the second cathode extension portion 160d extend from the first cathode 158c and the second cathode 160c in different directions.

[0156] For example, a first low-potential voltage line 192 may be disposed in a non-display area NDA on one side of the display area DA, and a first cathode extension 158d may extend from the first cathode 158c along a first direction to contact the first low-potential voltage line 192. A second low-potential voltage line 194 may be disposed in a non-display area NDA on the other side of the display area DA, and a second cathode extension 160d may extend from the second cathode 160c along a second direction opposite to the first direction to contact the second low-potential voltage line 194.

[0157] The first low-potential voltage line 192 and the second low-potential voltage line 194 are disposed on the same layer, namely the first planarization layer 152, and are formed on the same material. In embodiments of this disclosure, the first low-potential voltage line 192 and the second low-potential voltage line 194 may be disposed on different layers. For example, one of the first low-potential voltage line 192 and the second low-potential voltage line 194 may be disposed on the first planarization layer 152, and the other of the first low-potential voltage line 192 and the second low-potential voltage line 194 may be disposed between the substrate 102 and the first planarization layer 152.

[0158] An encapsulation layer (or encapsulation film) 162 is disposed on the entire surface of the substrate 102, including a first cathode 158c, a first cathode extension 158d, a second cathode 160c, a second cathode extension 160d, a cathode separation pattern 182, and an anti-deposition pattern 184, to prevent moisture penetration. The encapsulation layer 162 includes, but is not limited to, a first inorganic insulating layer 162a, an organic insulating layer 162b, and a second inorganic insulating layer 162c stacked in sequence.

[0159] Each of the first inorganic insulating layer 162a and the second inorganic insulating layer 162c may be formed of an inorganic insulating material, such as silicon oxide or silicon nitride. The organic insulating layer 162b may be formed of an organic insulating material, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0160] A bridging pattern 166 is formed on the encapsulation layer 162. The bridging pattern 166 may correspond to the boundary of each of the first pixel region P1, the second pixel region P2, and the third pixel region P3. For example, the bridging pattern 166 may be formed from one of ITO, IZO, Al, Ag, Cu, Pb, Mg, Mo, Ti, and alloys thereof, and may have a single-layer structure or a multi-layer structure.

[0161] A second buffer layer may be provided between the encapsulation layer 162 and the bridging pattern 166. For example, the second buffer layer may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, and may have a single-layer structure or a multi-layer structure.

[0162] A fourth interlayer insulating layer 168 is disposed over the entire surface of the substrate 102 to cover the bridging pattern 166. The fourth interlayer insulating layer 168 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, and may have a single-layer structure or a multi-layer structure.

[0163] A touch electrode 170 is disposed on the fourth interlayer insulating layer 168. The touch electrode 170 is connected to the bridging pattern 166 through a contact hole in the fourth interlayer insulating layer 168. For example, the touch electrode 170 may be formed of one of ITO, IZO, Al, Ag, Cu, Pb, Mg, Mo, Ti and alloys thereof, and may have a single-layer structure or a multi-layer structure.

[0164] A first protective layer 172 is disposed over the entire surface of the substrate 102 to cover the touch electrode 170. The first protective layer 172 may be formed of an organic insulating material such as photosensitive acrylic or benzocyclobutene, or an inorganic insulating material such as silicon oxide or silicon nitride, and may have a single-layer structure or a multi-layer structure.

[0165] A black matrix 174 is formed on the first protective layer 172. The black matrix 174 is located at the boundaries of the first to third pixel regions P1, P2, and P3, and includes openings corresponding to the transmission regions TA of the first to third light-emitting diodes D1, D2, and D3 and the second pixel region P2. The openings of the black matrix 174 correspond to the openings of the embankment 156.

[0166] For a wide viewing angle, the size (e.g., planar area) of the opening in the black matrix 174 can be larger than the size of the opening in the embankment 156. That is, the embankment 156 can have a first width, and the black matrix 174 can have a second width smaller than the first width.

[0167] The black matrix 174 may be disposed in at least a portion of the non-display area NDA. For example, the black matrix 174 may be disposed corresponding to the entire surface of the non-display area NDA.

[0168] A color filter layer 176 corresponding to the black matrix 174 is provided on the first protective layer 172. The color filter layer 176 may include a red color filter corresponding to the red pixel area, a green color filter corresponding to the green pixel area, and a blue color filter corresponding to the blue pixel area.

[0169] The color filter layer 176 may include organic materials and color particles (e.g., colored pigments or colored dyes). For example, the organic materials may be selected from, but are not limited to, polymethyl methacrylate, polycarbonate, polyacrylate, polyurethane, epoxy resin, polyester and polyimide.

[0170] A second protective layer 178 is disposed on the black matrix 174 and the color filter layer 176 and over the entire substrate 102. The second protective layer 178 may be formed of an organic insulating material such as photoacrylic acid or benzocyclobutene, or an inorganic insulating material such as silicon oxide or silicon nitride, and may have a single-layer structure or a multi-layer structure.

[0171] In the display device 100 according to the first embodiment of the present disclosure, a cathode separation pattern 182 is disposed between a first display area DA1 including a first pixel area P1 as a light-emitting pixel area and a second display area DA2 including a second pixel area P2 as a sensing pixel area. The first cathode 158c of the first light-emitting diode D1 in the first pixel area P1 and the second cathode 160c of the second light-emitting diode D2 in the second pixel area P2 are respectively connected to a first low-potential voltage line 192 and a second low-potential voltage line 194. Therefore, brightness reduction in the second pixel area P2, which includes a transmission area TA and a light-emitting area TA, thus having a smaller light-emitting area than the first pixel area P1, can be prevented, allowing the display device 100 to provide a high-brightness image.

[0172] Furthermore, in the display device 100, by selectively depositing (or forming) the first cathode 158c and the second cathode 160c in the desired area using the cathode separation pattern 182 and the anti-deposition pattern 184 formed by the same process and the same materials, a display device 100 with sensing function and high brightness can be provided without additional processes.

[0173] Figure 7 This is a schematic plan view of a display device according to a second embodiment of the present disclosure.

[0174] Reference Figure 7 and Figure 2 The display device according to the second embodiment of the present disclosure includes a substrate 102 and a plurality of pixel regions P1, P2 and P3 arranged on the substrate 102.

[0175] A display area DA and a non-display area NDA outside the display area DA are defined on the substrate 102. The display area DA includes a first display area DA1 and a second display area DA2 outside the first display area DA1.

[0176] A first pixel region P1 is set in the first display region DA. A first light-emitting diode D1 is set in the first pixel region P1.

[0177] A second pixel region P2 is set in the second display area DA2. A second light-emitting diode D2 is set in the second pixel region P2. The second pixel region P2 can be one of a red pixel region, a green pixel region, or a blue pixel region.

[0178] The second pixel region P2 includes a light-emitting region EA and a transmissive region TA on one side of the light-emitting region EA, and the first pixel region P1 includes a light-emitting region but no transmissive region. For example, the area (e.g., planar area) of the light-emitting region of the first pixel region P1 may be approximately the same as the sum of the area of ​​the light-emitting region of the second pixel region P2 and the area of ​​the transmissive region of the second pixel region P2.

[0179] The first pixel region P1 can be a pixel region that provides an image, and the second pixel region P2 can be a pixel region that provides a sensing function. For example, the first pixel region P1 can be referred to as a light-emitting pixel region, and the second pixel region P2 can be referred to as a sensing pixel region.

[0180] A third pixel region P3 can be further arranged in the second display region DA2. A third light-emitting diode D3 is set in the third pixel region P3.

[0181] The third pixel region P3 can be a light-emitting pixel region or a sensing pixel region. Multiple third pixel regions P3 can be arranged in the second display area DA2, and these multiple third pixel regions P3 may include red pixel regions, green pixel regions, and blue pixel regions. For ease of explanation, a display device having a third pixel region P3 as a light-emitting pixel region is shown.

[0182] Multiple light-emitting pixel regions are arranged in the first display area DA1, and multiple sensing pixel regions or multiple sensing pixel regions and multiple light-emitting pixel regions are arranged in the second display area DA2.

[0183] A cathode separation pattern 280 is provided in the second display area DA2 to separate the second cathode 260c of the second light-emitting diode D2 in the second pixel area P2 from the first cathode 258c of the first light-emitting diode D1 in the first pixel area P1 and the third cathode of the third light-emitting diode D3 in the third pixel area P3. The second cathode 260c includes a second cathode extension 260d extending into the non-display area NDA. The cathode separation pattern 280 surrounds the second cathode 260c including the second cathode extension 260d to separate the second cathode 260c from the first cathode 258c and the third cathode.

[0184] The cathode separation pattern 280 may include a first pattern 282 surrounding the second cathode 260c, and a second pattern 286 and a third pattern 288 extending from the first pattern 282 along both sides of the second cathode extension portion 260d.

[0185] In each of the first to third light-emitting diodes D1, D2, and D3, the anode is connected to the drain electrode of the driving TFT T2. The cathode 258c of the first light-emitting diode D1 and the cathode of the third light-emitting diode D3 are connected to (…). Figure 8 The first low-potential voltage line 192 is used to receive the first low-potential voltage VSS1, and the cathode 260c of the second light-emitting diode D2 is connected to ( Figure 8 The second low potential voltage line 194 is used to receive the second low potential voltage VSS2.

[0186] exist Figure 7 In this configuration, the cathode separation pattern 280 is configured to surround the second cathode 260c and the second cathode extension 260d in the second pixel region P2. Alternatively, the cathode separation pattern 280 may further include a pattern spanning the space between the first display region DA1 and the second display region DA2 to separate the cathode in the first display region DA1 from the cathode in the second display region DA2.

[0187] Figure 8 This is a schematic cross-sectional view illustrating the connection between the light-emitting pixel region and the first low-potential voltage line, and the connection between the sensing pixel region and the second low-potential voltage line in a display device according to a second embodiment of the present disclosure. Figure 8 It is along Figure 7 The cross-sectional view taken by line V-V' in the diagram.

[0188] Figure 8 A display device 200 is shown with no components between the substrate 102 and the first planarization layer 152 and above the light-emitting diode.

[0189] Reference Figure 8 as well as Figure 2 and Figure 7According to the second embodiment of the present disclosure, the display device 200 includes: a substrate 102 including a display area DA and a non-display area NDA outside the display area DA; the display area DA includes a first display area DA1 and a second display area DA2; a first light-emitting diode D1 in the first display area DA1; a second light-emitting diode D2 in the second display area DA2; a cathode separation pattern 280 disposed between the first display area DA1 and the second display area DA2; an anti-deposition pattern 284 disposed in a portion of the second display area DA2; and a first low-potential voltage line 192 and a second low-potential voltage line 194 in the non-display area NDA.

[0190] Compared to the display device 100 according to the first embodiment of this disclosure, the display device 200 according to the second embodiment of this disclosure has a major difference in the cathode separation pattern 280. The description of the display device 200 focuses on the cathode separation pattern 280.

[0191] The first low-potential voltage line 192 and the second low-potential voltage line 194 are disposed in the non-display area NDA and on the first planarization layer 152.

[0192] The first to third light-emitting diodes D1, D2 and D3 are disposed in the display area DA and above the first planarization layer 152, for example on the second planarization layer 154.

[0193] The embankment 256 is disposed between two adjacent pixel regions in the first to third pixel regions P1, P2 and P3 in the display area DA, and between the first low potential voltage line 192 and the second low potential voltage line 194 in the non-display area, and on the first planarization layer 152.

[0194] In embodiments of this disclosure, the first low-potential voltage line 192 may include a first line positioned on one side of the second low-potential voltage line 194 and a second line positioned on the other side of the second low-potential voltage line 194. In this case, the embankment 256 may include a first embankment positioned between the first line and the second low-potential voltage line 194 and a second embankment positioned between the second line and the second low-potential voltage line 194.

[0195] The embankment 256 includes openings corresponding to each of the first to third pixel regions P1, P2, and P3. Furthermore, the embankment 256 further includes a first contact hole CH1 and a third contact hole CH3 that expose the first and second lines of the first low-potential voltage line 192, respectively, and a second contact hole CH2 that exposes the second low-potential voltage line 194.

[0196] Although not shown, ( Figure 4The second planarization layer 154 may be disposed between the first planarization layer 152 and the embankment 256 in the non-display area NDA. For example, the second planarization layer 154 may have the same shape as the embankment 256. That is, in the non-display area NDA, the embankment 256 and the second planarization layer 154 can form a first contact hole CH1 and a third contact hole CH3 that expose the first line and the second line of the first low-potential voltage line 192, respectively, and a second contact hole CH2 that exposes the second low-potential voltage line 194.

[0197] Each of the first light-emitting diode D1 in the first pixel region P1 and the third light-emitting diode D3 in the third pixel region P3 includes ( Figure 4 The first anode 158a, ( Figure 4 The first light-emitting layer 158b and the first cathode 258c, wherein the first cathode 258c includes a first cathode extension 258d extending into the non-display area NDA.

[0198] The second light-emitting diode D2 in the second pixel region P2 includes ( Figure 4 The second anode 160a, Figure 4 The second light-emitting layer 160b and the second cathode 260c, wherein the second cathode 260c includes a second cathode extension 260d extending into the non-display area NDA.

[0199] The second cathode extension 260d is spaced apart from the first cathode extension 258d. The second cathode extension 260d can be positioned between the first cathode extension 258d of the first light-emitting diode D1 and the first cathode extension 258d of the third light-emitting diode D3.

[0200] A cathode separation pattern 280 surrounds a second cathode 260c and a second cathode extension 260d. The cathode separation pattern 280 includes a first pattern 282 surrounding the second cathode 260c, and second patterns 286 and third patterns 288 extending from the first pattern 282 along both sides of the second cathode extension 260d. That is, the cathode separation pattern 280 may have a shape substantially the same as the second cathode 260c, which includes the second cathode extension 260d. In other words, the first pattern 282 may surround three sides of the second cathode 260c or the second pixel region P2 and have an opening corresponding to the second cathode extension 260d, and each of the second pattern 286 and the third pattern 288 extends from the first pattern 282 along the first cathode extension 260d.

[0201] The first pattern 282 is disposed on the embankment 256 at the boundary of the second pixel region P2, and the second pattern 286 and the third pattern 288 are disposed on the embankment 256 between the first low potential voltage line 192 and the second low potential voltage line 194.

[0202] Anti-deposition pattern 284 is disposed in the transmission region TA of the second pixel region P2. Anti-deposition pattern 284 may extend from cathode separation pattern 280.

[0203] Each of the cathode separation pattern 280 and the anti-deposition pattern 284 may include a compound represented by Formula 1. For example, each of the cathode separation pattern 280 and the anti-deposition pattern 284 may independently include a compound selected from the compounds in Formula 2.

[0204] In embodiments of this disclosure, when a plurality of second pixel regions P2 are arranged in the second display area DA2, a second cathode extension portion 260d in one of the second pixel regions P2 can be connected to a second cathode extension portion 260d in another second pixel region P2.

[0205] In embodiments of this disclosure, each of the second cathode extension 260d in one second pixel region of the second pixel region P2 and the second cathode extension 260d in another second pixel region of the second pixel region P2 extends into the non-display area NDA to connect to the second low-potential voltage line 194.

[0206] In the display device 200 according to the second embodiment of the present disclosure, a first low potential voltage line 192 and a second low potential voltage line 194 are provided in a non-display area NDA on one side of the display area DA, and a first cathode extension portion 258d and a second cathode extension portion 260d extend from the first cathode 258c and the second cathode 260c in the same direction.

[0207] In embodiments of this disclosure, the first low-potential voltage line 192 and the second low-potential voltage line 194 may be disposed in different regions of the non-display area NDA, and the first cathode extension portion 258d and the second cathode extension portion 260d extend from the first cathode 258c and the second cathode 260c in different directions.

[0208] For example, a first low-potential voltage line 192 may be disposed in a non-display area NDA on one side of the display area DA, and a first cathode extension 258d may extend from the first cathode 258c along a first direction to contact the first low-potential voltage line 192. A second low-potential voltage line 194 may be disposed in a non-display area NDA on the other side of the display area DA, and a second cathode extension 260d may extend from the second cathode 260c along a second direction opposite to the first direction to contact the second low-potential voltage line 194.

[0209] In the display device 200 according to the second embodiment of the present disclosure, a cathode separation pattern 280 is disposed between a first pixel region P1, which is a light-emitting pixel region, and a second pixel region P2, which is a sensing pixel region. The first cathode 258c of the first light-emitting diode D1 in the first pixel region P1 and the second cathode 260c of the second light-emitting diode D2 in the second pixel region P2 are respectively connected to a first low-potential voltage line 192 and a second low-potential voltage line 194. Therefore, brightness reduction in the second pixel region P2, which includes a transmission region TA and a light-emitting region TA, and thus has a smaller light-emitting region than the first pixel region P1, can be prevented, allowing the display device 200 to provide a high-brightness image.

[0210] Furthermore, in the display device 200, by selectively depositing (or forming) the first cathode 258c and the second cathode 260c in the desired area using the cathode separation pattern 280 and the anti-deposition pattern 284 formed by the same process and the same materials, a display device 200 with sensing function and high brightness can be provided without additional processes.

[0211] Furthermore, in the display device 200, when a third pixel region P3, which serves as a light-emitting pixel region, is arranged in the second display region DA2, the cathode in the third pixel region P3 is separated from the cathode 260c in the second pixel region P2, which serves as a sensing pixel region, and connected to the first low-potential voltage line 192. As a result, brightness non-uniformity in the first pixel region P1 and the third pixel region P3, which serve as light-emitting pixel regions, can be prevented.

[0212] Figure 9 This is a schematic plan view of a display device according to a third embodiment of the present disclosure.

[0213] Reference Figure 9 and Figure 2 The display device 300 according to the third embodiment of the present disclosure includes a substrate 102 and a plurality of pixel regions P1, P2 and P3 disposed on the substrate 102.

[0214] A display area DA and a non-display area NDA outside the display area DA are defined on the substrate 102. The display area DA includes a first display area DA1 and a second display area DA2 outside the first display area DA1.

[0215] A first pixel region P1 is arranged in the first display region DA. A first light-emitting diode D1 is disposed in the first pixel region P1.

[0216] A second pixel region P2 is arranged in the second display area DA2. A second light-emitting diode D2 is disposed in the second pixel region P2. The second pixel region P2 can be one of a red pixel region, a green pixel region, or a blue pixel region.

[0217] The second pixel region P2 includes a light-emitting region EA and a transmissive region TA on one side of the light-emitting region EA, and the first pixel region P1 includes a light-emitting region but no transmissive region. For example, the area (e.g., planar area) of the light-emitting region of the first pixel region P1 may be approximately the same as the sum of the area of ​​the light-emitting region of the second pixel region P2 and the area of ​​the transmissive region of the second pixel region P2.

[0218] The first pixel region P1 can be a pixel region that provides an image, and the second pixel region P2 can be a pixel region that provides a sensing function. For example, the first pixel region P1 can be referred to as a light-emitting pixel region, and the second pixel region P2 can be referred to as a sensing pixel region.

[0219] A third pixel region P3 can be further arranged in the second display region DA2. A third light-emitting diode D3 is set in the third pixel region P3.

[0220] The third pixel region P3 can be a light-emitting pixel region or a sensing pixel region. Multiple third pixel regions P3 can be arranged in the second display area DA2, and these multiple third pixel regions P3 may include red pixel regions, green pixel regions, and blue pixel regions. For ease of explanation, a display device having a third pixel region P3 as a light-emitting pixel region is shown.

[0221] Multiple light-emitting pixel regions are arranged in the first display area DA1, and multiple sensing pixel regions or multiple sensing pixel regions and multiple light-emitting pixel regions are arranged in the second display area DA2.

[0222] A cathode separation pattern 380 is provided in the second display area DA2 to separate the second cathode 360c of the second light-emitting diode D2 in the second pixel area P2 from the first cathode 358c of the first light-emitting diode D1 in the first pixel area P1, and the third cathode of the third light-emitting diode D3 in the third pixel area P3. The cathode separation pattern 380 surrounds the second cathode 360c to separate it from the first cathode 358c and the third cathode.

[0223] In each of the first to third light-emitting diodes D1, D2, and D3, the anode is connected to the drain electrode of the driving TFT T2. The cathode 258c of the first light-emitting diode D1 and the cathode of the third light-emitting diode D3 are connected to (…). Figure 5 The first low-potential voltage line 192 is used to receive the first low-potential voltage VSS1, and the cathode 260c of the second light-emitting diode D2 is connected to ( Figure 10 The second low potential voltage line 394 is used to receive the second low potential voltage VSS2.

[0224] The second low-potential voltage line 394 extends into the second pixel region P2, and the second cathode 360c in the second pixel region P2 and the second low-potential voltage line 394 are connected to each other. That is, the cathode separation pattern 380 completely surrounds each second pixel region P2, and the second cathode 360c in the second pixel region P2 is separated from the first cathode 358c in the first pixel region P2 and the third cathode in the third pixel region P3. Furthermore, the second cathode 360c in one second pixel region of the second pixel region P2 is separated from the second cathode 360c in another second pixel region of the second pixel region P2.

[0225] In one embodiment of this disclosure, the second cathode 360c in one second pixel region of the second pixel region P2 and the second cathode 360c in another second pixel region of the second pixel region P2 can be connected to each other.

[0226] exist Figure 9 In this configuration, the cathode separation pattern 380 is configured to surround the second pixel region P2. Alternatively, the cathode separation pattern 380 may further include a pattern spanning the space between the first display region DA1 and the second display region DA2 to separate the cathode in the first display region DA1 from the cathode in the second display region DA2.

[0227] Figure 10 This is a schematic cross-sectional view illustrating the sensing pixel region in a display device according to a third embodiment of the present disclosure, and the connection between the sensing pixel region and the second low-potential voltage line. Figure 10 It is along Figure 9 The cross-sectional view taken from line VI-VI' in the diagram.

[0228] Figure 8 A display device 200 is shown with no components between the substrate 102 and the third interlayer insulating layer 142 and above the light-emitting diode.

[0229] Reference Figure 10 as well as Figure 2 and Figure 9 According to a second embodiment of the present disclosure, a display device 300 includes: a substrate 102 comprising a display area DA and a non-display area NDA outside the display area DA; the display area DA includes a first display area DA1 and a second display area DA2; a first light-emitting diode D1 in the first display area DA1; a second light-emitting diode D2 in the second display area DA2; a cathode separation pattern 280 disposed between the first display area DA1 and the second display area DA2; an anti-deposition pattern 284 disposed in a portion of the second display area DA2; and a ( ) in the non-display area NDA. Figure 5 (The first low potential voltage line 192 and the second low potential voltage line 194.)

[0230] Compared to the display device 100 according to the first embodiment of this disclosure, the display device 300 according to the third embodiment of this disclosure has a major difference in the cathode separation pattern 380. The description of the display device 300 focuses on the cathode separation pattern 380.

[0231] A third interlayer insulating layer 142 is formed on the substrate 102, and a first planarization layer 152 is formed on the third interlayer insulating layer 142. A second low-potential voltage line 394 is formed on the first planarization layer 152.

[0232] In embodiments of this disclosure, a second low-potential voltage line 394 may be disposed between the substrate 102 and the first planarization layer 152.

[0233] A second planarization layer 154 covering the second low-potential voltage line 394 is formed on the first planarization layer 152. The first planarization layer 152 and the second planarization layer 154 in the transmission region TA of the second pixel region P2 can be removed, thereby exposing the third interlayer insulating layer 142.

[0234] A second anode 360a, corresponding to the light-emitting region EA, is disposed on the second planarization layer 154 and in the second pixel region P2. Furthermore, an auxiliary electrode 361 is disposed on the second planarization layer 154 and between the light-emitting region EA and the transmission region TA. The auxiliary electrode 361 is connected to a second low-potential voltage line 394 through a contact hole in the second planarization layer 154.

[0235] The auxiliary electrode 361 may be formed of the same material as the second anode 360a. Alternatively, the auxiliary electrode 361 may be formed of the same material as the second low-potential voltage line 394.

[0236] A dam 356 is disposed at the boundary of the second pixel region P2 and between the transmissive region TA and the luminescent region EA. The dam 356 covers the edge of the second anode 360a and includes openings corresponding to the transmissive region TA and the luminescent region EA. The second anode 360a is exposed through the opening in the luminescent region EA, and the third interlayer insulating layer 142 is exposed through the opening in the transmissive region TA.

[0237] Furthermore, the embankment 356 further includes an auxiliary contact hole CH that exposes the auxiliary electrode 361.

[0238] A second light-emitting layer 360b is disposed on the second anode 360a in the light-emitting region EA of the second pixel region P2. The second light-emitting layer 360b may not exist in the transmission region TA, thereby exposing the third interlayer insulating layer 142.

[0239] The cathode separation pattern 380 is configured to surround the second pixel region P2, and the anti-deposition pattern 384 is configured in the transmission region TA of the second pixel region P2. The cathode separation pattern 380 may be positioned on the embankment 356 surrounding the second pixel region P2, and the anti-deposition pattern 384 may be positioned on the third interlayer insulating layer 142 in the transmission region TA.

[0240] In embodiments of this disclosure, at least one of the first planarization layer 152 and the second planarization layer 154 may be formed on the third interlayer insulating layer 142 in the transmission region TA. In this case, the anti-deposition pattern 384 may be positioned on the first planarization layer 152 or the second planarization layer 154 in the transmission region TA.

[0241] exist Figure 10 In this embodiment, the second light-emitting layer 360b is present in the light-emitting region EA but not in the transmission region TA. In embodiments of this disclosure, the second light-emitting layer 360b may exist in both the light-emitting region EA and the transmission region TA. In this case, the anti-deposition pattern 384 may be positioned on the second light-emitting layer 360b in the transmission region TA.

[0242] Each of the cathode separation pattern 380 and the anti-deposition pattern 384 may include a compound represented by Formula 1. For example, each of the cathode separation pattern 380 and the anti-deposition pattern 384 may independently include a compound selected from the compounds in Formula 2.

[0243] The second cathode 360c is disposed on the second light-emitting layer 360b in the light-emitting region EA. The second cathode 360c extends into the auxiliary contact hole CH in the embankment 356 to be connected to the auxiliary electrode 361 through the auxiliary contact hole CH. Therefore, the second cathode 360c is electrically connected to the second low-potential voltage line 394 through the auxiliary electrode 361.

[0244] A first light-emitting diode D1 is disposed in a first pixel region P1, and a third light-emitting diode D3 is disposed in a third pixel region P3. For example, the first cathode 358c of the first light-emitting diode D1 in the first pixel region P1 can extend into the non-display region NDA to connect to ( Figure 5 The first low-potential voltage line 192. In embodiments of this disclosure, the first cathode 358c may be connected to the first low-potential voltage line 192 in the first pixel region P1.

[0245] In the display device 300 according to the third embodiment of the present disclosure, a cathode separation pattern 380 is disposed between a first pixel region P1, which is a light-emitting pixel region, and a second pixel region P2, which is a sensing pixel region. The first cathode 358c of the first light-emitting diode D1 in the first pixel region P1 and the second cathode 360c of the second light-emitting diode D2 in the second pixel region P2 are respectively connected to a first low-potential voltage line 192 and a second low-potential voltage line 394. Therefore, brightness reduction in the second pixel region P2, which includes a transmission region TA and a light-emitting region TA, and thus has a smaller light-emitting region than the first pixel region P1, can be prevented, allowing the display device 300 to provide a high-brightness image.

[0246] Furthermore, in the display device 300, by selectively depositing (or forming) the first cathode 358c and the second cathode 360c in the desired area using the cathode separation pattern 380 and the anti-deposition pattern 384 formed by the same process and the same materials, a display device 300 with sensing function and high brightness can be provided without additional processes.

[0247] Furthermore, in the display device 300, when a third pixel region P3, which serves as a light-emitting pixel region, is arranged in the second display region DA2, the cathode in the third pixel region P3 is separated from the second cathode 360c in the second pixel region P2, which serves as a sensing pixel region, and connected to the first low-potential voltage line 192. Therefore, brightness uniformity between the first pixel region P1 and the third pixel region P3, which serve as light-emitting pixel regions, can be prevented.

[0248] Those skilled in the art will recognize that various modifications and variations may be made to the embodiments of this disclosure without departing from the spirit or scope thereof. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area outside the display area, the display area including a first display area and a second display area, the first display area including a first pixel area, the second display area including a second pixel area, the second pixel area including a first light-emitting area and a transmissive area; A first light-emitting diode, wherein the first light-emitting diode is located in the first pixel region and includes a first anode, a first light-emitting layer and a first cathode; The second light-emitting diode is located in the first light-emitting region and includes a second anode, a second light-emitting layer, and a second cathode. Cathode separation pattern between the first pixel region and the second pixel region; Anti-deposition pattern in the transmission area; The first low-potential voltage line in the non-display area; and The second low-potential voltage line in the non-display area. The first cathode and the second cathode are separated by the cathode separation pattern, and The first cathode is connected to the first low-potential voltage line and the second cathode is connected to the second low-potential voltage line.

2. The display device according to claim 1, wherein the anti-deposition pattern extends from the cathode separation pattern.

3. The display device according to claim 1, wherein the cathode separation pattern spans the space between the first display area and the second display area.

4. The display device according to claim 3, wherein the first cathode in one of the first pixel regions is connected to the first cathode in another of the first pixel regions, and the second cathode in one of the second pixel regions is connected to the second cathode in another of the second pixel regions.

5. The display device of claim 1, wherein the second cathode includes a cathode extension portion extending into the non-display area to connect to the second low-potential voltage line, and the cathode separation pattern surrounds the second cathode and the cathode extension portion.

6. The display device according to claim 5, wherein the cathode extension portion in one of the second pixel regions is connected to the cathode extension portion in another of the second pixel regions.

7. The display device according to claim 5, wherein the first low-potential voltage line includes a first line on one side of the second low-potential voltage line and a second line on the other side of the second low-potential voltage line.

8. The display device according to claim 7, further comprising: The first dike is located between the first line and the second low-potential voltage line; and The second dike is located between the second line and the second low-potential voltage line. The cathode separation pattern is disposed on the first embankment and the second embankment.

9. The display device according to claim 1, wherein the cathode separation pattern surrounds the second pixel region.

10. The display device of claim 9, wherein the second cathode is connected to the second low-potential voltage line in the second pixel region.

11. The display device according to claim 1, wherein the first pixel region includes a second light-emitting region.

12. The display device according to claim 11, wherein the area of ​​the second light-emitting region is larger than the area of ​​the first light-emitting region.

13. The display device according to claim 12, wherein the area of ​​the second light-emitting region is equal to the sum of the area of ​​the first light-emitting region and the area of ​​the transmissive region.

14. The display device according to claim 1, wherein the area of ​​the first cathode is larger than the area of ​​the second cathode.

15. The display device according to claim 1, wherein the first low-potential voltage line and the second low-potential voltage line are disposed on the same layer.

16. The display device of claim 1, wherein a first voltage is applied to the first low-potential voltage line and a second voltage is applied to the second low-potential voltage line, and The second voltage is less than the first voltage.

17. The display device according to claim 1, further comprising: A sensor is disposed in the transmission region.

18. The display device according to claim 1, wherein the cathode separation pattern and the anti-deposition pattern are formed of the same material.

19. The display device according to claim 1, wherein the side surface of the cathode separation pattern is in contact with the side surface of the first cathode and the side surface of the second cathode.

20. The display device according to claim 1, wherein the side surface of the anti-deposition pattern is in contact with the side surface of the first cathode and the side surface of the second cathode.

21. The display device according to claim 16, wherein the brightness of the first light-emitting diode is uniform with the brightness of the second light-emitting diode.

22. The display device according to claim 1, wherein the second cathode is not disposed in the transmission region.

23. The display device according to claim 1, wherein the second display area further includes a third pixel area, and a third light-emitting diode is disposed in the third pixel area.

24. The display device according to claim 23, wherein the cathode of the third light-emitting diode is connected to the first low-potential voltage line.

25. The display device of claim 5, wherein the cathode separation pattern comprises a first pattern surrounding three sides of the second cathode and having openings corresponding to the cathode extension portion, and a second pattern and a third pattern extending from the first pattern along both sides of the cathode extension portion.

26. The display device of claim 7, further comprising a dam including a first contact hole and a third contact hole exposing the first line and the second line respectively, and a second contact hole exposing the second low-potential voltage line.

27. The display device according to claim 26, wherein the embankment is formed on the planarization layer, and The embankment and a portion of the planarization layer are disposed in the third contact hole.

28. The display device of claim 1, wherein the cathode separation pattern completely surrounds each second pixel region, and The second low-potential voltage line extends into the second pixel region.

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