A capacitive micromechanical array ultrasonic transducer and its electrical insulation testing method
By using an all-silicon electrode structure and electrical insulation testing methods, the problem of electrode isolation defects in CMUT devices before bonding was solved, enabling efficient testing and repair, improving the yield of CMUT devices and reducing manufacturing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- EAST CHINA INST OF OPTOELECTRONICS INTEGRATEDDEVICE
- Filing Date
- 2026-04-09
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies cannot detect electrode isolation defects before wafer bonding, leading to short-circuit failure of CMUT devices and increasing manufacturing costs.
A capacitive micromechanical array ultrasonic transducer with an all-silicon electrode structure was used to detect and repair incompletely etched isolation trenches by performing electrical insulation testing before wafer bonding and testing the insulation of the bottom electrode using a probe station.
This method enables the detection and repair of electrode isolation defects before wafer bonding, improving yield, reducing manufacturing costs, and is simple, fast, and applicable to wafers of different sizes and process routes.
Smart Images
Figure CN122298646A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of ultrasonic transducers, specifically to a capacitive micromechanical array ultrasonic transducer and a method for detecting the electrical insulation of its bottom electrode before wafer bonding. Background Technology
[0002] A capacitive micromachined ultrasonic transducer (CMUT) is an ultrasonic sensor based on MEMS (Micro-Electro-Mechanical Systems) technology. It can realize the mutual conversion of electrical energy and mechanical energy and is widely used in industrial non-destructive testing and ultrasonic medical imaging.
[0003] Wafer bonding is one of the mainstream manufacturing processes for CMUTs (Computer-Assisted Transformers). In this process, before wafer-level bonding, the bottom electrode needs to be patterned, and it must achieve good electrical insulation isolation from the substrate, anchor points, and other adjacent electrodes; otherwise, short-circuit failure will occur. However, due to the complex three-dimensional structure of CMUTs, the bottom electrode isolation trenches are long, narrow, deep, and dense, making it impossible to determine the completeness of etching using conventional optical methods. Therefore, insulation testing of CMUTs is often performed at the wafer level after all manufacturing processes are completed. However, this method can only determine whether a device has failed, but cannot pinpoint the cause and form of the failure, let alone rework it. Therefore, once a short circuit is detected, it often means that all devices have failed, or even the entire wafer is scrapped, significantly increasing manufacturing costs. Summary of the Invention
[0004] The purpose of this invention is to solve the problem that electrode isolation defects cannot be detected before bonding in the prior art. It provides a capacitive micromechanical array ultrasonic transducer with an all-silicon electrode structure and a manufacturing process and testing method with electrical insulation detection function before bonding.
[0005] To achieve the above objectives, the present invention adopts the following technical solution: A capacitive micromechanical array ultrasonic transducer, characterized by comprising the following components: (1) Top electrode layer, including silicon diaphragm, on the surface of silicon diaphragm are passivation layer and top electrode pad, and an array of cavities are etched at the bottom of silicon diaphragm; (2) Bottom electrode layer (i.e., CMUTs array), including SOI substrate silicon, SOI buried oxide layer and SOI silicon device layer on the buried oxide layer; an array of isolation trenches is formed on the silicon device layer, the isolation trenches divide the SOI silicon device layer into array bottom electrodes corresponding to the array cavity, and silicon wires interconnected by the isolation trenches are provided between adjacent bottom electrodes, bottom electrode islands surrounded by the isolation trenches are provided on the silicon device layer, bottom electrode pads are formed on the bottom electrode islands, and silicon wires interconnected by the isolation trenches are provided between the bottom electrode islands and a bottom electrode, and external anchor points are formed outside the isolation trenches of the silicon device layer, and metal anchor pads are formed on the surface of the external anchor points; (3) After the top electrode layer and the bottom electrode layer are bonded together, a capacitive micromechanical array ultrasonic transducer is formed. The vacuum cavity array formed and the corresponding bottom electrode array constitute the acoustic sensitive area.
[0006] The fabrication methods for the top electrode layer and the bottom electrode layer are both conventional methods in the field of MEMS and wafer manufacturing.
[0007] This invention also provides a method for detecting the electrical insulation of a capacitive micromechanical array ultrasonic transducer, characterized by comprising the following steps: Step S1: After completing the fabrication of the bottom electrode layer (i.e., CMUTs array) within the wafer pattern area, select a test area containing a certain number of bottom electrode layers within the pattern area. Step S2: Use a probe station to perform wafer-level testing on the bottom electrode of the array in the selected test area, that is, two test probes contact the center area of the bottom electrode pad and the anchor pad respectively. Step S3: Set the test voltage to 1~5V DC, set the measurement mode to resistance mode or voltage-current mode, and read the resistance value; if the resistance is >1GΩ, it indicates good insulation; if the resistance is <1GΩ, it indicates that the isolation groove is not completely etched. Step S4: Re-etch the areas that were not completely etched, and re-measure the insulation resistance of the area to ensure that the entire array is electrically insulated. Step S5: Perform wafer bonding and proceed with subsequent processes.
[0008] The beneficial effects achieved by this invention are: (1) The present invention provides a method for detecting the electrical insulation of a CMUT array and wafer before bonding. The detection method can detect the etching defects of the bottom electrode isolation trench before wafer bonding, and make timely adjustments to process parameters or re-fabrication, which facilitates rework, prevents defects from flowing into subsequent processes and causing irreparable losses, greatly improves yield and reduces manufacturing costs. (2) The detection method provided by the present invention uses a standard semiconductor probe station, which can be implemented online. The detection time is short, the method is simple, it does not occupy the critical process path, and the detection results can be incorporated into the process MES system to form a complete quality traceability chain and meet the quality compliance requirements. (3) The detection method provided by the present invention is applicable to the manufacturing of CMUTs with different wafer sizes and different process routes, and can be extended to the electrical insulation detection of other MEMS devices such as PMUTs and microphones, and has good technical promotion value. Attached Figure Description
[0009] Figure 1 This is an overall schematic diagram of a CMUTs array (chip) in an embodiment of the present invention; Figure 2 This is a cross-sectional structural diagram of a CMUTs array (chip) in an embodiment of the present invention; Figure 3 This is a schematic diagram of the bottom electrode pattern in a CMUTs array (chip) according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the first instance of ineffective isolation in an embodiment of the present invention; Figure 5 This is a schematic diagram of the second type of failure to form effective isolation in an embodiment of the present invention; Figure 6 This is a schematic diagram of the third type of failure to form effective isolation in the embodiments of the present invention; Figure 7 This is a flowchart of the electrical insulation test performed before bonding in an embodiment of the present invention; Figure 8 This is a schematic diagram of selecting an array (chip) of CMUTs on a wafer in an embodiment of the present invention.
[0010] The diagram is labeled as follows: 01, CMUTs array (chip); 02, acoustic sensitive area of the chip; 03, top electrode pad; 04, bottom electrode pad; 05, passivation layer; 06, diaphragm silicon (top electrode); 07, vacuum cavity (sealed); 08, insulating layer; 09, anchor pad; 10, SOI silicon device layer; 10a, bottom electrode; 10b, bottom electrode silicon wire; 10c, bottom electrode pad island; 10d, external anchor area; 10e, internal anchor; 11, bottom electrode isolation trench; 12, SOI buried oxide layer; 13, SOI silicon substrate; 14, wafer; 15, chip pattern area; 16, five-point selection box. Detailed Implementation
[0011] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.
[0012] It should be noted that in the description of this invention, the terms "front", "rear", "left", "right", "upper", "lower", "middle", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention. Example 1
[0013] I. The present invention provides a capacitive micromechanical array ultrasonic transducer, such as... Figure 1 , Figure 2 and Figure 3 As shown, it includes the following components: (1) The top electrode layer includes a silicon diaphragm 06, a passivation layer 05 and a top electrode pad 03 are formed on the surface of the silicon diaphragm 06, and an array of cavities 07 are etched at the bottom of the silicon diaphragm 06. (2) Bottom electrode layer, including SOI substrate silicon 13, SOI buried oxide layer 12 and SOI silicon device layer 10 on buried oxide layer 12; a series of isolation trenches 11 are formed on silicon device layer 10, the series of isolation trenches 11 divide SOI silicon device layer 10 into bottom electrodes 10a of array corresponding to array cavity 07, and silicon wires 10b connecting the bottom electrodes are formed between adjacent bottom electrodes 10a by isolation trenches. Bottom electrode islands 10c are provided on silicon device layer 10 by isolation trenches, bottom electrode pads 04 are formed on bottom electrode islands, and silicon wires 10b connected by isolation trenches are provided between bottom electrode islands and a bottom electrode 10a. The part outside the isolation trenches of silicon device layer 10 is an external anchor point 10d, and a metal anchor point pad 09 is formed on the surface of the external anchor point. (3) After the top electrode part and the bottom electrode part are bonded together, a capacitive micromechanical array ultrasonic transducer 01 is formed. The vacuum cavity 07 array and the corresponding bottom electrode 10a array constitute the acoustic sensitive area 02. Its overall shape includes but is not limited to square, rectangle, polygon and circle. Preferably, its overall shape should be easy to dicing operation on the premise of meeting the design requirements. Furthermore, the overall shape of the acoustically sensitive area 02 includes, but is not limited to, a circle, a square, a rectangle, a polygon, or other complex symmetrical shapes. Preferably, while increasing the area fill rate, the acoustic performance of the CMUTs array should be guaranteed. The top electrode pad 03 can be distributed in any area except the acoustically sensitive area 02. Preferably, its shape is circular or rounded square, which can effectively reduce tip discharge under high voltage. Furthermore, the pad metal material can be Ti / Au or Cr / Au; The bottom electrode pad 04 can be distributed in any area other than the acoustically sensitive area 02 and the top electrode pad 03, including but not limited to... Figure 1 The diagonal of the top electrode pad 03 shown can also be a corner on the same side as the top electrode pad 03, or even the same corner of the top electrode pad 03 but not in contact with it.
[0014] The passivation layer 05 is located on the surface of the diaphragm silicon 06. Preferably, the passivation layer material can be silicon dioxide or silicon nitride. Further, a suitable window is etched into the passivation layer 05 to fabricate the top electrode pad 03 on the surface of the diaphragm silicon 06, thus creating an electrical connection between the two. Furthermore, densely packed cavities are etched at the bottom of the silicon diaphragm 06, forming a vacuum-sealed cavity 07 after wafer bonding. Furthermore, each vacuum-sealed cavity 07, together with the silicon diaphragm 06 directly above it and the patterned bottom electrode silicon 10a directly below it, forms a basic acoustic sensing unit. Furthermore, the array of all acoustic sensing units is combined to form an acoustic sensing region 02.
[0015] 2. The silicon device layer 10 is patterned so that it is divided by the bottom electrode isolation trench 11 into bottom electrode silicon 10a, bottom electrode silicon wire 10b, bottom electrode pad island 10c, external anchor point 10d and internal anchor point 10e. Metal pads are prepared on the surface of the SOI device layer silicon 10 to form bottom electrode pad 04 and anchor pad 09. Below the SOI device layer silicon are SOI buried oxide layer 12 and SOI substrate silicon 13. The above structure constitutes the bottom electrode part for wafer bonding.
[0016] The SOI device layer silicon 10 is used as the bottom electrode layer. Preferably, low-resistivity silicon with a resistivity of 0.01~0.02Ω·cm or less is used. Further, bottom electrode pads 04 and anchor pads 09 are prepared on the surface of SOI device layer 10. Further, an insulating layer 08 is prepared on the upper surface of SOI device layer 10, bottom electrode pads 04 and anchor pads 09. The insulating layer 08 serves as the bonding surface for wafer bonding and is bonded to the diaphragm silicon 06. Therefore, to ensure good pre-bonding and high-strength annealing, the surface roughness of the bonding layer should be less than 0.5 nm, preferably less than 0.3 nm. Further, the insulating layer 08 can be silicon dioxide prepared using a PECVD process, and its thickness should be greater than the thickness of the metal pads. Furthermore, a cavity of a certain depth is etched on the surface of the insulating layer 08 to expose the bottom electrode pad 04 and the anchor pad 09 buried in the insulating layer 08. Furthermore, the SOI silicon device layer 10 after completing the above steps is patterned to form an isolation trench 11, which isolates the bottom electrode silicon from the anchor point. Preferably, the isolation trench should be the smallest width that the process can achieve while ensuring thorough etching, so as to obtain the maximum area utilization. After wafer bonding is completed, the diaphragm silicon should be etched to expose the bottom electrode pad 04.
[0017] III. Figure 3 As shown, the patterning process for the SOI device layer 10 should be performed before wafer bonding. This involves etching the SOI device layer 10 to form a bottom electrode isolation trench 11 of a certain width, dividing the SOI device layer 10 into inner and outer parts. The etching depth of the bottom electrode isolation trench 11 should be at least the sum of the thickness of the insulating layer 08 and the thickness of the SOI device layer 10. This ensures that no residual silicon remains within the isolation trench 11, preventing physical and electrical connections between the inner and outer parts. Inside the isolation groove are a circular bottom electrode 10a, a bottom electrode pad island 10c, a bottom electrode silicon wire 10b connecting two adjacent bottom electrodes 10a or connecting a bottom electrode 10a and a bottom electrode pad island 10c, and an internal anchor point 10e. The circular bottom electrode 10a should be located directly below the vacuum sealing cavity 07, and the number and position of the two should correspond one-to-one. Further, any two adjacent bottom electrode silicon 10a are connected by bottom electrode silicon wires 10b, and any four adjacent bottom electrode silicon 10a are separated by an internal anchor point 10e by the bottom electrode isolation groove 11. Further, any bottom electrode silicon 10a located at the boundary of the acoustically sensitive area 02 is arbitrarily selected and connected to the bottom electrode pad island 10c by silicon wires 10b, preferably a bottom electrode silicon 10a near a corner of the CMUTs array 01. Further, the bottom electrode pad 04 should be located on the surface of the bottom electrode pad island 10c, thereby realizing the connection between the bottom electrode pad and all bottom electrode silicon.
[0018] The external anchor point 10d is located outside the isolation groove. Furthermore, the anchor pad 09 should be located on the surface of the external anchor point 10d. Therefore, the anchor pad 09 and the bottom electrode pad 04 are electrically insulated from each other by the physical isolation of the bottom electrode isolation groove 11. Example 2
[0019] Before wafer bonding, the patterned SOI device layer 10 is subjected to electrical insulation testing. The electrical insulation problems proposed in this invention include, but are not limited to, the following three situations: 1. For example Figure 4 As shown, among the four adjacent bottom electrode silicon 10a, one does not have a bottom electrode silicon wire 10b led out, causing the bottom electrode silicon wire 10b to be cut off in the middle. This results in the bottom electrode isolation trench 11 not being fully formed. At this time, a portion of the silicon wire 10b crosses the bottom electrode isolation trench 11 and forms a physical connection with the outer anchor point 10d and the inner anchor point 10e of the bottom electrode. Therefore, no physical isolation is formed between the bottom electrode silicon 10a and the outer anchor point 10d, resulting in electrical conduction. The reasons for this situation include, but are not limited to, structural design / layout errors or incorrect etching parameter settings, and incomplete etching of the silicon at the bottom of both isolation trenches. 2. For example Figure 5As shown, among the four bottom electrode silicon wires connecting four adjacent bottom electrode silicon 10a, the outer isolation groove 11 of one silicon wire is not fully formed, that is, the side of the isolation groove 11 near the external anchor point 10d is not thoroughly etched. At this time, the silicon wire is directly physically connected to the external anchor point 10d. Therefore, the bottom electrode silicon 10a is electrically conductive because there is no physical isolation between this silicon wire 10b and the external anchor point 10d. The reasons for this situation include, but are not limited to, structural design / layout drawing errors or incorrect etching parameter settings, and incomplete etching of the silicon at the bottom of the outer isolation groove. 3. For example Figure 6 As shown, among the four bottom electrode silicon wires connecting four adjacent bottom electrode silicon 10a, the inner isolation groove 11 of one silicon wire is not fully formed, that is, the side of the isolation groove 11 near the inner anchor point 10e is not thoroughly etched. In this case, the silicon wire is directly physically connected to the inner anchor point 10e. Therefore, the insulation resistance of the bottom electrode silicon 10a is reduced because there is no physical isolation between this silicon wire 10b and the inner anchor point 10e. The reasons for this situation include, but are not limited to, structural design / layout errors or incorrect etching parameter settings, and incomplete etching of the silicon at the bottom of the inner isolation groove. In this case, the bottom electrode silicon 10a is still electrically insulated from the outer anchor point 10d, but the insulation resistance will be significantly reduced compared to the normal insulation state, and a significant parasitic capacitance will be formed between it and the top electrode after wafer bonding, affecting the acoustic performance of the CMUTs array.
[0020] like Figure 7 As shown, the present invention provides a specific testing procedure for electrical insulation testing: Step S1: As Figure 8 As shown, a chip patterning area 15 is formed on a wafer 14 after a patterning process. Within this patterning area, an array of unbonded CMUTs (chips) 01 is densely distributed; that is, it does not include the passivation layer 05, the silicon diaphragm (upper electrode) 06, or the top electrode pad 03, but only contains... Figure 3The bottom electrode layer structure shown is referred to as CMUTs array (chip) 01 in the following steps of this embodiment. A portion of the CMUTs array (chip) 01 is randomly selected from five locations (top / middle / bottom / left / right) of the chip pattern area 15 using a five-point method. However, the five locations (top / middle / bottom / left / right) are general descriptions and can be any five different areas of the chip pattern area 15; the selection box should not be limited to the five directions shown in the figure. Each selection box should include one or more CMUTs array (chip) 01s. Preferably, the selection box can be square, circular, or any regular or irregular shape. The number of CMUTs array (chip) 01s included in the selection box can be consistent or inconsistent, but the total number of CMUTs array (chip) 01s selected by the five-point method should be 10% to 15% of the total number of CMUTs array (chip) 01s on a wafer 14. Alternatively, some or all of them can be selected for electrical insulation testing depending on the actual situation. Step S2: Perform wafer-level testing on the CMUTs array (chip) 01 selected in Step 1 using a probe station. During testing, for any CMUTs array (chip) 01 to be tested, ensuring that the wafer surface is clean and free of contaminants, place two test probes in the center areas of its bottom electrode pad 04 and anchor pad 09 respectively. At this time, observe under a microscope that the probes are just in contact with the pads or that the probes are slightly bent. Step S3: Set the test voltage to 1~5V DC, set the measurement mode to resistance mode or voltage-current mode, read the resistance value, and repeat the measurement three to five times, taking the average value. If the resistance > 1GΩ, it indicates good insulation between the bottom electrode silicon 10a and the external anchor point 10d; if the resistance < 1GΩ, it indicates incomplete etching of the isolation trench. Furthermore, if the resistance < 100MΩ, it may be... Figure 4 and Figure 5 The situation shown; if the resistance is between 100MΩ and 1GΩ, it may be... Figure 6 As shown in the figure. It should be noted that the insulation resistance value proposed in this invention refers to the order of magnitude rather than a specific value. The specific value should be determined based on the actual structure and the resistivity of the materials. When the measured resistance value is much lower than the theoretical / empirical value, it proves that the insulation is not working. Step S4: Based on the resistance test results, carefully check the structure and layout. If there are structural or layout issues, the board needs to be remade. If the issue is with the process parameter settings, the etching time should be appropriately increased to achieve just the right etching state, thus ensuring insulation. Rework should be performed according to these two scenarios, and the insulation resistance of the corresponding areas should be retested until the entire array achieves electrical insulation. Step S5: Perform wafer bonding and proceed with subsequent processes.
[0021] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles and spirit of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A capacitive micromechanical array ultrasonic transducer, characterized in that... It includes the following components: (1) Top electrode layer, including silicon diaphragm (06), passivation layer (05) and top electrode pad (03) are formed on the surface of silicon diaphragm (06), and an array of cavities (07) are etched at the bottom of silicon diaphragm (06). (2) Bottom electrode layer, including SOI substrate silicon (13), SOI buried oxide layer (12) and SOI silicon device layer (10) on buried oxide layer (12); an array of isolation trenches (11) is formed on the silicon device layer (10), the isolation trenches (11) divide the SOI silicon device layer (10) into array bottom electrodes (10a) corresponding to the array cavity (07), and interconnecting silicon wires (10b) formed by isolation trenches are provided between adjacent bottom electrodes (10a), bottom electrode islands (10c) surrounded by isolation trenches are provided on the silicon device layer (10), bottom electrode pads (04) are formed on the bottom electrode islands, and interconnecting silicon wires (10b) formed by isolation trenches are provided between the bottom electrode islands and a bottom electrode (10a), and external anchor points (10d) are set in the area outside the isolation trenches of the silicon device layer (10), and metal anchor pads (09) are formed on the surface of the external anchor points; (3) After the top electrode layer and the bottom electrode layer are bonded together, a capacitive micromechanical array ultrasonic transducer is formed. The vacuum cavity (07) array and the corresponding bottom electrode (10a) array constitute the acoustic sensitive area (02).
2. The method for detecting the electrical insulation of a capacitive micromechanical array ultrasonic transducer according to claim 1, characterized in that... Includes the following steps: Step S1: After completing the fabrication of the bottom electrode layer of the array within the patterned area (15) of the wafer (14), a test area (16) containing a certain number of bottom electrode layers is selected within the patterned area. Step S2: Use a probe station to perform wafer-level testing on the bottom electrode of the array in the selected test area (16), that is, two test probes contact the center areas of the bottom electrode pad (04) and the anchor pad (09) respectively. Step S3: Set the test voltage to 1~5V DC, set the measurement mode to resistance mode or voltage-current mode, and read the resistance value; if the resistance is >1GΩ, it indicates good insulation; if the resistance is <1GΩ, it indicates that the isolation groove is not completely etched. Step S4: Re-etch the areas that were not completely etched, and re-measure the insulation resistance of the area to ensure that the entire array is electrically insulated. Step S5: Perform wafer bonding and proceed with subsequent processes.