Polishing Composition and Its Application

Abstract

This disclosure relates to a polishing composition comprising at least one abrasive; at least one nitride removal reducing agent; an acid or alkali; and water. The at least one nitride removal reducing agent may include C... 12 To C 40 The polishing composition comprises a hydrophobic portion of a hydrocarbon group and a hydrophilic portion containing at least one group selected from the group consisting of sulfinic acid, sulfate, sulfonic acid, carboxyl, phosphate, and phosphonic acid groups; wherein the hydrophobic and hydrophilic portions are separated by 0 to 10 epoxy alkyl groups. The polishing composition may have a pH of about 2 to about 6.5.

Description

Case Analysis

[0001] This application is a divisional application of Chinese Patent Application No. 201910812821.8, filed August 30, 2019, entitled "Polishing Composition and Method of Using the Same". That Chinese Patent Application claims priority to U.S. Application Serial No. 16 / 356,669, filed March 18, 2019, which in turn claims priority to U.S. Provisional Application Serial No. 62 / 781,648, filed December 19, 2018, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This invention relates to polishing compositions and methods of using them. Background Technology

[0003] The semiconductor industry is continuously driven by the further miniaturization of devices through process and integration innovations to improve chip performance. Chemical mechanical polishing / planarization (CMP) is a powerful technology because it enables many complex integration schemes at the transistor level, thereby facilitating increased chip density.

[0004] Transistors are typically fabricated in the Front End of Line (FEOL) transistor manufacturing process. FEOL material stacks typically consist of a metal gate and a stack of multiple dielectric materials. Electrical isolation of the billions of active components in various integrated circuits is the goal in FEOL and can be achieved using a shallow trench isolation (STI) process. For illustrative purposes, a portion of the STI process is shown. Figure 1 For example from Figure 1 As can be seen, prior to the STI CMP process, thermally oxidized silicon and SiN can be deposited on top of silicon (e.g., silicon wafer). Figure 1 (a) and then etched out to create trench / isolation and “active” non-trench regions (to form transistor-containing regions) Figure 1 (b) Subsequently, these trench / isolation regions can be filled by depositing silicon oxide (e.g., TEOS) in the trenches (e.g., by using plasma-enhanced chemical vapor deposition (PECVD)), thereby isolating the active non-trench regions with silicon oxide in the trenches. Figure 1 (c) Subsequently, the "overload / extra" silica in the active non-trench region may optionally be removed while retaining silica in the trench. Figure 1(d) Selective removal of silicon oxide is achieved by a shallow trench isolation (STI) chemical mechanical polishing / planarization (CMP) process, wherein a CMP polishing composition (such as that described in this invention) with high material removal rate (MRR) selectivity for silicon oxide and silicon nitride (e.g., SiN) is used to remove silicon oxide at a high rate, preferably without significant removal of silicon nitride (stop layer). After the above STI CMP step, etching may be used to expose silicon to complete the isolation and prevent adjacent transistors formed in the active non-trench region from becoming in contact with each other, thereby preventing short circuits in the circuit.

[0005] Commonly used dielectric films for STI are silicon nitride (e.g., SiN), silicon oxide (e.g., TEOS: tetraethyl orthosilicate), polycrystalline silicon (P-Si), silicon carbonitride (e.g., SiCN), and low-k / ultra-low-k dielectric films (e.g., SiCOH). With the introduction of high-k metal gate technology at 45nm and FinFET technology in 22nm chip fabrication, SiN, TEOS, SiCN, and P-Si films have become more commonly used and are found in more applications of FEOL. Furthermore, in back-end processes (BEOL), because the resistivity of conventional barrier materials (e.g., Ta / TaN or Ti / TiN) has been shown to be ineffective for scaling down to advanced 10nm manufacturing nodes, these barrier materials can be replaced by dielectrics (such as SiN, TEOS, SiCN, and P-Si) for various different BEOL material stacks. Therefore, for both FEOL and BEOL, these dielectric films can be used as etch stop layers, cover materials, spacers, additional pads, diffusion / passivation barriers, hard masks, and / or stop layers.

[0006] Generally speaking, dielectric thin films are used more generously in advanced semiconductor manufacturing. From a CMP perspective, much of the integration of these dielectrics requires polishing compositions (slurries) that can work / polish and / or stop on these films, such as slurries that can remove SiN but not remove (stop) TEOS / P-Si or slurries that can remove TEOS / p-Si but not remove (stop) SiN. Summary of the Invention

[0007] This invention relates to stable aqueous slurries that can optionally polish a variety of different materials (e.g., oxides such as silicon oxide) while achieving very low polishing / removal rates on silicon nitride and associated silicon and nitrogen-based thin films (like SiCN (silicon carbide nitride)). For example, the polishing composition can polish silicon oxide (e.g., SiO2) with a relatively high material removal rate (MRR) and stop on silicon nitride (e.g., SiN) or associated thin films or polish silicon nitride (e.g., SiN) or associated thin films at a very low rate. For example, silicon oxide that can be removed by the polishing composition described herein includes silicon oxide selected from: TEOS, thermal oxide (TOX) (e.g., oxidation induced by autoclave of bare silicon), silicon oxide formed by plasma-enhanced PVD deposition (e.g., high-density plasma or high aspect ratio plasma), silicon oxide formed by CVD deposition followed by post-plasma surface curing, carbon-doped silicon oxide (SiOC), and silicon oxide formed by liquid application of an oxide precursor followed by photo- or thermally induced curing. In some examples, the target film to be removed at high MRR can be a metal, metal oxide, or metal nitride instead of a silicon oxide dielectric. Common examples of metals, metal oxides, and metal nitrides include copper, cobalt, ruthenium, aluminum, titanium, tungsten, and tantalum for metals; hafnium oxide, titanium oxide, aluminum oxide, zirconium oxide, and tantalum oxide for metal oxides; and nitrides of ruthenium, aluminum, titanium, tungsten, and tantalum. In this case, the stop / low removal rate film can still be a silicon nitride film and therefore the desired selectivity can be achieved using polishing compositions from the present invention containing nitride removal rate reducing agents.

[0008] More specifically, the present invention relates to polishing compositions comprising abrasives, a nitride removal reducing agent, an acid or alkali, water, and optionally a dishing reducing agent (e.g., an anionic dishing agent). The pH of the polishing compositions described herein may be in the range of 2 to 6.5 or, more specifically, in the range of 2 to 4.5. The compositions of the present invention may be diluted (e.g., at the point of use) to form a polishing composition without any degradation in performance. The present invention also discusses methods for polishing semiconductor substrates using the polishing compositions described above.

[0009] In one aspect, the specific embodiments disclosed herein relate to a polishing composition comprising at least one abrasive, at least one nitride removal reducing agent, an acid or alkali, and water. The nitride removal reducing agent comprises substances containing C... 12 To C 40The polishing composition comprises a hydrophobic portion of a hydrocarbon group and a hydrophilic portion containing at least one group selected from the group consisting of sulfinite, sulfate, sulfonic acid, carboxyl, phosphate, and phosphonic acid groups; wherein the hydrophobic and hydrophilic portions are separated by 0 to 10 epoxy alkyl groups. The polishing composition has a pH of about 2 to about 6.5.

[0010] In another aspect, specific embodiments disclosed herein relate to a polishing composition comprising: at least one abrasive; at least one nitride removal rate reducing agent comprising a hydrophobic portion and a hydrophilic portion; an acid or base; and water; wherein the polishing composition has a pH of about 2 to about 6.5; and during polishing of a patterned wafer comprising at least a silicon nitride pattern, the polishing composition has a silicon oxide removal rate to silicon nitride removal rate ratio of at least about 3:1, wherein the silicon nitride pattern is covered with at least silicon oxide (and optionally other materials, such as metals or dielectrics).

[0011] In another aspect, the specific embodiments disclosed herein relate to a polishing composition comprising: at least one abrasive; at least one nitride removal rate reducing agent comprising a hydrophobic portion and a hydrophilic portion; an acid or base; and water; wherein the polishing composition has a pH of about 2 to about 6.5; wherein when a patterned wafer comprising at least a silicon nitride pattern covered with at least silicon oxide is polished with the polishing composition, silicon oxide depressions of less than about 1000 angstroms occur, wherein the polishing exposes the silicon nitride pattern on the patterned wafer.

[0012] In another aspect, the specific embodiments disclosed herein relate to a polishing composition comprising: at least one abrasive; at least one nitride removal rate reducing agent comprising a hydrophobic portion and a hydrophilic portion; an acid or base; and water; wherein the polishing composition has a pH of about 2 to about 6.5; wherein when a patterned wafer comprising at least a silicon nitride pattern covered with at least silicon oxide is polished with the polishing composition, silicon nitride etching of less than about 500 angstroms occurs, wherein the polishing exposes the silicon nitride pattern on the patterned wafer.

[0013] In another aspect, specific embodiments disclosed herein relate to a method comprising: applying a polishing composition described herein to a substrate having at least silicon nitride and at least silicon oxide on its surface; and contacting a pad with the surface of the substrate and moving the pad relative to the substrate. The synergistic use of the abrasive, nitride RR reducer, and optionally an indentation reducer in the same composition provides unique advantages not found in currently available slurries. These benefits include the following: 1. The compositions described herein achieve very low silicon nitride (e.g., SiN) removal rates. Excellent silicon nitride protection can be achieved through the prudent selection and formulation / loading of silicon nitride removal reducing agents. Furthermore, as demonstrated in this invention, low silicon nitride removal rates are observed in both blank wafers (i.e., wafers containing only a silicon nitride film) and patterned wafers (i.e., wafers containing silicon nitride films etched in a pattern and other films (e.g., TEOS)).

[0014] 2. Very low silicon nitride removal rate enables minimal silicon nitride loss, thus resulting in very low silicon nitride etching after polishing on patterned wafers.

[0015] 3. The composition achieves low silica sink / step height. Sink performance can be adjusted through the judicious selection and loading / concentration of the sink reducing agent.

[0016] 4. The composition is compatible with a wide variety of abrasives. Through particle modification, the zeta potential of the abrasive can be adjusted to further modulate the removal rate on the target film. Anionic, cationic, and neutral abrasives can all form stable slurries with higher silica removal rates and relatively lower silicon nitride removal rates.

[0017] 5. The composition can form a stable slurry with high-purity silica as the abrasive. This allows for the production of a slurry with low trace metal counts and low large particle counts when polished with conventionally used cerium dioxide abrasives (which generally produce a large number of defects on the polished wafer), resulting in a reduction of defects on the polished wafer. Furthermore, the composition described herein overcomes some of the drawbacks of conventional silica-based STI CMP compositions, such as their high silicon nitride removal rates and low removal selectivity between silica and silicon nitride.

[0018] 6. The compositions produce low nitride removal rates under various polishing conditions. For example, silicon nitride removal rates remain low on both hard polishing pads (e.g., polyurethane-based pads) and soft polishing pads (e.g., porous pads with low Shore D hardness). Furthermore, it has been observed that pressure and speed do not significantly affect silicon nitride removal rates, a desirable CMP property because the stopping film behavior is non-prestonian. The fact that the compositions disclosed in this invention exhibit very small variations in removal rates with pressure and speed results in excellent topography and high yields after patterned wafer polishing. In the language of the art, the compositions disclosed in this invention result in low values ​​for silicon oxide pitting and step height, along with low values ​​for silicon nitride corrosion / loss.

[0019] The polishing compositions and concentrates discussed in this invention offer performance support on current-generation integrated circuit substrates compared to contemporary pastes available today, while exhibiting significant advantages for next-generation substrates and integration solutions. The compositions disclosed in this invention can selectively and successfully remove a wide variety of different metal and dielectric layers with high efficiency relative to silicon nitride removal. These compositions can be used in shallow trench isolation (STI) processes, self-aligned contact processes, or other processes requiring very low silicon nitride material removal rates. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the shallow trench isolation (STI) process (including STI CMP) in semiconductor manufacturing. Figure 1 (a) shows that thermally deposited silicon oxide (TOX) and silicon nitride (SiN) are deposited on top of silicon (Si) prior to shallow trench isolation (STI) chemical mechanical planarization (CMP). Etching is then performed to create active regions. Figure 1 (b) This shows that the trench has been created, leaving an active region of silicon covered by TOX and SiN. It is then filled with a dielectric – typically PE-CVD silicon oxide (SiO2). Figure 1 (c) Showing: The active region is isolated by a silicon oxide dielectric in a shallow trench. To complete STI, SiO2 is optionally removed from the active region while retaining SiO2 within the shallow trench. This can be accomplished by STI CMP (the objective of this invention), in which SiO2 is removed at a high rate and SiN (stop layer) is not removed. Figure 1 (d) shows that etching can be used to remove SiN and expose silicon to complete STI. Once the gate, metal wiring, and device fabrication are completed, the active region of silicon becomes a transistor.

[0021] Figure 2 This is a schematic diagram of an STI patterned wafer thin film stack before polishing. .

[0022] Figure 3 It is a wafer plot depicting the overall defect rate after STI CMP using the silicon dioxide-based polishing composition according to the present invention.

[0023] Figure 4 It is a wafer plot depicting the overall defect rate after STI CMP using a commercially available composition containing cerium dioxide abrasive. Detailed Implementation

[0024] This invention relates to polishing compositions and methods for polishing semiconductor substrates using them. In some specific embodiments, the invention relates to the selective polishing of silicon oxide surfaces relative to silicon nitride surfaces. Selective polishing of silicon oxide relative to silicon nitride is a critical process in semiconductor manufacturing and is typically performed during shallow trench isolation (STI) processes. Conventionally, STI polishing compositions (slurries) utilize cerium dioxide abrasives to achieve the desired polishing performance (e.g., selectivity) in the STI process because compositions using silicon oxide abrasives perform poorly (e.g., high silicon nitride removal rates). However, it is known that cerium dioxide abrasives, due to their “inorganic hard” properties, produce high rates of defects and scratches when used in polishing compositions. Furthermore, cerium dioxide-based polishing compositions exhibit shorter shelf lives (e.g., lower storage capacity, shorter usable time period, and earlier shelf life) and shorter pot lifespans (e.g., activity after opening the container and / or in the storage tank or dispensing loop) than silicon dioxide-based polishing compositions, and cerium dioxide has greater price volatility than silicon dioxide. In addition, cerium dioxide includes rare earth metals, which are more expensive than silicon dioxide. The compositions disclosed in this invention allow the use of silica abrasives, which are softer than cerium dioxide abrasives, in STI slurries. Compared to STI processes using cerium dioxide abrasives, the silica-containing polishing compositions provide significantly better selectivity in terms of the material removal rate (MRR) of silicon oxide (e.g., TEOS) relative to silicon nitride (e.g., SiN), while providing polished wafer surfaces with very low defect rates. Therefore, the polishing compositions according to this application can increase wafer device yield compared to conventional polishing compositions using cerium dioxide abrasives.

[0025] The polishing compositions disclosed herein may include (a) an abrasive, (b) a nitride removal reducing agent, (c) an acid or base, (d) water, and optionally (e) a depression reducing agent (e.g., an anionic depression reducing agent). The polishing compositions may have a pH of at least about 2 and at most about 6.5. The polishing compositions disclosed herein can polish dielectrics or metals with high selectivity relative to polishing silicon nitride. The present invention also provides a method for polishing a semiconductor substrate using the polishing compositions. In particular, the present invention provides a method for polishing dielectrics or metals with high selectivity relative to silicon nitride.

[0026] In one or more embodiments, the at least one (e.g., two or three) abrasive is selected from cationic abrasives, substantially abrasives, and anionic abrasives. In one or more embodiments, the at least one abrasive is selected from the group consisting of: alumina, silica, titanium dioxide, cerium dioxide, zirconium oxide, co-formed products thereof, coated abrasives, surface-modified abrasives, and mixtures thereof. In some embodiments, the at least one abrasive does not include cerium dioxide.

[0027] In one or more embodiments, the abrasive is a silica-based abrasive, such as one selected from the group consisting of silica gel, calcined silica, and mixtures thereof. In one or more embodiments, the abrasive has a surface modified with organic groups and / or non-silica inorganic groups. For example, the cationic abrasive may include terminal groups having the following chemical formula (I): -O m -X-(CH2) n -Y (I), Where m is an integer from 1 to 3; n is an integer from 1 to 10; X is Al, Si, Ti, or Zr; and Y is a cationic amino or thiol group. As another example, the anionic abrasive may include terminal groups having the following chemical formula (I): -O m -X-(CH2) n -Y (I), Where m is an integer from 1 to 3; n is an integer from 1 to 10; X is Al, Si, Ti, or Zr; and Y is an acid group. In some specific embodiments, the at least one abrasive may be present in the polishing composition described herein in an amount of at least about 0.05 wt% (e.g., at least about 0.1 wt%, at least about 0.5 wt%, at least about 1 wt%, at least about 2 wt%, at least about 3 wt%, or at least about 5 wt%) to at most about 20 wt% (e.g., at most about 15 wt%, at most about 10 wt%, at most about 8 wt%, at most about 6 wt%, at most about 4 wt%, or at most about 2 wt%) based on the total weight of the composition.

[0028] In one or more embodiments, the abrasive described herein may have an average particle size of at least about 1 nm (e.g., at least about 5 nm, at least about 10 nm, at least about 20 nm, at least about 40 nm, at least about 50 nm, at least about 60 nm, at least about 80 nm, or at least about 100 nm) to at most about 1000 nm (e.g., at most about 800 nm, at most about 600 nm, at most about 500 nm, at most about 400 nm, or at most about 200 nm). As used herein, the average particle size (MPS) is determined by dynamic light scattering techniques.

[0029] In one or more specific embodiments, the at least one (e.g., two or three different) nitride removal rate reducing agent comprises C 12 To C 40A compound comprising a hydrophobic portion of a hydrocarbon group (e.g., containing an alkyl group and / or an alkenyl group) and a hydrophilic portion of at least one group selected from the group consisting of sulfinic acid, sulfate, sulfonic acid, carboxyl, phosphate, and phosphonic acid groups. In one or more embodiments, the hydrophobic portion and the hydrophilic portion are separated by 0 to 10 (e.g., 1, 2, 3, 4, 5, 6, 7, 8, or 9) epoxy alkyl groups (e.g., -(CH2)). n O- groups, where n can be 1, 2, 3, or 4, are separated. In one or more embodiments, the nitride removal rate reducing agent has a hydrophobic portion and a hydrophilic portion separated by 0 epoxy alkyl groups. It is believed, rather than being bound by theory, that the presence of epoxy alkyl groups in the nitride removal rate reducing agent may not be preferable in some embodiments, as they can cause slurry stability problems and reduce silicon nitride removal rates.

[0030] In one or more embodiments, the nitride removal reducing agent is included in the polishing composition described herein in an amount of at least about 0.1 ppm (e.g., at least about 0.5 ppm, at least about 1 ppm, at least about 5 ppm, at least about 10 ppm, at least about 25 ppm, at least about 50 ppm, at least about 75 ppm, or at least about 100 ppm) to at most about 1000 ppm (e.g., at most about 900 ppm, at most about 800 ppm, at most about 700 ppm, at most about 600 ppm, at most about 500 ppm, or at most about 250 ppm) based on the total weight of the composition.

[0031] In one or more embodiments, the nitride removal reducing agent has a hydrophobic portion containing a hydrocarbon group, said hydrocarbon group comprising at least 12 carbon atoms (C). 12 (For example, at least 14 carbon atoms (C) 14 ), at least 16 carbon atoms (C 16 ), at least 18 carbon atoms (C 18 ), at least 20 carbon atoms (C 20 ), or at least 22 carbon atoms (C 22 )) and / or up to 40 carbon atoms (C 40 (For example, up to 38 carbon atoms (C) 38 ), up to 36 carbon atoms (C 36 ), up to 34 carbon atoms (C 34 ), up to 32 carbon atoms (C 32 ), up to 30 carbon atoms (C 30） A maximum of 28 carbon atoms (C 28 ), up to 26 carbon atoms (C 26), up to 24 carbon atoms (C 24 ), or at most 22 carbon atoms (C 22） The hydrocarbon groups mentioned herein refer to groups containing only carbon and hydrogen atoms, and may include saturated groups (e.g., straight-chain alkyl groups, branched alkyl groups, or cyclic alkyl groups) and unsaturated groups (e.g., straight-chain alkenyl groups, branched alkenyl groups, or cyclic alkenyl groups; straight-chain alkynyl groups, branched alkynyl groups, or cyclic alkynyl groups; or aromatic groups (e.g., phenyl or naphthyl)). In one or more embodiments, the hydrophilic portion of the nitrogen removal reducing agent contains at least one group selected from phosphate groups and phosphonate groups. It should be noted that the term "phosphonate group" is explicitly intended to include phosphonic acid groups.

[0032] In one or more specific embodiments, the nitrogen removal rate reducing agent is selected from the group consisting of: napthalenesulfonic acid-formalin condensate, lauryl phosphate, myristyl phosphate, stearyl phosphate, octadecyl phosphate, oleyl phosphate, behenyl phosphate, octadecyl sulfate, lacteryl phosphate, oleth-3-phosphate, and oleth-10-phosphate.

[0033] In one or more embodiments, the polishing composition described herein optionally further comprises at least one (e.g., two or three) depression reducing agent (e.g., anionic depression reducing agent). In one or more embodiments, the at least one depression reducing agent is a compound comprising at least one group selected from the group consisting of: hydroxyl, sulfate, phosphonate, phosphate, sulfonic acid, amino, nitrate, nitrite, carboxyl, and carbonate groups. In one or more embodiments, the at least one depression reducing agent is selected from at least one group consisting of polysaccharides and substituted polysaccharides. In one or more embodiments, the at least one depression reducing agent is selected from at least one group consisting of: carrageenan, xanthan gum, hydroxypropyl cellulose, methylcellulose, ethylcellulose, hydroxypropyl methylcellulose, and carboxymethyl cellulose. In one or more embodiments, the at least one nitride removal rate reducing agent and the at least one depression reducing agent are chemically distinct from each other.

[0034] In one or more embodiments, the depression reducing agent is included in the polishing composition described herein in an amount of at least about 0.1 ppm (e.g., at least about 0.5 ppm, at least about 1 ppm, at least about 5 ppm, at least about 10 ppm, at least about 25 ppm, at least about 50 ppm, at least about 75 ppm, or at least about 100 ppm) to at most about 1000 ppm (e.g., at most about 900 ppm, at most about 800 ppm, at most about 700 ppm, at most about 600 ppm, or at most about 500 ppm) based on the total weight of the composition.

[0035] In one or more specific embodiments, the acid is selected from the group consisting of: formic acid, acetic acid, malonic acid, citric acid, propionic acid, malic acid, adipic acid, succinic acid, lactic acid, oxalic acid, hydroxyethylidene diphosphonic acid, 2-phosphonobutane-1,2,4-tricarboxylic acid, aminotrimethylphosphonic acid, hexamethylenetetramethylphosphonic acid, bis(hexamethylene)triaminephosphonic acid, glycine, peracetic acid, potassium acetate, phenoxyacetic acid, glycine, N-diglycine, diethylene glycol, glyceric acid, trimethylglycine, alanine, histidine, valine, phenylalanine, proline, glutamine, aspartic acid, glutamic acid, arginine, lysine, tyrosine, benzoic acid, nitric acid, sulfuric acid, sulfurous acid, phosphoric acid, phosphonic acid, hydrochloric acid, periodic acid, and mixtures thereof.

[0036] In one or more specific embodiments, the alkali is selected from the group consisting of: potassium hydroxide, sodium hydroxide, cesium hydroxide, ammonium hydroxide, triethanolamine, diethanolamine, monoethanolamine, tetrabutylammonium hydroxide, tetramethylammonium hydroxide, lithium hydroxide, imidazole, triazole, aminotriazole, tetraazole, benzotriazole, methylbenzotriazole, pyrazole, isothiazole, and mixtures thereof.

[0037] In one or more embodiments, the acid or base may be present in the polishing composition described herein in an amount from at least about 0.01 wt% (e.g., at least about 0.05 wt%, at least about 0.1 wt%, at least about 0.5 wt%, or at least about 1 wt%) to at most about 10 wt% (e.g., at most about 8 wt%, at most about 6 wt%, at most about 5 wt%, at most about 4 wt%, or at most about 2 wt%) based on the total weight of the composition. For example, the acid or base may be added in an amount sufficient to adjust the pH of the polishing composition to the desired value.

[0038] In one or more embodiments, the water may be present in the polishing composition described herein (e.g., as a liquid medium or carrier) in an amount from at least about 50 wt% (e.g., at least about 55 wt%, at least about 60 wt%, at least about 65 wt%, at least about 70 wt%, or at least about 75 wt%) to at most about 99.9 wt% (e.g., at most about 99.5 wt%, at most about 99 wt%, at most about 97 wt%, at most about 95 wt%, or at most about 90 wt%) based on the total weight of the composition.

[0039] In one or more embodiments, the polishing compositions described herein may have a pH of at least about 2 (e.g., at least about 2.5, at least about 3, at least about 3.5, or at least about 4) to at most about 6.5 (e.g., at most about 6, at most about 5.5, at most about 5, or at most about 4.5). It is believed, without being bound by theory, that polishing compositions having a pH greater than 6.5 may reduce the selectivity of silica / silicon nitride removal and have stability issues.

[0040] In one or more embodiments, the polishing described herein may substantially be free of one or more of the following components: salts (e.g., halides), polymers (e.g., cationic or anionic polymers, or polymers that are not sink-reducing agents), surfactants (e.g., those surfactants that are not nitride removal reducers), plasticizers, oxidants, corrosion inhibitors (e.g., azole or nonazole corrosion inhibitors), and / or certain abrasives (e.g., cerium dioxide abrasives or nonionic abrasives). Halides that can be excluded from the polishing composition include alkali metal halides (e.g., sodium halides or potassium halides) or ammonium halides (e.g., ammonium chloride), and may be chlorides, bromides, or iodides. As used herein, a component “substantially free” in the polishing composition means a component that is not intentionally added to the polishing composition. In some embodiments, the polishing composition described herein may contain up to about 1000 ppm (e.g., up to about 500 ppm, up to about 250 ppm, up to about 100 ppm, up to about 50 ppm, up to about 10 ppm, or up to about 1 ppm) of one or more of the aforementioned components that are substantially absent from the polishing composition. In some embodiments, the described polishing composition may be completely free of one or more of the aforementioned components.

[0041] In one or more embodiments, the polishing compositions described herein have a silicon oxide (e.g., TEOS) removal rate to silicon nitride removal rate ratio (i.e., removal rate selectivity) of at least about 3:1, or at least about 4:1, or at least about 5:1, or at least about 10:1, or at least about 25:1, or at least about 50:1, or at least about 60:1, or at least about 75:1, or at least about 100:1, or at least about 150:1, or at least about 200:1, or at least about 250:1, or at least about 300:1, or at least about 500:1, or at least about 750:1, or at most about 1000:1, or at most about 5000:1. In one or more embodiments, the ratio described above may be applicable when measuring the removal rate for polished blank wafers or patterned wafers (i.e., wafers comprising at least a silicon nitride pattern, wherein the silicon nitride pattern is covered with at least silicon oxide (and optionally covered with other materials such as metals and dielectrics)).

[0042] In one or more embodiments, when a patterned wafer (which may include at least a silicon nitride pattern covered with at least silicon oxide) is polished with the polishing composition (e.g., until the silicon nitride pattern on the patterned wafer is exposed by polishing), a silicon oxide (e.g., TEOS) depression of up to about 1000 angstroms, up to about 500 angstroms, or up to about 375 angstroms, or up to about 250 angstroms, or up to about 200 angstroms, or up to about 100 angstroms, or up to about 50 angstroms, and / or at least about 0 angstroms occurs. In one or more embodiments, when a patterned wafer (which may include at least a silicon nitride pattern covered with at least silicon oxide) is polished with the polishing composition (e.g., until the silicon nitride pattern on the patterned wafer is exposed by polishing), silicon nitride etching of up to about 500 angstroms, or up to about 400 angstroms, or up to about 300 angstroms, or up to about 250 angstroms, or up to about 200 angstroms, or up to about 100 angstroms, or up to about 75 angstroms, or up to about 65 angstroms, or up to about 50 angstroms, or up to about 32 angstroms and / or at least about 0 angstroms occurs.

[0043] In one or more embodiments, when a patterned wafer is polished using a polishing composition disclosed in this invention, the planarization efficiency (i.e., the change in silicon oxide step height divided by the amount of silicon oxide removed during polishing, multiplied by 100) is at least about 14% (e.g., at least about 20%, at least about 30%, at least about 38%, at least about 40%, at least about 46%, at least about 50%, at least about 60%, at least about 70%, or at least about 74%) and at most about 100% (e.g., at most about 99.9%, at most about 99%, at most about 95%, at most about 90%, at most about 80%, at most about 70%, and at most about 60%). In one or more embodiments, when a patterned wafer is polished using a polishing composition disclosed in this invention (e.g., a composition comprising a silicon oxide abrasive and the nitride removal rate reducing agent), the total defect count on a patterned wafer having a 12-inch (i.e., about 300 mm) diameter is at most 175 (e.g., at most 170, at most 160, at most 150, at most 125, at most 100, at most 75, at most 50, at most 25, at most 10, or at most 5). As described herein, the defects counted are those with a size of at least about 90 nm.

[0044] In one or more embodiments, the present invention is characterized by a polishing method that may include applying a polishing composition disclosed in the present invention to a substrate having at least silicon nitride and silicon oxide (e.g., a wafer) on its surface; and contacting a pad with the surface of the substrate and moving the pad relative to the substrate. In some embodiments, when the substrate comprises a pattern of at least silicon nitride covered with at least silicon oxide (e.g., silicon oxide in the presence of other materials such as silicon-based dielectrics (e.g., silicon carbide, etc.), metals, metal oxides, and nitrides, etc.), the above method may remove at least a portion of the silicon oxide (e.g., silicon oxide in active, non-trench regions) to expose the silicon nitride. It should be noted that the terms “silicon nitride” and “silicon oxide” described herein are explicitly intended to include both undoped and doped forms of silicon nitride and / or silicon oxide. For example, in one or more embodiments, the silicon nitride and silicon oxide may be independently doped with at least one dopant selected from carbon, nitrogen (for silicon oxide), oxygen, hydrogen, or any other known dopant for silicon nitride or silicon oxide. Some examples of silicon oxide thin film types include TEOS (tetraethyl orthosilicate), SiOC, SiOCN, SiOCH, SiOH, and SiON, to name just a few. Some examples of silicon nitride thin film types include SiN (pure silicon nitride), SiCN, SiCNH, and SiNH, to name just a few.

[0045] In some specific embodiments, the method using the polishing composition described herein may further include one or more additional steps to produce a semiconductor device from a substrate treated with the polishing composition. For example, prior to the polishing method described above, the method may include one or more of the following steps: (1) depositing silicon oxide (e.g., thermal silicon oxide) on a substrate (e.g., a silicon wafer) to form a silicon oxide layer, (2) depositing silicon nitride on the silicon oxide layer to form a silicon nitride layer, (3) etching the substrate to form trench and non-trench regions, and (4) depositing silicon oxide onto the etched substrate to fill the trenches with silicon oxide. As another example, after the polishing method described above, the method may include at least one additional step, such as etching the substrate (e.g., to remove silicon nitride and silicon oxide) to expose silicon and / or silicon oxide or other heterogeneous films on the wafer substrate.

[0046] Example Examples are provided to further illustrate the capabilities of the polishing compositions and methods disclosed in this invention. The examples provided are not intended and should not be construed as limiting the scope of the invention. Unless otherwise specified, any percentages listed are by weight (wt%). The nitride removal reducing agents described in the examples are available from a variety of different suppliers and, in some instances, may include smaller quantities of similar compounds having carbon chain lengths that are smaller or larger than those specified in the table below. The carbon chain lengths specified in the table determine the major components of the nitride removal reducing agents.

[0047] Example 1: Proof of Nitride Cessation In this embodiment, the polishing composition used for samples 1A-1F primarily comprises: 3 w / w% neutral silica abrasive, malonic acid as a pH adjuster, a nitride removal rate reducing agent (if present), and water as a liquid carrier. The pH of the polishing composition is 2.3. 200 mm blank silicon oxide (TEOS) and silicon nitride (SiN) wafers were polished on a Dow VP6000 pad using an Applied Materials Mirra CMP polisher at a downpressure of 2 psi and a flow rate of 175 mL / min.

[0048] Table 1. Removal rates of TEOS and SiN vs. Nitrogen oxide removal rates (types of surfactants) “EO” refers to ethylene oxide. “RR” refers to the removal rate.

[0049] The results in Table 1 show that the control polishing composition (excluding the nitride removal rate reducer) has a removal rate selectivity of 8 between silicon oxide and silicon nitride, which is too low for most applications requiring low silicon nitride rates. However, with the addition of the nitride removal rate reducer, the silicon nitride removal rate of the polishing composition decreases to as low as 1 Å / min and the removal rate selectivity increases to as high as 868.

[0050] Example 2: Evidence of pH range and different abrasive surface charges In this embodiment, the polishing composition used for samples 2A-2I comprises: 3 w / w% silica gel abrasive, an organic acid as a pH adjuster, n-octadecyl phosphate, and water as a liquid carrier. n-octadecyl phosphate is representative of the type of nitride removal reducer described herein. Furthermore, in this embodiment, the silica gel charge is varied by using neutral, cationic, and anionic silica (as shown in Table 2). The pH of the polishing composition varies from about 2.25 to about 4.25. 200 mm blank silicon oxide (TEOS) and silicon nitride wafers were polished on a Dow VP6000 pad using an Applied Materials Mirra CMP polisher at a downpressure of 2 psi and a flow rate of 175 mL / min.

[0051] Table 2. TEOS and SiN Removal Rates vs. pH and Three Types of Silica As shown in Table 2, the nitride removal rate reducer, together with neutral silica, cationic silica, and anionic silica, can control silica removal rates in a pH range of approximately 2.25 to approximately 4.25. The robust nitride rate reduction of the above system is surprising, regardless of the surface charge of the silica abrasive. For example, it is generally believed that cationic abrasives have poor compatibility with anionic nitride removal rate reducers. Conversely, in this system, the slurry remains stable and the nitride removal rate reducer remains active.

[0052] Typically, silicon nitride removal rates are very high (~400 Å / min) and difficult to control when using anionic abrasives. Notably, the nitride removal reducers described herein can significantly reduce silicon nitride removal rates. This type of system can be useful when low TEOS and silicon nitride removal rates, along with high removal rates on well-polished films (e.g., silicon carbide films) using anionic abrasives, are desired.

[0053] Example 3: Demonstration of the effect of chain length and head shape of nitrogen oxide removal rate reducing agent In this embodiment, the polishing composition for samples 3A-3L comprises: 3 w / w% silica gel abrasive, malonic acid as a pH adjuster, a nitride removal rate reducing agent shown in Table 3, and water as a liquid carrier. The pH of the polishing composition is 2.25. Specifically, the nitride removal rate reducing agent for samples 3A-3L comprises the head type and hydrophobic material described in Table 3 and does not contain any epoxy alkyl groups. Furthermore, the nitride removal rate reducing agents for samples 3I, 3J, and 3K comprise a mixture of surfactants, wherein lauryl phosphate / myristyl phosphate, stearoyl phosphate, and tridecyl phosphate are the main components.

[0054] 200 mm silicon oxide (TEOS) and silicon nitride blank wafers were polished on a Dow VP6000 pad using an Applied Materials Mirra CMP polisher at a downpressure of 2 psi and a flow rate of 175 mL / min.

[0055] Table 3. Head groups and hydrophobicities of TEOS and SiN removal rates vs. nitride removal rate reducing agents As shown in Table 3, the size of the hydrophobic components in the nitride removal rate reducer plays a significant role in determining the rate reduction of silicon nitride. Table 3 shows that, among the tested reagents, a chain length of 12 or greater is better for effective nitride stopping under the test conditions. A carbon chain length of 12 or greater in the nitride removal rate reducer (see samples 3D, 3E, 3F, 3G, 3I, 3J, 3K, and 3L in Table 3) ensures low SiN RR (typically <5 A / min) and produces a high selectivity ratio (>250) for TEOS:SiN RR in blank films. Therefore, this polishing composition is ideally suited for STI CMP processes where a high selectivity ratio of silicon oxide to silicon nitride is desired.

[0056] Example 4: Proof of Downward Pressure In this embodiment, the polishing composition for samples 4A-4C comprises: 3 w / w% silica abrasive, an organic acid as a pH adjuster, n-octadecyl phosphate, and water as a liquid carrier. The pH of the polishing composition is from 2 to 6.5. 200 mm high-density plasma (HDP) silicon oxide, tetraethyl orthosilicate oxide (TEOS), borosilicate glass (BPSG), and silicon nitride-coated wafers were polished on Dow IC1010 pads using an Applied Materials Mirra CMP polisher at pressures of 2, 3, and 4 psi and a flow rate of 175 mL / min.

[0057] Table 4. HDP, TEOS, BPSG, and SiN removal rates vs. pressure. As shown in Table 4, silica films (HDP, TEOS, and BPSG) exhibit Prestonian behavior, while silicon nitride removal rates exhibit non-Prestonian behavior and maintain good control regardless of applied downpressure. In CMP terminology, Prestonian behavior of removal rate means that the polishing rate increases linearly with increasing polishing pressure and / or angular velocity / rpm (revolutions per minute) on the polisher. Prestonian behavior is desirable for high-rate target films (silica films in this case). Non-Prestonian behavior means that the polishing rate does not change significantly with changes in pressure or speed. Non-Prestonian behavior is somewhat desirable for stopping films (SiN in this case). As seen in Table 4, the removal rate of silica films increases linearly / Prestonianly with increasing downpressure (e.g., as the downpressure increases from 2 psi to 3 to 4 psi, the TEOS RR increases from 1835 to 2324 to 3140 A / min). Conversely, the SiN (stopping film) removal rate did not change significantly with increasing pressure (i.e., as the pressure increased from 2 psi to 3-4 psi, the SiN RR fluctuated from 4 A / min to 2 A / min to 1 A / min). Furthermore, this example demonstrates that the polishing composition exhibits similar behavior on silicon oxide family films as previously defined. For further illustration, in Table 4, we describe three examples of silicon oxide films: HDP, TEOS, and BPSG. The polishing composition disclosed in this invention works very effectively to provide high material removal rates on all different types of silicon oxide films. Equivalent experiments using examples of different types of silicon nitride films (SiN, SiCN, etc.) show similar slurry stopping behavior as depicted on the SiN films in Table 4. For simplicity, only SiN film rates are depicted in Table 4.

[0058] Example 5: Proof of the Padding Effect In this embodiment, the polishing composition used for samples 5A-5C comprises: 3 w / w% silica gel abrasive, an organic acid as a pH adjuster, a nitride removal rate reducing agent, and water as a liquid carrier. The pH of the polishing composition is from 2 to 6.5. 200 mm blank wafers of tetraethyl orthosilicate oxide (TEOS) and silicon nitride (SiN) were polished on Dow VP6000 or Fujibo H800 pads using an Applied Materials Mirra CMP polisher at a downpressure of 2 psi and a flow rate of 175 mL / min.

[0059] Table 5. TEOS and SiN Removal Rates vs. Liners and Nitride Removal Reducers As shown in Table 5, the nitride removal rate reducer has an effect on silicon nitride protection. On the Dow VP6000 pad (which has medium hardness), all samples (5A-5C) provided effective nitride protection, as demonstrated by the low SiN removal rate and TEOS / SiN removal rate selectivity. However, on the Fujibo H800 pad (which is a soft pad), only the samples (5A, 5B) containing the nitride removal rate reducer with long-chain saturated hydrophobic substances provided effective nitride stopping. Therefore, this example demonstrates that the polishing composition disclosed in this invention works effectively on all types of polishing pads. Furthermore, this example shows a trend towards enhanced nitride protection when the nitride removal rate reducer includes longer hydrophobic substances, is more saturated, and / or more hydrophobic.

[0060] Example 6: Proof of Depression Reduction In this embodiment, the polishing composition for samples 6A-6D comprises: 3 w / w% silica abrasive, an organic acid as a pH adjuster, n-octadecyl phosphate, an anionic depression reducing polymer (if present), and water as a liquid carrier. The pH of the polishing composition is 3.0. A 200 mm STI 1 silicon oxide / silicon nitride patterned wafer was polished on a Dow VP6000 pad using an AppliedMaterials Mirra CMP polisher at a downpressure of 2 psi and a flow rate of 175 mL / min. After overpolishing for approximately 50 seconds and 20 seconds, the wafer was terminally aligned by laser measurement.

[0061] Table 6. The effect of anionic pitting on reducing polymers' influence on oxide pitting. As shown in Table 6, the addition of anionic depression-reducing polymers is effective in controlling oxide depression, especially for small features. Sample 6A does not contain a depression reducer, while samples 6B, 6C & 6D contain three different types of depression reducers. As can be seen from Table 6, when compared with sample 6A, the silica depression values ​​on both the 5 μm and 20 μm features of samples 6B, 6C, and 6D are much smaller.

[0062] Example 7: Proof of Concentrate In this embodiment, the polishing composition for samples 7A-7C comprises a concentrate corresponding to the point formulation used: 3 w / w% neutral silica abrasive, an organic acid and / or potassium hydroxide as a pH adjuster, n-octadecyl phosphate, and water as a liquid carrier. The single-tank solution contains all components required for polishing, while the two-part system contains all components except the organic acid. Average particle size (MPS) is a reliable indicator of slurry stability. In unstable systems, particles aggregate over time, leading to measurable MPS growth. MPS was measured using dynamic light scattering technology on a Malvern instrument. The slurry was stored in an oven set to 60°C and measured every 7 days. According to the Arrhenius model relationship used for accelerated aging testing, a complete 21-day test run corresponds to approximately one year of room temperature aging. In other words, if the slurry is maintained at 60°C for 21 days and there is no significant MPS growth in silica, it demonstrates that the slurry has a real-time shelf life / shelf life of one year.

[0063] Table 7. Accelerated aging of slurry concentrate (60℃) As shown in Table 7, all formulations were stable throughout the test run. Stability in the acidic region of neutral silica is typically difficult to achieve. Single-tank solutions were stable at pH from approximately 2 to approximately 6.5 at 2x concentrations (selected data shown in Table 7) and at other concentration levels (e.g., 3x, 4x, and up to 10x concentrates) (not shown). In two-part solutions (7C), all components except the acid were concentrated to a greater extent and remained stable (up to 10x). At the point of use, acid and water were added to reconstitute the slurry before running it on the polishing tool.

[0064] Example 8: Demonstration of the selectivity of patterned wafer removal rate In this embodiment, a 200 mm STI patterned wafer was polished using a polishing composition for samples 8A, 8B, and 8C (containing silica abrasive and nitride removal rate reducers shown in Tables 1, 3, and 5), wherein the patterned silicon nitride was filled with high-density silicon oxide, such as... Figure 2 As shown, the patterns in silicon nitride are as follows: various line spacings, squares, grid patterns, and grid arrays with various spacings and densities are arranged across the entire wafer surface.

[0065] Polishing was performed on an Applied Materials 200mm Mirra polishing tool, fitted with a DowDupont VP6000 pad, a 3M A165 CIP1 adjustment disk, and using 2PSI wafer back pressure. Polishing time was varied based on in-situ endpoints detected by both motor torque and red laser (650nm) absorbance. During polishing, characteristics within these two endpoint signals were observed, indicating the removal of silicon oxide and the exposure of underlying silicon nitride within the effective lines of the thin-film stack. Patterned silicon oxide removal rate was calculated by dividing the amount of material removed before silicon nitride exposure by the polishing time. Conversely, patterned silicon nitride removal rate was calculated by dividing the amount of material removed by the time since it was exposed to the polishing composition. After polishing, the wafer was cleaned using Fujifilm Wako 8901 post-CMP cleaning chemicals via a 200mm OnTrack post-CMP cleaning tool (from LamResearch). Thin film thickness measurements were taken on all wafers using a KLA Tencor F5X ellipsometry (e.g., to determine removal rates).

[0066] Table 8. Patterned wafer removal rates and selectivity on various line-spaced arrays As shown in Table 8, the high selectivity between silicon oxide and silicon nitride material removal rates previously observed on blank wafers is also observed on patterned wafers containing both silicon oxide (top) and silicon nitride (bottom). As can be seen in Table 8, for sample 8A, the silicon oxide selectivity to silicon nitride ranges from 86 to 190, depending on pattern size, density, and spacing. For sample 8B, the silicon oxide selectivity to silicon nitride is 54, while for sample 8C, the selectivity is 4. Table 8 provides only representative examples of performance on patterned wafers. In our internal experiments, selectivity ratios have been observed on patterned test wafers ranging from 3 (considered satisfactory for patterned wafers) to approximately 1000, depending on film complexity. Furthermore, the polishing compositions containing nitride removal reducers presented herein exhibit selectivity exceeding that of many prior art, industry-standard, commercially available cerium dioxide-based STI polishing compositions.

[0067] Example 9: Proof of Patterned Wafer Depression and Etching In this embodiment, to quantify the silicon oxide recess / step height and silicon nitride etch / loss at the terminal, measurements were taken in a Park Systems AFM tool similar to those used for the patterned wafer in Example 8. The polishing compositions used for samples 9A and 9B contained the nitride removal rate reducers shown in Tables 1, 3, and 5, and were used to polish patterned wafers (whose stacks are depicted on…) Figure 2 (Middle). The results for silicon oxide pitting / step height and silicon nitride corrosion / loss are shown in Table 9. Planarization efficiency (PE) is reported as a percentage and is equal to the change in silicon oxide step height divided by the amount of oxide removed during polishing, then multiplied by one hundred (converted to a percentage).

[0068] Table 9. Patterned Wafer Recesses and Etching As can be seen in Table 9, the silicon oxide pitting and silicon nitride etching are very small. Typically, very low numbers are preferred for pitting and etching. The pitting and etching numbers represent the flatness of the final morphology of the patterned wafer after CMP polishing. Therefore, low values ​​(Å) of these numbers are desirable because these numbers measure the separation of peaks and valleys on a wafer containing multiple thin film types in a patterned wafer. The lower the number, the smaller the separation between peaks and trenches, meaning a flatter wafer surface, which is the overall goal of the CMP process steps in semiconductor manufacturing. Ideally, zero pitting and etching values ​​are preferred (meaning a completely flat wafer surface). However, typically, these numbers are generally in the hundreds or thousands of Å values ​​for patterned wafers in actual devices / products. Therefore, the data shown in Table 9 indicates that the polishing composition offers unique / extraordinary performance in achieving very low pitting and etching values ​​and therefore very good morphology of the patterned wafer. As can be seen in Table 9, silicon oxide pits can range from as low as 35 Å to as high as 375 Å. SiN etching is much better than pitting, with etching figures ranging from as low as 30 Å to as high as 74 Å. Furthermore, these are representative examples; in our experiments we have seen pit and etching figures ranging from as high as 1000 Å to as low as 1 Å, which remains satisfactory for the purposes of this invention and acceptable to semiconductor manufacturers.

[0069] Regarding planarization efficiency (PE), a higher number indicates better results. Ideally, 100% PE is desired because this value signifies that the entire wafer has been planarized and is flat, meaning there are no staircases between peaks and valleys. As seen in Table 9, PE ranges from a low of 14% to 74%. Therefore, these polishing compositions provide good planarization efficiency on patterned wafers.

[0070] Furthermore, the data presented in Table 9 show that the polishing composition presented in this paper surpasses the oxide pitting, silicon nitride etching, and planarization efficiencies of commercially available cerium dioxide-based STI polishing compositions in the prior art.

[0071] Example 10: Proof of defect rate in patterned wafers after polishing In this embodiment, the defect rate of the patterned wafers used in Examples 8 and 9 was measured in the KLA-AIT XUV defect counting tool using a commercial cerium dioxide-based STI formulation and composition 8A described in Example 8 (which is a silicon dioxide-based polishing composition containing a nitride removal rate reducer). Wafer patterns for wafers polished using composition 8A are presented in... Figure 3 The wafer pattern presented for wafers polished using a commercial cerium dioxide-based STI polishing composition is shown in... Figure 4 middle.

[0072] As by Figure 4 It has been demonstrated that, due to the relative hardness and size of the abrasive, cerium dioxide-based formulations readily produce severe arc scratches and numerous defects (total defect count greater than 10,000) throughout the wafer. Careful examination of the defects revealed numerous large and small scratches along with many residues, many of which could be considered fatal defects in the overall device. However, Figure 3 Display: Polishing composition containing high-purity silica gel as an abrasive 8A compared to cerium dioxide-based compositions ( Figure 4 It exhibits significantly fewer scratches. Indeed, the silicon oxide polishing composition displays a near-defect-free and clean surface. For defects at least 90nm in size, the total defect count is approximately 175. Defects are critical to final device yield and the production of marketable chips. Figure 4 In the patterned wafers shown, it is assumed that each patterned wafer has 1000 dies (per square meter). If the defects are fatal to the device, the individual dies with defects become unsellable. Therefore, because the cerium dioxide-based polishing composition exhibits a high number of defects, the yield of marketable chips per wafer will be low. Conversely, with the polishing composition disclosed in this invention, defects are significantly fewer and therefore the yield of marketable chips per wafer is significantly higher.

[0073] Therefore, the low defect rate achieved by using the polishing compositions disclosed in this invention is highly attractive to semiconductor companies because it improves both their top and bottom lines of revenue. From a technical point of view, cerium dioxide abrasives are inherently inorganic (e.g., cerium-lanthanide metal-based oxides) and are generally hard, and are larger in size than silicon dioxide abrasives, thus they readily generate a large number of scratches and defects on wafer surfaces. Conversely, silicone abrasives are inherently organic (silicon nonmetal-based oxides and in colloidal dispersion form) and are generally soft, thus not generating scratches or defects during polishing.

[0074] Those skilled in the art have not been able to develop silica-based STI polishing compositions with satisfactory silica removal selectivity relative to silicon nitride. As disclosed herein, the inventors have discovered a synergistic combination of silica and silicon nitride removal reducing agents that can supply silica-based STI polishing compositions to the industry. Furthermore, the invention described herein can be applied to abrasives other than silica (such as alumina, titanium dioxide, etc.).

[0075] Although the invention has been described with respect to the embodiments mentioned herein, it should be understood that other modifications and variations are possible without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A polishing composition comprising: At least one abrasive; At least one nitrogen oxide removal reducing agent, comprising: hydrocarbon group; and 12 to C 40 hydrophobic portion of the hydrocarbon group; and A hydrophilic portion containing at least one group, said at least one group being selected from the group consisting of sulfinic acid group, sulfate group, sulfonic acid group, carboxyl group, phosphate group, and phosphonic acid group; and in, The hydrophobic portion and the hydrophilic portion are separated by 0 to 10 epoxy alkyl groups; Acids or bases; and water; The polishing composition has a pH of about 2 to about 6.

5.

2. The polishing composition of claim 1, further comprising: At least one depression reducing agent; in, The at least one depression reducing agent is a compound containing at least one group, wherein the at least one group is selected from the group consisting of hydroxyl, sulfate, phosphonic acid, phosphate, sulfonic acid, amino, nitrate, nitrite, carboxyl, and carbonate groups.

3. The polishing composition of claim 1, wherein, The at least one depression reducing agent is selected from at least one group consisting of polysaccharides and substituted polysaccharides.

4. The polishing composition of claim 1, wherein, The at least one depression reducing agent comprises carrageenan, xanthan gum, hydroxypropyl cellulose, methylcellulose, ethylcellulose, hydroxypropyl methylcellulose, or carboxymethyl cellulose.

5. The polishing composition of claim 1, wherein, The hydrophobic portion comprises C 12 to C 32 hydrocarbon groups.

6. The polishing composition of claim 1, wherein, The hydrophobic portion contains C 16 To C 22 Hydrocarbon group.

7. The polishing composition of claim 1, wherein, The hydrophilic portion contains phosphate groups or phosphonic acid groups.

8. The polishing composition of claim 1, wherein, The at least one nitrogen removal rate reducing agent is selected from the group consisting of: naphthalenesulfonic acid-formalin condensate, lauryl phosphate, myristyl phosphate, stearoyl phosphate, octadecyl phosphate, oleyl phosphate, dodecyl phosphate, octadecyl sulfate, tridecyl phosphate, oleyl polyether-3-phosphate, and oleyl polyether-10-phosphate.

9. The polishing composition of claim 1, wherein, The at least one nitride removal rate reducing agent has 0 epoxy alkyl groups separating the hydrophobic portion and the hydrophilic portion.

10. The polishing composition of claim 2, wherein, The at least one nitride removal rate reducing agent and the at least one depression reducing agent are chemically different from each other.

11. The polishing composition of claim 1, wherein, The polishing composition has a silicon oxide removal rate to silicon nitride removal rate ratio of at least about 3:

1.

12. The polishing composition of claim 1, wherein, The polishing composition has a silicon oxide removal rate to silicon nitride removal rate ratio of at least about 100:

1.

13. The polishing composition of claim 1, wherein, The at least one abrasive is selected from the group consisting of: cationic abrasives, substantially abrasives, and anionic abrasives.

14. The polishing composition of claim 1, wherein, The at least one abrasive is selected from the group consisting of: alumina, silicon dioxide, titanium dioxide, cerium dioxide, zirconium oxide, co-formed products thereof, coated abrasives, surface-modified abrasives, and mixtures thereof.

15. The composition of claim 1, wherein, The acid is selected from the group consisting of: formic acid, acetic acid, malonic acid, citric acid, propionic acid, malic acid, adipic acid, succinic acid, lactic acid, oxalic acid, hydroxyethylidene diphosphonic acid, 2-phosphonobutane-1,2,4-tricarboxylic acid, aminotrimethylphosphonic acid, hexamethylenetetramethylphosphonic acid, bis(hexamethylene)triaminephosphonic acid, glycine, peracetic acid, potassium acetate, phenoxyacetic acid, glycine, N-diglycine, diethylene glycol, glyceric acid, trimethylglycine, alanine, histidine, valine, phenylalanine, proline, glutamine, aspartic acid, glutamic acid, arginine, lysine, tyrosine, benzoic acid, nitric acid, sulfuric acid, sulfurous acid, phosphoric acid, phosphonic acid, hydrochloric acid, periodic acid, and mixtures thereof.

16. The composition of claim 1, wherein, The alkali is selected from the group consisting of: potassium hydroxide, sodium hydroxide, cesium hydroxide, ammonium hydroxide, triethanolamine, diethanolamine, monoethanolamine, tetrabutylammonium hydroxide, tetramethylammonium hydroxide, lithium hydroxide, imidazole, triazole, aminotriazole, tetraazole, benzotriazole, methylbenzotriazole, pyrazole, isothiazole and mixtures thereof.

17. A method comprising: The polishing composition of claim 1 is applied to a substrate having at least silicon nitride and at least silicon oxide on its surface; and The pad is brought into contact with the surface of the substrate and the pad is moved relative to the substrate.

18. The method of claim 17, wherein, At least one of the silicon nitride and silicon oxide is doped with at least one dopant selected from the group consisting of carbon, nitrogen, oxygen and hydrogen.

19. The method of claim 17, further comprising forming a semiconductor device on the substrate.

20. The method of claim 18, further comprising forming a semiconductor device from the substrate.

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